Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-next-5.5-2019-12-03' of git://people.freedesktop.org/~agd5f/linux into drm-next
drm-next-5.5-2019-12-03:
amdgpu:
- Fix vram lost handling with BACO on VI/CI asics
- DC fixes for Navi14
- Misc gfx10 fixes
- SR-IOV fixes
- Fix driver unload
- Fix XGMI limits on Arcturus
amdkfd:
- Enable KFD on PPC
- Optimize KFD page table reservations
radeon:
- Fix register checker for r1xx/r2xx
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191203204135.5437-1-alexander.deucher@amd.com
+237
-305
-1
MAINTAINERS
-1
MAINTAINERS
+14
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+14
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
···
105
105
(kfd_mem_limit.max_ttm_mem_limit >> 20));
106
106
}
107
107
108
+
/* Estimate page table size needed to represent a given memory size
109
+
*
110
+
* With 4KB pages, we need one 8 byte PTE for each 4KB of memory
111
+
* (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
112
+
* of memory (factor 256K, >> 18). ROCm user mode tries to optimize
113
+
* for 2MB pages for TLB efficiency. However, small allocations and
114
+
* fragmented system memory still need some 4KB pages. We choose a
115
+
* compromise that should work in most cases without reserving too
116
+
* much memory for page tables unnecessarily (factor 16K, >> 14).
117
+
*/
118
+
#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
119
+
108
120
static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
109
121
uint64_t size, u32 domain, bool sg)
110
122
{
123
+
uint64_t reserved_for_pt =
124
+
ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
111
125
size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
112
-
uint64_t reserved_for_pt = amdgpu_amdkfd_total_mem_size >> 9;
113
126
int ret = 0;
114
127
115
128
acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
1487
1487
return ret;
1488
1488
1489
1489
/* Start rlc autoload after psp recieved all the gfx firmware */
1490
-
if (psp->autoload_supported && ucode->ucode_id ==
1491
-
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
1490
+
if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1491
+
AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
1492
1492
ret = psp_rlc_autoload(psp);
1493
1493
if (ret) {
1494
1494
DRM_ERROR("Failed to start rlc autoload\n");
+12
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+12
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
···
27
27
#include <linux/bits.h>
28
28
#include "smu_v11_0_i2c.h"
29
29
30
-
#define EEPROM_I2C_TARGET_ADDR 0xA0
30
+
#define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
31
+
#define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
31
32
32
33
/*
33
34
* The 2 macros bellow represent the actual size in bytes that
···
84
83
{
85
84
int ret = 0;
86
85
struct i2c_msg msg = {
87
-
.addr = EEPROM_I2C_TARGET_ADDR,
86
+
.addr = 0,
88
87
.flags = 0,
89
88
.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
90
89
.buf = buff,
···
93
92
94
93
*(uint16_t *)buff = EEPROM_HDR_START;
95
94
__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
95
+
96
+
msg.addr = control->i2c_address;
96
97
97
98
ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
98
99
if (ret < 1)
···
206
203
unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
207
204
struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
208
205
struct i2c_msg msg = {
209
-
.addr = EEPROM_I2C_TARGET_ADDR,
206
+
.addr = 0,
210
207
.flags = I2C_M_RD,
211
208
.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
212
209
.buf = buff,
···
216
213
217
214
switch (adev->asic_type) {
218
215
case CHIP_VEGA20:
216
+
control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20;
219
217
ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
220
218
break;
221
219
222
220
case CHIP_ARCTURUS:
221
+
control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
223
222
ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
224
223
break;
225
224
···
233
228
DRM_ERROR("Failed to init I2C controller, ret:%d", ret);
234
229
return ret;
235
230
}
231
+
232
+
msg.addr = control->i2c_address;
236
233
237
234
/* Read/Create table header from EEPROM address 0 */
238
235
ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
···
415
408
* Update bits 16,17 of EEPROM address in I2C address by setting them
416
409
* to bits 1,2 of Device address byte
417
410
*/
418
-
msg->addr = EEPROM_I2C_TARGET_ADDR |
419
-
((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
411
+
msg->addr = control->i2c_address |
412
+
((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
420
413
msg->flags = write ? 0 : I2C_M_RD;
421
414
msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
422
415
msg->buf = buff;
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
+1
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+1
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
···
124
124
*/
125
125
int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev)
126
126
{
127
-
volatile u32 *dst_ptr;
128
127
u32 dws;
129
128
int r;
130
129
131
130
/* allocate clear state block */
132
131
adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
133
-
r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
132
+
r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
134
133
AMDGPU_GEM_DOMAIN_VRAM,
135
134
&adev->gfx.rlc.clear_state_obj,
136
135
&adev->gfx.rlc.clear_state_gpu_addr,
···
139
140
amdgpu_gfx_rlc_fini(adev);
140
141
return r;
141
142
}
142
-
143
-
/* set up the cs buffer */
144
-
dst_ptr = adev->gfx.rlc.cs_ptr;
145
-
adev->gfx.rlc.funcs->get_csb_buffer(adev, dst_ptr);
146
-
amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
147
-
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
148
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
149
143
150
144
return 0;
151
145
}
+5
-2
drivers/gpu/drm/amd/amdgpu/cik.c
+5
-2
drivers/gpu/drm/amd/amdgpu/cik.c
···
1346
1346
{
1347
1347
int r;
1348
1348
1349
-
if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
1349
+
if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
1350
+
if (!adev->in_suspend)
1351
+
amdgpu_inc_vram_lost(adev);
1350
1352
r = smu7_asic_baco_reset(adev);
1351
-
else
1353
+
} else {
1352
1354
r = cik_asic_pci_config_reset(adev);
1355
+
}
1353
1356
1354
1357
return r;
1355
1358
}
+53
-129
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+53
-129
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
690
690
adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
691
691
adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
692
692
693
-
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
694
-
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
695
-
if (err)
696
-
goto out;
697
-
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
698
-
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
699
-
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
700
-
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
701
-
if (version_major == 2 && version_minor == 1)
702
-
adev->gfx.rlc.is_rlc_v2_1 = true;
693
+
if (!amdgpu_sriov_vf(adev)) {
694
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
695
+
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
696
+
if (err)
697
+
goto out;
698
+
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
699
+
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
700
+
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
701
+
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
702
+
if (version_major == 2 && version_minor == 1)
703
+
adev->gfx.rlc.is_rlc_v2_1 = true;
703
704
704
-
adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
705
-
adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
706
-
adev->gfx.rlc.save_and_restore_offset =
705
+
adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
706
+
adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
707
+
adev->gfx.rlc.save_and_restore_offset =
707
708
le32_to_cpu(rlc_hdr->save_and_restore_offset);
708
-
adev->gfx.rlc.clear_state_descriptor_offset =
709
+
adev->gfx.rlc.clear_state_descriptor_offset =
709
710
le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
710
-
adev->gfx.rlc.avail_scratch_ram_locations =
711
+
adev->gfx.rlc.avail_scratch_ram_locations =
711
712
le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
712
-
adev->gfx.rlc.reg_restore_list_size =
713
+
adev->gfx.rlc.reg_restore_list_size =
713
714
le32_to_cpu(rlc_hdr->reg_restore_list_size);
714
-
adev->gfx.rlc.reg_list_format_start =
715
+
adev->gfx.rlc.reg_list_format_start =
715
716
le32_to_cpu(rlc_hdr->reg_list_format_start);
716
-
adev->gfx.rlc.reg_list_format_separate_start =
717
+
adev->gfx.rlc.reg_list_format_separate_start =
717
718
le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
718
-
adev->gfx.rlc.starting_offsets_start =
719
+
adev->gfx.rlc.starting_offsets_start =
719
720
le32_to_cpu(rlc_hdr->starting_offsets_start);
720
-
adev->gfx.rlc.reg_list_format_size_bytes =
721
+
adev->gfx.rlc.reg_list_format_size_bytes =
721
722
le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
722
-
adev->gfx.rlc.reg_list_size_bytes =
723
+
adev->gfx.rlc.reg_list_size_bytes =
723
724
le32_to_cpu(rlc_hdr->reg_list_size_bytes);
724
-
adev->gfx.rlc.register_list_format =
725
+
adev->gfx.rlc.register_list_format =
725
726
kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
726
-
adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
727
-
if (!adev->gfx.rlc.register_list_format) {
728
-
err = -ENOMEM;
729
-
goto out;
727
+
adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
728
+
if (!adev->gfx.rlc.register_list_format) {
729
+
err = -ENOMEM;
730
+
goto out;
731
+
}
732
+
733
+
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
734
+
le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
735
+
for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
736
+
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
737
+
738
+
adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
739
+
740
+
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
741
+
le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
742
+
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
743
+
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
744
+
745
+
if (adev->gfx.rlc.is_rlc_v2_1)
746
+
gfx_v10_0_init_rlc_ext_microcode(adev);
730
747
}
731
-
732
-
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
733
-
le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
734
-
for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
735
-
adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
736
-
737
-
adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
738
-
739
-
tmp = (unsigned int *)((uintptr_t)rlc_hdr +
740
-
le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
741
-
for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
742
-
adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
743
-
744
-
if (adev->gfx.rlc.is_rlc_v2_1)
745
-
gfx_v10_0_init_rlc_ext_microcode(adev);
746
748
747
749
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
748
750
err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
···
993
991
}
994
992
995
993
return 0;
996
-
}
997
-
998
-
static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
999
-
{
1000
-
int r;
1001
-
1002
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1003
-
if (unlikely(r != 0))
1004
-
return r;
1005
-
1006
-
r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1007
-
AMDGPU_GEM_DOMAIN_VRAM);
1008
-
if (!r)
1009
-
adev->gfx.rlc.clear_state_gpu_addr =
1010
-
amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1011
-
1012
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1013
-
1014
-
return r;
1015
-
}
1016
-
1017
-
static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
1018
-
{
1019
-
int r;
1020
-
1021
-
if (!adev->gfx.rlc.clear_state_obj)
1022
-
return;
1023
-
1024
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1025
-
if (likely(r == 0)) {
1026
-
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1027
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1028
-
}
1029
994
}
1030
995
1031
996
static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
···
1756
1787
1757
1788
static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1758
1789
{
1759
-
int r;
1760
-
1761
-
if (adev->in_gpu_reset) {
1762
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1763
-
if (r)
1764
-
return r;
1765
-
1766
-
r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj,
1767
-
(void **)&adev->gfx.rlc.cs_ptr);
1768
-
if (!r) {
1769
-
adev->gfx.rlc.funcs->get_csb_buffer(adev,
1770
-
adev->gfx.rlc.cs_ptr);
1771
-
amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1772
-
}
1773
-
1774
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1775
-
if (r)
1776
-
return r;
1777
-
}
1790
+
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1778
1791
1779
1792
/* csib */
1780
1793
WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
···
1765
1814
adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1766
1815
WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1767
1816
1768
-
return 0;
1769
-
}
1770
-
1771
-
static int gfx_v10_0_init_pg(struct amdgpu_device *adev)
1772
-
{
1773
-
int i;
1774
-
int r;
1775
-
1776
-
r = gfx_v10_0_init_csb(adev);
1777
-
if (r)
1778
-
return r;
1779
-
1780
-
for (i = 0; i < adev->num_vmhubs; i++)
1781
-
amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
1782
-
1783
-
/* TODO: init power gating */
1784
1817
return 0;
1785
1818
}
1786
1819
···
1860
1925
{
1861
1926
int r;
1862
1927
1863
-
if (amdgpu_sriov_vf(adev))
1864
-
return 0;
1865
-
1866
1928
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1929
+
1867
1930
r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1868
1931
if (r)
1869
1932
return r;
1870
1933
1871
-
r = gfx_v10_0_init_pg(adev);
1872
-
if (r)
1873
-
return r;
1934
+
gfx_v10_0_init_csb(adev);
1874
1935
1875
-
/* enable RLC SRM */
1876
-
gfx_v10_0_rlc_enable_srm(adev);
1877
-
1936
+
if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1937
+
gfx_v10_0_rlc_enable_srm(adev);
1878
1938
} else {
1879
1939
adev->gfx.rlc.funcs->stop(adev);
1880
1940
···
1891
1961
return r;
1892
1962
}
1893
1963
1894
-
r = gfx_v10_0_init_pg(adev);
1895
-
if (r)
1896
-
return r;
1964
+
gfx_v10_0_init_csb(adev);
1897
1965
1898
1966
adev->gfx.rlc.funcs->start(adev);
1899
1967
···
2753
2825
/* Init gfx ring 0 for pipe 0 */
2754
2826
mutex_lock(&adev->srbm_mutex);
2755
2827
gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2756
-
mutex_unlock(&adev->srbm_mutex);
2828
+
2757
2829
/* Set ring buffer size */
2758
2830
ring = &adev->gfx.gfx_ring[0];
2759
2831
rb_bufsz = order_base_2(ring->ring_size / 8);
···
2791
2863
WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2792
2864
2793
2865
gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2866
+
mutex_unlock(&adev->srbm_mutex);
2794
2867
2795
2868
/* Init gfx ring 1 for pipe 1 */
2796
2869
mutex_lock(&adev->srbm_mutex);
2797
2870
gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2798
-
mutex_unlock(&adev->srbm_mutex);
2799
2871
ring = &adev->gfx.gfx_ring[1];
2800
2872
rb_bufsz = order_base_2(ring->ring_size / 8);
2801
2873
tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
···
2825
2897
WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2826
2898
2827
2899
gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2900
+
mutex_unlock(&adev->srbm_mutex);
2828
2901
2829
2902
/* Switch to pipe 0 */
2830
2903
mutex_lock(&adev->srbm_mutex);
···
3704
3775
int r;
3705
3776
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3706
3777
3707
-
r = gfx_v10_0_csb_vram_pin(adev);
3708
-
if (r)
3709
-
return r;
3710
-
3711
3778
if (!amdgpu_emu_mode)
3712
3779
gfx_v10_0_init_golden_registers(adev);
3713
3780
···
3786
3861
if (amdgpu_gfx_disable_kcq(adev))
3787
3862
DRM_ERROR("KCQ disable failed\n");
3788
3863
if (amdgpu_sriov_vf(adev)) {
3789
-
pr_debug("For SRIOV client, shouldn't do anything.\n");
3864
+
gfx_v10_0_cp_gfx_enable(adev, false);
3790
3865
return 0;
3791
3866
}
3792
3867
gfx_v10_0_cp_enable(adev, false);
3793
3868
gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3794
-
gfx_v10_0_csb_vram_unpin(adev);
3795
3869
3796
3870
return 0;
3797
3871
}
+2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+1
-39
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+1
-39
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
1321
1321
return 0;
1322
1322
}
1323
1323
1324
-
static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
1325
-
{
1326
-
int r;
1327
-
1328
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1329
-
if (unlikely(r != 0))
1330
-
return r;
1331
-
1332
-
r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1333
-
AMDGPU_GEM_DOMAIN_VRAM);
1334
-
if (!r)
1335
-
adev->gfx.rlc.clear_state_gpu_addr =
1336
-
amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1337
-
1338
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1339
-
1340
-
return r;
1341
-
}
1342
-
1343
-
static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
1344
-
{
1345
-
int r;
1346
-
1347
-
if (!adev->gfx.rlc.clear_state_obj)
1348
-
return;
1349
-
1350
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1351
-
if (likely(r == 0)) {
1352
-
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1353
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1354
-
}
1355
-
}
1356
-
1357
1324
static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1358
1325
{
1359
1326
amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
···
3884
3917
3885
3918
static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3886
3919
{
3920
+
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3887
3921
/* csib */
3888
3922
WREG32(mmRLC_CSIB_ADDR_HI,
3889
3923
adev->gfx.rlc.clear_state_gpu_addr >> 32);
···
4805
4837
gfx_v8_0_init_golden_registers(adev);
4806
4838
gfx_v8_0_constants_init(adev);
4807
4839
4808
-
r = gfx_v8_0_csb_vram_pin(adev);
4809
-
if (r)
4810
-
return r;
4811
-
4812
4840
r = adev->gfx.rlc.funcs->resume(adev);
4813
4841
if (r)
4814
4842
return r;
···
4921
4957
else
4922
4958
pr_err("rlc is busy, skip halt rlc\n");
4923
4959
amdgpu_gfx_rlc_exit_safe_mode(adev);
4924
-
4925
-
gfx_v8_0_csb_vram_unpin(adev);
4926
4960
4927
4961
return 0;
4928
4962
}
+1
-39
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+1
-39
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
1695
1695
return 0;
1696
1696
}
1697
1697
1698
-
static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1699
-
{
1700
-
int r;
1701
-
1702
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1703
-
if (unlikely(r != 0))
1704
-
return r;
1705
-
1706
-
r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1707
-
AMDGPU_GEM_DOMAIN_VRAM);
1708
-
if (!r)
1709
-
adev->gfx.rlc.clear_state_gpu_addr =
1710
-
amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1711
-
1712
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1713
-
1714
-
return r;
1715
-
}
1716
-
1717
-
static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1718
-
{
1719
-
int r;
1720
-
1721
-
if (!adev->gfx.rlc.clear_state_obj)
1722
-
return;
1723
-
1724
-
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1725
-
if (likely(r == 0)) {
1726
-
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1727
-
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1728
-
}
1729
-
}
1730
-
1731
1698
static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1732
1699
{
1733
1700
amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
···
2382
2415
2383
2416
static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2384
2417
{
2418
+
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2385
2419
/* csib */
2386
2420
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2387
2421
adev->gfx.rlc.clear_state_gpu_addr >> 32);
···
3674
3706
3675
3707
gfx_v9_0_constants_init(adev);
3676
3708
3677
-
r = gfx_v9_0_csb_vram_pin(adev);
3678
-
if (r)
3679
-
return r;
3680
-
3681
3709
r = adev->gfx.rlc.funcs->resume(adev);
3682
3710
if (r)
3683
3711
return r;
···
3754
3790
3755
3791
gfx_v9_0_cp_enable(adev, false);
3756
3792
adev->gfx.rlc.funcs->stop(adev);
3757
-
3758
-
gfx_v9_0_csb_vram_unpin(adev);
3759
3793
3760
3794
return 0;
3761
3795
}
+17
-2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+17
-2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
···
33
33
u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
34
34
u32 max_region =
35
35
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
36
+
u32 max_num_physical_nodes = 0;
37
+
u32 max_physical_node_id = 0;
38
+
39
+
switch (adev->asic_type) {
40
+
case CHIP_VEGA20:
41
+
max_num_physical_nodes = 4;
42
+
max_physical_node_id = 3;
43
+
break;
44
+
case CHIP_ARCTURUS:
45
+
max_num_physical_nodes = 8;
46
+
max_physical_node_id = 7;
47
+
break;
48
+
default:
49
+
return -EINVAL;
50
+
}
36
51
37
52
/* PF_MAX_REGION=0 means xgmi is disabled */
38
53
if (max_region) {
39
54
adev->gmc.xgmi.num_physical_nodes = max_region + 1;
40
-
if (adev->gmc.xgmi.num_physical_nodes > 4)
55
+
if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
41
56
return -EINVAL;
42
57
43
58
adev->gmc.xgmi.physical_node_id =
44
59
REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
45
-
if (adev->gmc.xgmi.physical_node_id > 3)
60
+
if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
46
61
return -EINVAL;
47
62
adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
48
63
RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
+2
-1
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
···
326
326
327
327
if (!adev->mman.buffer_funcs_enabled ||
328
328
!adev->ib_pool_ready ||
329
-
adev->in_gpu_reset) {
329
+
adev->in_gpu_reset ||
330
+
ring->sched.ready == false) {
330
331
gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
331
332
mutex_unlock(&adev->mman.gtt_window_lock);
332
333
return;
+5
-2
drivers/gpu/drm/amd/amdgpu/vi.c
+5
-2
drivers/gpu/drm/amd/amdgpu/vi.c
···
783
783
{
784
784
int r;
785
785
786
-
if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
786
+
if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
787
+
if (!adev->in_suspend)
788
+
amdgpu_inc_vram_lost(adev);
787
789
r = smu7_asic_baco_reset(adev);
788
-
else
790
+
} else {
789
791
r = vi_asic_pci_config_reset(adev);
792
+
}
790
793
791
794
return r;
792
795
}
+1
-1
drivers/gpu/drm/amd/amdkfd/Kconfig
+1
-1
drivers/gpu/drm/amd/amdkfd/Kconfig
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
···
342
342
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
343
343
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
344
344
dc_to_pp_clock_type(clk_type), &pp_clks)) {
345
-
/* Error in pplib. Provide default values. */
345
+
/* Error in pplib. Provide default values. */
346
+
get_default_clock_levels(clk_type, dc_clks);
346
347
return true;
347
348
}
348
349
} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
+19
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+19
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
···
1037
1037
if (pipe->plane_state != NULL)
1038
1038
flip_immediate = pipe->plane_state->flip_immediate;
1039
1039
1040
+
if (flip_immediate && lock) {
1041
+
const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1042
+
int i;
1043
+
1044
+
for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1045
+
if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1046
+
break;
1047
+
udelay(1);
1048
+
}
1049
+
1050
+
if (pipe->bottom_pipe != NULL) {
1051
+
for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1052
+
if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1053
+
break;
1054
+
udelay(1);
1055
+
}
1056
+
}
1057
+
}
1058
+
1040
1059
/* In flip immediate and pipe splitting case, we need to use GSL
1041
1060
* for synchronization. Only do setup on locking and on flip type change.
1042
1061
*/
+74
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+74
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
···
157
157
.xfc_fill_constant_bytes = 0,
158
158
};
159
159
160
+
struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
161
+
.odm_capable = 1,
162
+
.gpuvm_enable = 0,
163
+
.hostvm_enable = 0,
164
+
.gpuvm_max_page_table_levels = 4,
165
+
.hostvm_max_page_table_levels = 4,
166
+
.hostvm_cached_page_table_levels = 0,
167
+
.num_dsc = 5,
168
+
.rob_buffer_size_kbytes = 168,
169
+
.det_buffer_size_kbytes = 164,
170
+
.dpte_buffer_size_in_pte_reqs_luma = 84,
171
+
.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
172
+
.dpp_output_buffer_pixels = 2560,
173
+
.opp_output_buffer_lines = 1,
174
+
.pixel_chunk_size_kbytes = 8,
175
+
.pte_enable = 1,
176
+
.max_page_table_levels = 4,
177
+
.pte_chunk_size_kbytes = 2,
178
+
.meta_chunk_size_kbytes = 2,
179
+
.writeback_chunk_size_kbytes = 2,
180
+
.line_buffer_size_bits = 789504,
181
+
.is_line_buffer_bpp_fixed = 0,
182
+
.line_buffer_fixed_bpp = 0,
183
+
.dcc_supported = true,
184
+
.max_line_buffer_lines = 12,
185
+
.writeback_luma_buffer_size_kbytes = 12,
186
+
.writeback_chroma_buffer_size_kbytes = 8,
187
+
.writeback_chroma_line_buffer_width_pixels = 4,
188
+
.writeback_max_hscl_ratio = 1,
189
+
.writeback_max_vscl_ratio = 1,
190
+
.writeback_min_hscl_ratio = 1,
191
+
.writeback_min_vscl_ratio = 1,
192
+
.writeback_max_hscl_taps = 12,
193
+
.writeback_max_vscl_taps = 12,
194
+
.writeback_line_buffer_luma_buffer_size = 0,
195
+
.writeback_line_buffer_chroma_buffer_size = 14643,
196
+
.cursor_buffer_size = 8,
197
+
.cursor_chunk_size = 2,
198
+
.max_num_otg = 5,
199
+
.max_num_dpp = 5,
200
+
.max_num_wb = 1,
201
+
.max_dchub_pscl_bw_pix_per_clk = 4,
202
+
.max_pscl_lb_bw_pix_per_clk = 2,
203
+
.max_lb_vscl_bw_pix_per_clk = 4,
204
+
.max_vscl_hscl_bw_pix_per_clk = 4,
205
+
.max_hscl_ratio = 8,
206
+
.max_vscl_ratio = 8,
207
+
.hscl_mults = 4,
208
+
.vscl_mults = 4,
209
+
.max_hscl_taps = 8,
210
+
.max_vscl_taps = 8,
211
+
.dispclk_ramp_margin_percent = 1,
212
+
.underscan_factor = 1.10,
213
+
.min_vblank_lines = 32, //
214
+
.dppclk_delay_subtotal = 77, //
215
+
.dppclk_delay_scl_lb_only = 16,
216
+
.dppclk_delay_scl = 50,
217
+
.dppclk_delay_cnvc_formatter = 8,
218
+
.dppclk_delay_cnvc_cursor = 6,
219
+
.dispclk_delay_subtotal = 87, //
220
+
.dcfclk_cstate_latency = 10, // SRExitTime
221
+
.max_inter_dcn_tile_repeaters = 8,
222
+
.xfc_supported = true,
223
+
.xfc_fill_bw_overhead_percent = 10.0,
224
+
.xfc_fill_constant_bytes = 0,
225
+
.ptoi_supported = 0
226
+
};
227
+
160
228
struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
161
229
/* Defaults that get patched on driver load from firmware. */
162
230
.clock_limits = {
···
922
854
.num_pll = 5,
923
855
.num_dwb = 1,
924
856
.num_ddc = 5,
857
+
.num_vmid = 16,
858
+
.num_dsc = 5,
925
859
};
926
860
927
861
static const struct dc_debug_options debug_defaults_drv = {
···
3282
3212
static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3283
3213
uint32_t hw_internal_rev)
3284
3214
{
3215
+
/* NV14 */
3216
+
if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3217
+
return &dcn2_0_nv14_ip;
3218
+
3285
3219
/* NV12 and NV10 */
3286
3220
return &dcn2_0_ip;
3287
3221
}
+9
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+9
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
-1
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
-1
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
···
2130
2130
.set_tool_table_location = smu_v11_0_set_tool_table_location,
2131
2131
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2132
2132
.system_features_control = smu_v11_0_system_features_control,
2133
-
.send_smc_msg = smu_v11_0_send_msg,
2134
2133
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2135
2134
.read_smc_arg = smu_v11_0_read_arg,
2136
2135
.init_display_count = smu_v11_0_init_display_count,
+2
-2
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+2
-2
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
···
497
497
int (*notify_memory_pool_location)(struct smu_context *smu);
498
498
int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
499
499
int (*system_features_control)(struct smu_context *smu, bool en);
500
-
int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
501
-
int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
500
+
int (*send_smc_msg_with_param)(struct smu_context *smu,
501
+
enum smu_message_type msg, uint32_t param);
502
502
int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
503
503
int (*init_display_count)(struct smu_context *smu, uint32_t count);
504
504
int (*set_allowed_mask)(struct smu_context *smu);
+2
-3
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+2
-3
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
···
177
177
int smu_v11_0_system_features_control(struct smu_context *smu,
178
178
bool en);
179
179
180
-
int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg);
181
-
182
180
int
183
-
smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
181
+
smu_v11_0_send_msg_with_param(struct smu_context *smu,
182
+
enum smu_message_type msg,
184
183
uint32_t param);
185
184
186
185
int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg);
+2
-3
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+2
-3
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
···
44
44
45
45
int smu_v12_0_wait_for_response(struct smu_context *smu);
46
46
47
-
int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg);
48
-
49
47
int
50
-
smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
48
+
smu_v12_0_send_msg_with_param(struct smu_context *smu,
49
+
enum smu_message_type msg,
51
50
uint32_t param);
52
51
53
52
int smu_v12_0_check_fw_status(struct smu_context *smu);
-1
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
-1
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
···
697
697
.check_fw_version = smu_v12_0_check_fw_version,
698
698
.powergate_sdma = smu_v12_0_powergate_sdma,
699
699
.powergate_vcn = smu_v12_0_powergate_vcn,
700
-
.send_smc_msg = smu_v12_0_send_msg,
701
700
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
702
701
.read_smc_arg = smu_v12_0_read_arg,
703
702
.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
+2
-2
drivers/gpu/drm/amd/powerplay/smu_internal.h
+2
-2
drivers/gpu/drm/amd/powerplay/smu_internal.h
···
75
75
#define smu_set_default_od_settings(smu, initialize) \
76
76
((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0)
77
77
78
-
#define smu_send_smc_msg(smu, msg) \
79
-
((smu)->ppt_funcs->send_smc_msg? (smu)->ppt_funcs->send_smc_msg((smu), (msg)) : 0)
78
+
int smu_send_smc_msg(struct smu_context *smu, enum smu_message_type msg);
79
+
80
80
#define smu_send_smc_msg_with_param(smu, msg, param) \
81
81
((smu)->ppt_funcs->send_smc_msg_with_param? (smu)->ppt_funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
82
82
#define smu_read_smc_arg(smu, arg) \
+2
-27
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+2
-27
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
···
90
90
return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
91
91
}
92
92
93
-
int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
94
-
{
95
-
struct amdgpu_device *adev = smu->adev;
96
-
int ret = 0, index = 0;
97
-
98
-
index = smu_msg_get_index(smu, msg);
99
-
if (index < 0)
100
-
return index;
101
-
102
-
smu_v11_0_wait_for_response(smu);
103
-
104
-
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
105
-
106
-
smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
107
-
108
-
ret = smu_v11_0_wait_for_response(smu);
109
-
110
-
if (ret)
111
-
pr_err("failed send message: %10s (%d) response %#x\n",
112
-
smu_get_message_name(smu, msg), index, ret);
113
-
114
-
return ret;
115
-
116
-
}
117
-
118
93
int
119
-
smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
94
+
smu_v11_0_send_msg_with_param(struct smu_context *smu,
95
+
enum smu_message_type msg,
120
96
uint32_t param)
121
97
{
122
-
123
98
struct amdgpu_device *adev = smu->adev;
124
99
int ret = 0, index = 0;
125
100
+2
-26
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+2
-26
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
···
77
77
return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
78
78
}
79
79
80
-
int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
81
-
{
82
-
struct amdgpu_device *adev = smu->adev;
83
-
int ret = 0, index = 0;
84
-
85
-
index = smu_msg_get_index(smu, msg);
86
-
if (index < 0)
87
-
return index;
88
-
89
-
smu_v12_0_wait_for_response(smu);
90
-
91
-
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
92
-
93
-
smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
94
-
95
-
ret = smu_v12_0_wait_for_response(smu);
96
-
97
-
if (ret)
98
-
pr_err("Failed to send message 0x%x, response 0x%x\n", index,
99
-
ret);
100
-
101
-
return ret;
102
-
103
-
}
104
-
105
80
int
106
-
smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
81
+
smu_v12_0_send_msg_with_param(struct smu_context *smu,
82
+
enum smu_message_type msg,
107
83
uint32_t param)
108
84
{
109
85
struct amdgpu_device *adev = smu->adev;
-1
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
-1
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
···
3231
3231
.set_tool_table_location = smu_v11_0_set_tool_table_location,
3232
3232
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3233
3233
.system_features_control = smu_v11_0_system_features_control,
3234
-
.send_smc_msg = smu_v11_0_send_msg,
3235
3234
.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
3236
3235
.read_smc_arg = smu_v11_0_read_arg,
3237
3236
.init_display_count = smu_v11_0_init_display_count,
+2
-2
drivers/gpu/drm/radeon/r100.c
+2
-2
drivers/gpu/drm/radeon/r100.c
···
1826
1826
track->textures[i].use_pitch = 1;
1827
1827
} else {
1828
1828
track->textures[i].use_pitch = 0;
1829
-
track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1830
-
track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1829
+
track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1830
+
track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1831
1831
}
1832
1832
if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1833
1833
track->textures[i].tex_coord_type = 2;
+2
-2
drivers/gpu/drm/radeon/r200.c
+2
-2
drivers/gpu/drm/radeon/r200.c
···
476
476
track->textures[i].use_pitch = 1;
477
477
} else {
478
478
track->textures[i].use_pitch = 0;
479
-
track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
480
-
track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
479
+
track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
480
+
track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
481
481
}
482
482
if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
483
483
track->textures[i].lookup_disable = true;