Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New hardware support:
- Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS
PHY and SDM630 USBC support
- Rockchip HDMI/eDP Combo PHY driver
- Mediatek MT8365 CSI phy driver
Updates:
- Rework on Qualcomm phy PCS registers and type-c handling
- Cadence torrent phy updates for multilink configuration
- TI gmii resume support"
* tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
phy: constify of_phandle_args in xlate
phy: ti: tusb1210: Define device IDs
phy: ti: tusb1210: Use temporary variable for struct device
phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver
dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
phy: ti: gmii-sel: add resume support
phy: mtk-mipi-csi: add driver for CSI phy
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200
dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration
phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API
dt-bindings: phy: qmp-ufs: Fix PHY clocks
phy: qcom: sgmii-eth: move PCS registers to separate header
phy: qcom: sgmii-eth: use existing register definitions
phy: qcom: qmp-usbc: drop has_pwrdn_delay handling
phy: qcom: qmp: move common bits definitions to common header
phy: qcom: qmp: split DP PHY registers to separate headers
...
+4636
-1321
+79
Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
+79
Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright (c) 2023 MediaTek, BayLibre
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Mediatek Sensor Interface MIPI CSI CD-PHY
9
+
10
+
maintainers:
11
+
- Julien Stephan <jstephan@baylibre.com>
12
+
- Andy Hsieh <andy.hsieh@mediatek.com>
13
+
14
+
description:
15
+
The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
16
+
receivers. The number of PHYs depends on the SoC model.
17
+
Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
18
+
capable.
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- mediatek,mt8365-csi-rx
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
num-lanes:
29
+
enum: [2, 3, 4]
30
+
31
+
'#phy-cells':
32
+
enum: [0, 1]
33
+
description: |
34
+
If the PHY doesn't support mode selection then #phy-cells must be 0 and
35
+
PHY mode is described using phy-type property.
36
+
If the PHY supports mode selection, then #phy-cells must be 1 and mode
37
+
is set in the PHY cells. Supported modes are:
38
+
- PHY_TYPE_DPHY
39
+
- PHY_TYPE_CPHY
40
+
See include/dt-bindings/phy/phy.h for constants.
41
+
42
+
phy-type:
43
+
description:
44
+
If the PHY doesn't support mode selection then this set the operating mode.
45
+
See include/dt-bindings/phy/phy.h for constants.
46
+
const: 10
47
+
$ref: /schemas/types.yaml#/definitions/uint32
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- num-lanes
53
+
- '#phy-cells'
54
+
55
+
additionalProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/phy/phy.h>
60
+
soc {
61
+
#address-cells = <2>;
62
+
#size-cells = <2>;
63
+
64
+
csi0_rx: phy@11c10000 {
65
+
compatible = "mediatek,mt8365-csi-rx";
66
+
reg = <0 0x11c10000 0 0x2000>;
67
+
num-lanes = <2>;
68
+
#phy-cells = <1>;
69
+
};
70
+
71
+
csi1_rx: phy@11c12000 {
72
+
compatible = "mediatek,mt8365-csi-rx";
73
+
reg = <0 0x11c12000 0 0x2000>;
74
+
phy-type = <PHY_TYPE_DPHY>;
75
+
num-lanes = <2>;
76
+
#phy-cells = <0>;
77
+
};
78
+
};
79
+
...
+8
-3
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+8
-3
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
···
20
20
compatible:
21
21
enum:
22
22
- cdns,torrent-phy
23
+
- ti,j7200-serdes-10g
23
24
- ti,j721e-serdes-10g
24
25
25
26
'#address-cells':
···
36
35
minItems: 1
37
36
maxItems: 2
38
37
description:
39
-
PHY reference clock for 1 item. Must contain an entry in clock-names.
40
-
Optional Parent to enable output reference clock.
38
+
PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
39
+
pll1_refclk is optional and used for multi-protocol configurations requiring
40
+
separate reference clock for each protocol.
41
+
Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
42
+
Optional parent clock (phy_en_refclk) to enable a reference clock output feature
43
+
on some platforms to output either derived or received reference clock.
41
44
42
45
clock-names:
43
46
minItems: 1
44
47
items:
45
48
- const: refclk
46
-
- const: phy_en_refclk
49
+
- enum: [ pll1_refclk, phy_en_refclk ]
47
50
48
51
reg:
49
52
minItems: 1
+184
Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
+184
Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm QMP PHY controller (USB, MSM8998)
8
+
9
+
maintainers:
10
+
- Vinod Koul <vkoul@kernel.org>
11
+
12
+
description:
13
+
The QMP PHY controller supports physical layer functionality for USB-C on
14
+
several Qualcomm chipsets.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,msm8998-qmp-usb3-phy
20
+
- qcom,qcm2290-qmp-usb3-phy
21
+
- qcom,sdm660-qmp-usb3-phy
22
+
- qcom,sm6115-qmp-usb3-phy
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
clocks:
28
+
maxItems: 4
29
+
30
+
clock-names:
31
+
maxItems: 4
32
+
33
+
resets:
34
+
maxItems: 2
35
+
36
+
reset-names:
37
+
items:
38
+
- const: phy
39
+
- const: phy_phy
40
+
41
+
vdda-phy-supply: true
42
+
43
+
vdda-pll-supply: true
44
+
45
+
"#clock-cells":
46
+
const: 0
47
+
48
+
clock-output-names:
49
+
maxItems: 1
50
+
51
+
"#phy-cells":
52
+
const: 0
53
+
54
+
orientation-switch:
55
+
description:
56
+
Flag the PHY as possible handler of USB Type-C orientation switching
57
+
type: boolean
58
+
59
+
qcom,tcsr-reg:
60
+
$ref: /schemas/types.yaml#/definitions/phandle-array
61
+
items:
62
+
- items:
63
+
- description: phandle to TCSR hardware block
64
+
- description: offset of the VLS CLAMP register
65
+
description: Clamp register present in the TCSR
66
+
67
+
ports:
68
+
$ref: /schemas/graph.yaml#/properties/ports
69
+
properties:
70
+
port@0:
71
+
$ref: /schemas/graph.yaml#/properties/port
72
+
description: Output endpoint of the PHY
73
+
74
+
port@1:
75
+
$ref: /schemas/graph.yaml#/properties/port
76
+
description: Incoming endpoint from the USB controller
77
+
78
+
required:
79
+
- compatible
80
+
- reg
81
+
- clocks
82
+
- clock-names
83
+
- resets
84
+
- reset-names
85
+
- vdda-phy-supply
86
+
- vdda-pll-supply
87
+
- "#clock-cells"
88
+
- clock-output-names
89
+
- "#phy-cells"
90
+
- qcom,tcsr-reg
91
+
92
+
allOf:
93
+
- if:
94
+
properties:
95
+
compatible:
96
+
contains:
97
+
enum:
98
+
- qcom,msm8998-qmp-usb3-phy
99
+
- qcom,sdm660-qmp-usb3-phy
100
+
then:
101
+
properties:
102
+
clocks:
103
+
maxItems: 4
104
+
clock-names:
105
+
items:
106
+
- const: aux
107
+
- const: ref
108
+
- const: cfg_ahb
109
+
- const: pipe
110
+
111
+
- if:
112
+
properties:
113
+
compatible:
114
+
contains:
115
+
enum:
116
+
- qcom,qcm2290-qmp-usb3-phy
117
+
- qcom,sm6115-qmp-usb3-phy
118
+
then:
119
+
properties:
120
+
clocks:
121
+
maxItems: 4
122
+
clock-names:
123
+
items:
124
+
- const: cfg_ahb
125
+
- const: ref
126
+
- const: com_aux
127
+
- const: pipe
128
+
129
+
additionalProperties: false
130
+
131
+
examples:
132
+
- |
133
+
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
134
+
#include <dt-bindings/clock/qcom,rpmh.h>
135
+
136
+
phy@c010000 {
137
+
compatible = "qcom,msm8998-qmp-usb3-phy";
138
+
reg = <0x0c010000 0x1000>;
139
+
140
+
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
141
+
<&gcc GCC_USB3_CLKREF_CLK>,
142
+
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
143
+
<&gcc GCC_USB3_PHY_PIPE_CLK>;
144
+
clock-names = "aux",
145
+
"ref",
146
+
"cfg_ahb",
147
+
"pipe";
148
+
clock-output-names = "usb3_phy_pipe_clk_src";
149
+
#clock-cells = <0>;
150
+
#phy-cells = <0>;
151
+
152
+
resets = <&gcc GCC_USB3_PHY_BCR>,
153
+
<&gcc GCC_USB3PHY_PHY_BCR>;
154
+
reset-names = "phy",
155
+
"phy_phy";
156
+
157
+
vdda-phy-supply = <&vreg_l1a_0p875>;
158
+
vdda-pll-supply = <&vreg_l2a_1p2>;
159
+
160
+
orientation-switch;
161
+
162
+
qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
163
+
164
+
ports {
165
+
#address-cells = <1>;
166
+
#size-cells = <0>;
167
+
168
+
port@0 {
169
+
reg = <0>;
170
+
171
+
endpoint {
172
+
remote-endpoint = <&pmic_typec_mux_in>;
173
+
};
174
+
};
175
+
176
+
port@1 {
177
+
reg = <1>;
178
+
179
+
endpoint {
180
+
remote-endpoint = <&usb_dwc3_ss>;
181
+
};
182
+
};
183
+
};
184
+
};
+6
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+6
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
···
38
38
- qcom,sm8550-qmp-gen4x2-pcie-phy
39
39
- qcom,sm8650-qmp-gen3x2-pcie-phy
40
40
- qcom,sm8650-qmp-gen4x2-pcie-phy
41
+
- qcom,x1e80100-qmp-gen3x2-pcie-phy
42
+
- qcom,x1e80100-qmp-gen4x2-pcie-phy
41
43
42
44
reg:
43
45
minItems: 1
···
153
151
- qcom,sm8550-qmp-gen4x2-pcie-phy
154
152
- qcom,sm8650-qmp-gen3x2-pcie-phy
155
153
- qcom,sm8650-qmp-gen4x2-pcie-phy
154
+
- qcom,x1e80100-qmp-gen3x2-pcie-phy
155
+
- qcom,x1e80100-qmp-gen4x2-pcie-phy
156
156
then:
157
157
properties:
158
158
clocks:
···
198
194
enum:
199
195
- qcom,sm8550-qmp-gen4x2-pcie-phy
200
196
- qcom,sm8650-qmp-gen4x2-pcie-phy
197
+
- qcom,x1e80100-qmp-gen3x2-pcie-phy
198
+
- qcom,x1e80100-qmp-gen4x2-pcie-phy
201
199
then:
202
200
properties:
203
201
resets:
+22
-26
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+22
-26
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
···
19
19
- qcom,msm8996-qmp-ufs-phy
20
20
- qcom,msm8998-qmp-ufs-phy
21
21
- qcom,sa8775p-qmp-ufs-phy
22
+
- qcom,sc7180-qmp-ufs-phy
22
23
- qcom,sc7280-qmp-ufs-phy
23
24
- qcom,sc8180x-qmp-ufs-phy
24
25
- qcom,sc8280xp-qmp-ufs-phy
···
39
38
maxItems: 1
40
39
41
40
clocks:
42
-
minItems: 1
41
+
minItems: 2
43
42
maxItems: 3
44
43
45
44
clock-names:
46
-
minItems: 1
47
-
items:
48
-
- const: ref
49
-
- const: ref_aux
50
-
- const: qref
45
+
minItems: 2
46
+
maxItems: 3
51
47
52
48
power-domains:
53
49
maxItems: 1
···
84
86
compatible:
85
87
contains:
86
88
enum:
89
+
- qcom,msm8998-qmp-ufs-phy
87
90
- qcom,sa8775p-qmp-ufs-phy
88
91
- qcom,sc7280-qmp-ufs-phy
89
-
- qcom,sm8450-qmp-ufs-phy
90
-
then:
91
-
properties:
92
-
clocks:
93
-
minItems: 3
94
-
clock-names:
95
-
minItems: 3
96
-
97
-
- if:
98
-
properties:
99
-
compatible:
100
-
contains:
101
-
enum:
102
-
- qcom,msm8998-qmp-ufs-phy
103
92
- qcom,sc8180x-qmp-ufs-phy
104
93
- qcom,sc8280xp-qmp-ufs-phy
105
94
- qcom,sdm845-qmp-ufs-phy
···
97
112
- qcom,sm8150-qmp-ufs-phy
98
113
- qcom,sm8250-qmp-ufs-phy
99
114
- qcom,sm8350-qmp-ufs-phy
115
+
- qcom,sm8450-qmp-ufs-phy
100
116
- qcom,sm8550-qmp-ufs-phy
101
117
- qcom,sm8650-qmp-ufs-phy
102
118
then:
103
119
properties:
104
120
clocks:
105
-
maxItems: 2
121
+
minItems: 3
122
+
maxItems: 3
106
123
clock-names:
107
-
maxItems: 2
124
+
items:
125
+
- const: ref
126
+
- const: ref_aux
127
+
- const: qref
108
128
109
129
- if:
110
130
properties:
···
120
130
then:
121
131
properties:
122
132
clocks:
123
-
maxItems: 1
133
+
minItems: 2
134
+
maxItems: 2
124
135
clock-names:
125
-
maxItems: 1
136
+
items:
137
+
- const: ref
138
+
- const: qref
126
139
127
140
additionalProperties: false
128
141
129
142
examples:
130
143
- |
131
144
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
145
+
#include <dt-bindings/clock/qcom,rpmh.h>
132
146
133
147
ufs_mem_phy: phy@1d87000 {
134
148
compatible = "qcom,sc8280xp-qmp-ufs-phy";
135
149
reg = <0x01d87000 0x1000>;
136
150
137
-
clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
138
-
clock-names = "ref", "ref_aux";
151
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
152
+
<&gcc GCC_UFS_REF_CLKREF_CLK>;
153
+
154
+
clock-names = "ref", "ref_aux", "qref";
139
155
140
156
power-domains = <&gcc UFS_PHY_GDSC>;
141
157
-22
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
-22
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
···
20
20
- qcom,ipq8074-qmp-usb3-phy
21
21
- qcom,ipq9574-qmp-usb3-phy
22
22
- qcom,msm8996-qmp-usb3-phy
23
-
- qcom,msm8998-qmp-usb3-phy
24
-
- qcom,qcm2290-qmp-usb3-phy
25
23
- qcom,sa8775p-qmp-usb3-uni-phy
26
24
- qcom,sc8280xp-qmp-usb3-uni-phy
27
25
- qcom,sdm845-qmp-usb3-uni-phy
28
26
- qcom,sdx55-qmp-usb3-uni-phy
29
27
- qcom,sdx65-qmp-usb3-uni-phy
30
28
- qcom,sdx75-qmp-usb3-uni-phy
31
-
- qcom,sm6115-qmp-usb3-phy
32
29
- qcom,sm8150-qmp-usb3-uni-phy
33
30
- qcom,sm8250-qmp-usb3-uni-phy
34
31
- qcom,sm8350-qmp-usb3-uni-phy
···
90
93
- qcom,ipq8074-qmp-usb3-phy
91
94
- qcom,ipq9574-qmp-usb3-phy
92
95
- qcom,msm8996-qmp-usb3-phy
93
-
- qcom,msm8998-qmp-usb3-phy
94
96
- qcom,sdx55-qmp-usb3-uni-phy
95
97
- qcom,sdx65-qmp-usb3-uni-phy
96
98
- qcom,sdx75-qmp-usb3-uni-phy
···
102
106
- const: aux
103
107
- const: ref
104
108
- const: cfg_ahb
105
-
- const: pipe
106
-
107
-
- if:
108
-
properties:
109
-
compatible:
110
-
contains:
111
-
enum:
112
-
- qcom,qcm2290-qmp-usb3-phy
113
-
- qcom,sm6115-qmp-usb3-phy
114
-
then:
115
-
properties:
116
-
clocks:
117
-
maxItems: 4
118
-
clock-names:
119
-
items:
120
-
- const: cfg_ahb
121
-
- const: ref
122
-
- const: com_aux
123
109
- const: pipe
124
110
125
111
- if:
+91
Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
+91
Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
8
+
9
+
maintainers:
10
+
- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- rockchip,rk3588-hdptx-phy
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
clocks:
21
+
items:
22
+
- description: Reference clock
23
+
- description: APB clock
24
+
25
+
clock-names:
26
+
items:
27
+
- const: ref
28
+
- const: apb
29
+
30
+
"#phy-cells":
31
+
const: 0
32
+
33
+
resets:
34
+
items:
35
+
- description: PHY reset line
36
+
- description: APB reset line
37
+
- description: INIT reset line
38
+
- description: CMN reset line
39
+
- description: LANE reset line
40
+
- description: ROPLL reset line
41
+
- description: LCPLL reset line
42
+
43
+
reset-names:
44
+
items:
45
+
- const: phy
46
+
- const: apb
47
+
- const: init
48
+
- const: cmn
49
+
- const: lane
50
+
- const: ropll
51
+
- const: lcpll
52
+
53
+
rockchip,grf:
54
+
$ref: /schemas/types.yaml#/definitions/phandle
55
+
description: Some PHY related data is accessed through GRF regs.
56
+
57
+
required:
58
+
- compatible
59
+
- reg
60
+
- clocks
61
+
- clock-names
62
+
- "#phy-cells"
63
+
- resets
64
+
- reset-names
65
+
- rockchip,grf
66
+
67
+
additionalProperties: false
68
+
69
+
examples:
70
+
- |
71
+
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
72
+
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
73
+
74
+
soc {
75
+
#address-cells = <2>;
76
+
#size-cells = <2>;
77
+
78
+
phy@fed60000 {
79
+
compatible = "rockchip,rk3588-hdptx-phy";
80
+
reg = <0x0 0xfed60000 0x0 0x2000>;
81
+
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
82
+
clock-names = "ref", "apb";
83
+
#phy-cells = <0>;
84
+
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
85
+
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
86
+
<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
87
+
<&cru SRST_HDPTX0_LCPLL>;
88
+
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
89
+
rockchip,grf = <&hdptxphy_grf>;
90
+
};
91
+
};
+7
MAINTAINERS
+7
MAINTAINERS
···
13800
13800
F: drivers/media/platform/mediatek/vcodec/
13801
13801
F: drivers/media/platform/mediatek/vpu/
13802
13802
13803
+
MEDIATEK MIPI-CSI CDPHY DRIVER
13804
+
M: Julien Stephan <jstephan@baylibre.com>
13805
+
M: Andy Hsieh <andy.hsieh@mediatek.com>
13806
+
S: Supported
13807
+
F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
13808
+
F: drivers/phy/mediatek/phy-mtk-mipi-csi-0-5*
13809
+
13803
13810
MEDIATEK MMC/SD/SDIO DRIVER
13804
13811
M: Chaotian Jing <chaotian.jing@mediatek.com>
13805
13812
S: Maintained
+1
-1
drivers/phy/allwinner/phy-sun4i-usb.c
+1
-1
drivers/phy/allwinner/phy-sun4i-usb.c
+1
-1
drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
+1
-1
drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
+1
-1
drivers/phy/broadcom/phy-bcm-sr-pcie.c
+1
-1
drivers/phy/broadcom/phy-bcm-sr-pcie.c
+1
-1
drivers/phy/broadcom/phy-bcm-sr-usb.c
+1
-1
drivers/phy/broadcom/phy-bcm-sr-usb.c
+1
-1
drivers/phy/broadcom/phy-bcm63xx-usbh.c
+1
-1
drivers/phy/broadcom/phy-bcm63xx-usbh.c
+1
-1
drivers/phy/broadcom/phy-brcm-usb.c
+1
-1
drivers/phy/broadcom/phy-brcm-usb.c
+711
-9
drivers/phy/cadence/phy-cadence-torrent.c
+711
-9
drivers/phy/cadence/phy-cadence-torrent.c
···
355
355
struct reset_control *apb_rst;
356
356
struct device *dev;
357
357
struct clk *clk;
358
+
struct clk *clk1;
358
359
enum cdns_torrent_ref_clk ref_clk_rate;
360
+
enum cdns_torrent_ref_clk ref_clk1_rate;
359
361
struct cdns_torrent_inst phys[MAX_NUM_LANES];
360
362
int nsubnodes;
361
363
const struct cdns_torrent_data *init_data;
···
2462
2460
{
2463
2461
const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2464
2462
struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2463
+
enum cdns_torrent_ref_clk ref_clk1 = cdns_phy->ref_clk1_rate;
2465
2464
enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2466
2465
struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2467
2466
enum cdns_torrent_phy_type phy_t1, phy_t2;
2467
+
struct cdns_torrent_vals *phy_pma_cmn_vals;
2468
2468
struct cdns_torrent_vals *pcs_cmn_vals;
2469
2469
int i, j, node, mlane, num_lanes, ret;
2470
2470
struct cdns_reg_pairs *reg_pairs;
···
2493
2489
* Get the array values as [phy_t2][phy_t1][ssc].
2494
2490
*/
2495
2491
swap(phy_t1, phy_t2);
2492
+
swap(ref_clk, ref_clk1);
2496
2493
}
2497
2494
2498
2495
mlane = cdns_phy->phys[node].mlane;
···
2557
2552
reg_pairs[i].val);
2558
2553
}
2559
2554
2555
+
/* PHY PMA common registers configurations */
2556
+
phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,
2557
+
CLK_ANY, CLK_ANY,
2558
+
phy_t1, phy_t2, ANY_SSC);
2559
+
if (phy_pma_cmn_vals) {
2560
+
reg_pairs = phy_pma_cmn_vals->reg_pairs;
2561
+
num_regs = phy_pma_cmn_vals->num_regs;
2562
+
regmap = cdns_phy->regmap_phy_pma_common_cdb;
2563
+
for (i = 0; i < num_regs; i++)
2564
+
regmap_write(regmap, reg_pairs[i].off,
2565
+
reg_pairs[i].val);
2566
+
}
2567
+
2560
2568
/* PMA common registers configurations */
2561
2569
cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,
2562
-
ref_clk, ref_clk,
2570
+
ref_clk, ref_clk1,
2563
2571
phy_t1, phy_t2, ssc);
2564
2572
if (cmn_vals) {
2565
2573
reg_pairs = cmn_vals->reg_pairs;
···
2585
2567
2586
2568
/* PMA TX lane registers configurations */
2587
2569
tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,
2588
-
ref_clk, ref_clk,
2570
+
ref_clk, ref_clk1,
2589
2571
phy_t1, phy_t2, ssc);
2590
2572
if (tx_ln_vals) {
2591
2573
reg_pairs = tx_ln_vals->reg_pairs;
···
2600
2582
2601
2583
/* PMA RX lane registers configurations */
2602
2584
rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,
2603
-
ref_clk, ref_clk,
2585
+
ref_clk, ref_clk1,
2604
2586
phy_t1, phy_t2, ssc);
2605
2587
if (rx_ln_vals) {
2606
2588
reg_pairs = rx_ln_vals->reg_pairs;
···
2702
2684
static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2703
2685
{
2704
2686
struct device *dev = cdns_phy->dev;
2687
+
unsigned long ref_clk1_rate;
2705
2688
unsigned long ref_clk_rate;
2706
2689
int ret;
2707
2690
2691
+
/* refclk: Input reference clock for PLL0 */
2708
2692
cdns_phy->clk = devm_clk_get(dev, "refclk");
2709
2693
if (IS_ERR(cdns_phy->clk)) {
2710
2694
dev_err(dev, "phy ref clock not found\n");
···
2715
2695
2716
2696
ret = clk_prepare_enable(cdns_phy->clk);
2717
2697
if (ret) {
2718
-
dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2698
+
dev_err(cdns_phy->dev, "Failed to prepare ref clock: %d\n", ret);
2719
2699
return ret;
2720
2700
}
2721
2701
2722
2702
ref_clk_rate = clk_get_rate(cdns_phy->clk);
2723
2703
if (!ref_clk_rate) {
2724
2704
dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2725
-
clk_disable_unprepare(cdns_phy->clk);
2726
-
return -EINVAL;
2705
+
ret = -EINVAL;
2706
+
goto disable_clk;
2727
2707
}
2728
2708
2729
2709
switch (ref_clk_rate) {
···
2740
2720
cdns_phy->ref_clk_rate = CLK_156_25_MHZ;
2741
2721
break;
2742
2722
default:
2743
-
dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2744
-
clk_disable_unprepare(cdns_phy->clk);
2745
-
return -EINVAL;
2723
+
dev_err(cdns_phy->dev, "Invalid ref clock rate\n");
2724
+
ret = -EINVAL;
2725
+
goto disable_clk;
2726
+
}
2727
+
2728
+
/* refclk1: Input reference clock for PLL1 */
2729
+
cdns_phy->clk1 = devm_clk_get_optional(dev, "pll1_refclk");
2730
+
if (IS_ERR(cdns_phy->clk1)) {
2731
+
dev_err(dev, "phy PLL1 ref clock not found\n");
2732
+
ret = PTR_ERR(cdns_phy->clk1);
2733
+
goto disable_clk;
2734
+
}
2735
+
2736
+
if (cdns_phy->clk1) {
2737
+
ret = clk_prepare_enable(cdns_phy->clk1);
2738
+
if (ret) {
2739
+
dev_err(cdns_phy->dev, "Failed to prepare PLL1 ref clock: %d\n", ret);
2740
+
goto disable_clk;
2741
+
}
2742
+
2743
+
ref_clk1_rate = clk_get_rate(cdns_phy->clk1);
2744
+
if (!ref_clk1_rate) {
2745
+
dev_err(cdns_phy->dev, "Failed to get PLL1 ref clock rate\n");
2746
+
ret = -EINVAL;
2747
+
goto disable_clk1;
2748
+
}
2749
+
2750
+
switch (ref_clk1_rate) {
2751
+
case REF_CLK_19_2MHZ:
2752
+
cdns_phy->ref_clk1_rate = CLK_19_2_MHZ;
2753
+
break;
2754
+
case REF_CLK_25MHZ:
2755
+
cdns_phy->ref_clk1_rate = CLK_25_MHZ;
2756
+
break;
2757
+
case REF_CLK_100MHZ:
2758
+
cdns_phy->ref_clk1_rate = CLK_100_MHZ;
2759
+
break;
2760
+
case REF_CLK_156_25MHZ:
2761
+
cdns_phy->ref_clk1_rate = CLK_156_25_MHZ;
2762
+
break;
2763
+
default:
2764
+
dev_err(cdns_phy->dev, "Invalid PLL1 ref clock rate\n");
2765
+
ret = -EINVAL;
2766
+
goto disable_clk1;
2767
+
}
2768
+
} else {
2769
+
cdns_phy->ref_clk1_rate = cdns_phy->ref_clk_rate;
2746
2770
}
2747
2771
2748
2772
return 0;
2773
+
2774
+
disable_clk1:
2775
+
clk_disable_unprepare(cdns_phy->clk1);
2776
+
disable_clk:
2777
+
clk_disable_unprepare(cdns_phy->clk);
2778
+
return ret;
2749
2779
}
2750
2780
2751
2781
static int cdns_torrent_phy_probe(struct platform_device *pdev)
···
3050
2980
reset_control_put(cdns_phy->phys[i].lnk_rst);
3051
2981
of_node_put(child);
3052
2982
reset_control_assert(cdns_phy->apb_rst);
2983
+
clk_disable_unprepare(cdns_phy->clk1);
3053
2984
clk_disable_unprepare(cdns_phy->clk);
3054
2985
clk_cleanup:
3055
2986
cdns_torrent_clk_cleanup(cdns_phy);
···
3069
2998
reset_control_put(cdns_phy->phys[i].lnk_rst);
3070
2999
}
3071
3000
3001
+
clk_disable_unprepare(cdns_phy->clk1);
3072
3002
clk_disable_unprepare(cdns_phy->clk);
3073
3003
cdns_torrent_clk_cleanup(cdns_phy);
3074
3004
}
···
3104
3032
static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {
3105
3033
.reg_pairs = dp_usb_xcvr_diag_ln_regs,
3106
3034
.num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),
3035
+
};
3036
+
3037
+
/* USXGMII and SGMII/QSGMII link configuration */
3038
+
static struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = {
3039
+
{0x0002, PHY_PLL_CFG},
3040
+
{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0},
3041
+
{0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3042
+
};
3043
+
3044
+
static struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = {
3045
+
{0x0000, XCVR_DIAG_HSCLK_SEL},
3046
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3047
+
{0x0001, XCVR_DIAG_PLLDRC_CTRL}
3048
+
};
3049
+
3050
+
static struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = {
3051
+
{0x0111, XCVR_DIAG_HSCLK_SEL},
3052
+
{0x0103, XCVR_DIAG_HSCLK_DIV},
3053
+
{0x0A9B, XCVR_DIAG_PLLDRC_CTRL}
3054
+
};
3055
+
3056
+
static struct cdns_torrent_vals usxgmii_sgmii_link_cmn_vals = {
3057
+
.reg_pairs = usxgmii_sgmii_link_cmn_regs,
3058
+
.num_regs = ARRAY_SIZE(usxgmii_sgmii_link_cmn_regs),
3059
+
};
3060
+
3061
+
static struct cdns_torrent_vals usxgmii_sgmii_xcvr_diag_ln_vals = {
3062
+
.reg_pairs = usxgmii_sgmii_xcvr_diag_ln_regs,
3063
+
.num_regs = ARRAY_SIZE(usxgmii_sgmii_xcvr_diag_ln_regs),
3064
+
};
3065
+
3066
+
static struct cdns_torrent_vals sgmii_usxgmii_xcvr_diag_ln_vals = {
3067
+
.reg_pairs = sgmii_usxgmii_xcvr_diag_ln_regs,
3068
+
.num_regs = ARRAY_SIZE(sgmii_usxgmii_xcvr_diag_ln_regs),
3069
+
};
3070
+
3071
+
/* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3072
+
static struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {
3073
+
{0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3074
+
{0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3075
+
{0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3076
+
{0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3077
+
{0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3078
+
{0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3079
+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3080
+
{0x0138, CMN_PLL0_LOCK_REFCNT_START},
3081
+
{0x0138, CMN_PLL0_LOCK_PLLCNT_START}
3082
+
};
3083
+
3084
+
static struct cdns_torrent_vals ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {
3085
+
.reg_pairs = ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,
3086
+
.num_regs = ARRAY_SIZE(ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),
3087
+
};
3088
+
3089
+
/* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */
3090
+
static struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {
3091
+
{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3092
+
{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3093
+
{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3094
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3095
+
{0x007F, CMN_TXPUCAL_TUNE},
3096
+
{0x007F, CMN_TXPDCAL_TUNE}
3097
+
};
3098
+
3099
+
static struct cdns_torrent_vals ml_sgmii_pll1_100_no_ssc_cmn_vals = {
3100
+
.reg_pairs = ml_sgmii_pll1_100_no_ssc_cmn_regs,
3101
+
.num_regs = ARRAY_SIZE(ml_sgmii_pll1_100_no_ssc_cmn_regs),
3102
+
};
3103
+
3104
+
/* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */
3105
+
static struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {
3106
+
{0x0014, CMN_SSM_BIAS_TMR},
3107
+
{0x0028, CMN_PLLSM0_PLLPRE_TMR},
3108
+
{0x00A4, CMN_PLLSM0_PLLLOCK_TMR},
3109
+
{0x0062, CMN_BGCAL_INIT_TMR},
3110
+
{0x0062, CMN_BGCAL_ITER_TMR},
3111
+
{0x0014, CMN_IBCAL_INIT_TMR},
3112
+
{0x0018, CMN_TXPUCAL_INIT_TMR},
3113
+
{0x0005, CMN_TXPUCAL_ITER_TMR},
3114
+
{0x0018, CMN_TXPDCAL_INIT_TMR},
3115
+
{0x0005, CMN_TXPDCAL_ITER_TMR},
3116
+
{0x024A, CMN_RXCAL_INIT_TMR},
3117
+
{0x0005, CMN_RXCAL_ITER_TMR},
3118
+
{0x000B, CMN_SD_CAL_REFTIM_START},
3119
+
{0x0132, CMN_SD_CAL_PLLCNT_START},
3120
+
{0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},
3121
+
{0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},
3122
+
{0x061B, CMN_PLL0_VCOCAL_INIT_TMR},
3123
+
{0x0019, CMN_PLL0_VCOCAL_ITER_TMR},
3124
+
{0x1354, CMN_PLL0_VCOCAL_REFTIM_START},
3125
+
{0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},
3126
+
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
3127
+
{0x0138, CMN_PLL0_LOCK_REFCNT_START},
3128
+
{0x0138, CMN_PLL0_LOCK_PLLCNT_START}
3129
+
};
3130
+
3131
+
static struct cdns_torrent_vals j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {
3132
+
.reg_pairs = j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,
3133
+
.num_regs = ARRAY_SIZE(j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),
3134
+
};
3135
+
3136
+
/* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */
3137
+
static struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {
3138
+
{0x0028, CMN_PLLSM1_PLLPRE_TMR},
3139
+
{0x00A4, CMN_PLLSM1_PLLLOCK_TMR},
3140
+
{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3141
+
{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3142
+
{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3143
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3144
+
{0x007F, CMN_TXPUCAL_TUNE},
3145
+
{0x007F, CMN_TXPDCAL_TUNE}
3146
+
};
3147
+
3148
+
static struct cdns_torrent_vals j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals = {
3149
+
.reg_pairs = j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs,
3150
+
.num_regs = ARRAY_SIZE(j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs),
3151
+
};
3152
+
3153
+
/* PCIe and USXGMII link configuration */
3154
+
static struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = {
3155
+
{0x0003, PHY_PLL_CFG},
3156
+
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3157
+
{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3158
+
{0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0}
3159
+
};
3160
+
3161
+
static struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = {
3162
+
{0x0000, XCVR_DIAG_HSCLK_SEL},
3163
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3164
+
{0x0012, XCVR_DIAG_PLLDRC_CTRL}
3165
+
};
3166
+
3167
+
static struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = {
3168
+
{0x0011, XCVR_DIAG_HSCLK_SEL},
3169
+
{0x0001, XCVR_DIAG_HSCLK_DIV},
3170
+
{0x0089, XCVR_DIAG_PLLDRC_CTRL}
3171
+
};
3172
+
3173
+
static struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = {
3174
+
.reg_pairs = pcie_usxgmii_link_cmn_regs,
3175
+
.num_regs = ARRAY_SIZE(pcie_usxgmii_link_cmn_regs),
3176
+
};
3177
+
3178
+
static struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = {
3179
+
.reg_pairs = pcie_usxgmii_xcvr_diag_ln_regs,
3180
+
.num_regs = ARRAY_SIZE(pcie_usxgmii_xcvr_diag_ln_regs),
3181
+
};
3182
+
3183
+
static struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = {
3184
+
.reg_pairs = usxgmii_pcie_xcvr_diag_ln_regs,
3185
+
.num_regs = ARRAY_SIZE(usxgmii_pcie_xcvr_diag_ln_regs),
3186
+
};
3187
+
3188
+
/*
3189
+
* Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC
3190
+
*/
3191
+
static struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = {
3192
+
{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3193
+
{0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},
3194
+
{0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},
3195
+
{0x061B, CMN_PLL1_VCOCAL_INIT_TMR},
3196
+
{0x0019, CMN_PLL1_VCOCAL_ITER_TMR},
3197
+
{0x1354, CMN_PLL1_VCOCAL_REFTIM_START},
3198
+
{0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},
3199
+
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
3200
+
{0x0138, CMN_PLL1_LOCK_REFCNT_START},
3201
+
{0x0138, CMN_PLL1_LOCK_PLLCNT_START},
3202
+
{0x007F, CMN_TXPUCAL_TUNE},
3203
+
{0x007F, CMN_TXPDCAL_TUNE}
3204
+
};
3205
+
3206
+
static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = {
3207
+
{0x00F3, TX_PSC_A0},
3208
+
{0x04A2, TX_PSC_A2},
3209
+
{0x04A2, TX_PSC_A3 },
3210
+
{0x0000, TX_TXCC_CPOST_MULT_00},
3211
+
{0x0000, XCVR_DIAG_PSC_OVRD}
3212
+
};
3213
+
3214
+
static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = {
3215
+
{0x091D, RX_PSC_A0},
3216
+
{0x0900, RX_PSC_A2},
3217
+
{0x0100, RX_PSC_A3},
3218
+
{0x0030, RX_REE_SMGM_CTRL1},
3219
+
{0x03C7, RX_REE_GCSM1_EQENM_PH1},
3220
+
{0x01C7, RX_REE_GCSM1_EQENM_PH2},
3221
+
{0x0000, RX_DIAG_DFE_CTRL},
3222
+
{0x0019, RX_REE_TAP1_CLIP},
3223
+
{0x0019, RX_REE_TAP2TON_CLIP},
3224
+
{0x00B9, RX_DIAG_NQST_CTRL},
3225
+
{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
3226
+
{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3227
+
{0x0033, RX_DIAG_PI_RATE},
3228
+
{0x0001, RX_DIAG_ACYA},
3229
+
{0x018C, RX_CDRLF_CNFG}
3230
+
};
3231
+
3232
+
static struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = {
3233
+
.reg_pairs = ml_usxgmii_pll1_156_25_no_ssc_cmn_regs,
3234
+
.num_regs = ARRAY_SIZE(ml_usxgmii_pll1_156_25_no_ssc_cmn_regs),
3235
+
};
3236
+
3237
+
static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = {
3238
+
.reg_pairs = ml_usxgmii_156_25_no_ssc_tx_ln_regs,
3239
+
.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_tx_ln_regs),
3240
+
};
3241
+
3242
+
static struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = {
3243
+
.reg_pairs = ml_usxgmii_156_25_no_ssc_rx_ln_regs,
3244
+
.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_rx_ln_regs),
3107
3245
};
3108
3246
3109
3247
/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */
···
4093
3811
.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
4094
3812
};
4095
3813
3814
+
/* TI J7200, multilink SGMII */
3815
+
static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = {
3816
+
{0x07A2, TX_RCVDET_ST_TMR},
3817
+
{0x00F3, TX_PSC_A0},
3818
+
{0x04A2, TX_PSC_A2},
3819
+
{0x04A2, TX_PSC_A3 },
3820
+
{0x0000, TX_TXCC_CPOST_MULT_00},
3821
+
{0x00B3, DRV_DIAG_TX_DRV},
3822
+
{0x0002, XCVR_DIAG_PSC_OVRD},
3823
+
{0x4000, XCVR_DIAG_RXCLK_CTRL}
3824
+
};
3825
+
3826
+
static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_tx_ln_vals = {
3827
+
.reg_pairs = j7200_sgmii_100_no_ssc_tx_ln_regs,
3828
+
.num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_tx_ln_regs),
3829
+
};
3830
+
3831
+
static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = {
3832
+
{0x0014, RX_SDCAL0_INIT_TMR},
3833
+
{0x0062, RX_SDCAL0_ITER_TMR},
3834
+
{0x0014, RX_SDCAL1_INIT_TMR},
3835
+
{0x0062, RX_SDCAL1_ITER_TMR},
3836
+
{0x091D, RX_PSC_A0},
3837
+
{0x0900, RX_PSC_A2},
3838
+
{0x0100, RX_PSC_A3},
3839
+
{0x03C7, RX_REE_GCSM1_EQENM_PH1},
3840
+
{0x01C7, RX_REE_GCSM1_EQENM_PH2},
3841
+
{0x0000, RX_DIAG_DFE_CTRL},
3842
+
{0x0019, RX_REE_TAP1_CLIP},
3843
+
{0x0019, RX_REE_TAP2TON_CLIP},
3844
+
{0x0098, RX_DIAG_NQST_CTRL},
3845
+
{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3846
+
{0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3847
+
{0x0000, RX_DIAG_PI_CAP},
3848
+
{0x0010, RX_DIAG_PI_RATE},
3849
+
{0x0001, RX_DIAG_ACYA},
3850
+
{0x018C, RX_CDRLF_CNFG}
3851
+
};
3852
+
3853
+
static struct cdns_torrent_vals j7200_sgmii_100_no_ssc_rx_ln_vals = {
3854
+
.reg_pairs = j7200_sgmii_100_no_ssc_rx_ln_regs,
3855
+
.num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_rx_ln_regs),
3856
+
};
3857
+
4096
3858
/* SGMII 100 MHz Ref clk, internal SSC */
4097
3859
static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
4098
3860
{0x0004, CMN_PLL0_DSM_DIAG_M0},
···
4268
3942
static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
4269
3943
.reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
4270
3944
.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3945
+
};
3946
+
3947
+
/* TI J7200, multilink QSGMII */
3948
+
static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = {
3949
+
{0x07A2, TX_RCVDET_ST_TMR},
3950
+
{0x00F3, TX_PSC_A0},
3951
+
{0x04A2, TX_PSC_A2},
3952
+
{0x04A2, TX_PSC_A3 },
3953
+
{0x0000, TX_TXCC_CPOST_MULT_00},
3954
+
{0x0011, TX_TXCC_MGNFS_MULT_100},
3955
+
{0x0003, DRV_DIAG_TX_DRV},
3956
+
{0x0002, XCVR_DIAG_PSC_OVRD},
3957
+
{0x4000, XCVR_DIAG_RXCLK_CTRL}
3958
+
};
3959
+
3960
+
static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_tx_ln_vals = {
3961
+
.reg_pairs = j7200_qsgmii_100_no_ssc_tx_ln_regs,
3962
+
.num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_tx_ln_regs),
3963
+
};
3964
+
3965
+
static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = {
3966
+
{0x0014, RX_SDCAL0_INIT_TMR},
3967
+
{0x0062, RX_SDCAL0_ITER_TMR},
3968
+
{0x0014, RX_SDCAL1_INIT_TMR},
3969
+
{0x0062, RX_SDCAL1_ITER_TMR},
3970
+
{0x091D, RX_PSC_A0},
3971
+
{0x0900, RX_PSC_A2},
3972
+
{0x0100, RX_PSC_A3},
3973
+
{0x03C7, RX_REE_GCSM1_EQENM_PH1},
3974
+
{0x01C7, RX_REE_GCSM1_EQENM_PH2},
3975
+
{0x0000, RX_DIAG_DFE_CTRL},
3976
+
{0x0019, RX_REE_TAP1_CLIP},
3977
+
{0x0019, RX_REE_TAP2TON_CLIP},
3978
+
{0x0098, RX_DIAG_NQST_CTRL},
3979
+
{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3980
+
{0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3981
+
{0x0000, RX_DIAG_PI_CAP},
3982
+
{0x0010, RX_DIAG_PI_RATE},
3983
+
{0x0001, RX_DIAG_ACYA},
3984
+
{0x018C, RX_CDRLF_CNFG}
3985
+
};
3986
+
3987
+
static struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_rx_ln_vals = {
3988
+
.reg_pairs = j7200_qsgmii_100_no_ssc_rx_ln_regs,
3989
+
.num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_rx_ln_regs),
4271
3990
};
4272
3991
4273
3992
/* QSGMII 100 MHz Ref clk, internal SSC */
···
4537
4166
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
4538
4167
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
4539
4168
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
4169
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
4540
4170
4541
4171
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4542
4172
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4543
4173
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4174
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},
4544
4175
4545
4176
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
4546
4177
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
4547
4178
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},
4179
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},
4548
4180
4549
4181
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},
4550
4182
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},
···
4556
4182
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
4557
4183
4558
4184
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals},
4185
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals},
4186
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_link_cmn_vals},
4187
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_link_cmn_vals},
4559
4188
};
4560
4189
4561
4190
static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
···
4571
4194
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
4572
4195
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
4573
4196
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
4197
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
4574
4198
4575
4199
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4576
4200
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4577
4201
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4202
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},
4578
4203
4579
4204
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
4580
4205
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
4581
4206
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},
4207
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},
4582
4208
4583
4209
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},
4584
4210
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},
···
4590
4210
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
4591
4211
4592
4212
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals},
4213
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals},
4214
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
4215
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
4593
4216
};
4594
4217
4595
4218
static struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
···
4668
4285
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
4669
4286
4670
4287
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
4288
+
4289
+
/* Dual refclk */
4290
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4291
+
4292
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},
4293
+
4294
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},
4295
+
4296
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},
4297
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4298
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4671
4299
};
4672
4300
4673
4301
static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
···
4746
4352
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4747
4353
4748
4354
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4355
+
4356
+
/* Dual refclk */
4357
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4358
+
4359
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
4360
+
4361
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},
4362
+
4363
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4364
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4365
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4749
4366
};
4750
4367
4751
4368
static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
···
4824
4419
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4825
4420
4826
4421
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4422
+
4423
+
/* Dual refclk */
4424
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4425
+
4426
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4427
+
4428
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4429
+
4430
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4431
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4432
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4827
4433
};
4828
4434
4829
4435
static const struct cdns_torrent_data cdns_map_torrent = {
···
4868
4452
4869
4453
static struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = {
4870
4454
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals},
4455
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &ti_usxgmii_phy_pma_cmn_vals},
4456
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &ti_usxgmii_phy_pma_cmn_vals},
4457
+
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &ti_usxgmii_phy_pma_cmn_vals},
4871
4458
};
4872
4459
4873
4460
static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
···
4938
4519
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4939
4520
4940
4521
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4522
+
4523
+
/* Dual refclk */
4524
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4525
+
4526
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4527
+
4528
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4529
+
4530
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4531
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4532
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4941
4533
};
4942
4534
4943
4535
static const struct cdns_torrent_data ti_j721e_map_torrent = {
···
4984
4554
},
4985
4555
};
4986
4556
4557
+
/* TI J7200 (Torrent SD0805) */
4558
+
static struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
4559
+
{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},
4560
+
{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},
4561
+
4562
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4563
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},
4564
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},
4565
+
4566
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4567
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4568
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
4569
+
4570
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4571
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4572
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4573
+
4574
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4575
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4576
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4577
+
4578
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},
4579
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
4580
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
4581
+
4582
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4583
+
4584
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
4585
+
4586
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4587
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4588
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},
4589
+
4590
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
4591
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4592
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},
4593
+
4594
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},
4595
+
4596
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4597
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4598
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},
4599
+
4600
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},
4601
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4602
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},
4603
+
4604
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4605
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4606
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4607
+
4608
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},
4609
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
4610
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
4611
+
4612
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4613
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4614
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4615
+
4616
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
4617
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
4618
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
4619
+
4620
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
4621
+
4622
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
4623
+
4624
+
/* Dual refclk */
4625
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4626
+
4627
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},
4628
+
4629
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},
4630
+
4631
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},
4632
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4633
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},
4634
+
};
4635
+
4636
+
static struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
4637
+
{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},
4638
+
{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},
4639
+
4640
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},
4641
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4642
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},
4643
+
4644
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},
4645
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
4646
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
4647
+
4648
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
4649
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
4650
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
4651
+
4652
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},
4653
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},
4654
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},
4655
+
4656
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},
4657
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},
4658
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},
4659
+
4660
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
4661
+
4662
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4663
+
4664
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4665
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4666
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4667
+
4668
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4669
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4670
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
4671
+
4672
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4673
+
4674
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4675
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4676
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4677
+
4678
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4679
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4680
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},
4681
+
4682
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4683
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4684
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4685
+
4686
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4687
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4688
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4689
+
4690
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4691
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4692
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4693
+
4694
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4695
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4696
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
4697
+
4698
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
4699
+
4700
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4701
+
4702
+
/* Dual refclk */
4703
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},
4704
+
4705
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_tx_ln_vals},
4706
+
4707
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_tx_ln_vals},
4708
+
4709
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},
4710
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4711
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
4712
+
};
4713
+
4714
+
static struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
4715
+
{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},
4716
+
{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},
4717
+
4718
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},
4719
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4720
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},
4721
+
4722
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4723
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4724
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4725
+
4726
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4727
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4728
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4729
+
4730
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4731
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4732
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4733
+
4734
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4735
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4736
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
4737
+
4738
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4739
+
4740
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4741
+
4742
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4743
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4744
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4745
+
4746
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4747
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4748
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},
4749
+
4750
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4751
+
4752
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4753
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4754
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4755
+
4756
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4757
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4758
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},
4759
+
4760
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4761
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4762
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4763
+
4764
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4765
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4766
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4767
+
4768
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4769
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4770
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4771
+
4772
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4773
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4774
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
4775
+
4776
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
4777
+
4778
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4779
+
4780
+
/* Dual refclk */
4781
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
4782
+
4783
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_rx_ln_vals},
4784
+
4785
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_rx_ln_vals},
4786
+
4787
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},
4788
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4789
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
4790
+
};
4791
+
4792
+
static const struct cdns_torrent_data ti_j7200_map_torrent = {
4793
+
.block_offset_shift = 0x0,
4794
+
.reg_offset_shift = 0x1,
4795
+
.link_cmn_vals_tbl = {
4796
+
.entries = link_cmn_vals_entries,
4797
+
.num_entries = ARRAY_SIZE(link_cmn_vals_entries),
4798
+
},
4799
+
.xcvr_diag_vals_tbl = {
4800
+
.entries = xcvr_diag_vals_entries,
4801
+
.num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),
4802
+
},
4803
+
.pcs_cmn_vals_tbl = {
4804
+
.entries = pcs_cmn_vals_entries,
4805
+
.num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),
4806
+
},
4807
+
.phy_pma_cmn_vals_tbl = {
4808
+
.entries = j721e_phy_pma_cmn_vals_entries,
4809
+
.num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),
4810
+
},
4811
+
.cmn_vals_tbl = {
4812
+
.entries = ti_j7200_cmn_vals_entries,
4813
+
.num_entries = ARRAY_SIZE(ti_j7200_cmn_vals_entries),
4814
+
},
4815
+
.tx_ln_vals_tbl = {
4816
+
.entries = ti_j7200_tx_ln_vals_entries,
4817
+
.num_entries = ARRAY_SIZE(ti_j7200_tx_ln_vals_entries),
4818
+
},
4819
+
.rx_ln_vals_tbl = {
4820
+
.entries = ti_j7200_rx_ln_vals_entries,
4821
+
.num_entries = ARRAY_SIZE(ti_j7200_rx_ln_vals_entries),
4822
+
},
4823
+
};
4824
+
4987
4825
static const struct of_device_id cdns_torrent_phy_of_match[] = {
4988
4826
{
4989
4827
.compatible = "cdns,torrent-phy",
···
5260
4562
{
5261
4563
.compatible = "ti,j721e-serdes-10g",
5262
4564
.data = &ti_j721e_map_torrent,
4565
+
},
4566
+
{
4567
+
.compatible = "ti,j7200-serdes-10g",
4568
+
.data = &ti_j7200_map_torrent,
5263
4569
},
5264
4570
{}
5265
4571
};
+1
-1
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
+1
-1
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
+1
-1
drivers/phy/freescale/phy-fsl-lynx-28g.c
+1
-1
drivers/phy/freescale/phy-fsl-lynx-28g.c
+1
-1
drivers/phy/hisilicon/phy-histb-combphy.c
+1
-1
drivers/phy/hisilicon/phy-histb-combphy.c
+1
-1
drivers/phy/intel/phy-intel-lgm-combo.c
+1
-1
drivers/phy/intel/phy-intel-lgm-combo.c
+1
-1
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
+1
-1
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
+1
-1
drivers/phy/marvell/phy-armada375-usb2.c
+1
-1
drivers/phy/marvell/phy-armada375-usb2.c
+7
-2
drivers/phy/marvell/phy-armada38x-comphy.c
+7
-2
drivers/phy/marvell/phy-armada38x-comphy.c
···
47
47
struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
48
48
};
49
49
50
+
/*
51
+
* Map serdes lanes and gbe ports to serdes mux configuration values:
52
+
* row index = serdes lane,
53
+
* column index = gbe port number.
54
+
*/
50
55
static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = {
51
-
{ 0, 0, 0 },
56
+
{ 3, 0, 0 },
52
57
{ 4, 5, 0 },
53
58
{ 0, 4, 0 },
54
59
{ 0, 0, 4 },
···
160
155
};
161
156
162
157
static struct phy *a38x_comphy_xlate(struct device *dev,
163
-
struct of_phandle_args *args)
158
+
const struct of_phandle_args *args)
164
159
{
165
160
struct a38x_comphy_lane *lane;
166
161
struct phy *phy;
+1
-1
drivers/phy/marvell/phy-berlin-sata.c
+1
-1
drivers/phy/marvell/phy-berlin-sata.c
+1
-1
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+1
-1
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+1
-1
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+1
-1
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+12
drivers/phy/mediatek/Kconfig
+12
drivers/phy/mediatek/Kconfig
···
58
58
help
59
59
Support HDMI PHY for Mediatek SoCs.
60
60
61
+
config PHY_MTK_MIPI_CSI_0_5
62
+
tristate "MediaTek MIPI CSI CD-PHY v0.5 Driver"
63
+
depends on ARCH_MEDIATEK || COMPILE_TEST
64
+
depends on OF
65
+
select GENERIC_PHY
66
+
help
67
+
Enable this to support the MIPI CSI CD-PHY receiver version 0.5.
68
+
The driver supports multiple CSI cdphy ports simultaneously.
69
+
70
+
To compile this driver as a module, choose M here: the
71
+
module will be called phy-mtk-mipi-csi-0-5.
72
+
61
73
config PHY_MTK_MIPI_DSI
62
74
tristate "MediaTek MIPI-DSI Driver"
63
75
depends on ARCH_MEDIATEK || COMPILE_TEST
+2
drivers/phy/mediatek/Makefile
+2
drivers/phy/mediatek/Makefile
···
15
15
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8195.o
16
16
obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
17
17
18
+
obj-$(CONFIG_PHY_MTK_MIPI_CSI_0_5) += phy-mtk-mipi-csi-0-5.o
19
+
18
20
phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
19
21
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o
20
22
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o
+62
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
+62
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5-rx-reg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, MediaTek Inc.
4
+
* Copyright (c) 2023, BayLibre Inc.
5
+
*/
6
+
7
+
#ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
8
+
#define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
9
+
10
+
/*
11
+
* CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are
12
+
* applicable to the three PHYs. Where differences exist, they are denoted by
13
+
* macro names using CSI0 and CSI1, the latter being applicable to CSI1 and
14
+
* CSI2 alike.
15
+
*/
16
+
17
+
#define MIPI_RX_ANA00_CSIXA 0x0000
18
+
#define RG_CSI0A_CPHY_EN BIT(0)
19
+
#define RG_CSIXA_EQ_PROTECT_EN BIT(1)
20
+
#define RG_CSIXA_BG_LPF_EN BIT(2)
21
+
#define RG_CSIXA_BG_CORE_EN BIT(3)
22
+
#define RG_CSIXA_DPHY_L0_CKMODE_EN BIT(5)
23
+
#define RG_CSIXA_DPHY_L0_CKSEL BIT(6)
24
+
#define RG_CSIXA_DPHY_L1_CKMODE_EN BIT(8)
25
+
#define RG_CSIXA_DPHY_L1_CKSEL BIT(9)
26
+
#define RG_CSIXA_DPHY_L2_CKMODE_EN BIT(11)
27
+
#define RG_CSIXA_DPHY_L2_CKSEL BIT(12)
28
+
29
+
#define MIPI_RX_ANA18_CSIXA 0x0018
30
+
#define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4)
31
+
#define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6)
32
+
#define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20)
33
+
#define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22)
34
+
#define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20)
35
+
#define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22)
36
+
#define RG_CSI1A_L0_EQ_IS GENMASK(5, 4)
37
+
#define RG_CSI1A_L0_EQ_BW GENMASK(7, 6)
38
+
#define RG_CSI1A_L1_EQ_IS GENMASK(21, 20)
39
+
#define RG_CSI1A_L1_EQ_BW GENMASK(23, 22)
40
+
#define RG_CSI1A_L2_EQ_IS GENMASK(5, 4)
41
+
#define RG_CSI1A_L2_EQ_BW GENMASK(7, 6)
42
+
43
+
#define MIPI_RX_ANA1C_CSIXA 0x001c
44
+
#define MIPI_RX_ANA20_CSI0A 0x0020
45
+
46
+
#define MIPI_RX_ANA24_CSIXA 0x0024
47
+
#define RG_CSIXA_RESERVE GENMASK(31, 24)
48
+
49
+
#define MIPI_RX_ANA40_CSIXA 0x0040
50
+
#define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0)
51
+
#define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4)
52
+
#define RG_CSIXA_CPHY_SPARE GENMASK(31, 16)
53
+
54
+
#define MIPI_RX_WRAPPER80_CSIXA 0x0080
55
+
#define CSR_CSI_RST_MODE GENMASK(17, 16)
56
+
57
+
#define MIPI_RX_ANAA8_CSIXA 0x00a8
58
+
#define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT BIT(0)
59
+
#define RG_CSIXA_DPHY_L1_BYTECK_INVERT BIT(1)
60
+
#define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT BIT(2)
61
+
62
+
#endif
+294
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
+294
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek MIPI CSI v0.5 driver
4
+
*
5
+
* Copyright (c) 2023, MediaTek Inc.
6
+
* Copyright (c) 2023, BayLibre Inc.
7
+
*/
8
+
9
+
#include <dt-bindings/phy/phy.h>
10
+
#include <linux/bitfield.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/io.h>
13
+
#include <linux/module.h>
14
+
#include <linux/mutex.h>
15
+
#include <linux/phy/phy.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include "phy-mtk-io.h"
20
+
#include "phy-mtk-mipi-csi-0-5-rx-reg.h"
21
+
22
+
#define CSIXB_OFFSET 0x1000
23
+
24
+
struct mtk_mipi_cdphy_port {
25
+
struct device *dev;
26
+
void __iomem *base;
27
+
struct phy *phy;
28
+
u32 type;
29
+
u32 mode;
30
+
u32 num_lanes;
31
+
};
32
+
33
+
enum PHY_TYPE {
34
+
DPHY = 0,
35
+
CPHY,
36
+
CDPHY,
37
+
};
38
+
39
+
static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base)
40
+
{
41
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);
42
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);
43
+
mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);
44
+
mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);
45
+
mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);
46
+
mtk_phy_update_field(base + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);
47
+
48
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1);
49
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1);
50
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1);
51
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1);
52
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_IS, 1);
53
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA20_CSI0A, RG_CSI0A_L2_T1BC_EQ_BW, 1);
54
+
}
55
+
56
+
static void mtk_phy_csi_dphy_ana_eq_tune(void __iomem *base)
57
+
{
58
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1);
59
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1);
60
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1);
61
+
mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1);
62
+
mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1);
63
+
mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1);
64
+
65
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_IS, 1);
66
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L0_EQ_BW, 1);
67
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_IS, 1);
68
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA18_CSIXA, RG_CSI1A_L1_EQ_BW, 1);
69
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_IS, 1);
70
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA1C_CSIXA, RG_CSI1A_L2_EQ_BW, 1);
71
+
}
72
+
73
+
static int mtk_mipi_phy_power_on(struct phy *phy)
74
+
{
75
+
struct mtk_mipi_cdphy_port *port = phy_get_drvdata(phy);
76
+
void __iomem *base = port->base;
77
+
78
+
/*
79
+
* The driver currently supports DPHY and CD-PHY phys,
80
+
* but the only mode supported is DPHY,
81
+
* so CD-PHY capable phys must be configured in DPHY mode
82
+
*/
83
+
if (port->type == CDPHY) {
84
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSI0A_CPHY_EN, 0);
85
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
86
+
RG_CSI0A_CPHY_EN, 0);
87
+
}
88
+
89
+
/*
90
+
* Lane configuration:
91
+
*
92
+
* Only 4 data + 1 clock is supported for now with the following mapping:
93
+
*
94
+
* CSIXA_LNR0 --> D2
95
+
* CSIXA_LNR1 --> D0
96
+
* CSIXA_LNR2 --> C
97
+
* CSIXB_LNR0 --> D1
98
+
* CSIXB_LNR1 --> D3
99
+
*/
100
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKMODE_EN, 0);
101
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1);
102
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKMODE_EN, 0);
103
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1);
104
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKMODE_EN, 1);
105
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1);
106
+
107
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
108
+
RG_CSIXA_DPHY_L0_CKMODE_EN, 0);
109
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L0_CKSEL, 1);
110
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
111
+
RG_CSIXA_DPHY_L1_CKMODE_EN, 0);
112
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L1_CKSEL, 1);
113
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA,
114
+
RG_CSIXA_DPHY_L2_CKMODE_EN, 0);
115
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_DPHY_L2_CKSEL, 1);
116
+
117
+
/* Byte clock invert */
118
+
mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1);
119
+
mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1);
120
+
mtk_phy_update_field(base + MIPI_RX_ANAA8_CSIXA, RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1);
121
+
122
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
123
+
RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT, 1);
124
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
125
+
RG_CSIXA_DPHY_L1_BYTECK_INVERT, 1);
126
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANAA8_CSIXA,
127
+
RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT, 1);
128
+
129
+
/* Start ANA EQ tuning */
130
+
if (port->type == CDPHY)
131
+
mtk_phy_csi_cdphy_ana_eq_tune(base);
132
+
else
133
+
mtk_phy_csi_dphy_ana_eq_tune(base);
134
+
135
+
/* End ANA EQ tuning */
136
+
mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90);
137
+
138
+
mtk_phy_update_field(base + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40);
139
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA24_CSIXA, RG_CSIXA_RESERVE, 0x40);
140
+
mtk_phy_update_field(base + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0);
141
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_WRAPPER80_CSIXA, CSR_CSI_RST_MODE, 0);
142
+
/* ANA power on */
143
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1);
144
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 1);
145
+
usleep_range(20, 40);
146
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1);
147
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 1);
148
+
149
+
return 0;
150
+
}
151
+
152
+
static int mtk_mipi_phy_power_off(struct phy *phy)
153
+
{
154
+
struct mtk_mipi_cdphy_port *port = phy_get_drvdata(phy);
155
+
void __iomem *base = port->base;
156
+
157
+
/* Disable MIPI BG. */
158
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0);
159
+
mtk_phy_update_field(base + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0);
160
+
161
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_CORE_EN, 0);
162
+
mtk_phy_update_field(base + CSIXB_OFFSET + MIPI_RX_ANA00_CSIXA, RG_CSIXA_BG_LPF_EN, 0);
163
+
164
+
return 0;
165
+
}
166
+
167
+
static struct phy *mtk_mipi_cdphy_xlate(struct device *dev,
168
+
const struct of_phandle_args *args)
169
+
{
170
+
struct mtk_mipi_cdphy_port *priv = dev_get_drvdata(dev);
171
+
172
+
/*
173
+
* If PHY is CD-PHY then we need to get the operating mode
174
+
* For now only D-PHY mode is supported
175
+
*/
176
+
if (priv->type == CDPHY) {
177
+
if (args->args_count != 1) {
178
+
dev_err(dev, "invalid number of arguments\n");
179
+
return ERR_PTR(-EINVAL);
180
+
}
181
+
switch (args->args[0]) {
182
+
case PHY_TYPE_DPHY:
183
+
priv->mode = DPHY;
184
+
if (priv->num_lanes != 4) {
185
+
dev_err(dev, "Only 4D1C mode is supported for now!\n");
186
+
return ERR_PTR(-EINVAL);
187
+
}
188
+
break;
189
+
default:
190
+
dev_err(dev, "Unsupported PHY type: %i\n", args->args[0]);
191
+
return ERR_PTR(-EINVAL);
192
+
}
193
+
} else {
194
+
if (args->args_count) {
195
+
dev_err(dev, "invalid number of arguments\n");
196
+
return ERR_PTR(-EINVAL);
197
+
}
198
+
priv->mode = DPHY;
199
+
}
200
+
201
+
return priv->phy;
202
+
}
203
+
204
+
static const struct phy_ops mtk_cdphy_ops = {
205
+
.power_on = mtk_mipi_phy_power_on,
206
+
.power_off = mtk_mipi_phy_power_off,
207
+
.owner = THIS_MODULE,
208
+
};
209
+
210
+
static int mtk_mipi_cdphy_probe(struct platform_device *pdev)
211
+
{
212
+
struct device *dev = &pdev->dev;
213
+
struct phy_provider *phy_provider;
214
+
struct mtk_mipi_cdphy_port *port;
215
+
struct phy *phy;
216
+
int ret;
217
+
u32 phy_type;
218
+
219
+
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
220
+
if (!port)
221
+
return -ENOMEM;
222
+
223
+
dev_set_drvdata(dev, port);
224
+
225
+
port->dev = dev;
226
+
227
+
port->base = devm_platform_ioremap_resource(pdev, 0);
228
+
if (IS_ERR(port->base))
229
+
return PTR_ERR(port->base);
230
+
231
+
ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes);
232
+
if (ret) {
233
+
dev_err(dev, "Failed to read num-lanes property: %i\n", ret);
234
+
return ret;
235
+
}
236
+
237
+
/*
238
+
* phy-type is optional, if not present, PHY is considered to be CD-PHY
239
+
*/
240
+
if (device_property_present(dev, "phy-type")) {
241
+
ret = of_property_read_u32(dev->of_node, "phy-type", &phy_type);
242
+
if (ret) {
243
+
dev_err(dev, "Failed to read phy-type property: %i\n", ret);
244
+
return ret;
245
+
}
246
+
switch (phy_type) {
247
+
case PHY_TYPE_DPHY:
248
+
port->type = DPHY;
249
+
break;
250
+
default:
251
+
dev_err(dev, "Unsupported PHY type: %i\n", phy_type);
252
+
return -EINVAL;
253
+
}
254
+
} else {
255
+
port->type = CDPHY;
256
+
}
257
+
258
+
phy = devm_phy_create(dev, NULL, &mtk_cdphy_ops);
259
+
if (IS_ERR(phy)) {
260
+
dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(phy));
261
+
return PTR_ERR(phy);
262
+
}
263
+
264
+
port->phy = phy;
265
+
phy_set_drvdata(phy, port);
266
+
267
+
phy_provider = devm_of_phy_provider_register(dev, mtk_mipi_cdphy_xlate);
268
+
if (IS_ERR(phy_provider)) {
269
+
dev_err(dev, "Failed to register PHY provider: %ld\n",
270
+
PTR_ERR(phy_provider));
271
+
return PTR_ERR(phy_provider);
272
+
}
273
+
274
+
return 0;
275
+
}
276
+
277
+
static const struct of_device_id mtk_mipi_cdphy_of_match[] = {
278
+
{ .compatible = "mediatek,mt8365-csi-rx" },
279
+
{ /* sentinel */},
280
+
};
281
+
MODULE_DEVICE_TABLE(of, mtk_mipi_cdphy_of_match);
282
+
283
+
static struct platform_driver mipi_cdphy_pdrv = {
284
+
.probe = mtk_mipi_cdphy_probe,
285
+
.driver = {
286
+
.name = "mtk-mipi-csi-0-5",
287
+
.of_match_table = mtk_mipi_cdphy_of_match,
288
+
},
289
+
};
290
+
module_platform_driver(mipi_cdphy_pdrv);
291
+
292
+
MODULE_DESCRIPTION("MediaTek MIPI CSI CD-PHY v0.5 Driver");
293
+
MODULE_AUTHOR("Louis Kuo <louis.kuo@mediatek.com>");
294
+
MODULE_LICENSE("GPL");
+1
-1
drivers/phy/mediatek/phy-mtk-tphy.c
+1
-1
drivers/phy/mediatek/phy-mtk-tphy.c
+1
-1
drivers/phy/mediatek/phy-mtk-xsphy.c
+1
-1
drivers/phy/mediatek/phy-mtk-xsphy.c
+1
-1
drivers/phy/microchip/lan966x_serdes.c
+1
-1
drivers/phy/microchip/lan966x_serdes.c
+1
-1
drivers/phy/microchip/sparx5_serdes.c
+1
-1
drivers/phy/microchip/sparx5_serdes.c
···
2509
2509
2510
2510
/* Client lookup function, uses serdes index */
2511
2511
static struct phy *sparx5_serdes_xlate(struct device *dev,
2512
-
struct of_phandle_args *args)
2512
+
const struct of_phandle_args *args)
2513
2513
{
2514
2514
struct sparx5_serdes_private *priv = dev_get_drvdata(dev);
2515
2515
int idx;
+1
-1
drivers/phy/mscc/phy-ocelot-serdes.c
+1
-1
drivers/phy/mscc/phy-ocelot-serdes.c
+4
-4
drivers/phy/phy-core.c
+4
-4
drivers/phy/phy-core.c
···
700
700
* should provide a custom of_xlate function that reads the *args* and returns
701
701
* the appropriate phy.
702
702
*/
703
-
struct phy *of_phy_simple_xlate(struct device *dev, struct of_phandle_args
704
-
*args)
703
+
struct phy *of_phy_simple_xlate(struct device *dev,
704
+
const struct of_phandle_args *args)
705
705
{
706
706
struct phy *phy;
707
707
struct class_dev_iter iter;
···
1095
1095
struct phy_provider *__of_phy_provider_register(struct device *dev,
1096
1096
struct device_node *children, struct module *owner,
1097
1097
struct phy * (*of_xlate)(struct device *dev,
1098
-
struct of_phandle_args *args))
1098
+
const struct of_phandle_args *args))
1099
1099
{
1100
1100
struct phy_provider *phy_provider;
1101
1101
···
1158
1158
struct phy_provider *__devm_of_phy_provider_register(struct device *dev,
1159
1159
struct device_node *children, struct module *owner,
1160
1160
struct phy * (*of_xlate)(struct device *dev,
1161
-
struct of_phandle_args *args))
1161
+
const struct of_phandle_args *args))
1162
1162
{
1163
1163
struct phy_provider **ptr, *phy_provider;
1164
1164
+1
-1
drivers/phy/phy-xgene.c
+1
-1
drivers/phy/phy-xgene.c
+1
-1
drivers/phy/qualcomm/Makefile
+1
-1
drivers/phy/qualcomm/Makefile
···
7
7
obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8
8
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
9
9
10
-
obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
10
+
obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o
11
11
obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
12
12
obj-$(CONFIG_PHY_QCOM_QMP_PCIE_8996) += phy-qcom-qmp-pcie-msm8996.o
13
13
obj-$(CONFIG_PHY_QCOM_QMP_UFS) += phy-qcom-qmp-ufs.o
+2
-1
drivers/phy/qualcomm/phy-qcom-edp.c
+2
-1
drivers/phy/qualcomm/phy-qcom-edp.c
+25
-86
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+25
-86
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
···
25
25
26
26
#include <dt-bindings/phy/phy-qcom-qmp.h>
27
27
28
+
#include "phy-qcom-qmp-common.h"
29
+
28
30
#include "phy-qcom-qmp.h"
29
31
#include "phy-qcom-qmp-pcs-misc-v3.h"
30
32
#include "phy-qcom-qmp-pcs-usb-v4.h"
31
33
#include "phy-qcom-qmp-pcs-usb-v5.h"
32
34
#include "phy-qcom-qmp-pcs-usb-v6.h"
33
35
34
-
/* QPHY_SW_RESET bit */
35
-
#define SW_RESET BIT(0)
36
-
/* QPHY_POWER_DOWN_CONTROL */
37
-
#define SW_PWRDN BIT(0)
38
-
/* QPHY_START_CONTROL bits */
39
-
#define SERDES_START BIT(0)
40
-
#define PCS_START BIT(1)
41
-
/* QPHY_PCS_STATUS bit */
42
-
#define PHYSTATUS BIT(6)
36
+
#include "phy-qcom-qmp-dp-com-v3.h"
37
+
38
+
#include "phy-qcom-qmp-dp-phy.h"
39
+
#include "phy-qcom-qmp-dp-phy-v3.h"
40
+
#include "phy-qcom-qmp-dp-phy-v4.h"
41
+
#include "phy-qcom-qmp-dp-phy-v5.h"
42
+
#include "phy-qcom-qmp-dp-phy-v6.h"
43
43
44
44
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
45
45
/* DP PHY soft reset */
···
55
55
#define USB3_MODE BIT(0) /* enables USB3 mode */
56
56
#define DP_MODE BIT(1) /* enables DP mode */
57
57
58
-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
59
-
#define ARCVR_DTCT_EN BIT(0)
60
-
#define ALFPS_DTCT_EN BIT(1)
61
-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
62
-
63
-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
64
-
#define IRQ_CLEAR BIT(0)
65
-
66
-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67
-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
68
-
69
58
/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
70
59
#define SW_PORTSELECT_VAL BIT(0)
71
60
#define SW_PORTSELECT_MUX BIT(1)
72
61
73
62
#define PHY_INIT_COMPLETE_TIMEOUT 10000
74
-
75
-
struct qmp_phy_init_tbl {
76
-
unsigned int offset;
77
-
unsigned int val;
78
-
/*
79
-
* mask of lanes for which this register is written
80
-
* for cases when second lane needs different values
81
-
*/
82
-
u8 lane_mask;
83
-
};
84
-
85
-
#define QMP_PHY_INIT_CFG(o, v) \
86
-
{ \
87
-
.offset = o, \
88
-
.val = v, \
89
-
.lane_mask = 0xff, \
90
-
}
91
-
92
-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
93
-
{ \
94
-
.offset = o, \
95
-
.val = v, \
96
-
.lane_mask = l, \
97
-
}
98
63
99
64
/* set of registers with offsets different per-PHY */
100
65
enum qphy_reg_layout {
···
1996
2031
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1997
2032
};
1998
2033
1999
-
static void qmp_combo_configure_lane(void __iomem *base,
2000
-
const struct qmp_phy_init_tbl tbl[],
2001
-
int num,
2002
-
u8 lane_mask)
2003
-
{
2004
-
int i;
2005
-
const struct qmp_phy_init_tbl *t = tbl;
2006
-
2007
-
if (!t)
2008
-
return;
2009
-
2010
-
for (i = 0; i < num; i++, t++) {
2011
-
if (!(t->lane_mask & lane_mask))
2012
-
continue;
2013
-
2014
-
writel(t->val, base + t->offset);
2015
-
}
2016
-
}
2017
-
2018
-
static void qmp_combo_configure(void __iomem *base,
2019
-
const struct qmp_phy_init_tbl tbl[],
2020
-
int num)
2021
-
{
2022
-
qmp_combo_configure_lane(base, tbl, num, 0xff);
2023
-
}
2024
-
2025
2034
static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
2026
2035
{
2027
2036
const struct qmp_phy_cfg *cfg = qmp->cfg;
2028
2037
void __iomem *serdes = qmp->dp_serdes;
2029
2038
const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2030
2039
2031
-
qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
2040
+
qmp_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
2032
2041
2033
2042
switch (dp_opts->link_rate) {
2034
2043
case 1620:
2035
-
qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
2044
+
qmp_configure(serdes, cfg->serdes_tbl_rbr,
2036
2045
cfg->serdes_tbl_rbr_num);
2037
2046
break;
2038
2047
case 2700:
2039
-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
2048
+
qmp_configure(serdes, cfg->serdes_tbl_hbr,
2040
2049
cfg->serdes_tbl_hbr_num);
2041
2050
break;
2042
2051
case 5400:
2043
-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
2052
+
qmp_configure(serdes, cfg->serdes_tbl_hbr2,
2044
2053
cfg->serdes_tbl_hbr2_num);
2045
2054
break;
2046
2055
case 8100:
2047
-
qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
2056
+
qmp_configure(serdes, cfg->serdes_tbl_hbr3,
2048
2057
cfg->serdes_tbl_hbr3_num);
2049
2058
break;
2050
2059
default:
···
2309
2370
u32 status;
2310
2371
int ret;
2311
2372
2312
-
writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
2373
+
writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
2313
2374
2314
2375
qmp_combo_configure_dp_mode(qmp);
2315
2376
···
2620
2681
2621
2682
qmp_combo_dp_serdes_init(qmp);
2622
2683
2623
-
qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2624
-
qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2684
+
qmp_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2685
+
qmp_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2625
2686
2626
2687
/* Configure special DP tx tunings */
2627
2688
cfg->configure_dp_tx(qmp);
···
2663
2724
unsigned int val;
2664
2725
int ret;
2665
2726
2666
-
qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2727
+
qmp_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2667
2728
2668
2729
ret = clk_prepare_enable(qmp->pipe_clk);
2669
2730
if (ret) {
···
2672
2733
}
2673
2734
2674
2735
/* Tx, Rx, and PCS configurations */
2675
-
qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2676
-
qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2736
+
qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2737
+
qmp_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2677
2738
2678
-
qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2679
-
qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2739
+
qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2740
+
qmp_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2680
2741
2681
-
qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2742
+
qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2682
2743
2683
2744
if (pcs_usb)
2684
-
qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2745
+
qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2685
2746
2686
2747
if (cfg->has_pwrdn_delay)
2687
2748
usleep_range(10, 20);
···
3454
3515
return 0;
3455
3516
}
3456
3517
3457
-
static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args)
3518
+
static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
3458
3519
{
3459
3520
struct qmp_combo *qmp = dev_get_drvdata(dev);
3460
3521
+59
drivers/phy/qualcomm/phy-qcom-qmp-common.h
+59
drivers/phy/qualcomm/phy-qcom-qmp-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_COMMON_H_
7
+
#define QCOM_PHY_QMP_COMMON_H_
8
+
9
+
struct qmp_phy_init_tbl {
10
+
unsigned int offset;
11
+
unsigned int val;
12
+
/*
13
+
* mask of lanes for which this register is written
14
+
* for cases when second lane needs different values
15
+
*/
16
+
u8 lane_mask;
17
+
};
18
+
19
+
#define QMP_PHY_INIT_CFG(o, v) \
20
+
{ \
21
+
.offset = o, \
22
+
.val = v, \
23
+
.lane_mask = 0xff, \
24
+
}
25
+
26
+
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
27
+
{ \
28
+
.offset = o, \
29
+
.val = v, \
30
+
.lane_mask = l, \
31
+
}
32
+
33
+
static inline void qmp_configure_lane(void __iomem *base,
34
+
const struct qmp_phy_init_tbl tbl[],
35
+
int num,
36
+
u8 lane_mask)
37
+
{
38
+
int i;
39
+
const struct qmp_phy_init_tbl *t = tbl;
40
+
41
+
if (!t)
42
+
return;
43
+
44
+
for (i = 0; i < num; i++, t++) {
45
+
if (!(t->lane_mask & lane_mask))
46
+
continue;
47
+
48
+
writel(t->val, base + t->offset);
49
+
}
50
+
}
51
+
52
+
static inline void qmp_configure(void __iomem *base,
53
+
const struct qmp_phy_init_tbl tbl[],
54
+
int num)
55
+
{
56
+
qmp_configure_lane(base, tbl, num, 0xff);
57
+
}
58
+
59
+
#endif
+18
drivers/phy/qualcomm/phy-qcom-qmp-dp-com-v3.h
+18
drivers/phy/qualcomm/phy-qcom-qmp-dp-com-v3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_COM_V3_H_
7
+
#define QCOM_PHY_QMP_DP_COM_V3_H_
8
+
9
+
/* Only for QMP V3 & V4 PHY - DP COM registers */
10
+
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
11
+
#define QPHY_V3_DP_COM_SW_RESET 0x04
12
+
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
13
+
#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
14
+
#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
15
+
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
16
+
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
17
+
18
+
#endif
+21
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v3.h
+21
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_PHY_V3_H_
7
+
#define QCOM_PHY_QMP_DP_PHY_V3_H_
8
+
9
+
/* Only for QMP V3 PHY - DP PHY registers */
10
+
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
11
+
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
12
+
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
13
+
14
+
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
15
+
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
16
+
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
17
+
18
+
#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
19
+
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
20
+
21
+
#endif
+19
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v4.h
+19
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v4.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_PHY_V4_H_
7
+
#define QCOM_PHY_QMP_DP_PHY_V4_H_
8
+
9
+
/* Only for QMP V4 PHY - DP PHY registers */
10
+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
11
+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
12
+
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
13
+
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
14
+
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
15
+
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
16
+
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
17
+
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
18
+
19
+
#endif
+13
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v5.h
+13
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v5.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_PHY_V5_H_
7
+
#define QCOM_PHY_QMP_DP_PHY_V5_H_
8
+
9
+
/* Only for QMP V5 PHY - DP PHY registers */
10
+
#define QSERDES_V5_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
11
+
#define QSERDES_V5_DP_PHY_STATUS 0x0dc
12
+
13
+
#endif
+13
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v6.h
+13
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v6.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_PHY_V6_H_
7
+
#define QCOM_PHY_QMP_DP_PHY_V6_H_
8
+
9
+
/* Only for QMP V6 PHY - DP PHY registers */
10
+
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
11
+
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
12
+
13
+
#endif
+62
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h
+62
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_DP_PHY_H_
7
+
#define QCOM_PHY_QMP_DP_PHY_H_
8
+
9
+
/* QMP PHY - DP PHY registers */
10
+
#define QSERDES_DP_PHY_REVISION_ID0 0x000
11
+
#define QSERDES_DP_PHY_REVISION_ID1 0x004
12
+
#define QSERDES_DP_PHY_REVISION_ID2 0x008
13
+
#define QSERDES_DP_PHY_REVISION_ID3 0x00c
14
+
#define QSERDES_DP_PHY_CFG 0x010
15
+
#define QSERDES_DP_PHY_CFG_1 0x014
16
+
#define QSERDES_DP_PHY_PD_CTL 0x018
17
+
#define QSERDES_DP_PHY_MODE 0x01c
18
+
#define QSERDES_DP_PHY_AUX_CFG0 0x020
19
+
#define QSERDES_DP_PHY_AUX_CFG1 0x024
20
+
#define QSERDES_DP_PHY_AUX_CFG2 0x028
21
+
#define QSERDES_DP_PHY_AUX_CFG3 0x02c
22
+
#define QSERDES_DP_PHY_AUX_CFG4 0x030
23
+
#define QSERDES_DP_PHY_AUX_CFG5 0x034
24
+
#define QSERDES_DP_PHY_AUX_CFG6 0x038
25
+
#define QSERDES_DP_PHY_AUX_CFG7 0x03c
26
+
#define QSERDES_DP_PHY_AUX_CFG8 0x040
27
+
#define QSERDES_DP_PHY_AUX_CFG9 0x044
28
+
29
+
/* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */
30
+
# define QSERDES_V3_COM_BIAS_EN 0x0001
31
+
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
32
+
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
33
+
# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
34
+
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
35
+
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
36
+
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
37
+
38
+
/* QPHY_TX_TX_EMP_POST1_LVL bits */
39
+
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
40
+
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
41
+
42
+
/* QPHY_TX_TX_DRV_LVL bits */
43
+
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
44
+
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
45
+
46
+
/* QSERDES_DP_PHY_PD_CTL bits */
47
+
# define DP_PHY_PD_CTL_PWRDN 0x001
48
+
# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
49
+
# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
50
+
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
51
+
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
52
+
# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
53
+
# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
54
+
55
+
/* QPHY_DP_PHY_AUX_INTERRUPT_STATUS bits */
56
+
# define PHY_AUX_STOP_ERR_MASK 0x01
57
+
# define PHY_AUX_DEC_ERR_MASK 0x02
58
+
# define PHY_AUX_SYNC_ERR_MASK 0x04
59
+
# define PHY_AUX_ALIGN_ERR_MASK 0x08
60
+
# define PHY_AUX_REQ_ERR_MASK 0x10
61
+
62
+
#endif
+7
-63
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+7
-63
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
···
19
19
#include <linux/reset.h>
20
20
#include <linux/slab.h>
21
21
22
+
#include "phy-qcom-qmp-common.h"
23
+
22
24
#include "phy-qcom-qmp.h"
23
25
24
-
/* QPHY_SW_RESET bit */
25
-
#define SW_RESET BIT(0)
26
-
/* QPHY_POWER_DOWN_CONTROL */
27
-
#define SW_PWRDN BIT(0)
28
-
#define REFCLK_DRV_DSBL BIT(1)
29
26
/* QPHY_START_CONTROL bits */
30
-
#define SERDES_START BIT(0)
31
-
#define PCS_START BIT(1)
32
27
#define PLL_READY_GATE_EN BIT(3)
33
-
/* QPHY_PCS_STATUS bit */
34
-
#define PHYSTATUS BIT(6)
28
+
35
29
/* QPHY_COM_PCS_READY_STATUS bit */
36
30
#define PCS_READY BIT(0)
37
31
38
32
#define PHY_INIT_COMPLETE_TIMEOUT 10000
39
33
#define POWER_DOWN_DELAY_US_MIN 10
40
34
#define POWER_DOWN_DELAY_US_MAX 20
41
-
42
-
struct qmp_phy_init_tbl {
43
-
unsigned int offset;
44
-
unsigned int val;
45
-
/*
46
-
* mask of lanes for which this register is written
47
-
* for cases when second lane needs different values
48
-
*/
49
-
u8 lane_mask;
50
-
};
51
-
52
-
#define QMP_PHY_INIT_CFG(o, v) \
53
-
{ \
54
-
.offset = o, \
55
-
.val = v, \
56
-
.lane_mask = 0xff, \
57
-
}
58
-
59
-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
60
-
{ \
61
-
.offset = o, \
62
-
.val = v, \
63
-
.lane_mask = l, \
64
-
}
65
35
66
36
/* set of registers with offsets different per-PHY */
67
37
enum qphy_reg_layout {
···
277
307
.regs = pciephy_regs_layout,
278
308
};
279
309
280
-
static void qmp_pcie_msm8996_configure_lane(void __iomem *base,
281
-
const struct qmp_phy_init_tbl tbl[],
282
-
int num,
283
-
u8 lane_mask)
284
-
{
285
-
int i;
286
-
const struct qmp_phy_init_tbl *t = tbl;
287
-
288
-
if (!t)
289
-
return;
290
-
291
-
for (i = 0; i < num; i++, t++) {
292
-
if (!(t->lane_mask & lane_mask))
293
-
continue;
294
-
295
-
writel(t->val, base + t->offset);
296
-
}
297
-
}
298
-
299
-
static void qmp_pcie_msm8996_configure(void __iomem *base,
300
-
const struct qmp_phy_init_tbl tbl[],
301
-
int num)
302
-
{
303
-
qmp_pcie_msm8996_configure_lane(base, tbl, num, 0xff);
304
-
}
305
-
306
310
static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
307
311
{
308
312
struct qcom_qmp *qmp = qphy->qmp;
···
288
344
unsigned int val;
289
345
int ret;
290
346
291
-
qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num);
347
+
qmp_configure(serdes, serdes_tbl, serdes_tbl_num);
292
348
293
349
qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
294
350
qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
···
431
487
}
432
488
433
489
/* Tx, Rx, and PCS configurations */
434
-
qmp_pcie_msm8996_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
435
-
qmp_pcie_msm8996_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
436
-
qmp_pcie_msm8996_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
490
+
qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
491
+
qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
492
+
qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
437
493
438
494
/*
439
495
* Pull out PHY from POWER DOWN state.
+208
-80
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+208
-80
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
···
22
22
#include <linux/reset.h>
23
23
#include <linux/slab.h>
24
24
25
+
#include "phy-qcom-qmp-common.h"
26
+
25
27
#include "phy-qcom-qmp.h"
26
28
#include "phy-qcom-qmp-pcs-misc-v3.h"
27
29
#include "phy-qcom-qmp-pcs-pcie-v4.h"
···
34
32
#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
35
33
#include "phy-qcom-qmp-pcie-qhp.h"
36
34
37
-
/* QPHY_SW_RESET bit */
38
-
#define SW_RESET BIT(0)
39
-
/* QPHY_POWER_DOWN_CONTROL */
40
-
#define SW_PWRDN BIT(0)
41
-
#define REFCLK_DRV_DSBL BIT(1)
42
-
/* QPHY_START_CONTROL bits */
43
-
#define SERDES_START BIT(0)
44
-
#define PCS_START BIT(1)
45
-
/* QPHY_PCS_STATUS bit */
46
-
#define PHYSTATUS BIT(6)
47
-
#define PHYSTATUS_4_20 BIT(7)
48
-
49
35
#define PHY_INIT_COMPLETE_TIMEOUT 10000
50
-
51
-
struct qmp_phy_init_tbl {
52
-
unsigned int offset;
53
-
unsigned int val;
54
-
/*
55
-
* mask of lanes for which this register is written
56
-
* for cases when second lane needs different values
57
-
*/
58
-
u8 lane_mask;
59
-
};
60
-
61
-
#define QMP_PHY_INIT_CFG(o, v) \
62
-
{ \
63
-
.offset = o, \
64
-
.val = v, \
65
-
.lane_mask = 0xff, \
66
-
}
67
-
68
-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
69
-
{ \
70
-
.offset = o, \
71
-
.val = v, \
72
-
.lane_mask = l, \
73
-
}
74
36
75
37
/* set of registers with offsets different per-PHY */
76
38
enum qphy_reg_layout {
···
80
114
[QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
81
115
[QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
82
116
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
117
+
};
118
+
119
+
static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
120
+
[QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
121
+
[QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
122
+
[QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
123
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
83
124
};
84
125
85
126
static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
···
955
982
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
956
983
};
957
984
985
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {
986
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
987
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
988
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
989
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
990
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
991
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
992
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
993
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
994
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
995
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
996
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
997
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
998
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
999
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1000
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1001
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1002
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1003
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1004
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1005
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1006
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1007
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1008
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1009
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1010
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1011
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1012
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1013
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1014
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1015
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1016
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1017
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1018
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1019
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1020
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1021
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1022
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1023
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1024
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1025
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1026
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1027
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1028
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1029
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1030
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1031
+
};
1032
+
1033
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1034
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1035
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1036
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1037
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1038
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),
1039
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1040
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1041
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1042
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),
1043
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1044
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1045
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1046
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1047
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1048
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1049
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1050
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1051
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1052
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1053
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1054
+
};
1055
+
1056
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {
1057
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1058
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1059
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1060
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1061
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1062
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1063
+
};
1064
+
1065
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {
1066
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1067
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1068
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1069
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1070
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1071
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1072
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1073
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1074
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),
1075
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),
1076
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1077
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b),
1078
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1079
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1080
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1081
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1082
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1083
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1084
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1085
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1086
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1087
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1088
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1089
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1090
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1091
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),
1092
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),
1093
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1094
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1095
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),
1096
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1097
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1098
+
};
1099
+
1100
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {
1101
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1102
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
1103
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1104
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1105
+
};
1106
+
1107
+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1108
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1109
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1110
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1111
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1112
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1113
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1114
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1115
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1116
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1117
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1118
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1119
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1120
+
};
1121
+
958
1122
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
959
1123
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
960
1124
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
···
1857
1747
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
1858
1748
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
1859
1749
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
1860
-
QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
1750
+
QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
1861
1751
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
1862
1752
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
1863
1753
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
···
1877
1767
};
1878
1768
1879
1769
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1770
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
1771
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
1880
1772
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1881
1773
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1882
1774
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
···
1935
1823
1936
1824
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1937
1825
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1938
-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
1939
1826
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
1940
-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1941
-
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1827
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1828
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1942
1829
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1943
1830
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1944
1831
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
···
1954
1843
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1955
1844
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1956
1845
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1846
+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1957
1847
};
1958
1848
1959
1849
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
···
1967
1855
};
1968
1856
1969
1857
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
1970
-
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
1858
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1971
1859
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1860
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1972
1861
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1973
1862
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1974
1863
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1975
1864
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1976
1865
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
1866
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1977
1867
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1978
1868
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1979
1869
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
···
1997
1883
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
1998
1884
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1999
1885
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1886
+
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
2000
1887
};
2001
1888
2002
1889
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
1890
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2003
1891
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
2004
-
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
1892
+
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
2005
1893
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
2006
1894
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
2007
1895
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
···
2014
1898
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
2015
1899
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
2016
1900
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1901
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
1902
+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
2017
1903
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
2018
1904
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
2019
1905
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
···
3054
2936
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3055
2937
.vreg_list = qmp_phy_vreg_l,
3056
2938
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3057
-
.regs = pciephy_v5_regs_layout,
2939
+
.regs = pciephy_v6_regs_layout,
3058
2940
3059
2941
.pwrdn_ctrl = SW_PWRDN,
3060
2942
.phy_status = PHYSTATUS_4_20,
···
3187
3069
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3188
3070
.vreg_list = sm8550_qmp_phy_vreg_l,
3189
3071
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3190
-
.regs = pciephy_v5_regs_layout,
3072
+
.regs = pciephy_v6_regs_layout,
3191
3073
3192
3074
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3193
3075
.phy_status = PHYSTATUS_4_20,
···
3217
3099
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3218
3100
.vreg_list = sm8550_qmp_phy_vreg_l,
3219
3101
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3220
-
.regs = pciephy_v5_regs_layout,
3102
+
.regs = pciephy_v6_regs_layout,
3221
3103
3222
3104
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3223
3105
.phy_status = PHYSTATUS_4_20,
···
3301
3183
.phy_status = PHYSTATUS_4_20,
3302
3184
};
3303
3185
3304
-
static void qmp_pcie_configure_lane(void __iomem *base,
3305
-
const struct qmp_phy_init_tbl tbl[],
3306
-
int num,
3307
-
u8 lane_mask)
3308
-
{
3309
-
int i;
3310
-
const struct qmp_phy_init_tbl *t = tbl;
3186
+
static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
3187
+
.lanes = 2,
3311
3188
3312
-
if (!t)
3313
-
return;
3189
+
.offsets = &qmp_pcie_offsets_v6_20,
3314
3190
3315
-
for (i = 0; i < num; i++, t++) {
3316
-
if (!(t->lane_mask & lane_mask))
3317
-
continue;
3191
+
.tbls = {
3192
+
.serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl,
3193
+
.serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),
3194
+
.tx = x1e80100_qmp_gen4x2_pcie_tx_tbl,
3195
+
.tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),
3196
+
.rx = x1e80100_qmp_gen4x2_pcie_rx_tbl,
3197
+
.rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),
3198
+
.pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl,
3199
+
.pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),
3200
+
.pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,
3201
+
.pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),
3202
+
.ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,
3203
+
.ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),
3204
+
},
3205
+
.reset_list = sdm845_pciephy_reset_l,
3206
+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3207
+
.vreg_list = sm8550_qmp_phy_vreg_l,
3208
+
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3209
+
.regs = pciephy_v6_regs_layout,
3318
3210
3319
-
writel(t->val, base + t->offset);
3320
-
}
3321
-
}
3322
-
3323
-
static void qmp_pcie_configure(void __iomem *base,
3324
-
const struct qmp_phy_init_tbl tbl[],
3325
-
int num)
3326
-
{
3327
-
qmp_pcie_configure_lane(base, tbl, num, 0xff);
3328
-
}
3211
+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3212
+
.phy_status = PHYSTATUS_4_20,
3213
+
.has_nocsr_reset = true,
3214
+
};
3329
3215
3330
3216
static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3331
3217
{
···
3342
3220
tx4 = qmp->port_b + offs->tx2;
3343
3221
rx4 = qmp->port_b + offs->rx2;
3344
3222
3345
-
qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
3346
-
qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
3223
+
qmp_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
3224
+
qmp_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
3347
3225
3348
-
qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
3349
-
qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
3226
+
qmp_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
3227
+
qmp_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
3350
3228
}
3351
3229
3352
3230
static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
···
3364
3242
if (!tbls)
3365
3243
return;
3366
3244
3367
-
qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num);
3245
+
qmp_configure(serdes, tbls->serdes, tbls->serdes_num);
3368
3246
3369
-
qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
3370
-
qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
3247
+
qmp_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
3248
+
qmp_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
3371
3249
3372
3250
if (cfg->lanes >= 2) {
3373
-
qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
3374
-
qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
3251
+
qmp_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
3252
+
qmp_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
3375
3253
}
3376
3254
3377
-
qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
3378
-
qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
3255
+
qmp_configure(pcs, tbls->pcs, tbls->pcs_num);
3256
+
qmp_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
3379
3257
3380
3258
if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3381
-
qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
3259
+
qmp_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
3382
3260
qmp_pcie_init_port_b(qmp, tbls);
3383
3261
}
3384
3262
3385
-
qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
3263
+
qmp_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
3386
3264
}
3387
3265
3388
3266
static int qmp_pcie_init(struct phy *phy)
···
4007
3885
}, {
4008
3886
.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
4009
3887
.data = &sm8650_qmp_gen4x2_pciephy_cfg,
3888
+
}, {
3889
+
.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
3890
+
.data = &sm8550_qmp_gen3x2_pciephy_cfg,
3891
+
}, {
3892
+
.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
3893
+
.data = &x1e80100_qmp_gen4x2_pciephy_cfg,
4010
3894
},
4011
3895
{ },
4012
3896
};
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
···
7
7
#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
8
8
9
9
/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
10
+
#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4
11
+
#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4
10
12
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
11
13
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
12
14
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
···
12
12
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13
13
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14
14
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15
+
#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0
16
+
#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4
15
17
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16
18
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17
19
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
+20
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
+20
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2023, Linaro Limited
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_SGMII_H_
7
+
#define QCOM_PHY_QMP_PCS_SGMII_H_
8
+
9
+
#define QPHY_PCS_PHY_START 0x000
10
+
#define QPHY_PCS_POWER_DOWN_CONTROL 0x004
11
+
#define QPHY_PCS_SW_RESET 0x008
12
+
#define QPHY_PCS_LINE_RESET_TIME 0x00c
13
+
#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
14
+
#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
15
+
#define QPHY_PCS_PCS_READY_STATUS 0x094
16
+
#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
17
+
#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
18
+
#define QPHY_PCS_SGMII_MISC_CTRL8 0x118
19
+
20
+
#endif
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
···
19
19
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
20
20
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
21
21
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
22
+
#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
22
23
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
23
24
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
24
25
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
···
29
28
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
30
29
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
31
30
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
31
+
#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
32
32
33
33
#endif
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
···
7
7
#define QCOM_PHY_QMP_PCS_V6_20_H_
8
8
9
9
/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
10
+
#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
10
11
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
11
12
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
12
13
#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
···
60
60
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
61
61
#define QSERDES_V6_COM_PLL_IVCO 0xf4
62
62
#define QSERDES_V6_COM_PLL_IVCO_MODE1 0xf8
63
+
#define QSERDES_V6_COM_CMN_IETRIM 0xfc
64
+
#define QSERDES_V6_COM_CMN_IPTRIM 0x100
63
65
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
64
66
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
65
67
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
+8
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+8
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
···
15
15
16
16
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
17
17
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
18
+
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
18
19
#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
20
+
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
19
21
#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58
20
22
#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4
21
23
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
22
24
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
25
+
#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
26
+
#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
23
27
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
28
+
#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
24
29
#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
30
+
#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
25
31
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
26
32
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
27
33
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
···
39
33
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
40
34
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
41
35
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
36
+
#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
42
37
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
38
+
#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
43
39
44
40
#endif
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
···
23
23
#define QSERDES_V6_20_RX_DFE_1 0xac
24
24
#define QSERDES_V6_20_RX_DFE_2 0xb0
25
25
#define QSERDES_V6_20_RX_DFE_3 0xb4
26
+
#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4
27
+
#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0
26
28
#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
27
29
#define QSERDES_V6_20_RX_GM_CAL 0x10c
28
30
#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
+165
-140
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+165
-140
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
···
20
20
#include <linux/slab.h>
21
21
22
22
#include <ufs/unipro.h>
23
+
24
+
#include "phy-qcom-qmp-common.h"
25
+
23
26
#include "phy-qcom-qmp.h"
24
27
#include "phy-qcom-qmp-pcs-ufs-v2.h"
25
28
#include "phy-qcom-qmp-pcs-ufs-v3.h"
···
32
29
33
30
#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
34
31
35
-
/* QPHY_SW_RESET bit */
36
-
#define SW_RESET BIT(0)
37
-
/* QPHY_POWER_DOWN_CONTROL */
38
-
#define SW_PWRDN BIT(0)
39
-
/* QPHY_START_CONTROL bits */
40
-
#define SERDES_START BIT(0)
41
-
#define PCS_START BIT(1)
42
32
/* QPHY_PCS_READY_STATUS bit */
43
33
#define PCS_READY BIT(0)
44
34
45
35
#define PHY_INIT_COMPLETE_TIMEOUT 10000
46
36
47
-
struct qmp_phy_init_tbl {
48
-
unsigned int offset;
49
-
unsigned int val;
50
-
/*
51
-
* mask of lanes for which this register is written
52
-
* for cases when second lane needs different values
53
-
*/
54
-
u8 lane_mask;
55
-
};
56
-
57
-
#define QMP_PHY_INIT_CFG(o, v) \
58
-
{ \
59
-
.offset = o, \
60
-
.val = v, \
61
-
.lane_mask = 0xff, \
62
-
}
63
-
64
-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
65
-
{ \
66
-
.offset = o, \
67
-
.val = v, \
68
-
.lane_mask = l, \
69
-
}
37
+
#define NUM_OVERLAY 2
70
38
71
39
/* set of registers with offsets different per-PHY */
72
40
enum qphy_reg_layout {
···
728
754
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
729
755
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
730
756
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
731
-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
732
-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
733
757
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
734
758
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
735
-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
736
759
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
737
760
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
738
761
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
739
762
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
763
+
};
764
+
765
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
766
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
767
+
};
768
+
769
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
770
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
771
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
772
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
740
773
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
741
774
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
742
775
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
···
752
771
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
753
772
};
754
773
755
-
static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
756
-
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
774
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
775
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
776
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
777
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
778
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
757
779
};
758
780
759
781
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
760
782
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
761
783
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
784
+
};
785
+
786
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
762
787
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
763
788
};
764
789
765
790
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
766
791
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
767
-
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
768
792
769
793
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
770
794
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
···
785
799
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
786
800
};
787
801
802
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
803
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
804
+
};
805
+
806
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
807
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
808
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
809
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
810
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
811
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
812
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
813
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
814
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
815
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
816
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
817
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
818
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
819
+
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
820
+
};
821
+
788
822
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
789
823
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
790
824
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
791
825
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
792
-
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
793
826
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
827
+
};
828
+
829
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
830
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
794
831
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
795
832
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
833
+
};
834
+
835
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
836
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
837
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
838
+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
796
839
};
797
840
798
841
static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
···
904
889
int rx_num;
905
890
const struct qmp_phy_init_tbl *pcs;
906
891
int pcs_num;
892
+
/* Maximum supported Gear of this tbls */
893
+
u32 max_gear;
907
894
};
908
895
909
896
/* struct qmp_phy_cfg - per-PHY initialization config */
···
913
896
int lanes;
914
897
915
898
const struct qmp_ufs_offsets *offsets;
899
+
/* Maximum supported Gear of this config */
900
+
u32 max_supported_gear;
916
901
917
902
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
918
903
const struct qmp_phy_cfg_tbls tbls;
919
904
/* Additional sequence for HS Series B */
920
905
const struct qmp_phy_cfg_tbls tbls_hs_b;
921
-
/* Additional sequence for HS G4 */
922
-
const struct qmp_phy_cfg_tbls tbls_hs_g4;
906
+
/* Additional sequence for different HS Gears */
907
+
const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
923
908
924
-
/* clock ids to be requested */
925
-
const char * const *clk_list;
926
-
int num_clks;
927
909
/* regulators to be requested */
928
910
const char * const *vreg_list;
929
911
int num_vregs;
···
948
932
void __iomem *rx2;
949
933
950
934
struct clk_bulk_data *clks;
935
+
int num_clks;
951
936
struct regulator_bulk_data *vregs;
952
937
struct reset_control *ufs_reset;
953
938
···
981
964
readl(base + offset);
982
965
}
983
966
984
-
/* list of clocks required by phy */
985
-
static const char * const msm8996_ufs_phy_clk_l[] = {
986
-
"ref",
987
-
};
988
-
989
-
/* the primary usb3 phy on sm8250 doesn't have a ref clock */
990
-
static const char * const sm8450_ufs_phy_clk_l[] = {
991
-
"qref", "ref", "ref_aux",
992
-
};
993
-
994
-
static const char * const sdm845_ufs_phy_clk_l[] = {
995
-
"ref", "ref_aux",
996
-
};
997
-
998
967
/* list of regulators */
999
968
static const char * const qmp_phy_vreg_l[] = {
1000
969
"vdda-phy", "vdda-pll",
···
1008
1005
.lanes = 1,
1009
1006
1010
1007
.offsets = &qmp_ufs_offsets,
1008
+
.max_supported_gear = UFS_HS_G3,
1011
1009
1012
1010
.tbls = {
1013
1011
.serdes = msm8996_ufsphy_serdes,
···
1018
1014
.rx = msm8996_ufsphy_rx,
1019
1015
.rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
1020
1016
},
1021
-
1022
-
.clk_list = msm8996_ufs_phy_clk_l,
1023
-
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
1024
1017
1025
1018
.vreg_list = qmp_phy_vreg_l,
1026
1019
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
···
1031
1030
.lanes = 2,
1032
1031
1033
1032
.offsets = &qmp_ufs_offsets,
1033
+
.max_supported_gear = UFS_HS_G4,
1034
1034
1035
1035
.tbls = {
1036
1036
.serdes = sm8350_ufsphy_serdes,
···
1047
1045
.serdes = sm8350_ufsphy_hs_b_serdes,
1048
1046
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1049
1047
},
1050
-
.tbls_hs_g4 = {
1048
+
.tbls_hs_overlay[0] = {
1051
1049
.tx = sm8350_ufsphy_g4_tx,
1052
1050
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1053
1051
.rx = sm8350_ufsphy_g4_rx,
1054
1052
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1055
1053
.pcs = sm8350_ufsphy_g4_pcs,
1056
1054
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1055
+
.max_gear = UFS_HS_G4,
1057
1056
},
1058
-
.clk_list = sm8450_ufs_phy_clk_l,
1059
-
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1060
1057
.vreg_list = qmp_phy_vreg_l,
1061
1058
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1062
1059
.regs = ufsphy_v5_regs_layout,
···
1065
1064
.lanes = 2,
1066
1065
1067
1066
.offsets = &qmp_ufs_offsets,
1067
+
.max_supported_gear = UFS_HS_G4,
1068
1068
1069
1069
.tbls = {
1070
1070
.serdes = sm8150_ufsphy_serdes,
···
1081
1079
.serdes = sm8150_ufsphy_hs_b_serdes,
1082
1080
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1083
1081
},
1084
-
.tbls_hs_g4 = {
1082
+
.tbls_hs_overlay[0] = {
1085
1083
.tx = sm8250_ufsphy_hs_g4_tx,
1086
1084
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1087
1085
.rx = sc7280_ufsphy_hs_g4_rx,
1088
1086
.rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1089
1087
.pcs = sm8150_ufsphy_hs_g4_pcs,
1090
1088
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1089
+
.max_gear = UFS_HS_G4,
1091
1090
},
1092
-
.clk_list = sm8450_ufs_phy_clk_l,
1093
-
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1094
1091
.vreg_list = qmp_phy_vreg_l,
1095
1092
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1096
1093
.regs = ufsphy_v4_regs_layout,
···
1099
1098
.lanes = 2,
1100
1099
1101
1100
.offsets = &qmp_ufs_offsets,
1101
+
.max_supported_gear = UFS_HS_G4,
1102
1102
1103
1103
.tbls = {
1104
1104
.serdes = sm8350_ufsphy_serdes,
···
1115
1113
.serdes = sm8350_ufsphy_hs_b_serdes,
1116
1114
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1117
1115
},
1118
-
.tbls_hs_g4 = {
1116
+
.tbls_hs_overlay[0] = {
1119
1117
.tx = sm8350_ufsphy_g4_tx,
1120
1118
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1121
1119
.rx = sm8350_ufsphy_g4_rx,
1122
1120
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1123
1121
.pcs = sm8350_ufsphy_g4_pcs,
1124
1122
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1123
+
.max_gear = UFS_HS_G4,
1125
1124
},
1126
-
.clk_list = sdm845_ufs_phy_clk_l,
1127
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1128
1125
.vreg_list = qmp_phy_vreg_l,
1129
1126
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1130
1127
.regs = ufsphy_v5_regs_layout,
···
1133
1132
.lanes = 2,
1134
1133
1135
1134
.offsets = &qmp_ufs_offsets,
1135
+
.max_supported_gear = UFS_HS_G3,
1136
1136
1137
1137
.tbls = {
1138
1138
.serdes = sdm845_ufsphy_serdes,
···
1149
1147
.serdes = sdm845_ufsphy_hs_b_serdes,
1150
1148
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1151
1149
},
1152
-
.clk_list = sdm845_ufs_phy_clk_l,
1153
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1154
1150
.vreg_list = qmp_phy_vreg_l,
1155
1151
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1156
1152
.regs = ufsphy_v3_regs_layout,
···
1160
1160
.lanes = 1,
1161
1161
1162
1162
.offsets = &qmp_ufs_offsets,
1163
+
.max_supported_gear = UFS_HS_G3,
1163
1164
1164
1165
.tbls = {
1165
1166
.serdes = sm6115_ufsphy_serdes,
···
1176
1175
.serdes = sm6115_ufsphy_hs_b_serdes,
1177
1176
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1178
1177
},
1179
-
.clk_list = sdm845_ufs_phy_clk_l,
1180
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1181
1178
.vreg_list = qmp_phy_vreg_l,
1182
1179
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1183
1180
.regs = ufsphy_v2_regs_layout,
···
1187
1188
.lanes = 1,
1188
1189
1189
1190
.offsets = &qmp_ufs_offsets,
1191
+
.max_supported_gear = UFS_HS_G3,
1190
1192
1191
1193
.tbls = {
1192
1194
.serdes = sdm845_ufsphy_serdes,
···
1203
1203
.serdes = sdm845_ufsphy_hs_b_serdes,
1204
1204
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1205
1205
},
1206
-
.clk_list = sdm845_ufs_phy_clk_l,
1207
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1208
1206
.vreg_list = qmp_phy_vreg_l,
1209
1207
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1210
1208
.regs = ufsphy_v3_regs_layout,
···
1214
1216
.lanes = 2,
1215
1217
1216
1218
.offsets = &qmp_ufs_offsets,
1219
+
.max_supported_gear = UFS_HS_G4,
1217
1220
1218
1221
.tbls = {
1219
1222
.serdes = sm8150_ufsphy_serdes,
···
1230
1231
.serdes = sm8150_ufsphy_hs_b_serdes,
1231
1232
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1232
1233
},
1233
-
.tbls_hs_g4 = {
1234
+
.tbls_hs_overlay[0] = {
1234
1235
.tx = sm8150_ufsphy_hs_g4_tx,
1235
1236
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1236
1237
.rx = sm8150_ufsphy_hs_g4_rx,
1237
1238
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1238
1239
.pcs = sm8150_ufsphy_hs_g4_pcs,
1239
1240
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1241
+
.max_gear = UFS_HS_G4,
1240
1242
},
1241
-
.clk_list = sdm845_ufs_phy_clk_l,
1242
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1243
1243
.vreg_list = qmp_phy_vreg_l,
1244
1244
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1245
1245
.regs = ufsphy_v4_regs_layout,
···
1248
1250
.lanes = 2,
1249
1251
1250
1252
.offsets = &qmp_ufs_offsets,
1253
+
.max_supported_gear = UFS_HS_G4,
1251
1254
1252
1255
.tbls = {
1253
1256
.serdes = sm8150_ufsphy_serdes,
···
1264
1265
.serdes = sm8150_ufsphy_hs_b_serdes,
1265
1266
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1266
1267
},
1267
-
.tbls_hs_g4 = {
1268
+
.tbls_hs_overlay[0] = {
1268
1269
.tx = sm8250_ufsphy_hs_g4_tx,
1269
1270
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1270
1271
.rx = sm8250_ufsphy_hs_g4_rx,
1271
1272
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1272
1273
.pcs = sm8150_ufsphy_hs_g4_pcs,
1273
1274
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1275
+
.max_gear = UFS_HS_G4,
1274
1276
},
1275
-
.clk_list = sdm845_ufs_phy_clk_l,
1276
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1277
1277
.vreg_list = qmp_phy_vreg_l,
1278
1278
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1279
1279
.regs = ufsphy_v4_regs_layout,
···
1282
1284
.lanes = 2,
1283
1285
1284
1286
.offsets = &qmp_ufs_offsets,
1287
+
.max_supported_gear = UFS_HS_G4,
1285
1288
1286
1289
.tbls = {
1287
1290
.serdes = sm8350_ufsphy_serdes,
···
1298
1299
.serdes = sm8350_ufsphy_hs_b_serdes,
1299
1300
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1300
1301
},
1301
-
.tbls_hs_g4 = {
1302
+
.tbls_hs_overlay[0] = {
1302
1303
.tx = sm8350_ufsphy_g4_tx,
1303
1304
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1304
1305
.rx = sm8350_ufsphy_g4_rx,
1305
1306
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1306
1307
.pcs = sm8350_ufsphy_g4_pcs,
1307
1308
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1309
+
.max_gear = UFS_HS_G4,
1308
1310
},
1309
-
.clk_list = sdm845_ufs_phy_clk_l,
1310
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1311
1311
.vreg_list = qmp_phy_vreg_l,
1312
1312
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1313
1313
.regs = ufsphy_v5_regs_layout,
···
1316
1318
.lanes = 2,
1317
1319
1318
1320
.offsets = &qmp_ufs_offsets,
1321
+
.max_supported_gear = UFS_HS_G4,
1319
1322
1320
1323
.tbls = {
1321
1324
.serdes = sm8350_ufsphy_serdes,
···
1332
1333
.serdes = sm8350_ufsphy_hs_b_serdes,
1333
1334
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1334
1335
},
1335
-
.tbls_hs_g4 = {
1336
+
.tbls_hs_overlay[0] = {
1336
1337
.tx = sm8350_ufsphy_g4_tx,
1337
1338
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1338
1339
.rx = sm8350_ufsphy_g4_rx,
1339
1340
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1340
1341
.pcs = sm8350_ufsphy_g4_pcs,
1341
1342
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1343
+
.max_gear = UFS_HS_G4,
1342
1344
},
1343
-
.clk_list = sm8450_ufs_phy_clk_l,
1344
-
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1345
1345
.vreg_list = qmp_phy_vreg_l,
1346
1346
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1347
1347
.regs = ufsphy_v5_regs_layout,
···
1350
1352
.lanes = 2,
1351
1353
1352
1354
.offsets = &qmp_ufs_offsets_v6,
1355
+
.max_supported_gear = UFS_HS_G5,
1353
1356
1354
1357
.tbls = {
1355
1358
.serdes = sm8550_ufsphy_serdes,
···
1366
1367
.serdes = sm8550_ufsphy_hs_b_serdes,
1367
1368
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1368
1369
},
1369
-
.clk_list = sdm845_ufs_phy_clk_l,
1370
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1370
+
.tbls_hs_overlay[0] = {
1371
+
.serdes = sm8550_ufsphy_g4_serdes,
1372
+
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
1373
+
.tx = sm8550_ufsphy_g4_tx,
1374
+
.tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1375
+
.rx = sm8550_ufsphy_g4_rx,
1376
+
.rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1377
+
.pcs = sm8550_ufsphy_g4_pcs,
1378
+
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
1379
+
.max_gear = UFS_HS_G4,
1380
+
},
1381
+
.tbls_hs_overlay[1] = {
1382
+
.serdes = sm8550_ufsphy_g5_serdes,
1383
+
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
1384
+
.rx = sm8550_ufsphy_g5_rx,
1385
+
.rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
1386
+
.pcs = sm8550_ufsphy_g5_pcs,
1387
+
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
1388
+
.max_gear = UFS_HS_G5,
1389
+
},
1371
1390
.vreg_list = qmp_phy_vreg_l,
1372
1391
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1373
1392
.regs = ufsphy_v6_regs_layout,
···
1395
1378
.lanes = 2,
1396
1379
1397
1380
.offsets = &qmp_ufs_offsets_v6,
1381
+
.max_supported_gear = UFS_HS_G5,
1398
1382
1399
1383
.tbls = {
1400
1384
.serdes = sm8650_ufsphy_serdes,
···
1407
1389
.pcs = sm8650_ufsphy_pcs,
1408
1390
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs),
1409
1391
},
1410
-
.clk_list = sdm845_ufs_phy_clk_l,
1411
-
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1412
1392
.vreg_list = qmp_phy_vreg_l,
1413
1393
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1414
1394
.regs = ufsphy_v6_regs_layout,
1415
1395
};
1416
1396
1417
-
static void qmp_ufs_configure_lane(void __iomem *base,
1418
-
const struct qmp_phy_init_tbl tbl[],
1419
-
int num,
1420
-
u8 lane_mask)
1421
-
{
1422
-
int i;
1423
-
const struct qmp_phy_init_tbl *t = tbl;
1424
-
1425
-
if (!t)
1426
-
return;
1427
-
1428
-
for (i = 0; i < num; i++, t++) {
1429
-
if (!(t->lane_mask & lane_mask))
1430
-
continue;
1431
-
1432
-
writel(t->val, base + t->offset);
1433
-
}
1434
-
}
1435
-
1436
-
static void qmp_ufs_configure(void __iomem *base,
1437
-
const struct qmp_phy_init_tbl tbl[],
1438
-
int num)
1439
-
{
1440
-
qmp_ufs_configure_lane(base, tbl, num, 0xff);
1441
-
}
1442
-
1443
1397
static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1444
1398
{
1445
1399
void __iomem *serdes = qmp->serdes;
1446
1400
1447
-
qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
1401
+
qmp_configure(serdes, tbls->serdes, tbls->serdes_num);
1448
1402
}
1449
1403
1450
1404
static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
···
1425
1435
void __iomem *tx = qmp->tx;
1426
1436
void __iomem *rx = qmp->rx;
1427
1437
1428
-
qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1429
-
qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1438
+
qmp_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1439
+
qmp_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1430
1440
1431
1441
if (cfg->lanes >= 2) {
1432
-
qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1433
-
qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1442
+
qmp_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1443
+
qmp_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1434
1444
}
1435
1445
}
1436
1446
···
1438
1448
{
1439
1449
void __iomem *pcs = qmp->pcs;
1440
1450
1441
-
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
1451
+
qmp_configure(pcs, tbls->pcs, tbls->pcs_num);
1452
+
}
1453
+
1454
+
static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1455
+
{
1456
+
u32 max_gear, floor_max_gear = cfg->max_supported_gear;
1457
+
int idx, ret = -EINVAL;
1458
+
1459
+
for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
1460
+
max_gear = cfg->tbls_hs_overlay[idx].max_gear;
1461
+
1462
+
/* Skip if the table is not available */
1463
+
if (max_gear == 0)
1464
+
continue;
1465
+
1466
+
/* Direct matching, bail */
1467
+
if (qmp->submode == max_gear)
1468
+
return idx;
1469
+
1470
+
/* If no direct matching, the lowest gear is the best matching */
1471
+
if (max_gear < floor_max_gear) {
1472
+
ret = idx;
1473
+
floor_max_gear = max_gear;
1474
+
}
1475
+
}
1476
+
1477
+
return ret;
1442
1478
}
1443
1479
1444
1480
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1445
1481
{
1482
+
int i;
1483
+
1446
1484
qmp_ufs_serdes_init(qmp, &cfg->tbls);
1485
+
qmp_ufs_lanes_init(qmp, &cfg->tbls);
1486
+
qmp_ufs_pcs_init(qmp, &cfg->tbls);
1487
+
1488
+
i = qmp_ufs_get_gear_overlay(qmp, cfg);
1489
+
if (i >= 0) {
1490
+
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
1491
+
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
1492
+
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
1493
+
}
1494
+
1447
1495
if (qmp->mode == PHY_MODE_UFS_HS_B)
1448
1496
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1449
-
qmp_ufs_lanes_init(qmp, &cfg->tbls);
1450
-
if (qmp->submode == UFS_HS_G4)
1451
-
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
1452
-
qmp_ufs_pcs_init(qmp, &cfg->tbls);
1453
-
if (qmp->submode == UFS_HS_G4)
1454
-
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
1455
1497
}
1456
1498
1457
1499
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
···
1498
1476
return ret;
1499
1477
}
1500
1478
1501
-
ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1479
+
ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1502
1480
if (ret)
1503
1481
goto err_disable_regulators;
1504
1482
···
1518
1496
1519
1497
reset_control_assert(qmp->ufs_reset);
1520
1498
1521
-
clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1499
+
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1522
1500
1523
1501
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1524
1502
···
1655
1633
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1656
1634
{
1657
1635
struct qmp_ufs *qmp = phy_get_drvdata(phy);
1636
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
1637
+
1638
+
if (submode > cfg->max_supported_gear || submode == 0) {
1639
+
dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
1640
+
return -EINVAL;
1641
+
}
1658
1642
1659
1643
qmp->mode = mode;
1660
1644
qmp->submode = submode;
···
1694
1666
1695
1667
static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
1696
1668
{
1697
-
const struct qmp_phy_cfg *cfg = qmp->cfg;
1698
1669
struct device *dev = qmp->dev;
1699
-
int num = cfg->num_clks;
1700
-
int i;
1701
1670
1702
-
qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1703
-
if (!qmp->clks)
1704
-
return -ENOMEM;
1671
+
qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks);
1672
+
if (qmp->num_clks < 0)
1673
+
return qmp->num_clks;
1705
1674
1706
-
for (i = 0; i < num; i++)
1707
-
qmp->clks[i].id = cfg->clk_list[i];
1708
-
1709
-
return devm_clk_bulk_get(dev, num, qmp->clks);
1675
+
return 0;
1710
1676
}
1711
1677
1712
1678
static void qmp_ufs_clk_release_provider(void *res)
···
1902
1880
}, {
1903
1881
.compatible = "qcom,sa8775p-qmp-ufs-phy",
1904
1882
.data = &sa8775p_ufsphy_cfg,
1883
+
}, {
1884
+
.compatible = "qcom,sc7180-qmp-ufs-phy",
1885
+
.data = &sm7150_ufsphy_cfg,
1905
1886
}, {
1906
1887
.compatible = "qcom,sc7280-qmp-ufs-phy",
1907
1888
.data = &sc7280_ufsphy_cfg,
+11
-65
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+11
-65
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
···
25
25
#include "phy-qcom-qmp-pcs-usb-v4.h"
26
26
#include "phy-qcom-qmp-pcs-usb-v5.h"
27
27
28
-
/* QPHY_SW_RESET bit */
29
-
#define SW_RESET BIT(0)
30
-
/* QPHY_POWER_DOWN_CONTROL */
31
-
#define SW_PWRDN BIT(0)
32
-
/* QPHY_START_CONTROL bits */
33
-
#define SERDES_START BIT(0)
34
-
#define PCS_START BIT(1)
35
-
/* QPHY_PCS_STATUS bit */
36
-
#define PHYSTATUS BIT(6)
28
+
#include "phy-qcom-qmp-dp-com-v3.h"
37
29
38
30
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
39
31
/* DP PHY soft reset */
···
40
48
/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
41
49
#define USB3_MODE BIT(0) /* enables USB3 mode */
42
50
#define DP_MODE BIT(1) /* enables DP mode */
43
-
44
-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
45
-
#define ARCVR_DTCT_EN BIT(0)
46
-
#define ALFPS_DTCT_EN BIT(1)
47
-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
48
-
49
-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
50
-
#define IRQ_CLEAR BIT(0)
51
-
52
-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
53
-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
54
51
55
52
#define PHY_INIT_COMPLETE_TIMEOUT 10000
56
53
···
488
507
489
508
/* struct qmp_phy_cfg - per-PHY initialization config */
490
509
struct qmp_phy_cfg {
491
-
int lanes;
492
-
493
510
const struct qmp_usb_legacy_offsets *offsets;
494
511
495
512
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
···
600
621
};
601
622
602
623
static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
603
-
.lanes = 2,
604
-
605
624
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
606
625
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
607
626
.tx_tbl = qmp_v3_usb3_tx_tbl,
···
618
641
};
619
642
620
643
static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
621
-
.lanes = 2,
622
-
623
644
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
624
645
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
625
646
.tx_tbl = qmp_v3_usb3_tx_tbl,
···
636
661
};
637
662
638
663
static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
639
-
.lanes = 2,
640
-
641
664
.serdes_tbl = sm8150_usb3_serdes_tbl,
642
665
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
643
666
.tx_tbl = sm8150_usb3_tx_tbl,
···
657
684
};
658
685
659
686
static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
660
-
.lanes = 2,
661
-
662
687
.serdes_tbl = sm8150_usb3_serdes_tbl,
663
688
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
664
689
.tx_tbl = sm8250_usb3_tx_tbl,
···
678
707
};
679
708
680
709
static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
681
-
.lanes = 2,
682
-
683
710
.serdes_tbl = sm8150_usb3_serdes_tbl,
684
711
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
685
712
.tx_tbl = sm8350_usb3_tx_tbl,
···
843
874
qmp_usb_legacy_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
844
875
qmp_usb_legacy_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
845
876
846
-
if (cfg->lanes >= 2) {
847
-
qmp_usb_legacy_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
848
-
qmp_usb_legacy_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
849
-
}
877
+
qmp_usb_legacy_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
878
+
qmp_usb_legacy_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
850
879
851
880
qmp_usb_legacy_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
852
881
···
1147
1180
return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
1148
1181
}
1149
1182
1150
-
static void __iomem *qmp_usb_legacy_iomap(struct device *dev, struct device_node *np,
1151
-
int index, bool exclusive)
1152
-
{
1153
-
struct resource res;
1154
-
1155
-
if (!exclusive) {
1156
-
if (of_address_to_resource(np, index, &res))
1157
-
return IOMEM_ERR_PTR(-EINVAL);
1158
-
1159
-
return devm_ioremap(dev, res.start, resource_size(&res));
1160
-
}
1161
-
1162
-
return devm_of_iomap(dev, np, index, NULL);
1163
-
}
1164
-
1165
1183
static int qmp_usb_legacy_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
1166
1184
{
1167
1185
struct platform_device *pdev = to_platform_device(qmp->dev);
1168
1186
const struct qmp_phy_cfg *cfg = qmp->cfg;
1169
1187
struct device *dev = qmp->dev;
1170
-
bool exclusive = true;
1171
1188
1172
1189
qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1173
1190
if (IS_ERR(qmp->serdes))
···
1175
1224
if (IS_ERR(qmp->rx))
1176
1225
return PTR_ERR(qmp->rx);
1177
1226
1178
-
qmp->pcs = qmp_usb_legacy_iomap(dev, np, 2, exclusive);
1227
+
qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
1179
1228
if (IS_ERR(qmp->pcs))
1180
1229
return PTR_ERR(qmp->pcs);
1181
1230
1182
1231
if (cfg->pcs_usb_offset)
1183
1232
qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
1184
1233
1185
-
if (cfg->lanes >= 2) {
1186
-
qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1187
-
if (IS_ERR(qmp->tx2))
1188
-
return PTR_ERR(qmp->tx2);
1234
+
qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1235
+
if (IS_ERR(qmp->tx2))
1236
+
return PTR_ERR(qmp->tx2);
1189
1237
1190
-
qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1191
-
if (IS_ERR(qmp->rx2))
1192
-
return PTR_ERR(qmp->rx2);
1238
+
qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1239
+
if (IS_ERR(qmp->rx2))
1240
+
return PTR_ERR(qmp->rx2);
1193
1241
1194
-
qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1195
-
} else {
1196
-
qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
1197
-
}
1198
-
1242
+
qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1199
1243
if (IS_ERR(qmp->pcs_misc)) {
1200
1244
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1201
1245
qmp->pcs_misc = NULL;
+8
-414
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+8
-414
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
···
19
19
#include <linux/reset.h>
20
20
#include <linux/slab.h>
21
21
22
+
#include "phy-qcom-qmp-common.h"
23
+
22
24
#include "phy-qcom-qmp.h"
23
25
#include "phy-qcom-qmp-pcs-misc-v3.h"
24
26
#include "phy-qcom-qmp-pcs-misc-v4.h"
···
29
27
#include "phy-qcom-qmp-pcs-usb-v6.h"
30
28
#include "phy-qcom-qmp-pcs-usb-v7.h"
31
29
32
-
/* QPHY_SW_RESET bit */
33
-
#define SW_RESET BIT(0)
34
-
/* QPHY_POWER_DOWN_CONTROL */
35
-
#define SW_PWRDN BIT(0)
36
-
/* QPHY_START_CONTROL bits */
37
-
#define SERDES_START BIT(0)
38
-
#define PCS_START BIT(1)
39
-
/* QPHY_PCS_STATUS bit */
40
-
#define PHYSTATUS BIT(6)
41
-
42
-
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
43
-
/* DP PHY soft reset */
44
-
#define SW_DPPHY_RESET BIT(0)
45
-
/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46
-
#define SW_DPPHY_RESET_MUX BIT(1)
47
-
/* USB3 PHY soft reset */
48
-
#define SW_USB3PHY_RESET BIT(2)
49
-
/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
50
-
#define SW_USB3PHY_RESET_MUX BIT(3)
51
-
52
-
/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
53
-
#define USB3_MODE BIT(0) /* enables USB3 mode */
54
-
#define DP_MODE BIT(1) /* enables DP mode */
55
-
56
-
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
57
-
#define ARCVR_DTCT_EN BIT(0)
58
-
#define ALFPS_DTCT_EN BIT(1)
59
-
#define ARCVR_DTCT_EVENT_SEL BIT(4)
60
-
61
-
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
62
-
#define IRQ_CLEAR BIT(0)
63
-
64
-
/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
65
-
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
66
-
67
30
#define PHY_INIT_COMPLETE_TIMEOUT 10000
68
-
69
-
struct qmp_phy_init_tbl {
70
-
unsigned int offset;
71
-
unsigned int val;
72
-
/*
73
-
* mask of lanes for which this register is written
74
-
* for cases when second lane needs different values
75
-
*/
76
-
u8 lane_mask;
77
-
};
78
-
79
-
#define QMP_PHY_INIT_CFG(o, v) \
80
-
{ \
81
-
.offset = o, \
82
-
.val = v, \
83
-
.lane_mask = 0xff, \
84
-
}
85
-
86
-
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
87
-
{ \
88
-
.offset = o, \
89
-
.val = v, \
90
-
.lane_mask = l, \
91
-
}
92
31
93
32
/* set of registers with offsets different per-PHY */
94
33
enum qphy_reg_layout {
···
62
119
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
63
120
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
64
121
[QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
65
-
};
66
-
67
-
static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
68
-
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
69
-
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
70
-
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
71
-
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
72
-
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
73
-
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
74
122
};
75
123
76
124
static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
···
446
512
447
513
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
448
514
QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
449
-
};
450
-
451
-
static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
452
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
453
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
454
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
455
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
456
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
457
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
458
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
459
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
460
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
461
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
462
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
463
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
464
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
465
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
466
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
467
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
468
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
469
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
470
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
471
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
472
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
473
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
474
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
475
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
476
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
477
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
478
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
479
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
480
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
481
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
482
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
483
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
484
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
485
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
486
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
487
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
488
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
489
-
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
490
-
};
491
-
492
-
static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
493
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
494
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
495
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
496
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
497
-
};
498
-
499
-
static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
500
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
501
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
502
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
503
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
504
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
505
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
506
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
507
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
508
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
509
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
510
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
511
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
512
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
513
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
514
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
515
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
516
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
517
-
};
518
-
519
-
static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
520
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
521
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
522
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
523
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
524
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
525
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
526
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
527
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
528
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
529
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
530
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
531
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
532
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
533
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
534
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
535
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
536
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
537
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
538
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
539
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
540
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
541
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
542
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
543
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
544
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
545
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
546
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
547
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
548
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
549
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
550
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
551
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
552
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
553
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
554
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
555
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
556
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
557
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
558
515
};
559
516
560
517
static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
···
914
1089
QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
915
1090
};
916
1091
917
-
static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
918
-
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
919
-
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
920
-
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
921
-
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
922
-
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
923
-
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
924
-
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
925
-
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
926
-
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
927
-
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
928
-
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
929
-
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
930
-
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
931
-
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
932
-
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
933
-
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
934
-
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
935
-
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
936
-
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
937
-
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
938
-
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
939
-
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
940
-
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
941
-
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
942
-
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
943
-
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
944
-
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
945
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
946
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
947
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
948
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
949
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
950
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
951
-
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
952
-
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
953
-
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
954
-
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
955
-
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
956
-
};
957
-
958
-
static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
959
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
960
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
961
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
962
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
963
-
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
964
-
};
965
-
966
-
static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
967
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
968
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
969
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
970
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
971
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
972
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
973
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
974
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
975
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
976
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
977
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
978
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
979
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
980
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
981
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
982
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
983
-
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
984
-
};
985
-
986
-
static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
987
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
988
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
989
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
990
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
991
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
992
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
993
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
994
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
995
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
996
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
997
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
998
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
999
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1000
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1001
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1002
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1003
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1004
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1005
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1006
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1007
-
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1008
-
};
1009
-
1010
1092
static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1011
1093
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1012
1094
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
···
1180
1448
u16 pcs_usb;
1181
1449
u16 tx;
1182
1450
u16 rx;
1183
-
/* for PHYs with >= 2 lanes */
1184
-
u16 tx2;
1185
-
u16 rx2;
1186
1451
};
1187
1452
1188
1453
/* struct qmp_phy_cfg - per-PHY initialization config */
1189
1454
struct qmp_phy_cfg {
1190
-
int lanes;
1191
-
1192
1455
const struct qmp_usb_offsets *offsets;
1193
1456
1194
1457
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
···
1223
1496
void __iomem *pcs_usb;
1224
1497
void __iomem *tx;
1225
1498
void __iomem *rx;
1226
-
void __iomem *tx2;
1227
-
void __iomem *rx2;
1228
1499
1229
1500
struct clk *pipe_clk;
1230
1501
struct clk_bulk_data *clks;
···
1304
1579
.rx = 0x400,
1305
1580
};
1306
1581
1307
-
static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = {
1308
-
.serdes = 0x0,
1309
-
.pcs = 0xc00,
1310
-
.pcs_misc = 0xa00,
1311
-
.tx = 0x200,
1312
-
.rx = 0x400,
1313
-
.tx2 = 0x600,
1314
-
.rx2 = 0x800,
1315
-
};
1316
-
1317
1582
static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1318
1583
.serdes = 0,
1319
1584
.pcs = 0x0800,
···
1337
1622
};
1338
1623
1339
1624
static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
1340
-
.lanes = 1,
1341
-
1342
1625
.offsets = &qmp_usb_offsets_v3,
1343
1626
1344
1627
.serdes_tbl = ipq9574_usb3_serdes_tbl,
···
1353
1640
};
1354
1641
1355
1642
static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1356
-
.lanes = 1,
1357
-
1358
1643
.offsets = &qmp_usb_offsets_v3,
1359
1644
1360
1645
.serdes_tbl = ipq8074_usb3_serdes_tbl,
···
1369
1658
};
1370
1659
1371
1660
static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1372
-
.lanes = 1,
1373
-
1374
1661
.offsets = &qmp_usb_offsets_ipq9574,
1375
1662
1376
1663
.serdes_tbl = ipq9574_usb3_serdes_tbl,
···
1385
1676
};
1386
1677
1387
1678
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1388
-
.lanes = 1,
1389
-
1390
1679
.offsets = &qmp_usb_offsets_v3_msm8996,
1391
1680
1392
1681
.serdes_tbl = msm8996_usb3_serdes_tbl,
···
1401
1694
};
1402
1695
1403
1696
static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1404
-
.lanes = 1,
1405
-
1406
1697
.offsets = &qmp_usb_offsets_v5,
1407
1698
1408
1699
.serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
···
1419
1714
};
1420
1715
1421
1716
static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1422
-
.lanes = 1,
1423
-
1424
1717
.offsets = &qmp_usb_offsets_v5,
1425
1718
1426
1719
.serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
···
1437
1734
};
1438
1735
1439
1736
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1440
-
.lanes = 1,
1441
-
1442
1737
.offsets = &qmp_usb_offsets_v3,
1443
1738
1444
1739
.serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
···
1454
1753
.has_pwrdn_delay = true,
1455
1754
};
1456
1755
1457
-
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1458
-
.lanes = 2,
1459
-
1460
-
.offsets = &qmp_usb_offsets_v3_qcm2290,
1461
-
1462
-
.serdes_tbl = msm8998_usb3_serdes_tbl,
1463
-
.serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1464
-
.tx_tbl = msm8998_usb3_tx_tbl,
1465
-
.tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1466
-
.rx_tbl = msm8998_usb3_rx_tbl,
1467
-
.rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1468
-
.pcs_tbl = msm8998_usb3_pcs_tbl,
1469
-
.pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1470
-
.vreg_list = qmp_phy_vreg_l,
1471
-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1472
-
.regs = qmp_v3_usb3phy_regs_layout,
1473
-
};
1474
-
1475
1756
static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1476
-
.lanes = 1,
1477
-
1478
1757
.offsets = &qmp_usb_offsets_v4,
1479
1758
1480
1759
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
···
1476
1795
};
1477
1796
1478
1797
static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1479
-
.lanes = 1,
1480
-
1481
1798
.offsets = &qmp_usb_offsets_v4,
1482
1799
1483
1800
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
···
1497
1818
};
1498
1819
1499
1820
static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1500
-
.lanes = 1,
1501
-
1502
1821
.offsets = &qmp_usb_offsets_v4,
1503
1822
1504
1823
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
···
1518
1841
};
1519
1842
1520
1843
static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1521
-
.lanes = 1,
1522
-
1523
1844
.offsets = &qmp_usb_offsets_v5,
1524
1845
1525
1846
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
···
1539
1864
};
1540
1865
1541
1866
static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
1542
-
.lanes = 1,
1543
1867
.offsets = &qmp_usb_offsets_v6,
1544
1868
1545
1869
.serdes_tbl = sdx75_usb3_uniphy_serdes_tbl,
···
1560
1886
};
1561
1887
1562
1888
static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1563
-
.lanes = 1,
1564
-
1565
1889
.offsets = &qmp_usb_offsets_v5,
1566
1890
1567
1891
.serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
···
1580
1908
.has_pwrdn_delay = true,
1581
1909
};
1582
1910
1583
-
static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1584
-
.lanes = 2,
1585
-
1586
-
.offsets = &qmp_usb_offsets_v3_qcm2290,
1587
-
1588
-
.serdes_tbl = qcm2290_usb3_serdes_tbl,
1589
-
.serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1590
-
.tx_tbl = qcm2290_usb3_tx_tbl,
1591
-
.tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1592
-
.rx_tbl = qcm2290_usb3_rx_tbl,
1593
-
.rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1594
-
.pcs_tbl = qcm2290_usb3_pcs_tbl,
1595
-
.pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1596
-
.vreg_list = qmp_phy_vreg_l,
1597
-
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1598
-
.regs = qmp_v3_usb3phy_regs_layout_qcm2290,
1599
-
};
1600
-
1601
1911
static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {
1602
-
.lanes = 1,
1603
-
1604
1912
.offsets = &qmp_usb_offsets_v7,
1605
1913
1606
1914
.serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl,
···
1598
1946
.regs = qmp_v7_usb3phy_regs_layout,
1599
1947
};
1600
1948
1601
-
static void qmp_usb_configure_lane(void __iomem *base,
1602
-
const struct qmp_phy_init_tbl tbl[],
1603
-
int num,
1604
-
u8 lane_mask)
1605
-
{
1606
-
int i;
1607
-
const struct qmp_phy_init_tbl *t = tbl;
1608
-
1609
-
if (!t)
1610
-
return;
1611
-
1612
-
for (i = 0; i < num; i++, t++) {
1613
-
if (!(t->lane_mask & lane_mask))
1614
-
continue;
1615
-
1616
-
writel(t->val, base + t->offset);
1617
-
}
1618
-
}
1619
-
1620
-
static void qmp_usb_configure(void __iomem *base,
1621
-
const struct qmp_phy_init_tbl tbl[],
1622
-
int num)
1623
-
{
1624
-
qmp_usb_configure_lane(base, tbl, num, 0xff);
1625
-
}
1626
-
1627
1949
static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1628
1950
{
1629
1951
const struct qmp_phy_cfg *cfg = qmp->cfg;
···
1605
1979
const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1606
1980
int serdes_tbl_num = cfg->serdes_tbl_num;
1607
1981
1608
-
qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1982
+
qmp_configure(serdes, serdes_tbl, serdes_tbl_num);
1609
1983
1610
1984
return 0;
1611
1985
}
···
1686
2060
}
1687
2061
1688
2062
/* Tx, Rx, and PCS configurations */
1689
-
qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1690
-
qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2063
+
qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2064
+
qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1691
2065
1692
-
if (cfg->lanes >= 2) {
1693
-
qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1694
-
qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1695
-
}
1696
-
1697
-
qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2066
+
qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1698
2067
1699
2068
if (pcs_usb)
1700
-
qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2069
+
qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1701
2070
1702
2071
if (cfg->has_pwrdn_delay)
1703
2072
usleep_range(10, 20);
···
2035
2414
/*
2036
2415
* Get memory resources for the PHY:
2037
2416
* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2038
-
* For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2039
2417
* For single lane PHYs: pcs_misc (optional) -> 3.
2040
2418
*/
2041
2419
qmp->tx = devm_of_iomap(dev, np, 0, NULL);
···
2052
2432
if (cfg->pcs_usb_offset)
2053
2433
qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2054
2434
2055
-
if (cfg->lanes >= 2) {
2056
-
qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2057
-
if (IS_ERR(qmp->tx2))
2058
-
return PTR_ERR(qmp->tx2);
2059
-
2060
-
qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2061
-
if (IS_ERR(qmp->rx2))
2062
-
return PTR_ERR(qmp->rx2);
2063
-
2064
-
qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2065
-
} else {
2066
-
qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2067
-
}
2435
+
qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2068
2436
2069
2437
if (IS_ERR(qmp->pcs_misc)) {
2070
2438
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
···
2103
2495
qmp->pcs_misc = base + offs->pcs_misc;
2104
2496
qmp->tx = base + offs->tx;
2105
2497
qmp->rx = base + offs->rx;
2106
-
2107
-
if (cfg->lanes >= 2) {
2108
-
qmp->tx2 = base + offs->tx2;
2109
-
qmp->rx2 = base + offs->rx2;
2110
-
}
2111
2498
2112
2499
ret = qmp_usb_clk_init(qmp);
2113
2500
if (ret)
···
2203
2600
.compatible = "qcom,msm8996-qmp-usb3-phy",
2204
2601
.data = &msm8996_usb3phy_cfg,
2205
2602
}, {
2206
-
.compatible = "qcom,msm8998-qmp-usb3-phy",
2207
-
.data = &msm8998_usb3phy_cfg,
2208
-
}, {
2209
-
.compatible = "qcom,qcm2290-qmp-usb3-phy",
2210
-
.data = &qcm2290_usb3phy_cfg,
2211
-
}, {
2212
2603
.compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2213
2604
.data = &sa8775p_usb3_uniphy_cfg,
2214
2605
}, {
···
2220
2623
}, {
2221
2624
.compatible = "qcom,sdx75-qmp-usb3-uni-phy",
2222
2625
.data = &sdx75_usb3_uniphy_cfg,
2223
-
}, {
2224
-
.compatible = "qcom,sm6115-qmp-usb3-phy",
2225
-
.data = &qcm2290_usb3phy_cfg,
2226
2626
}, {
2227
2627
.compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2228
2628
.data = &sm8150_usb3_uniphy_cfg,
+1149
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+1149
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/delay.h>
9
+
#include <linux/err.h>
10
+
#include <linux/io.h>
11
+
#include <linux/iopoll.h>
12
+
#include <linux/kernel.h>
13
+
#include <linux/mfd/syscon.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of.h>
16
+
#include <linux/of_address.h>
17
+
#include <linux/phy/phy.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/regulator/consumer.h>
21
+
#include <linux/reset.h>
22
+
#include <linux/slab.h>
23
+
#include <linux/usb/typec.h>
24
+
#include <linux/usb/typec_mux.h>
25
+
26
+
#include "phy-qcom-qmp-common.h"
27
+
28
+
#include "phy-qcom-qmp.h"
29
+
#include "phy-qcom-qmp-pcs-misc-v3.h"
30
+
31
+
#define PHY_INIT_COMPLETE_TIMEOUT 10000
32
+
33
+
/* set of registers with offsets different per-PHY */
34
+
enum qphy_reg_layout {
35
+
/* PCS registers */
36
+
QPHY_SW_RESET,
37
+
QPHY_START_CTRL,
38
+
QPHY_PCS_STATUS,
39
+
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
40
+
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
41
+
QPHY_PCS_POWER_DOWN_CONTROL,
42
+
/* Keep last to ensure regs_layout arrays are properly initialized */
43
+
QPHY_LAYOUT_SIZE
44
+
};
45
+
46
+
static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
47
+
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
48
+
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
49
+
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
50
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
51
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
52
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
53
+
};
54
+
55
+
static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
56
+
[QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
57
+
[QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
58
+
[QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
59
+
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
60
+
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
61
+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
62
+
};
63
+
64
+
static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
65
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
66
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
67
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
68
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
69
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
70
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
71
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
72
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
73
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
74
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
75
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
76
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
77
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
78
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
79
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
80
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
81
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
82
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
83
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
84
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
85
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
86
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
87
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
88
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
89
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
90
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
91
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
92
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
93
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
94
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
95
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
96
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
97
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
98
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
99
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
100
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
101
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
102
+
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
103
+
};
104
+
105
+
static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
106
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
107
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
108
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
109
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
110
+
};
111
+
112
+
static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
113
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
114
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
115
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
116
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
117
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
118
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
119
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
120
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
121
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
122
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
123
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
124
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
125
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
126
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
127
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
128
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
129
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
130
+
};
131
+
132
+
static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
133
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
134
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
135
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
136
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
137
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
138
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
139
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
140
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
141
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
142
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
143
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
144
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
145
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
146
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
147
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
148
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
149
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
150
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
151
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
152
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
153
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
154
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
155
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
156
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
157
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
158
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
159
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
160
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
161
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
162
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
163
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
164
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
165
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
166
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
167
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
168
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
169
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
170
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
171
+
};
172
+
173
+
static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
174
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
175
+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
176
+
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
177
+
QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
178
+
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
179
+
QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
180
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
181
+
QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
182
+
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
183
+
QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
184
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
185
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
186
+
QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
187
+
QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
188
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
189
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
190
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
191
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
192
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
193
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
194
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
195
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
196
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
197
+
QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
198
+
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
199
+
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
200
+
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
201
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
202
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
203
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
204
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
205
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
206
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
207
+
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
208
+
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
209
+
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
210
+
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
211
+
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
212
+
};
213
+
214
+
static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
215
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
216
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
217
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
218
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
219
+
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
220
+
};
221
+
222
+
static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
223
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
224
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
225
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
226
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
227
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
228
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
229
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
230
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
231
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
232
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
233
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
234
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
235
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
236
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
237
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
238
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
239
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
240
+
};
241
+
242
+
/* the only difference is QSERDES_V3_RX_UCDR_PI_CONTROLS */
243
+
static const struct qmp_phy_init_tbl sdm660_usb3_rx_tbl[] = {
244
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
245
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
246
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
247
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
248
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
249
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
250
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
251
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
252
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
253
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
254
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
255
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
256
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
257
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
258
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
259
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
260
+
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
261
+
};
262
+
263
+
static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
264
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
265
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
266
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
267
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
268
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
269
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
270
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
271
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
272
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
273
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
274
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
275
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
276
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
277
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
278
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
279
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
280
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
281
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
282
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
283
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
284
+
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
285
+
};
286
+
287
+
struct qmp_usbc_offsets {
288
+
u16 serdes;
289
+
u16 pcs;
290
+
u16 pcs_misc;
291
+
u16 tx;
292
+
u16 rx;
293
+
/* for PHYs with >= 2 lanes */
294
+
u16 tx2;
295
+
u16 rx2;
296
+
};
297
+
298
+
/* struct qmp_phy_cfg - per-PHY initialization config */
299
+
struct qmp_phy_cfg {
300
+
const struct qmp_usbc_offsets *offsets;
301
+
302
+
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
303
+
const struct qmp_phy_init_tbl *serdes_tbl;
304
+
int serdes_tbl_num;
305
+
const struct qmp_phy_init_tbl *tx_tbl;
306
+
int tx_tbl_num;
307
+
const struct qmp_phy_init_tbl *rx_tbl;
308
+
int rx_tbl_num;
309
+
const struct qmp_phy_init_tbl *pcs_tbl;
310
+
int pcs_tbl_num;
311
+
312
+
/* regulators to be requested */
313
+
const char * const *vreg_list;
314
+
int num_vregs;
315
+
316
+
/* array of registers with different offsets */
317
+
const unsigned int *regs;
318
+
};
319
+
320
+
struct qmp_usbc {
321
+
struct device *dev;
322
+
323
+
const struct qmp_phy_cfg *cfg;
324
+
325
+
void __iomem *serdes;
326
+
void __iomem *pcs;
327
+
void __iomem *pcs_misc;
328
+
void __iomem *tx;
329
+
void __iomem *rx;
330
+
void __iomem *tx2;
331
+
void __iomem *rx2;
332
+
333
+
struct regmap *tcsr_map;
334
+
u32 vls_clamp_reg;
335
+
336
+
struct clk *pipe_clk;
337
+
struct clk_bulk_data *clks;
338
+
int num_clks;
339
+
int num_resets;
340
+
struct reset_control_bulk_data *resets;
341
+
struct regulator_bulk_data *vregs;
342
+
343
+
struct mutex phy_mutex;
344
+
345
+
enum phy_mode mode;
346
+
unsigned int usb_init_count;
347
+
348
+
struct phy *phy;
349
+
350
+
struct clk_fixed_rate pipe_clk_fixed;
351
+
352
+
struct typec_switch_dev *sw;
353
+
enum typec_orientation orientation;
354
+
};
355
+
356
+
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
357
+
{
358
+
u32 reg;
359
+
360
+
reg = readl(base + offset);
361
+
reg |= val;
362
+
writel(reg, base + offset);
363
+
364
+
/* ensure that above write is through */
365
+
readl(base + offset);
366
+
}
367
+
368
+
static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
369
+
{
370
+
u32 reg;
371
+
372
+
reg = readl(base + offset);
373
+
reg &= ~val;
374
+
writel(reg, base + offset);
375
+
376
+
/* ensure that above write is through */
377
+
readl(base + offset);
378
+
}
379
+
380
+
/* list of clocks required by phy */
381
+
static const char * const qmp_usbc_phy_clk_l[] = {
382
+
"aux", "cfg_ahb", "ref", "com_aux",
383
+
};
384
+
385
+
/* list of resets */
386
+
static const char * const usb3phy_legacy_reset_l[] = {
387
+
"phy", "common",
388
+
};
389
+
390
+
static const char * const usb3phy_reset_l[] = {
391
+
"phy_phy", "phy",
392
+
};
393
+
394
+
/* list of regulators */
395
+
static const char * const qmp_phy_vreg_l[] = {
396
+
"vdda-phy", "vdda-pll",
397
+
};
398
+
399
+
static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = {
400
+
.serdes = 0x0,
401
+
.pcs = 0xc00,
402
+
.pcs_misc = 0xa00,
403
+
.tx = 0x200,
404
+
.rx = 0x400,
405
+
.tx2 = 0x600,
406
+
.rx2 = 0x800,
407
+
};
408
+
409
+
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
410
+
.offsets = &qmp_usbc_offsets_v3_qcm2290,
411
+
412
+
.serdes_tbl = msm8998_usb3_serdes_tbl,
413
+
.serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
414
+
.tx_tbl = msm8998_usb3_tx_tbl,
415
+
.tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
416
+
.rx_tbl = msm8998_usb3_rx_tbl,
417
+
.rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
418
+
.pcs_tbl = msm8998_usb3_pcs_tbl,
419
+
.pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
420
+
.vreg_list = qmp_phy_vreg_l,
421
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
422
+
.regs = qmp_v3_usb3phy_regs_layout,
423
+
};
424
+
425
+
static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
426
+
.offsets = &qmp_usbc_offsets_v3_qcm2290,
427
+
428
+
.serdes_tbl = qcm2290_usb3_serdes_tbl,
429
+
.serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
430
+
.tx_tbl = qcm2290_usb3_tx_tbl,
431
+
.tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
432
+
.rx_tbl = qcm2290_usb3_rx_tbl,
433
+
.rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
434
+
.pcs_tbl = qcm2290_usb3_pcs_tbl,
435
+
.pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
436
+
.vreg_list = qmp_phy_vreg_l,
437
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
438
+
.regs = qmp_v3_usb3phy_regs_layout_qcm2290,
439
+
};
440
+
441
+
static const struct qmp_phy_cfg sdm660_usb3phy_cfg = {
442
+
.offsets = &qmp_usbc_offsets_v3_qcm2290,
443
+
444
+
.serdes_tbl = qcm2290_usb3_serdes_tbl,
445
+
.serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
446
+
.tx_tbl = qcm2290_usb3_tx_tbl,
447
+
.tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
448
+
.rx_tbl = sdm660_usb3_rx_tbl,
449
+
.rx_tbl_num = ARRAY_SIZE(sdm660_usb3_rx_tbl),
450
+
.pcs_tbl = qcm2290_usb3_pcs_tbl,
451
+
.pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
452
+
.vreg_list = qmp_phy_vreg_l,
453
+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
454
+
.regs = qmp_v3_usb3phy_regs_layout_qcm2290,
455
+
};
456
+
457
+
static int qmp_usbc_init(struct phy *phy)
458
+
{
459
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
460
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
461
+
void __iomem *pcs = qmp->pcs;
462
+
u32 val = 0;
463
+
int ret;
464
+
465
+
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
466
+
if (ret) {
467
+
dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
468
+
return ret;
469
+
}
470
+
471
+
ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
472
+
if (ret) {
473
+
dev_err(qmp->dev, "reset assert failed\n");
474
+
goto err_disable_regulators;
475
+
}
476
+
477
+
ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
478
+
if (ret) {
479
+
dev_err(qmp->dev, "reset deassert failed\n");
480
+
goto err_disable_regulators;
481
+
}
482
+
483
+
ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
484
+
if (ret)
485
+
goto err_assert_reset;
486
+
487
+
qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
488
+
489
+
#define SW_PORTSELECT_VAL BIT(0)
490
+
#define SW_PORTSELECT_MUX BIT(1)
491
+
/* Use software based port select and switch on typec orientation */
492
+
val = SW_PORTSELECT_MUX;
493
+
if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
494
+
val |= SW_PORTSELECT_VAL;
495
+
writel(val, qmp->pcs_misc);
496
+
497
+
return 0;
498
+
499
+
err_assert_reset:
500
+
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
501
+
err_disable_regulators:
502
+
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
503
+
504
+
return ret;
505
+
}
506
+
507
+
static int qmp_usbc_exit(struct phy *phy)
508
+
{
509
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
510
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
511
+
512
+
reset_control_bulk_assert(qmp->num_resets, qmp->resets);
513
+
514
+
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
515
+
516
+
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
517
+
518
+
return 0;
519
+
}
520
+
521
+
static int qmp_usbc_power_on(struct phy *phy)
522
+
{
523
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
524
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
525
+
void __iomem *status;
526
+
unsigned int val;
527
+
int ret;
528
+
529
+
qmp_configure(qmp->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
530
+
531
+
ret = clk_prepare_enable(qmp->pipe_clk);
532
+
if (ret) {
533
+
dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
534
+
return ret;
535
+
}
536
+
537
+
/* Tx, Rx, and PCS configurations */
538
+
qmp_configure_lane(qmp->tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
539
+
qmp_configure_lane(qmp->rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
540
+
541
+
qmp_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
542
+
qmp_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
543
+
544
+
qmp_configure(qmp->pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
545
+
546
+
/* Pull PHY out of reset state */
547
+
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
548
+
549
+
/* start SerDes and Phy-Coding-Sublayer */
550
+
qphy_setbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
551
+
552
+
status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS];
553
+
ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
554
+
PHY_INIT_COMPLETE_TIMEOUT);
555
+
if (ret) {
556
+
dev_err(qmp->dev, "phy initialization timed-out\n");
557
+
goto err_disable_pipe_clk;
558
+
}
559
+
560
+
return 0;
561
+
562
+
err_disable_pipe_clk:
563
+
clk_disable_unprepare(qmp->pipe_clk);
564
+
565
+
return ret;
566
+
}
567
+
568
+
static int qmp_usbc_power_off(struct phy *phy)
569
+
{
570
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
571
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
572
+
573
+
clk_disable_unprepare(qmp->pipe_clk);
574
+
575
+
/* PHY reset */
576
+
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
577
+
578
+
/* stop SerDes and Phy-Coding-Sublayer */
579
+
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
580
+
SERDES_START | PCS_START);
581
+
582
+
/* Put PHY into POWER DOWN state: active low */
583
+
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
584
+
SW_PWRDN);
585
+
586
+
return 0;
587
+
}
588
+
589
+
static int qmp_usbc_enable(struct phy *phy)
590
+
{
591
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
592
+
int ret;
593
+
594
+
mutex_lock(&qmp->phy_mutex);
595
+
596
+
ret = qmp_usbc_init(phy);
597
+
if (ret)
598
+
goto out_unlock;
599
+
600
+
ret = qmp_usbc_power_on(phy);
601
+
if (ret) {
602
+
qmp_usbc_exit(phy);
603
+
goto out_unlock;
604
+
}
605
+
606
+
qmp->usb_init_count++;
607
+
out_unlock:
608
+
mutex_unlock(&qmp->phy_mutex);
609
+
610
+
return ret;
611
+
}
612
+
613
+
static int qmp_usbc_disable(struct phy *phy)
614
+
{
615
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
616
+
int ret;
617
+
618
+
qmp->usb_init_count--;
619
+
ret = qmp_usbc_power_off(phy);
620
+
if (ret)
621
+
return ret;
622
+
return qmp_usbc_exit(phy);
623
+
}
624
+
625
+
static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int submode)
626
+
{
627
+
struct qmp_usbc *qmp = phy_get_drvdata(phy);
628
+
629
+
qmp->mode = mode;
630
+
631
+
return 0;
632
+
}
633
+
634
+
static const struct phy_ops qmp_usbc_phy_ops = {
635
+
.init = qmp_usbc_enable,
636
+
.exit = qmp_usbc_disable,
637
+
.set_mode = qmp_usbc_set_mode,
638
+
.owner = THIS_MODULE,
639
+
};
640
+
641
+
static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp)
642
+
{
643
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
644
+
void __iomem *pcs = qmp->pcs;
645
+
u32 intr_mask;
646
+
647
+
if (qmp->mode == PHY_MODE_USB_HOST_SS ||
648
+
qmp->mode == PHY_MODE_USB_DEVICE_SS)
649
+
intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
650
+
else
651
+
intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
652
+
653
+
/* Clear any pending interrupts status */
654
+
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
655
+
/* Writing 1 followed by 0 clears the interrupt */
656
+
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
657
+
658
+
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
659
+
ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
660
+
661
+
/* Enable required PHY autonomous mode interrupts */
662
+
qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
663
+
664
+
/* Enable i/o clamp_n for autonomous mode */
665
+
if (qmp->tcsr_map && qmp->vls_clamp_reg)
666
+
regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 1);
667
+
}
668
+
669
+
static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp)
670
+
{
671
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
672
+
void __iomem *pcs = qmp->pcs;
673
+
674
+
/* Disable i/o clamp_n on resume for normal mode */
675
+
if (qmp->tcsr_map && qmp->vls_clamp_reg)
676
+
regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 0);
677
+
678
+
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
679
+
ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
680
+
681
+
qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
682
+
/* Writing 1 followed by 0 clears the interrupt */
683
+
qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
684
+
}
685
+
686
+
static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev)
687
+
{
688
+
struct qmp_usbc *qmp = dev_get_drvdata(dev);
689
+
690
+
dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
691
+
692
+
if (!qmp->phy->init_count) {
693
+
dev_vdbg(dev, "PHY not initialized, bailing out\n");
694
+
return 0;
695
+
}
696
+
697
+
qmp_usbc_enable_autonomous_mode(qmp);
698
+
699
+
clk_disable_unprepare(qmp->pipe_clk);
700
+
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
701
+
702
+
return 0;
703
+
}
704
+
705
+
static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev)
706
+
{
707
+
struct qmp_usbc *qmp = dev_get_drvdata(dev);
708
+
int ret = 0;
709
+
710
+
dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
711
+
712
+
if (!qmp->phy->init_count) {
713
+
dev_vdbg(dev, "PHY not initialized, bailing out\n");
714
+
return 0;
715
+
}
716
+
717
+
ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
718
+
if (ret)
719
+
return ret;
720
+
721
+
ret = clk_prepare_enable(qmp->pipe_clk);
722
+
if (ret) {
723
+
dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
724
+
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
725
+
return ret;
726
+
}
727
+
728
+
qmp_usbc_disable_autonomous_mode(qmp);
729
+
730
+
return 0;
731
+
}
732
+
733
+
static const struct dev_pm_ops qmp_usbc_pm_ops = {
734
+
SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend,
735
+
qmp_usbc_runtime_resume, NULL)
736
+
};
737
+
738
+
static int qmp_usbc_vreg_init(struct qmp_usbc *qmp)
739
+
{
740
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
741
+
struct device *dev = qmp->dev;
742
+
int num = cfg->num_vregs;
743
+
int i;
744
+
745
+
qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
746
+
if (!qmp->vregs)
747
+
return -ENOMEM;
748
+
749
+
for (i = 0; i < num; i++)
750
+
qmp->vregs[i].supply = cfg->vreg_list[i];
751
+
752
+
return devm_regulator_bulk_get(dev, num, qmp->vregs);
753
+
}
754
+
755
+
static int qmp_usbc_reset_init(struct qmp_usbc *qmp,
756
+
const char *const *reset_list,
757
+
int num_resets)
758
+
{
759
+
struct device *dev = qmp->dev;
760
+
int i;
761
+
int ret;
762
+
763
+
qmp->resets = devm_kcalloc(dev, num_resets,
764
+
sizeof(*qmp->resets), GFP_KERNEL);
765
+
if (!qmp->resets)
766
+
return -ENOMEM;
767
+
768
+
for (i = 0; i < num_resets; i++)
769
+
qmp->resets[i].id = reset_list[i];
770
+
771
+
qmp->num_resets = num_resets;
772
+
773
+
ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
774
+
if (ret)
775
+
return dev_err_probe(dev, ret, "failed to get resets\n");
776
+
777
+
return 0;
778
+
}
779
+
780
+
static int qmp_usbc_clk_init(struct qmp_usbc *qmp)
781
+
{
782
+
struct device *dev = qmp->dev;
783
+
int num = ARRAY_SIZE(qmp_usbc_phy_clk_l);
784
+
int i;
785
+
786
+
qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
787
+
if (!qmp->clks)
788
+
return -ENOMEM;
789
+
790
+
for (i = 0; i < num; i++)
791
+
qmp->clks[i].id = qmp_usbc_phy_clk_l[i];
792
+
793
+
qmp->num_clks = num;
794
+
795
+
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
796
+
}
797
+
798
+
static void phy_clk_release_provider(void *res)
799
+
{
800
+
of_clk_del_provider(res);
801
+
}
802
+
803
+
/*
804
+
* Register a fixed rate pipe clock.
805
+
*
806
+
* The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
807
+
* controls it. The <s>_pipe_clk coming out of the GCC is requested
808
+
* by the PHY driver for its operations.
809
+
* We register the <s>_pipe_clksrc here. The gcc driver takes care
810
+
* of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
811
+
* Below picture shows this relationship.
812
+
*
813
+
* +---------------+
814
+
* | PHY block |<<---------------------------------------+
815
+
* | | |
816
+
* | +-------+ | +-----+ |
817
+
* I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
818
+
* clk | +-------+ | +-----+
819
+
* +---------------+
820
+
*/
821
+
static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np)
822
+
{
823
+
struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
824
+
struct clk_init_data init = { };
825
+
int ret;
826
+
827
+
ret = of_property_read_string(np, "clock-output-names", &init.name);
828
+
if (ret) {
829
+
dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
830
+
return ret;
831
+
}
832
+
833
+
init.ops = &clk_fixed_rate_ops;
834
+
835
+
/* controllers using QMP phys use 125MHz pipe clock interface */
836
+
fixed->fixed_rate = 125000000;
837
+
fixed->hw.init = &init;
838
+
839
+
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
840
+
if (ret)
841
+
return ret;
842
+
843
+
ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
844
+
if (ret)
845
+
return ret;
846
+
847
+
/*
848
+
* Roll a devm action because the clock provider is the child node, but
849
+
* the child node is not actually a device.
850
+
*/
851
+
return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
852
+
}
853
+
854
+
#if IS_ENABLED(CONFIG_TYPEC)
855
+
static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw,
856
+
enum typec_orientation orientation)
857
+
{
858
+
struct qmp_usbc *qmp = typec_switch_get_drvdata(sw);
859
+
860
+
if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
861
+
return 0;
862
+
863
+
mutex_lock(&qmp->phy_mutex);
864
+
qmp->orientation = orientation;
865
+
866
+
if (qmp->usb_init_count) {
867
+
qmp_usbc_power_off(qmp->phy);
868
+
qmp_usbc_exit(qmp->phy);
869
+
870
+
qmp_usbc_init(qmp->phy);
871
+
qmp_usbc_power_on(qmp->phy);
872
+
}
873
+
874
+
mutex_unlock(&qmp->phy_mutex);
875
+
876
+
return 0;
877
+
}
878
+
879
+
static void qmp_usbc_typec_unregister(void *data)
880
+
{
881
+
struct qmp_usbc *qmp = data;
882
+
883
+
typec_switch_unregister(qmp->sw);
884
+
}
885
+
886
+
static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
887
+
{
888
+
struct typec_switch_desc sw_desc = {};
889
+
struct device *dev = qmp->dev;
890
+
891
+
sw_desc.drvdata = qmp;
892
+
sw_desc.fwnode = dev->fwnode;
893
+
sw_desc.set = qmp_usbc_typec_switch_set;
894
+
qmp->sw = typec_switch_register(dev, &sw_desc);
895
+
if (IS_ERR(qmp->sw)) {
896
+
dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
897
+
return PTR_ERR(qmp->sw);
898
+
}
899
+
900
+
return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp);
901
+
}
902
+
#else
903
+
static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
904
+
{
905
+
return 0;
906
+
}
907
+
#endif
908
+
909
+
static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np)
910
+
{
911
+
struct platform_device *pdev = to_platform_device(qmp->dev);
912
+
struct device *dev = qmp->dev;
913
+
int ret;
914
+
915
+
qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
916
+
if (IS_ERR(qmp->serdes))
917
+
return PTR_ERR(qmp->serdes);
918
+
919
+
/*
920
+
* Get memory resources for the PHY:
921
+
* Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
922
+
* For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
923
+
* For single lane PHYs: pcs_misc (optional) -> 3.
924
+
*/
925
+
qmp->tx = devm_of_iomap(dev, np, 0, NULL);
926
+
if (IS_ERR(qmp->tx))
927
+
return PTR_ERR(qmp->tx);
928
+
929
+
qmp->rx = devm_of_iomap(dev, np, 1, NULL);
930
+
if (IS_ERR(qmp->rx))
931
+
return PTR_ERR(qmp->rx);
932
+
933
+
qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
934
+
if (IS_ERR(qmp->pcs))
935
+
return PTR_ERR(qmp->pcs);
936
+
937
+
qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
938
+
if (IS_ERR(qmp->tx2))
939
+
return PTR_ERR(qmp->tx2);
940
+
941
+
qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
942
+
if (IS_ERR(qmp->rx2))
943
+
return PTR_ERR(qmp->rx2);
944
+
945
+
qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
946
+
if (IS_ERR(qmp->pcs_misc)) {
947
+
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
948
+
qmp->pcs_misc = NULL;
949
+
}
950
+
951
+
qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
952
+
if (IS_ERR(qmp->pipe_clk)) {
953
+
return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
954
+
"failed to get pipe clock\n");
955
+
}
956
+
957
+
ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
958
+
if (ret < 0)
959
+
return ret;
960
+
961
+
qmp->num_clks = ret;
962
+
963
+
ret = qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l,
964
+
ARRAY_SIZE(usb3phy_legacy_reset_l));
965
+
if (ret)
966
+
return ret;
967
+
968
+
return 0;
969
+
}
970
+
971
+
static int qmp_usbc_parse_dt(struct qmp_usbc *qmp)
972
+
{
973
+
struct platform_device *pdev = to_platform_device(qmp->dev);
974
+
const struct qmp_phy_cfg *cfg = qmp->cfg;
975
+
const struct qmp_usbc_offsets *offs = cfg->offsets;
976
+
struct device *dev = qmp->dev;
977
+
void __iomem *base;
978
+
int ret;
979
+
980
+
if (!offs)
981
+
return -EINVAL;
982
+
983
+
base = devm_platform_ioremap_resource(pdev, 0);
984
+
if (IS_ERR(base))
985
+
return PTR_ERR(base);
986
+
987
+
qmp->serdes = base + offs->serdes;
988
+
qmp->pcs = base + offs->pcs;
989
+
if (offs->pcs_misc)
990
+
qmp->pcs_misc = base + offs->pcs_misc;
991
+
qmp->tx = base + offs->tx;
992
+
qmp->rx = base + offs->rx;
993
+
994
+
qmp->tx2 = base + offs->tx2;
995
+
qmp->rx2 = base + offs->rx2;
996
+
997
+
ret = qmp_usbc_clk_init(qmp);
998
+
if (ret)
999
+
return ret;
1000
+
1001
+
qmp->pipe_clk = devm_clk_get(dev, "pipe");
1002
+
if (IS_ERR(qmp->pipe_clk)) {
1003
+
return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
1004
+
"failed to get pipe clock\n");
1005
+
}
1006
+
1007
+
ret = qmp_usbc_reset_init(qmp, usb3phy_reset_l,
1008
+
ARRAY_SIZE(usb3phy_reset_l));
1009
+
if (ret)
1010
+
return ret;
1011
+
1012
+
return 0;
1013
+
}
1014
+
1015
+
static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp)
1016
+
{
1017
+
struct of_phandle_args tcsr_args;
1018
+
struct device *dev = qmp->dev;
1019
+
int ret;
1020
+
1021
+
/* for backwards compatibility ignore if there is no property */
1022
+
ret = of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1, 0,
1023
+
&tcsr_args);
1024
+
if (ret == -ENOENT)
1025
+
return 0;
1026
+
else if (ret < 0)
1027
+
return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n");
1028
+
1029
+
qmp->tcsr_map = syscon_node_to_regmap(tcsr_args.np);
1030
+
of_node_put(tcsr_args.np);
1031
+
if (IS_ERR(qmp->tcsr_map))
1032
+
return PTR_ERR(qmp->tcsr_map);
1033
+
1034
+
qmp->vls_clamp_reg = tcsr_args.args[0];
1035
+
1036
+
return 0;
1037
+
}
1038
+
1039
+
static int qmp_usbc_probe(struct platform_device *pdev)
1040
+
{
1041
+
struct device *dev = &pdev->dev;
1042
+
struct phy_provider *phy_provider;
1043
+
struct device_node *np;
1044
+
struct qmp_usbc *qmp;
1045
+
int ret;
1046
+
1047
+
qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1048
+
if (!qmp)
1049
+
return -ENOMEM;
1050
+
1051
+
qmp->dev = dev;
1052
+
1053
+
qmp->orientation = TYPEC_ORIENTATION_NORMAL;
1054
+
1055
+
qmp->cfg = of_device_get_match_data(dev);
1056
+
if (!qmp->cfg)
1057
+
return -EINVAL;
1058
+
1059
+
mutex_init(&qmp->phy_mutex);
1060
+
1061
+
ret = qmp_usbc_vreg_init(qmp);
1062
+
if (ret)
1063
+
return ret;
1064
+
1065
+
ret = qmp_usbc_typec_switch_register(qmp);
1066
+
if (ret)
1067
+
return ret;
1068
+
1069
+
ret = qmp_usbc_parse_vls_clamp(qmp);
1070
+
if (ret)
1071
+
return ret;
1072
+
1073
+
/* Check for legacy binding with child node. */
1074
+
np = of_get_child_by_name(dev->of_node, "phy");
1075
+
if (np) {
1076
+
ret = qmp_usbc_parse_dt_legacy(qmp, np);
1077
+
} else {
1078
+
np = of_node_get(dev->of_node);
1079
+
ret = qmp_usbc_parse_dt(qmp);
1080
+
}
1081
+
if (ret)
1082
+
goto err_node_put;
1083
+
1084
+
pm_runtime_set_active(dev);
1085
+
ret = devm_pm_runtime_enable(dev);
1086
+
if (ret)
1087
+
goto err_node_put;
1088
+
/*
1089
+
* Prevent runtime pm from being ON by default. Users can enable
1090
+
* it using power/control in sysfs.
1091
+
*/
1092
+
pm_runtime_forbid(dev);
1093
+
1094
+
ret = phy_pipe_clk_register(qmp, np);
1095
+
if (ret)
1096
+
goto err_node_put;
1097
+
1098
+
qmp->phy = devm_phy_create(dev, np, &qmp_usbc_phy_ops);
1099
+
if (IS_ERR(qmp->phy)) {
1100
+
ret = PTR_ERR(qmp->phy);
1101
+
dev_err(dev, "failed to create PHY: %d\n", ret);
1102
+
goto err_node_put;
1103
+
}
1104
+
1105
+
phy_set_drvdata(qmp->phy, qmp);
1106
+
1107
+
of_node_put(np);
1108
+
1109
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1110
+
1111
+
return PTR_ERR_OR_ZERO(phy_provider);
1112
+
1113
+
err_node_put:
1114
+
of_node_put(np);
1115
+
return ret;
1116
+
}
1117
+
1118
+
static const struct of_device_id qmp_usbc_of_match_table[] = {
1119
+
{
1120
+
.compatible = "qcom,msm8998-qmp-usb3-phy",
1121
+
.data = &msm8998_usb3phy_cfg,
1122
+
}, {
1123
+
.compatible = "qcom,qcm2290-qmp-usb3-phy",
1124
+
.data = &qcm2290_usb3phy_cfg,
1125
+
}, {
1126
+
.compatible = "qcom,sdm660-qmp-usb3-phy",
1127
+
.data = &sdm660_usb3phy_cfg,
1128
+
}, {
1129
+
.compatible = "qcom,sm6115-qmp-usb3-phy",
1130
+
.data = &qcm2290_usb3phy_cfg,
1131
+
},
1132
+
{ },
1133
+
};
1134
+
MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table);
1135
+
1136
+
static struct platform_driver qmp_usbc_driver = {
1137
+
.probe = qmp_usbc_probe,
1138
+
.driver = {
1139
+
.name = "qcom-qmp-usbc-phy",
1140
+
.pm = &qmp_usbc_pm_ops,
1141
+
.of_match_table = qmp_usbc_of_match_table,
1142
+
},
1143
+
};
1144
+
1145
+
module_platform_driver(qmp_usbc_driver);
1146
+
1147
+
MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1148
+
MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver");
1149
+
MODULE_LICENSE("GPL");
+19
-82
drivers/phy/qualcomm/phy-qcom-qmp.h
+19
-82
drivers/phy/qualcomm/phy-qcom-qmp.h
···
50
50
51
51
#include "phy-qcom-qmp-pcs-v7.h"
52
52
53
-
/* Only for QMP V3 & V4 PHY - DP COM registers */
54
-
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
55
-
#define QPHY_V3_DP_COM_SW_RESET 0x04
56
-
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
57
-
#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
58
-
#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
59
-
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
60
-
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
53
+
/* QPHY_SW_RESET bit */
54
+
#define SW_RESET BIT(0)
55
+
/* QPHY_POWER_DOWN_CONTROL */
56
+
#define SW_PWRDN BIT(0)
57
+
#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
61
58
62
-
/* QSERDES V3 COM bits */
63
-
# define QSERDES_V3_COM_BIAS_EN 0x0001
64
-
# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
65
-
# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
66
-
# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
67
-
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
68
-
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
69
-
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
59
+
/* QPHY_START_CONTROL bits */
60
+
#define SERDES_START BIT(0)
61
+
#define PCS_START BIT(1)
70
62
71
-
/* QSERDES V3 TX bits */
72
-
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
73
-
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
74
-
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
75
-
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
63
+
/* QPHY_PCS_STATUS bit */
64
+
#define PHYSTATUS BIT(6)
65
+
#define PHYSTATUS_4_20 BIT(7)
76
66
77
-
/* QMP PHY - DP PHY registers */
78
-
#define QSERDES_DP_PHY_REVISION_ID0 0x000
79
-
#define QSERDES_DP_PHY_REVISION_ID1 0x004
80
-
#define QSERDES_DP_PHY_REVISION_ID2 0x008
81
-
#define QSERDES_DP_PHY_REVISION_ID3 0x00c
82
-
#define QSERDES_DP_PHY_CFG 0x010
83
-
#define QSERDES_DP_PHY_PD_CTL 0x018
84
-
# define DP_PHY_PD_CTL_PWRDN 0x001
85
-
# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
86
-
# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
87
-
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
88
-
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
89
-
# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
90
-
# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
91
-
#define QSERDES_DP_PHY_MODE 0x01c
92
-
#define QSERDES_DP_PHY_AUX_CFG0 0x020
93
-
#define QSERDES_DP_PHY_AUX_CFG1 0x024
94
-
#define QSERDES_DP_PHY_AUX_CFG2 0x028
95
-
#define QSERDES_DP_PHY_AUX_CFG3 0x02c
96
-
#define QSERDES_DP_PHY_AUX_CFG4 0x030
97
-
#define QSERDES_DP_PHY_AUX_CFG5 0x034
98
-
#define QSERDES_DP_PHY_AUX_CFG6 0x038
99
-
#define QSERDES_DP_PHY_AUX_CFG7 0x03c
100
-
#define QSERDES_DP_PHY_AUX_CFG8 0x040
101
-
#define QSERDES_DP_PHY_AUX_CFG9 0x044
67
+
/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
68
+
#define ARCVR_DTCT_EN BIT(0)
69
+
#define ALFPS_DTCT_EN BIT(1)
70
+
#define ARCVR_DTCT_EVENT_SEL BIT(4)
102
71
103
-
/* Only for QMP V3 PHY - DP PHY registers */
104
-
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
105
-
# define PHY_AUX_STOP_ERR_MASK 0x01
106
-
# define PHY_AUX_DEC_ERR_MASK 0x02
107
-
# define PHY_AUX_SYNC_ERR_MASK 0x04
108
-
# define PHY_AUX_ALIGN_ERR_MASK 0x08
109
-
# define PHY_AUX_REQ_ERR_MASK 0x10
72
+
/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
73
+
#define IRQ_CLEAR BIT(0)
110
74
111
-
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
112
-
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
113
-
114
-
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
115
-
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
116
-
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
117
-
118
-
#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
119
-
#define DP_PHY_SPARE0_MASK 0x0f
120
-
#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
121
-
122
-
#define QSERDES_V3_DP_PHY_STATUS 0x0c0
123
-
124
-
/* Only for QMP V4 PHY - DP PHY registers */
125
-
#define QSERDES_V4_DP_PHY_CFG_1 0x014
126
-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
127
-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
128
-
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
129
-
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
130
-
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
131
-
#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
132
-
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
133
-
#define QSERDES_V4_DP_PHY_STATUS 0x0dc
134
-
135
-
#define QSERDES_V5_DP_PHY_STATUS 0x0dc
136
-
137
-
/* Only for QMP V6 PHY - DP PHY registers */
138
-
#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
139
-
#define QSERDES_V6_DP_PHY_STATUS 0x0e4
75
+
/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
76
+
#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
140
77
141
78
#endif
+169
-248
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
+169
-248
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
···
11
11
#include <linux/platform_device.h>
12
12
#include <linux/regmap.h>
13
13
14
+
#include "phy-qcom-qmp-pcs-sgmii.h"
15
+
#include "phy-qcom-qmp-qserdes-com-v5.h"
16
+
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
17
+
14
18
#define QSERDES_QMP_PLL 0x0
15
-
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (QSERDES_QMP_PLL + 0x1ac)
16
-
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (QSERDES_QMP_PLL + 0x1b0)
17
-
#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL (QSERDES_QMP_PLL + 0x1bc)
18
-
#define QSERDES_COM_CORE_CLK_EN (QSERDES_QMP_PLL + 0x174)
19
-
#define QSERDES_COM_CORECLK_DIV_MODE0 (QSERDES_QMP_PLL + 0x168)
20
-
#define QSERDES_COM_CP_CTRL_MODE0 (QSERDES_QMP_PLL + 0x74)
21
-
#define QSERDES_COM_DEC_START_MODE0 (QSERDES_QMP_PLL + 0xbc)
22
-
#define QSERDES_COM_DIV_FRAC_START1_MODE0 (QSERDES_QMP_PLL + 0xcc)
23
-
#define QSERDES_COM_DIV_FRAC_START2_MODE0 (QSERDES_QMP_PLL + 0xd0)
24
-
#define QSERDES_COM_DIV_FRAC_START3_MODE0 (QSERDES_QMP_PLL + 0xd4)
25
-
#define QSERDES_COM_HSCLK_HS_SWITCH_SEL (QSERDES_QMP_PLL + 0x15c)
26
-
#define QSERDES_COM_HSCLK_SEL (QSERDES_QMP_PLL + 0x158)
27
-
#define QSERDES_COM_LOCK_CMP1_MODE0 (QSERDES_QMP_PLL + 0xac)
28
-
#define QSERDES_COM_LOCK_CMP2_MODE0 (QSERDES_QMP_PLL + 0xb0)
29
-
#define QSERDES_COM_PLL_CCTRL_MODE0 (QSERDES_QMP_PLL + 0x84)
30
-
#define QSERDES_COM_PLL_IVCO (QSERDES_QMP_PLL + 0x58)
31
-
#define QSERDES_COM_PLL_RCTRL_MODE0 (QSERDES_QMP_PLL + 0x7c)
32
-
#define QSERDES_COM_SYSCLK_EN_SEL (QSERDES_QMP_PLL + 0x94)
33
-
#define QSERDES_COM_VCO_TUNE1_MODE0 (QSERDES_QMP_PLL + 0x110)
34
-
#define QSERDES_COM_VCO_TUNE2_MODE0 (QSERDES_QMP_PLL + 0x114)
35
-
#define QSERDES_COM_VCO_TUNE_INITVAL2 (QSERDES_QMP_PLL + 0x124)
36
-
#define QSERDES_COM_C_READY_STATUS (QSERDES_QMP_PLL + 0x178)
37
-
#define QSERDES_COM_CMN_STATUS (QSERDES_QMP_PLL + 0x140)
38
-
39
19
#define QSERDES_RX 0x600
40
-
#define QSERDES_RX_UCDR_FO_GAIN (QSERDES_RX + 0x8)
41
-
#define QSERDES_RX_UCDR_SO_GAIN (QSERDES_RX + 0x14)
42
-
#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (QSERDES_RX + 0x30)
43
-
#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (QSERDES_RX + 0x34)
44
-
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (QSERDES_RX + 0x3c)
45
-
#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (QSERDES_RX + 0x40)
46
-
#define QSERDES_RX_UCDR_PI_CONTROLS (QSERDES_RX + 0x44)
47
-
#define QSERDES_RX_UCDR_PI_CTRL2 (QSERDES_RX + 0x48)
48
-
#define QSERDES_RX_RX_TERM_BW (QSERDES_RX + 0x80)
49
-
#define QSERDES_RX_VGA_CAL_CNTRL2 (QSERDES_RX + 0xd8)
50
-
#define QSERDES_RX_GM_CAL (QSERDES_RX + 0xdc)
51
-
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (QSERDES_RX + 0xe8)
52
-
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (QSERDES_RX + 0xec)
53
-
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (QSERDES_RX + 0xf0)
54
-
#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (QSERDES_RX + 0xf4)
55
-
#define QSERDES_RX_RX_IDAC_TSETTLE_LOW (QSERDES_RX + 0xf8)
56
-
#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH (QSERDES_RX + 0xfc)
57
-
#define QSERDES_RX_RX_IDAC_MEASURE_TIME (QSERDES_RX + 0x100)
58
-
#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (QSERDES_RX + 0x110)
59
-
#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (QSERDES_RX + 0x114)
60
-
#define QSERDES_RX_SIGDET_CNTRL (QSERDES_RX + 0x11c)
61
-
#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL (QSERDES_RX + 0x124)
62
-
#define QSERDES_RX_RX_BAND (QSERDES_RX + 0x128)
63
-
#define QSERDES_RX_RX_MODE_00_LOW (QSERDES_RX + 0x15c)
64
-
#define QSERDES_RX_RX_MODE_00_HIGH (QSERDES_RX + 0x160)
65
-
#define QSERDES_RX_RX_MODE_00_HIGH2 (QSERDES_RX + 0x164)
66
-
#define QSERDES_RX_RX_MODE_00_HIGH3 (QSERDES_RX + 0x168)
67
-
#define QSERDES_RX_RX_MODE_00_HIGH4 (QSERDES_RX + 0x16c)
68
-
#define QSERDES_RX_RX_MODE_01_LOW (QSERDES_RX + 0x170)
69
-
#define QSERDES_RX_RX_MODE_01_HIGH (QSERDES_RX + 0x174)
70
-
#define QSERDES_RX_RX_MODE_01_HIGH2 (QSERDES_RX + 0x178)
71
-
#define QSERDES_RX_RX_MODE_01_HIGH3 (QSERDES_RX + 0x17c)
72
-
#define QSERDES_RX_RX_MODE_01_HIGH4 (QSERDES_RX + 0x180)
73
-
#define QSERDES_RX_RX_MODE_10_LOW (QSERDES_RX + 0x184)
74
-
#define QSERDES_RX_RX_MODE_10_HIGH (QSERDES_RX + 0x188)
75
-
#define QSERDES_RX_RX_MODE_10_HIGH2 (QSERDES_RX + 0x18c)
76
-
#define QSERDES_RX_RX_MODE_10_HIGH3 (QSERDES_RX + 0x190)
77
-
#define QSERDES_RX_RX_MODE_10_HIGH4 (QSERDES_RX + 0x194)
78
-
#define QSERDES_RX_DCC_CTRL1 (QSERDES_RX + 0x1a8)
79
-
80
20
#define QSERDES_TX 0x400
81
-
#define QSERDES_TX_TX_BAND (QSERDES_TX + 0x24)
82
-
#define QSERDES_TX_SLEW_CNTL (QSERDES_TX + 0x28)
83
-
#define QSERDES_TX_RES_CODE_LANE_OFFSET_TX (QSERDES_TX + 0x3c)
84
-
#define QSERDES_TX_RES_CODE_LANE_OFFSET_RX (QSERDES_TX + 0x40)
85
-
#define QSERDES_TX_LANE_MODE_1 (QSERDES_TX + 0x84)
86
-
#define QSERDES_TX_LANE_MODE_3 (QSERDES_TX + 0x8c)
87
-
#define QSERDES_TX_RCV_DETECT_LVL_2 (QSERDES_TX + 0xa4)
88
-
#define QSERDES_TX_TRAN_DRVR_EMP_EN (QSERDES_TX + 0xc0)
89
-
90
-
#define QSERDES_PCS 0xC00
91
-
#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0)
92
-
#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
93
-
#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8)
94
-
#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc)
95
-
#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
96
-
#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
97
-
#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8)
98
-
#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc)
99
-
#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)
100
-
#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94)
21
+
#define QSERDES_PCS 0xc00
101
22
102
23
#define QSERDES_COM_C_READY BIT(0)
103
24
#define QSERDES_PCS_READY BIT(0)
···
33
112
34
113
static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap)
35
114
{
36
-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
37
-
regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
115
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
116
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
38
117
39
-
regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F);
40
-
regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06);
41
-
regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
42
-
regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);
43
-
regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A);
44
-
regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A);
45
-
regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A);
46
-
regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x82);
47
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55);
48
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55);
49
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03);
50
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0x24);
118
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
119
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
120
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16);
121
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36);
122
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A);
123
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A);
124
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A);
125
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82);
126
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55);
127
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55);
128
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03);
129
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24);
51
130
52
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02);
53
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00);
54
-
regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x04);
55
-
regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00);
56
-
regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x0A);
57
-
regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00);
58
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9);
59
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E);
60
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);
131
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02);
132
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00);
133
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x04);
134
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00);
135
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0A);
136
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00);
137
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9);
138
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E);
139
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);
61
140
62
-
regmap_write(regmap, QSERDES_TX_TX_BAND, 0x05);
63
-
regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A);
64
-
regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09);
65
-
regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x09);
66
-
regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05);
67
-
regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00);
68
-
regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12);
69
-
regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C);
141
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x05);
142
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);
143
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);
144
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09);
145
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);
146
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);
147
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);
148
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);
70
149
71
-
regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A);
72
-
regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06);
73
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);
74
-
regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);
75
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);
76
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);
77
-
regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81);
78
-
regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80);
79
-
regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x04);
80
-
regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08);
81
-
regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F);
82
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);
83
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);
84
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);
85
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);
86
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80);
87
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01);
88
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20);
89
-
regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);
90
-
regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);
91
-
regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F);
92
-
regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);
93
-
regmap_write(regmap, QSERDES_RX_RX_BAND, 0x05);
94
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0xE0);
95
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8);
96
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8);
97
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x09);
98
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB1);
99
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0);
100
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8);
101
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8);
102
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09);
103
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1);
104
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0);
105
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8);
106
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8);
107
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B);
108
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7);
109
-
regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C);
150
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A);
151
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06);
152
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);
153
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);
154
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);
155
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);
156
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81);
157
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80);
158
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x04);
159
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08);
160
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F);
161
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);
162
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);
163
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);
164
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);
165
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80);
166
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01);
167
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20);
168
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);
169
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);
170
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F);
171
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);
172
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x05);
173
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0xE0);
174
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8);
175
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8);
176
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x09);
177
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB1);
178
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0);
179
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8);
180
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8);
181
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09);
182
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1);
183
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0);
184
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8);
185
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8);
186
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B);
187
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
188
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
110
189
111
-
regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
112
-
regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
113
-
regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
114
-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
115
-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
116
-
regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C);
117
-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
190
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
191
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
192
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
193
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
194
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
195
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C);
196
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
118
197
119
-
regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
198
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
120
199
}
121
200
122
201
static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap)
123
202
{
124
-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
125
-
regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
203
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
204
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
126
205
127
-
regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F);
128
-
regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06);
129
-
regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
130
-
regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);
131
-
regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A);
132
-
regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x1A);
133
-
regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x41);
134
-
regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x7A);
135
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00);
136
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x20);
137
-
regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x01);
138
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0xA1);
206
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
207
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
208
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16);
209
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36);
210
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A);
211
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x1A);
212
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x41);
213
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x7A);
214
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x00);
215
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x20);
216
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x01);
217
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xA1);
139
218
140
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02);
141
-
regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00);
142
-
regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x03);
143
-
regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00);
144
-
regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x05);
145
-
regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00);
146
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD);
147
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C);
148
-
regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);
219
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02);
220
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00);
221
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x03);
222
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00);
223
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x05);
224
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00);
225
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD);
226
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C);
227
+
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11);
149
228
150
-
regmap_write(regmap, QSERDES_TX_TX_BAND, 0x04);
151
-
regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A);
152
-
regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09);
153
-
regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x02);
154
-
regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05);
155
-
regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00);
156
-
regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12);
157
-
regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C);
229
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x04);
230
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);
231
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);
232
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x02);
233
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);
234
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);
235
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);
236
+
regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);
158
237
159
-
regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A);
160
-
regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06);
161
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);
162
-
regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);
163
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);
164
-
regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);
165
-
regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81);
166
-
regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80);
167
-
regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x00);
168
-
regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08);
169
-
regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F);
170
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);
171
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);
172
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);
173
-
regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);
174
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80);
175
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01);
176
-
regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20);
177
-
regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);
178
-
regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);
179
-
regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F);
180
-
regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);
181
-
regmap_write(regmap, QSERDES_RX_RX_BAND, 0x18);
182
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0x18);
183
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8);
184
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8);
185
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x0C);
186
-
regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB8);
187
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0);
188
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8);
189
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8);
190
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09);
191
-
regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1);
192
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0);
193
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8);
194
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8);
195
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B);
196
-
regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7);
197
-
regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C);
238
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A);
239
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06);
240
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A);
241
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F);
242
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00);
243
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01);
244
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81);
245
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80);
246
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x00);
247
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08);
248
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F);
249
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04);
250
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00);
251
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A);
252
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A);
253
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80);
254
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01);
255
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20);
256
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17);
257
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00);
258
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F);
259
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E);
260
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x18);
261
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0x18);
262
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8);
263
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8);
264
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x0C);
265
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB8);
266
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0);
267
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8);
268
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8);
269
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09);
270
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1);
271
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0);
272
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8);
273
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8);
274
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B);
275
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
276
+
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
198
277
199
-
regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
200
-
regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
201
-
regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
202
-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
203
-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
204
-
regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C);
205
-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
278
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
279
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
280
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
281
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
282
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
283
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C);
284
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
206
285
207
-
regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
286
+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
208
287
}
209
288
210
289
static inline int
···
234
313
}
235
314
236
315
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
237
-
QSERDES_COM_C_READY_STATUS,
316
+
QSERDES_QMP_PLL + QSERDES_V5_COM_C_READY_STATUS,
238
317
QSERDES_COM_C_READY)) {
239
318
dev_err(dev, "QSERDES_COM_C_READY_STATUS timed-out");
240
319
return -ETIMEDOUT;
241
320
}
242
321
243
322
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
244
-
QSERDES_PCS_PCS_READY_STATUS,
323
+
QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
245
324
QSERDES_PCS_READY)) {
246
325
dev_err(dev, "PCS_READY timed-out");
247
326
return -ETIMEDOUT;
248
327
}
249
328
250
329
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
251
-
QSERDES_PCS_PCS_READY_STATUS,
330
+
QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
252
331
QSERDES_PCS_SGMIIPHY_READY)) {
253
332
dev_err(dev, "SGMIIPHY_READY timed-out");
254
333
return -ETIMEDOUT;
255
334
}
256
335
257
336
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
258
-
QSERDES_COM_CMN_STATUS,
337
+
QSERDES_QMP_PLL + QSERDES_V5_COM_CMN_STATUS,
259
338
QSERDES_COM_C_PLL_LOCKED)) {
260
339
dev_err(dev, "PLL Lock Status timed-out");
261
340
return -ETIMEDOUT;
···
275
354
{
276
355
struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
277
356
278
-
regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
279
-
regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01);
357
+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
358
+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
280
359
udelay(100);
281
-
regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00);
282
-
regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01);
360
+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
361
+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
283
362
284
363
clk_disable_unprepare(data->refclk);
285
364
+1
-1
drivers/phy/ralink/phy-mt7621-pci.c
+1
-1
drivers/phy/ralink/phy-mt7621-pci.c
+1
-1
drivers/phy/renesas/phy-rcar-gen2.c
+1
-1
drivers/phy/renesas/phy-rcar-gen2.c
···
306
306
MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
307
307
308
308
static struct phy *rcar_gen2_phy_xlate(struct device *dev,
309
-
struct of_phandle_args *args)
309
+
const struct of_phandle_args *args)
310
310
{
311
311
struct rcar_gen2_phy_driver *drv;
312
312
struct device_node *np = args->np;
+1
-1
drivers/phy/renesas/phy-rcar-gen3-usb2.c
+1
-1
drivers/phy/renesas/phy-rcar-gen3-usb2.c
+1
-1
drivers/phy/renesas/r8a779f0-ether-serdes.c
+1
-1
drivers/phy/renesas/r8a779f0-ether-serdes.c
+8
drivers/phy/rockchip/Kconfig
+8
drivers/phy/rockchip/Kconfig
···
83
83
help
84
84
Enable this to support the Rockchip PCIe PHY.
85
85
86
+
config PHY_ROCKCHIP_SAMSUNG_HDPTX
87
+
tristate "Rockchip Samsung HDMI/eDP Combo PHY driver"
88
+
depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
89
+
select GENERIC_PHY
90
+
help
91
+
Enable this to support the Rockchip HDMI/eDP Combo PHY
92
+
with Samsung IP block.
93
+
86
94
config PHY_ROCKCHIP_SNPS_PCIE3
87
95
tristate "Rockchip Snps PCIe3 PHY Driver"
88
96
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
+1
drivers/phy/rockchip/Makefile
+1
drivers/phy/rockchip/Makefile
···
8
8
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
9
9
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
10
10
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
11
+
obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX) += phy-rockchip-samsung-hdptx.o
11
12
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
12
13
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
13
14
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+1
-1
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+1
-1
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
···
251
251
.owner = THIS_MODULE,
252
252
};
253
253
254
-
static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
254
+
static struct phy *rockchip_combphy_xlate(struct device *dev, const struct of_phandle_args *args)
255
255
{
256
256
struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
257
257
+1
-1
drivers/phy/rockchip/phy-rockchip-pcie.c
+1
-1
drivers/phy/rockchip/phy-rockchip-pcie.c
+1028
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+1028
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
*
6
+
* Author: Algea Cao <algea.cao@rock-chips.com>
7
+
* Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
8
+
*/
9
+
#include <linux/bitfield.h>
10
+
#include <linux/clk.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/mfd/syscon.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of.h>
15
+
#include <linux/of_platform.h>
16
+
#include <linux/phy/phy.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/rational.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/reset.h>
21
+
22
+
#define GRF_HDPTX_CON0 0x00
23
+
#define HDPTX_I_PLL_EN BIT(7)
24
+
#define HDPTX_I_BIAS_EN BIT(6)
25
+
#define HDPTX_I_BGR_EN BIT(5)
26
+
#define GRF_HDPTX_STATUS 0x80
27
+
#define HDPTX_O_PLL_LOCK_DONE BIT(3)
28
+
#define HDPTX_O_PHY_CLK_RDY BIT(2)
29
+
#define HDPTX_O_PHY_RDY BIT(1)
30
+
#define HDPTX_O_SB_RDY BIT(0)
31
+
32
+
#define HDTPX_REG(_n, _min, _max) \
33
+
( \
34
+
BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
35
+
BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
36
+
((0x##_n) * 4) \
37
+
)
38
+
39
+
#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
40
+
#define SB_REG(n) HDTPX_REG(n, 0100, 0129)
41
+
#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
42
+
#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
43
+
44
+
/* CMN_REG(0008) */
45
+
#define LCPLL_EN_MASK BIT(6)
46
+
#define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
47
+
/* CMN_REG(001e) */
48
+
#define LCPLL_PI_EN_MASK BIT(5)
49
+
#define LCPLL_100M_CLK_EN_MASK BIT(0)
50
+
/* CMN_REG(0025) */
51
+
#define LCPLL_PMS_IQDIV_RSTN BIT(4)
52
+
/* CMN_REG(0028) */
53
+
#define LCPLL_SDC_FRAC_EN BIT(2)
54
+
#define LCPLL_SDC_FRAC_RSTN BIT(0)
55
+
/* CMN_REG(002d) */
56
+
#define LCPLL_SDC_N_MASK GENMASK(3, 1)
57
+
/* CMN_REG(002e) */
58
+
#define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
59
+
/* CMN_REG(002f) */
60
+
#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
61
+
#define LCPLL_SDC_NDIV_RSTN BIT(0)
62
+
/* CMN_REG(003d) */
63
+
#define ROPLL_LCVCO_EN BIT(4)
64
+
/* CMN_REG(004e) */
65
+
#define ROPLL_PI_EN BIT(5)
66
+
/* CMN_REG(005c) */
67
+
#define ROPLL_PMS_IQDIV_RSTN BIT(5)
68
+
/* CMN_REG(005e) */
69
+
#define ROPLL_SDM_EN_MASK BIT(6)
70
+
#define ROPLL_SDM_FRAC_EN_RBR BIT(3)
71
+
#define ROPLL_SDM_FRAC_EN_HBR BIT(2)
72
+
#define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
73
+
#define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
74
+
/* CMN_REG(0064) */
75
+
#define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
76
+
/* CMN_REG(0069) */
77
+
#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
78
+
/* CMN_REG(0074) */
79
+
#define ROPLL_SDC_NDIV_RSTN BIT(2)
80
+
#define ROPLL_SSC_EN BIT(0)
81
+
/* CMN_REG(0081) */
82
+
#define OVRD_PLL_CD_CLK_EN BIT(8)
83
+
#define PLL_CD_HSCLK_EAST_EN BIT(0)
84
+
/* CMN_REG(0086) */
85
+
#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
86
+
#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
87
+
#define PLL_PCG_CLK_EN BIT(0)
88
+
/* CMN_REG(0087) */
89
+
#define PLL_FRL_MODE_EN BIT(3)
90
+
#define PLL_TX_HS_CLK_EN BIT(2)
91
+
/* CMN_REG(0089) */
92
+
#define LCPLL_ALONE_MODE BIT(1)
93
+
/* CMN_REG(0097) */
94
+
#define DIG_CLK_SEL BIT(1)
95
+
#define ROPLL_REF BIT(1)
96
+
#define LCPLL_REF 0
97
+
/* CMN_REG(0099) */
98
+
#define CMN_ROPLL_ALONE_MODE BIT(2)
99
+
#define ROPLL_ALONE_MODE BIT(2)
100
+
/* CMN_REG(009a) */
101
+
#define HS_SPEED_SEL BIT(0)
102
+
#define DIV_10_CLOCK BIT(0)
103
+
/* CMN_REG(009b) */
104
+
#define IS_SPEED_SEL BIT(4)
105
+
#define LINK_SYMBOL_CLOCK BIT(4)
106
+
#define LINK_SYMBOL_CLOCK1_2 0
107
+
108
+
/* SB_REG(0102) */
109
+
#define OVRD_SB_RXTERM_EN_MASK BIT(5)
110
+
#define SB_RXTERM_EN_MASK BIT(4)
111
+
#define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
112
+
/* SB_REG(0103) */
113
+
#define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
114
+
#define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
115
+
#define SB_RX_RESCAL_DONE_MASK BIT(0)
116
+
/* SB_REG(0104) */
117
+
#define OVRD_SB_EN_MASK BIT(5)
118
+
#define SB_EN_MASK BIT(4)
119
+
/* SB_REG(0105) */
120
+
#define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
121
+
#define SB_EARC_CMDC_EN_MASK BIT(5)
122
+
#define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
123
+
/* SB_REG(0106) */
124
+
#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
125
+
/* SB_REG(0109) */
126
+
#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
127
+
/* SB_REG(010f) */
128
+
#define OVRD_SB_VREG_EN_MASK BIT(7)
129
+
#define SB_VREG_EN_MASK BIT(6)
130
+
#define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
131
+
#define SB_VREG_LPF_BYPASS_MASK BIT(4)
132
+
#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
133
+
/* SB_REG(0110) */
134
+
#define ANA_SB_VREG_REF_SEL_MASK BIT(0)
135
+
/* SB_REG(0113) */
136
+
#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
137
+
#define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
138
+
/* SB_REG(0114) */
139
+
#define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
140
+
#define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
141
+
/* SB_REG(0115) */
142
+
#define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
143
+
#define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
144
+
/* SB_REG(0116) */
145
+
#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
146
+
/* SB_REG(0117) */
147
+
#define FAST_PULSE_TIME_MASK GENMASK(3, 0)
148
+
/* SB_REG(011b) */
149
+
#define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
150
+
#define SB_AFC_TOL_MASK GENMASK(3, 0)
151
+
/* SB_REG(011f) */
152
+
#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
153
+
#define SB_RCAL_RSTN_MASK BIT(1)
154
+
/* SB_REG(0120) */
155
+
#define SB_EARC_EN_MASK BIT(1)
156
+
#define SB_EARC_AFC_EN_MASK BIT(2)
157
+
/* SB_REG(0123) */
158
+
#define OVRD_SB_READY_MASK BIT(5)
159
+
#define SB_READY_MASK BIT(4)
160
+
161
+
/* LNTOP_REG(0200) */
162
+
#define PROTOCOL_SEL BIT(2)
163
+
#define HDMI_MODE BIT(2)
164
+
#define HDMI_TMDS_FRL_SEL BIT(1)
165
+
/* LNTOP_REG(0206) */
166
+
#define DATA_BUS_SEL BIT(0)
167
+
#define DATA_BUS_36_40 BIT(0)
168
+
/* LNTOP_REG(0207) */
169
+
#define LANE_EN 0xf
170
+
#define ALL_LANE_EN 0xf
171
+
172
+
/* LANE_REG(0312) */
173
+
#define LN0_TX_SER_RATE_SEL_RBR BIT(5)
174
+
#define LN0_TX_SER_RATE_SEL_HBR BIT(4)
175
+
#define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
176
+
#define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
177
+
/* LANE_REG(0412) */
178
+
#define LN1_TX_SER_RATE_SEL_RBR BIT(5)
179
+
#define LN1_TX_SER_RATE_SEL_HBR BIT(4)
180
+
#define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
181
+
#define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
182
+
/* LANE_REG(0512) */
183
+
#define LN2_TX_SER_RATE_SEL_RBR BIT(5)
184
+
#define LN2_TX_SER_RATE_SEL_HBR BIT(4)
185
+
#define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
186
+
#define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
187
+
/* LANE_REG(0612) */
188
+
#define LN3_TX_SER_RATE_SEL_RBR BIT(5)
189
+
#define LN3_TX_SER_RATE_SEL_HBR BIT(4)
190
+
#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
191
+
#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
192
+
193
+
struct lcpll_config {
194
+
u32 bit_rate;
195
+
u8 lcvco_mode_en;
196
+
u8 pi_en;
197
+
u8 clk_en_100m;
198
+
u8 pms_mdiv;
199
+
u8 pms_mdiv_afc;
200
+
u8 pms_pdiv;
201
+
u8 pms_refdiv;
202
+
u8 pms_sdiv;
203
+
u8 pi_cdiv_rstn;
204
+
u8 pi_cdiv_sel;
205
+
u8 sdm_en;
206
+
u8 sdm_rstn;
207
+
u8 sdc_frac_en;
208
+
u8 sdc_rstn;
209
+
u8 sdm_deno;
210
+
u8 sdm_num_sign;
211
+
u8 sdm_num;
212
+
u8 sdc_n;
213
+
u8 sdc_n2;
214
+
u8 sdc_num;
215
+
u8 sdc_deno;
216
+
u8 sdc_ndiv_rstn;
217
+
u8 ssc_en;
218
+
u8 ssc_fm_dev;
219
+
u8 ssc_fm_freq;
220
+
u8 ssc_clk_div_sel;
221
+
u8 cd_tx_ser_rate_sel;
222
+
};
223
+
224
+
struct ropll_config {
225
+
u32 bit_rate;
226
+
u8 pms_mdiv;
227
+
u8 pms_mdiv_afc;
228
+
u8 pms_pdiv;
229
+
u8 pms_refdiv;
230
+
u8 pms_sdiv;
231
+
u8 pms_iqdiv_rstn;
232
+
u8 ref_clk_sel;
233
+
u8 sdm_en;
234
+
u8 sdm_rstn;
235
+
u8 sdc_frac_en;
236
+
u8 sdc_rstn;
237
+
u8 sdm_clk_div;
238
+
u8 sdm_deno;
239
+
u8 sdm_num_sign;
240
+
u8 sdm_num;
241
+
u8 sdc_n;
242
+
u8 sdc_num;
243
+
u8 sdc_deno;
244
+
u8 sdc_ndiv_rstn;
245
+
u8 ssc_en;
246
+
u8 ssc_fm_dev;
247
+
u8 ssc_fm_freq;
248
+
u8 ssc_clk_div_sel;
249
+
u8 ana_cpp_ctrl;
250
+
u8 ana_lpf_c_sel;
251
+
u8 cd_tx_ser_rate_sel;
252
+
};
253
+
254
+
enum rk_hdptx_reset {
255
+
RST_PHY = 0,
256
+
RST_APB,
257
+
RST_INIT,
258
+
RST_CMN,
259
+
RST_LANE,
260
+
RST_ROPLL,
261
+
RST_LCPLL,
262
+
RST_MAX
263
+
};
264
+
265
+
struct rk_hdptx_phy {
266
+
struct device *dev;
267
+
struct regmap *regmap;
268
+
struct regmap *grf;
269
+
270
+
struct phy *phy;
271
+
struct phy_config *phy_cfg;
272
+
struct clk_bulk_data *clks;
273
+
int nr_clks;
274
+
struct reset_control_bulk_data rsts[RST_MAX];
275
+
};
276
+
277
+
static const struct ropll_config ropll_tmds_cfg[] = {
278
+
{ 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
279
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
280
+
{ 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
281
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
282
+
{ 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
283
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
284
+
{ 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
285
+
1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
286
+
{ 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
287
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
288
+
{ 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
289
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
290
+
{ 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
291
+
0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
292
+
{ 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
293
+
1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
294
+
{ 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
295
+
1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
296
+
{ 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
297
+
1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
298
+
{ 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
299
+
0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
300
+
{ 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
301
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
302
+
{ 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
303
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
304
+
{ 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
305
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
306
+
{ 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
307
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
308
+
{ 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
309
+
1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
310
+
{ 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
311
+
1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
312
+
{ 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
313
+
0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
314
+
{ 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
315
+
0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
316
+
{ 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
317
+
1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
318
+
};
319
+
320
+
static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
321
+
REG_SEQ0(CMN_REG(0009), 0x0c),
322
+
REG_SEQ0(CMN_REG(000a), 0x83),
323
+
REG_SEQ0(CMN_REG(000b), 0x06),
324
+
REG_SEQ0(CMN_REG(000c), 0x20),
325
+
REG_SEQ0(CMN_REG(000d), 0xb8),
326
+
REG_SEQ0(CMN_REG(000e), 0x0f),
327
+
REG_SEQ0(CMN_REG(000f), 0x0f),
328
+
REG_SEQ0(CMN_REG(0010), 0x04),
329
+
REG_SEQ0(CMN_REG(0011), 0x00),
330
+
REG_SEQ0(CMN_REG(0012), 0x26),
331
+
REG_SEQ0(CMN_REG(0013), 0x22),
332
+
REG_SEQ0(CMN_REG(0014), 0x24),
333
+
REG_SEQ0(CMN_REG(0015), 0x77),
334
+
REG_SEQ0(CMN_REG(0016), 0x08),
335
+
REG_SEQ0(CMN_REG(0017), 0x00),
336
+
REG_SEQ0(CMN_REG(0018), 0x04),
337
+
REG_SEQ0(CMN_REG(0019), 0x48),
338
+
REG_SEQ0(CMN_REG(001a), 0x01),
339
+
REG_SEQ0(CMN_REG(001b), 0x00),
340
+
REG_SEQ0(CMN_REG(001c), 0x01),
341
+
REG_SEQ0(CMN_REG(001d), 0x64),
342
+
REG_SEQ0(CMN_REG(001f), 0x00),
343
+
REG_SEQ0(CMN_REG(0026), 0x53),
344
+
REG_SEQ0(CMN_REG(0029), 0x01),
345
+
REG_SEQ0(CMN_REG(0030), 0x00),
346
+
REG_SEQ0(CMN_REG(0031), 0x20),
347
+
REG_SEQ0(CMN_REG(0032), 0x30),
348
+
REG_SEQ0(CMN_REG(0033), 0x0b),
349
+
REG_SEQ0(CMN_REG(0034), 0x23),
350
+
REG_SEQ0(CMN_REG(0035), 0x00),
351
+
REG_SEQ0(CMN_REG(0038), 0x00),
352
+
REG_SEQ0(CMN_REG(0039), 0x00),
353
+
REG_SEQ0(CMN_REG(003a), 0x00),
354
+
REG_SEQ0(CMN_REG(003b), 0x00),
355
+
REG_SEQ0(CMN_REG(003c), 0x80),
356
+
REG_SEQ0(CMN_REG(003e), 0x0c),
357
+
REG_SEQ0(CMN_REG(003f), 0x83),
358
+
REG_SEQ0(CMN_REG(0040), 0x06),
359
+
REG_SEQ0(CMN_REG(0041), 0x20),
360
+
REG_SEQ0(CMN_REG(0042), 0xb8),
361
+
REG_SEQ0(CMN_REG(0043), 0x00),
362
+
REG_SEQ0(CMN_REG(0044), 0x46),
363
+
REG_SEQ0(CMN_REG(0045), 0x24),
364
+
REG_SEQ0(CMN_REG(0046), 0xff),
365
+
REG_SEQ0(CMN_REG(0047), 0x00),
366
+
REG_SEQ0(CMN_REG(0048), 0x44),
367
+
REG_SEQ0(CMN_REG(0049), 0xfa),
368
+
REG_SEQ0(CMN_REG(004a), 0x08),
369
+
REG_SEQ0(CMN_REG(004b), 0x00),
370
+
REG_SEQ0(CMN_REG(004c), 0x01),
371
+
REG_SEQ0(CMN_REG(004d), 0x64),
372
+
REG_SEQ0(CMN_REG(004e), 0x14),
373
+
REG_SEQ0(CMN_REG(004f), 0x00),
374
+
REG_SEQ0(CMN_REG(0050), 0x00),
375
+
REG_SEQ0(CMN_REG(005d), 0x0c),
376
+
REG_SEQ0(CMN_REG(005f), 0x01),
377
+
REG_SEQ0(CMN_REG(006b), 0x04),
378
+
REG_SEQ0(CMN_REG(0073), 0x30),
379
+
REG_SEQ0(CMN_REG(0074), 0x00),
380
+
REG_SEQ0(CMN_REG(0075), 0x20),
381
+
REG_SEQ0(CMN_REG(0076), 0x30),
382
+
REG_SEQ0(CMN_REG(0077), 0x08),
383
+
REG_SEQ0(CMN_REG(0078), 0x0c),
384
+
REG_SEQ0(CMN_REG(0079), 0x00),
385
+
REG_SEQ0(CMN_REG(007b), 0x00),
386
+
REG_SEQ0(CMN_REG(007c), 0x00),
387
+
REG_SEQ0(CMN_REG(007d), 0x00),
388
+
REG_SEQ0(CMN_REG(007e), 0x00),
389
+
REG_SEQ0(CMN_REG(007f), 0x00),
390
+
REG_SEQ0(CMN_REG(0080), 0x00),
391
+
REG_SEQ0(CMN_REG(0081), 0x09),
392
+
REG_SEQ0(CMN_REG(0082), 0x04),
393
+
REG_SEQ0(CMN_REG(0083), 0x24),
394
+
REG_SEQ0(CMN_REG(0084), 0x20),
395
+
REG_SEQ0(CMN_REG(0085), 0x03),
396
+
REG_SEQ0(CMN_REG(0086), 0x01),
397
+
REG_SEQ0(CMN_REG(0087), 0x0c),
398
+
REG_SEQ0(CMN_REG(008a), 0x55),
399
+
REG_SEQ0(CMN_REG(008b), 0x25),
400
+
REG_SEQ0(CMN_REG(008c), 0x2c),
401
+
REG_SEQ0(CMN_REG(008d), 0x22),
402
+
REG_SEQ0(CMN_REG(008e), 0x14),
403
+
REG_SEQ0(CMN_REG(008f), 0x20),
404
+
REG_SEQ0(CMN_REG(0090), 0x00),
405
+
REG_SEQ0(CMN_REG(0091), 0x00),
406
+
REG_SEQ0(CMN_REG(0092), 0x00),
407
+
REG_SEQ0(CMN_REG(0093), 0x00),
408
+
REG_SEQ0(CMN_REG(009a), 0x11),
409
+
REG_SEQ0(CMN_REG(009b), 0x10),
410
+
};
411
+
412
+
static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
413
+
REG_SEQ0(CMN_REG(0008), 0x00),
414
+
REG_SEQ0(CMN_REG(0011), 0x01),
415
+
REG_SEQ0(CMN_REG(0017), 0x20),
416
+
REG_SEQ0(CMN_REG(001e), 0x14),
417
+
REG_SEQ0(CMN_REG(0020), 0x00),
418
+
REG_SEQ0(CMN_REG(0021), 0x00),
419
+
REG_SEQ0(CMN_REG(0022), 0x11),
420
+
REG_SEQ0(CMN_REG(0023), 0x00),
421
+
REG_SEQ0(CMN_REG(0024), 0x00),
422
+
REG_SEQ0(CMN_REG(0025), 0x53),
423
+
REG_SEQ0(CMN_REG(0026), 0x00),
424
+
REG_SEQ0(CMN_REG(0027), 0x00),
425
+
REG_SEQ0(CMN_REG(0028), 0x01),
426
+
REG_SEQ0(CMN_REG(002a), 0x00),
427
+
REG_SEQ0(CMN_REG(002b), 0x00),
428
+
REG_SEQ0(CMN_REG(002c), 0x00),
429
+
REG_SEQ0(CMN_REG(002d), 0x00),
430
+
REG_SEQ0(CMN_REG(002e), 0x04),
431
+
REG_SEQ0(CMN_REG(002f), 0x00),
432
+
REG_SEQ0(CMN_REG(0030), 0x20),
433
+
REG_SEQ0(CMN_REG(0031), 0x30),
434
+
REG_SEQ0(CMN_REG(0032), 0x0b),
435
+
REG_SEQ0(CMN_REG(0033), 0x23),
436
+
REG_SEQ0(CMN_REG(0034), 0x00),
437
+
REG_SEQ0(CMN_REG(003d), 0x40),
438
+
REG_SEQ0(CMN_REG(0042), 0x78),
439
+
REG_SEQ0(CMN_REG(004e), 0x34),
440
+
REG_SEQ0(CMN_REG(005c), 0x25),
441
+
REG_SEQ0(CMN_REG(005e), 0x4f),
442
+
REG_SEQ0(CMN_REG(0074), 0x04),
443
+
REG_SEQ0(CMN_REG(0081), 0x01),
444
+
REG_SEQ0(CMN_REG(0087), 0x04),
445
+
REG_SEQ0(CMN_REG(0089), 0x00),
446
+
REG_SEQ0(CMN_REG(0095), 0x00),
447
+
REG_SEQ0(CMN_REG(0097), 0x02),
448
+
REG_SEQ0(CMN_REG(0099), 0x04),
449
+
REG_SEQ0(CMN_REG(009b), 0x00),
450
+
};
451
+
452
+
static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
453
+
REG_SEQ0(SB_REG(0114), 0x00),
454
+
REG_SEQ0(SB_REG(0115), 0x00),
455
+
REG_SEQ0(SB_REG(0116), 0x00),
456
+
REG_SEQ0(SB_REG(0117), 0x00),
457
+
};
458
+
459
+
static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
460
+
REG_SEQ0(LNTOP_REG(0201), 0x00),
461
+
REG_SEQ0(LNTOP_REG(0202), 0x00),
462
+
REG_SEQ0(LNTOP_REG(0203), 0x0f),
463
+
REG_SEQ0(LNTOP_REG(0204), 0xff),
464
+
REG_SEQ0(LNTOP_REG(0205), 0xff),
465
+
};
466
+
467
+
static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
468
+
REG_SEQ0(LNTOP_REG(0201), 0x07),
469
+
REG_SEQ0(LNTOP_REG(0202), 0xc1),
470
+
REG_SEQ0(LNTOP_REG(0203), 0xf0),
471
+
REG_SEQ0(LNTOP_REG(0204), 0x7c),
472
+
REG_SEQ0(LNTOP_REG(0205), 0x1f),
473
+
};
474
+
475
+
static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
476
+
REG_SEQ0(LANE_REG(0303), 0x0c),
477
+
REG_SEQ0(LANE_REG(0307), 0x20),
478
+
REG_SEQ0(LANE_REG(030a), 0x17),
479
+
REG_SEQ0(LANE_REG(030b), 0x77),
480
+
REG_SEQ0(LANE_REG(030c), 0x77),
481
+
REG_SEQ0(LANE_REG(030d), 0x77),
482
+
REG_SEQ0(LANE_REG(030e), 0x38),
483
+
REG_SEQ0(LANE_REG(0310), 0x03),
484
+
REG_SEQ0(LANE_REG(0311), 0x0f),
485
+
REG_SEQ0(LANE_REG(0316), 0x02),
486
+
REG_SEQ0(LANE_REG(031b), 0x01),
487
+
REG_SEQ0(LANE_REG(031f), 0x15),
488
+
REG_SEQ0(LANE_REG(0320), 0xa0),
489
+
REG_SEQ0(LANE_REG(0403), 0x0c),
490
+
REG_SEQ0(LANE_REG(0407), 0x20),
491
+
REG_SEQ0(LANE_REG(040a), 0x17),
492
+
REG_SEQ0(LANE_REG(040b), 0x77),
493
+
REG_SEQ0(LANE_REG(040c), 0x77),
494
+
REG_SEQ0(LANE_REG(040d), 0x77),
495
+
REG_SEQ0(LANE_REG(040e), 0x38),
496
+
REG_SEQ0(LANE_REG(0410), 0x03),
497
+
REG_SEQ0(LANE_REG(0411), 0x0f),
498
+
REG_SEQ0(LANE_REG(0416), 0x02),
499
+
REG_SEQ0(LANE_REG(041b), 0x01),
500
+
REG_SEQ0(LANE_REG(041f), 0x15),
501
+
REG_SEQ0(LANE_REG(0420), 0xa0),
502
+
REG_SEQ0(LANE_REG(0503), 0x0c),
503
+
REG_SEQ0(LANE_REG(0507), 0x20),
504
+
REG_SEQ0(LANE_REG(050a), 0x17),
505
+
REG_SEQ0(LANE_REG(050b), 0x77),
506
+
REG_SEQ0(LANE_REG(050c), 0x77),
507
+
REG_SEQ0(LANE_REG(050d), 0x77),
508
+
REG_SEQ0(LANE_REG(050e), 0x38),
509
+
REG_SEQ0(LANE_REG(0510), 0x03),
510
+
REG_SEQ0(LANE_REG(0511), 0x0f),
511
+
REG_SEQ0(LANE_REG(0516), 0x02),
512
+
REG_SEQ0(LANE_REG(051b), 0x01),
513
+
REG_SEQ0(LANE_REG(051f), 0x15),
514
+
REG_SEQ0(LANE_REG(0520), 0xa0),
515
+
REG_SEQ0(LANE_REG(0603), 0x0c),
516
+
REG_SEQ0(LANE_REG(0607), 0x20),
517
+
REG_SEQ0(LANE_REG(060a), 0x17),
518
+
REG_SEQ0(LANE_REG(060b), 0x77),
519
+
REG_SEQ0(LANE_REG(060c), 0x77),
520
+
REG_SEQ0(LANE_REG(060d), 0x77),
521
+
REG_SEQ0(LANE_REG(060e), 0x38),
522
+
REG_SEQ0(LANE_REG(0610), 0x03),
523
+
REG_SEQ0(LANE_REG(0611), 0x0f),
524
+
REG_SEQ0(LANE_REG(0616), 0x02),
525
+
REG_SEQ0(LANE_REG(061b), 0x01),
526
+
REG_SEQ0(LANE_REG(061f), 0x15),
527
+
REG_SEQ0(LANE_REG(0620), 0xa0),
528
+
};
529
+
530
+
static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
531
+
REG_SEQ0(LANE_REG(0312), 0x00),
532
+
REG_SEQ0(LANE_REG(031e), 0x00),
533
+
REG_SEQ0(LANE_REG(0412), 0x00),
534
+
REG_SEQ0(LANE_REG(041e), 0x00),
535
+
REG_SEQ0(LANE_REG(0512), 0x00),
536
+
REG_SEQ0(LANE_REG(051e), 0x00),
537
+
REG_SEQ0(LANE_REG(0612), 0x00),
538
+
REG_SEQ0(LANE_REG(061e), 0x08),
539
+
REG_SEQ0(LANE_REG(0303), 0x2f),
540
+
REG_SEQ0(LANE_REG(0403), 0x2f),
541
+
REG_SEQ0(LANE_REG(0503), 0x2f),
542
+
REG_SEQ0(LANE_REG(0603), 0x2f),
543
+
REG_SEQ0(LANE_REG(0305), 0x03),
544
+
REG_SEQ0(LANE_REG(0405), 0x03),
545
+
REG_SEQ0(LANE_REG(0505), 0x03),
546
+
REG_SEQ0(LANE_REG(0605), 0x03),
547
+
REG_SEQ0(LANE_REG(0306), 0x1c),
548
+
REG_SEQ0(LANE_REG(0406), 0x1c),
549
+
REG_SEQ0(LANE_REG(0506), 0x1c),
550
+
REG_SEQ0(LANE_REG(0606), 0x1c),
551
+
};
552
+
553
+
static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
554
+
{
555
+
switch (reg) {
556
+
case 0x0000 ... 0x029c:
557
+
case 0x0400 ... 0x04a4:
558
+
case 0x0800 ... 0x08a4:
559
+
case 0x0c00 ... 0x0cb4:
560
+
case 0x1000 ... 0x10b4:
561
+
case 0x1400 ... 0x14b4:
562
+
case 0x1800 ... 0x18b4:
563
+
return true;
564
+
}
565
+
566
+
return false;
567
+
}
568
+
569
+
static const struct regmap_config rk_hdptx_phy_regmap_config = {
570
+
.reg_bits = 32,
571
+
.reg_stride = 4,
572
+
.val_bits = 32,
573
+
.writeable_reg = rk_hdptx_phy_is_rw_reg,
574
+
.readable_reg = rk_hdptx_phy_is_rw_reg,
575
+
.fast_io = true,
576
+
.max_register = 0x18b4,
577
+
};
578
+
579
+
#define rk_hdptx_multi_reg_write(hdptx, seq) \
580
+
regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
581
+
582
+
static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
583
+
{
584
+
u32 val;
585
+
586
+
reset_control_assert(hdptx->rsts[RST_APB].rstc);
587
+
usleep_range(20, 25);
588
+
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
589
+
590
+
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
591
+
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
592
+
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
593
+
594
+
val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
595
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
596
+
}
597
+
598
+
static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
599
+
{
600
+
u32 val;
601
+
int ret;
602
+
603
+
reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
604
+
605
+
val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
606
+
HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
607
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
608
+
609
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
610
+
(val & HDPTX_O_PHY_RDY) &&
611
+
(val & HDPTX_O_PLL_LOCK_DONE),
612
+
100, 5000);
613
+
if (ret) {
614
+
dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
615
+
return ret;
616
+
}
617
+
618
+
dev_dbg(hdptx->dev, "PHY lane locked\n");
619
+
620
+
return 0;
621
+
}
622
+
623
+
static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
624
+
{
625
+
u32 val;
626
+
int ret;
627
+
628
+
val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
629
+
HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
630
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
631
+
632
+
usleep_range(10, 15);
633
+
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
634
+
635
+
usleep_range(10, 15);
636
+
val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
637
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
638
+
639
+
usleep_range(10, 15);
640
+
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
641
+
642
+
ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
643
+
val & HDPTX_O_PHY_CLK_RDY, 20, 400);
644
+
if (ret) {
645
+
dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
646
+
return ret;
647
+
}
648
+
649
+
dev_dbg(hdptx->dev, "PHY clk ready\n");
650
+
651
+
return 0;
652
+
}
653
+
654
+
static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
655
+
{
656
+
u32 val;
657
+
658
+
/* reset phy and apb, or phy locked flag may keep 1 */
659
+
reset_control_assert(hdptx->rsts[RST_PHY].rstc);
660
+
usleep_range(20, 30);
661
+
reset_control_deassert(hdptx->rsts[RST_PHY].rstc);
662
+
663
+
reset_control_assert(hdptx->rsts[RST_APB].rstc);
664
+
usleep_range(20, 30);
665
+
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
666
+
667
+
regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
668
+
regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
669
+
regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
670
+
regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
671
+
regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
672
+
regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
673
+
regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
674
+
675
+
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
676
+
reset_control_assert(hdptx->rsts[RST_CMN].rstc);
677
+
reset_control_assert(hdptx->rsts[RST_INIT].rstc);
678
+
679
+
val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
680
+
regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
681
+
}
682
+
683
+
static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
684
+
struct ropll_config *cfg)
685
+
{
686
+
const unsigned int fout = data_rate / 2, fref = 24000;
687
+
unsigned long k = 0, lc, k_sub, lc_sub;
688
+
unsigned int fvco, sdc;
689
+
u32 mdiv, sdiv, n = 8;
690
+
691
+
if (fout > 0xfffffff)
692
+
return false;
693
+
694
+
for (sdiv = 16; sdiv >= 1; sdiv--) {
695
+
if (sdiv % 2 && sdiv != 1)
696
+
continue;
697
+
698
+
fvco = fout * sdiv;
699
+
700
+
if (fvco < 2000000 || fvco > 4000000)
701
+
continue;
702
+
703
+
mdiv = DIV_ROUND_UP(fvco, fref);
704
+
if (mdiv < 20 || mdiv > 255)
705
+
continue;
706
+
707
+
if (fref * mdiv - fvco) {
708
+
for (sdc = 264000; sdc <= 750000; sdc += fref)
709
+
if (sdc * n > fref * mdiv)
710
+
break;
711
+
712
+
if (sdc > 750000)
713
+
continue;
714
+
715
+
rational_best_approximation(fref * mdiv - fvco,
716
+
sdc / 16,
717
+
GENMASK(6, 0),
718
+
GENMASK(7, 0),
719
+
&k, &lc);
720
+
721
+
rational_best_approximation(sdc * n - fref * mdiv,
722
+
sdc,
723
+
GENMASK(6, 0),
724
+
GENMASK(7, 0),
725
+
&k_sub, &lc_sub);
726
+
}
727
+
728
+
break;
729
+
}
730
+
731
+
if (sdiv < 1)
732
+
return false;
733
+
734
+
if (cfg) {
735
+
cfg->pms_mdiv = mdiv;
736
+
cfg->pms_mdiv_afc = mdiv;
737
+
cfg->pms_pdiv = 1;
738
+
cfg->pms_refdiv = 1;
739
+
cfg->pms_sdiv = sdiv - 1;
740
+
741
+
cfg->sdm_en = k > 0 ? 1 : 0;
742
+
if (cfg->sdm_en) {
743
+
cfg->sdm_deno = lc;
744
+
cfg->sdm_num_sign = 1;
745
+
cfg->sdm_num = k;
746
+
cfg->sdc_n = n - 3;
747
+
cfg->sdc_num = k_sub;
748
+
cfg->sdc_deno = lc_sub;
749
+
}
750
+
}
751
+
752
+
return true;
753
+
}
754
+
755
+
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
756
+
unsigned int rate)
757
+
{
758
+
const struct ropll_config *cfg = NULL;
759
+
struct ropll_config rc = {0};
760
+
int i;
761
+
762
+
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
763
+
if (rate == ropll_tmds_cfg[i].bit_rate) {
764
+
cfg = &ropll_tmds_cfg[i];
765
+
break;
766
+
}
767
+
768
+
if (!cfg) {
769
+
if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
770
+
cfg = &rc;
771
+
} else {
772
+
dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
773
+
return -EINVAL;
774
+
}
775
+
}
776
+
777
+
dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
778
+
cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
779
+
cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
780
+
781
+
rk_hdptx_pre_power_up(hdptx);
782
+
783
+
reset_control_assert(hdptx->rsts[RST_ROPLL].rstc);
784
+
usleep_range(20, 30);
785
+
reset_control_deassert(hdptx->rsts[RST_ROPLL].rstc);
786
+
787
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
788
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
789
+
790
+
regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
791
+
regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
792
+
regmap_write(hdptx->regmap, CMN_REG(0059),
793
+
(cfg->pms_pdiv << 4) | cfg->pms_refdiv);
794
+
regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
795
+
796
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
797
+
FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
798
+
if (!cfg->sdm_en)
799
+
regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
800
+
801
+
regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
802
+
FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
803
+
804
+
regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
805
+
regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
806
+
807
+
regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
808
+
FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
809
+
810
+
regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
811
+
regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
812
+
813
+
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
814
+
FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
815
+
816
+
regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
817
+
PLL_PCG_CLK_EN);
818
+
819
+
return rk_hdptx_post_enable_pll(hdptx);
820
+
}
821
+
822
+
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
823
+
unsigned int rate)
824
+
{
825
+
u32 val;
826
+
int ret;
827
+
828
+
ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
829
+
if (ret)
830
+
return ret;
831
+
832
+
if (!(val & HDPTX_O_PLL_LOCK_DONE)) {
833
+
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
834
+
if (ret)
835
+
return ret;
836
+
}
837
+
838
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
839
+
840
+
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
841
+
842
+
if (rate >= 3400000) {
843
+
/* For 1/40 bitrate clk */
844
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
845
+
} else {
846
+
/* For 1/10 bitrate clk */
847
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
848
+
}
849
+
850
+
regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
851
+
regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
852
+
853
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
854
+
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
855
+
856
+
return rk_hdptx_post_enable_lane(hdptx);
857
+
}
858
+
859
+
static int rk_hdptx_phy_power_on(struct phy *phy)
860
+
{
861
+
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
862
+
int ret, bus_width = phy_get_bus_width(hdptx->phy);
863
+
/*
864
+
* FIXME: Temporary workaround to pass pixel_clk_rate
865
+
* from the HDMI bridge driver until phy_configure_opts_hdmi
866
+
* becomes available in the PHY API.
867
+
*/
868
+
unsigned int rate = bus_width & 0xfffffff;
869
+
870
+
dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
871
+
__func__, bus_width, rate);
872
+
873
+
ret = pm_runtime_resume_and_get(hdptx->dev);
874
+
if (ret) {
875
+
dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret);
876
+
return ret;
877
+
}
878
+
879
+
ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
880
+
if (ret)
881
+
pm_runtime_put(hdptx->dev);
882
+
883
+
return ret;
884
+
}
885
+
886
+
static int rk_hdptx_phy_power_off(struct phy *phy)
887
+
{
888
+
struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
889
+
u32 val;
890
+
int ret;
891
+
892
+
ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
893
+
if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
894
+
rk_hdptx_phy_disable(hdptx);
895
+
896
+
pm_runtime_put(hdptx->dev);
897
+
898
+
return ret;
899
+
}
900
+
901
+
static const struct phy_ops rk_hdptx_phy_ops = {
902
+
.power_on = rk_hdptx_phy_power_on,
903
+
.power_off = rk_hdptx_phy_power_off,
904
+
.owner = THIS_MODULE,
905
+
};
906
+
907
+
static int rk_hdptx_phy_runtime_suspend(struct device *dev)
908
+
{
909
+
struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
910
+
911
+
clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
912
+
913
+
return 0;
914
+
}
915
+
916
+
static int rk_hdptx_phy_runtime_resume(struct device *dev)
917
+
{
918
+
struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
919
+
int ret;
920
+
921
+
ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
922
+
if (ret)
923
+
dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
924
+
925
+
return ret;
926
+
}
927
+
928
+
static int rk_hdptx_phy_probe(struct platform_device *pdev)
929
+
{
930
+
struct phy_provider *phy_provider;
931
+
struct device *dev = &pdev->dev;
932
+
struct rk_hdptx_phy *hdptx;
933
+
void __iomem *regs;
934
+
int ret;
935
+
936
+
hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
937
+
if (!hdptx)
938
+
return -ENOMEM;
939
+
940
+
hdptx->dev = dev;
941
+
942
+
regs = devm_platform_ioremap_resource(pdev, 0);
943
+
if (IS_ERR(regs))
944
+
return dev_err_probe(dev, PTR_ERR(regs),
945
+
"Failed to ioremap resource\n");
946
+
947
+
ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
948
+
if (ret < 0)
949
+
return dev_err_probe(dev, ret, "Failed to get clocks\n");
950
+
if (ret == 0)
951
+
return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
952
+
953
+
hdptx->nr_clks = ret;
954
+
955
+
hdptx->regmap = devm_regmap_init_mmio(dev, regs,
956
+
&rk_hdptx_phy_regmap_config);
957
+
if (IS_ERR(hdptx->regmap))
958
+
return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
959
+
"Failed to init regmap\n");
960
+
961
+
hdptx->rsts[RST_PHY].id = "phy";
962
+
hdptx->rsts[RST_APB].id = "apb";
963
+
hdptx->rsts[RST_INIT].id = "init";
964
+
hdptx->rsts[RST_CMN].id = "cmn";
965
+
hdptx->rsts[RST_LANE].id = "lane";
966
+
hdptx->rsts[RST_ROPLL].id = "ropll";
967
+
hdptx->rsts[RST_LCPLL].id = "lcpll";
968
+
969
+
ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
970
+
if (ret)
971
+
return dev_err_probe(dev, ret, "Failed to get resets\n");
972
+
973
+
hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
974
+
"rockchip,grf");
975
+
if (IS_ERR(hdptx->grf))
976
+
return dev_err_probe(dev, PTR_ERR(hdptx->grf),
977
+
"Could not get GRF syscon\n");
978
+
979
+
hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
980
+
if (IS_ERR(hdptx->phy))
981
+
return dev_err_probe(dev, PTR_ERR(hdptx->phy),
982
+
"Failed to create HDMI PHY\n");
983
+
984
+
platform_set_drvdata(pdev, hdptx);
985
+
phy_set_drvdata(hdptx->phy, hdptx);
986
+
phy_set_bus_width(hdptx->phy, 8);
987
+
988
+
ret = devm_pm_runtime_enable(dev);
989
+
if (ret)
990
+
return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
991
+
992
+
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
993
+
if (IS_ERR(phy_provider))
994
+
return dev_err_probe(dev, PTR_ERR(phy_provider),
995
+
"Failed to register PHY provider\n");
996
+
997
+
reset_control_deassert(hdptx->rsts[RST_APB].rstc);
998
+
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
999
+
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1000
+
1001
+
return 0;
1002
+
}
1003
+
1004
+
static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
1005
+
RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
1006
+
rk_hdptx_phy_runtime_resume, NULL)
1007
+
};
1008
+
1009
+
static const struct of_device_id rk_hdptx_phy_of_match[] = {
1010
+
{ .compatible = "rockchip,rk3588-hdptx-phy", },
1011
+
{}
1012
+
};
1013
+
MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
1014
+
1015
+
static struct platform_driver rk_hdptx_phy_driver = {
1016
+
.probe = rk_hdptx_phy_probe,
1017
+
.driver = {
1018
+
.name = "rockchip-hdptx-phy",
1019
+
.pm = &rk_hdptx_phy_pm_ops,
1020
+
.of_match_table = rk_hdptx_phy_of_match,
1021
+
},
1022
+
};
1023
+
module_platform_driver(rk_hdptx_phy_driver);
1024
+
1025
+
MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
1026
+
MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1027
+
MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
1028
+
MODULE_LICENSE("GPL");
+1
-1
drivers/phy/samsung/phy-exynos-mipi-video.c
+1
-1
drivers/phy/samsung/phy-exynos-mipi-video.c
+1
-1
drivers/phy/samsung/phy-exynos5-usbdrd.c
+1
-1
drivers/phy/samsung/phy-exynos5-usbdrd.c
+1
-1
drivers/phy/samsung/phy-samsung-usb2.c
+1
-1
drivers/phy/samsung/phy-samsung-usb2.c
+1
-1
drivers/phy/socionext/phy-uniphier-usb2.c
+1
-1
drivers/phy/socionext/phy-uniphier-usb2.c
+1
-1
drivers/phy/st/phy-miphy28lp.c
+1
-1
drivers/phy/st/phy-miphy28lp.c
+1
-1
drivers/phy/st/phy-spear1310-miphy.c
+1
-1
drivers/phy/st/phy-spear1310-miphy.c
+1
-1
drivers/phy/st/phy-spear1340-miphy.c
+1
-1
drivers/phy/st/phy-spear1340-miphy.c
+1
-1
drivers/phy/st/phy-stm32-usbphyc.c
+1
-1
drivers/phy/st/phy-stm32-usbphyc.c
+1
-1
drivers/phy/tegra/xusb.c
+1
-1
drivers/phy/tegra/xusb.c
+1
-1
drivers/phy/ti/phy-am654-serdes.c
+1
-1
drivers/phy/ti/phy-am654-serdes.c
+1
-1
drivers/phy/ti/phy-da8xx-usb.c
+1
-1
drivers/phy/ti/phy-da8xx-usb.c
+25
-1
drivers/phy/ti/phy-gmii-sel.c
+25
-1
drivers/phy/ti/phy-gmii-sel.c
···
297
297
};
298
298
299
299
static struct phy *phy_gmii_sel_of_xlate(struct device *dev,
300
-
struct of_phandle_args *args)
300
+
const struct of_phandle_args *args)
301
301
{
302
302
struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
303
303
int phy_id = args->args[0];
···
494
494
return 0;
495
495
}
496
496
497
+
static int phy_gmii_sel_resume_noirq(struct device *dev)
498
+
{
499
+
struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
500
+
struct phy_gmii_sel_phy_priv *if_phys = priv->if_phys;
501
+
int ret, i;
502
+
503
+
for (i = 0; i < priv->num_ports; i++) {
504
+
if (if_phys[i].phy_if_mode) {
505
+
ret = phy_gmii_sel_mode(if_phys[i].if_phy,
506
+
PHY_MODE_ETHERNET, if_phys[i].phy_if_mode);
507
+
if (ret) {
508
+
dev_err(dev, "port%u: restore mode fail %d\n",
509
+
if_phys[i].if_phy->id, ret);
510
+
return ret;
511
+
}
512
+
}
513
+
}
514
+
515
+
return 0;
516
+
}
517
+
518
+
static DEFINE_NOIRQ_DEV_PM_OPS(phy_gmii_sel_pm_ops, NULL, phy_gmii_sel_resume_noirq);
519
+
497
520
static struct platform_driver phy_gmii_sel_driver = {
498
521
.probe = phy_gmii_sel_probe,
499
522
.driver = {
500
523
.name = "phy-gmii-sel",
501
524
.of_match_table = phy_gmii_sel_id_table,
525
+
.pm = pm_sleep_ptr(&phy_gmii_sel_pm_ops),
502
526
},
503
527
};
504
528
module_platform_driver(phy_gmii_sel_driver);
+30
-27
drivers/phy/ti/phy-tusb1210.c
+30
-27
drivers/phy/ti/phy-tusb1210.c
···
17
17
#include <linux/property.h>
18
18
#include <linux/workqueue.h>
19
19
20
+
#define TI_VENDOR_ID 0x0451
21
+
#define TI_DEVICE_TUSB1210 0x1507
22
+
#define TI_DEVICE_TUSB1211 0x1508
23
+
20
24
#define TUSB1211_POWER_CONTROL 0x3d
21
25
#define TUSB1211_POWER_CONTROL_SET 0x3e
22
26
#define TUSB1211_POWER_CONTROL_CLEAR 0x3f
···
56
52
};
57
53
58
54
struct tusb1210 {
59
-
struct ulpi *ulpi;
55
+
struct device *dev;
60
56
struct phy *phy;
61
57
struct gpio_desc *gpio_reset;
62
58
struct gpio_desc *gpio_cs;
···
75
71
76
72
static int tusb1210_ulpi_write(struct tusb1210 *tusb, u8 reg, u8 val)
77
73
{
74
+
struct device *dev = tusb->dev;
78
75
int ret;
79
76
80
-
ret = ulpi_write(tusb->ulpi, reg, val);
77
+
ret = ulpi_write(to_ulpi_dev(dev), reg, val);
81
78
if (ret)
82
-
dev_err(&tusb->ulpi->dev, "error %d writing val 0x%02x to reg 0x%02x\n",
83
-
ret, val, reg);
79
+
dev_err(dev, "error %d writing val 0x%02x to reg 0x%02x\n", ret, val, reg);
84
80
85
81
return ret;
86
82
}
87
83
88
84
static int tusb1210_ulpi_read(struct tusb1210 *tusb, u8 reg, u8 *val)
89
85
{
86
+
struct device *dev = tusb->dev;
90
87
int ret;
91
88
92
-
ret = ulpi_read(tusb->ulpi, reg);
89
+
ret = ulpi_read(to_ulpi_dev(dev), reg);
93
90
if (ret >= 0) {
94
91
*val = ret;
95
92
ret = 0;
96
93
} else {
97
-
dev_err(&tusb->ulpi->dev, "error %d reading reg 0x%02x\n", ret, reg);
94
+
dev_err(dev, "error %d reading reg 0x%02x\n", ret, reg);
98
95
}
99
96
100
97
return ret;
···
183
178
static void tusb1210_chg_det_set_type(struct tusb1210 *tusb,
184
179
enum power_supply_usb_type type)
185
180
{
186
-
dev_dbg(&tusb->ulpi->dev, "charger type: %d\n", type);
181
+
dev_dbg(tusb->dev, "charger type: %d\n", type);
187
182
tusb->chg_type = type;
188
183
tusb->chg_det_retries = 0;
189
184
power_supply_changed(tusb->psy);
···
194
189
int delay_ms)
195
190
{
196
191
if (delay_ms)
197
-
dev_dbg(&tusb->ulpi->dev, "chg_det new state %s in %d ms\n",
192
+
dev_dbg(tusb->dev, "chg_det new state %s in %d ms\n",
198
193
tusb1210_chg_det_states[new_state], delay_ms);
199
194
200
195
tusb->chg_det_state = new_state;
···
258
253
int ret;
259
254
u8 val;
260
255
261
-
dev_dbg(&tusb->ulpi->dev, "chg_det state %s vbus_present %d\n",
256
+
dev_dbg(tusb->dev, "chg_det state %s vbus_present %d\n",
262
257
tusb1210_chg_det_states[tusb->chg_det_state], vbus_present);
263
258
264
259
switch (tusb->chg_det_state) {
···
266
261
tusb->chg_type = POWER_SUPPLY_USB_TYPE_UNKNOWN;
267
262
tusb->chg_det_retries = 0;
268
263
/* Power on USB controller for ulpi_read()/_write() */
269
-
ret = pm_runtime_resume_and_get(tusb->ulpi->dev.parent);
264
+
ret = pm_runtime_resume_and_get(tusb->dev->parent);
270
265
if (ret < 0) {
271
-
dev_err(&tusb->ulpi->dev, "error %d runtime-resuming\n", ret);
266
+
dev_err(tusb->dev, "error %d runtime-resuming\n", ret);
272
267
/* Should never happen, skip charger detection */
273
268
tusb1210_chg_det_set_state(tusb, TUSB1210_CHG_DET_CONNECTED, 0);
274
269
return;
···
337
332
338
333
mutex_unlock(&tusb->phy->mutex);
339
334
340
-
pm_runtime_put(tusb->ulpi->dev.parent);
335
+
pm_runtime_put(tusb->dev->parent);
341
336
tusb1210_chg_det_set_state(tusb, TUSB1210_CHG_DET_CONNECTED, 0);
342
337
break;
343
338
case TUSB1210_CHG_DET_CONNECTED:
···
433
428
static void tusb1210_probe_charger_detect(struct tusb1210 *tusb)
434
429
{
435
430
struct power_supply_config psy_cfg = { .drv_data = tusb };
436
-
struct device *dev = &tusb->ulpi->dev;
431
+
struct device *dev = tusb->dev;
432
+
struct ulpi *ulpi = to_ulpi_dev(dev);
437
433
int ret;
438
434
439
435
if (!device_property_read_bool(dev->parent, "linux,phy_charger_detect"))
440
436
return;
441
437
442
-
if (tusb->ulpi->id.product != 0x1508) {
438
+
if (ulpi->id.product != TI_DEVICE_TUSB1211) {
443
439
dev_err(dev, "error charger detection is only supported on the TUSB1211\n");
444
440
return;
445
441
}
···
491
485
492
486
static int tusb1210_probe(struct ulpi *ulpi)
493
487
{
488
+
struct device *dev = &ulpi->dev;
494
489
struct tusb1210 *tusb;
495
490
u8 val, reg;
496
491
int ret;
497
492
498
-
tusb = devm_kzalloc(&ulpi->dev, sizeof(*tusb), GFP_KERNEL);
493
+
tusb = devm_kzalloc(dev, sizeof(*tusb), GFP_KERNEL);
499
494
if (!tusb)
500
495
return -ENOMEM;
501
496
502
-
tusb->ulpi = ulpi;
497
+
tusb->dev = dev;
503
498
504
-
tusb->gpio_reset = devm_gpiod_get_optional(&ulpi->dev, "reset",
505
-
GPIOD_OUT_LOW);
499
+
tusb->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
506
500
if (IS_ERR(tusb->gpio_reset))
507
501
return PTR_ERR(tusb->gpio_reset);
508
502
509
503
gpiod_set_value_cansleep(tusb->gpio_reset, 1);
510
504
511
-
tusb->gpio_cs = devm_gpiod_get_optional(&ulpi->dev, "cs",
512
-
GPIOD_OUT_LOW);
505
+
tusb->gpio_cs = devm_gpiod_get_optional(dev, "cs", GPIOD_OUT_LOW);
513
506
if (IS_ERR(tusb->gpio_cs))
514
507
return PTR_ERR(tusb->gpio_cs);
515
508
···
524
519
return ret;
525
520
526
521
/* High speed output drive strength configuration */
527
-
if (!device_property_read_u8(&ulpi->dev, "ihstx", &val))
522
+
if (!device_property_read_u8(dev, "ihstx", &val))
528
523
u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_IHSTX_MASK);
529
524
530
525
/* High speed output impedance configuration */
531
-
if (!device_property_read_u8(&ulpi->dev, "zhsdrv", &val))
526
+
if (!device_property_read_u8(dev, "zhsdrv", &val))
532
527
u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_MASK);
533
528
534
529
/* DP/DM swap control */
535
-
if (!device_property_read_u8(&ulpi->dev, "datapolarity", &val))
530
+
if (!device_property_read_u8(dev, "datapolarity", &val))
536
531
u8p_replace_bits(®, val, (u8)TUSB1210_VENDOR_SPECIFIC2_DP_MASK);
537
532
538
533
ret = tusb1210_ulpi_write(tusb, TUSB1210_VENDOR_SPECIFIC2, reg);
···
566
561
tusb1210_remove_charger_detect(tusb);
567
562
}
568
563
569
-
#define TI_VENDOR_ID 0x0451
570
-
571
564
static const struct ulpi_device_id tusb1210_ulpi_id[] = {
572
-
{ TI_VENDOR_ID, 0x1507, }, /* TUSB1210 */
573
-
{ TI_VENDOR_ID, 0x1508, }, /* TUSB1211 */
565
+
{ TI_VENDOR_ID, TI_DEVICE_TUSB1210 },
566
+
{ TI_VENDOR_ID, TI_DEVICE_TUSB1211 },
574
567
{ },
575
568
};
576
569
MODULE_DEVICE_TABLE(ulpi, tusb1210_ulpi_id);
+1
-1
drivers/phy/xilinx/phy-zynqmp.c
+1
-1
drivers/phy/xilinx/phy-zynqmp.c
···
768
768
769
769
/* Translate OF phandle and args to PHY instance. */
770
770
static struct phy *xpsgtr_xlate(struct device *dev,
771
-
struct of_phandle_args *args)
771
+
const struct of_phandle_args *args)
772
772
{
773
773
struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
774
774
struct xpsgtr_phy *gtr_phy;
+1
-1
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+1
-1
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+7
-7
include/linux/phy/phy.h
+7
-7
include/linux/phy/phy.h
···
176
176
struct module *owner;
177
177
struct list_head list;
178
178
struct phy * (*of_xlate)(struct device *dev,
179
-
struct of_phandle_args *args);
179
+
const struct of_phandle_args *args);
180
180
};
181
181
182
182
/**
···
265
265
void devm_phy_put(struct device *dev, struct phy *phy);
266
266
struct phy *of_phy_get(struct device_node *np, const char *con_id);
267
267
struct phy *of_phy_simple_xlate(struct device *dev,
268
-
struct of_phandle_args *args);
268
+
const struct of_phandle_args *args);
269
269
struct phy *phy_create(struct device *dev, struct device_node *node,
270
270
const struct phy_ops *ops);
271
271
struct phy *devm_phy_create(struct device *dev, struct device_node *node,
···
275
275
struct phy_provider *__of_phy_provider_register(struct device *dev,
276
276
struct device_node *children, struct module *owner,
277
277
struct phy * (*of_xlate)(struct device *dev,
278
-
struct of_phandle_args *args));
278
+
const struct of_phandle_args *args));
279
279
struct phy_provider *__devm_of_phy_provider_register(struct device *dev,
280
280
struct device_node *children, struct module *owner,
281
281
struct phy * (*of_xlate)(struct device *dev,
282
-
struct of_phandle_args *args));
282
+
const struct of_phandle_args *args));
283
283
void of_phy_provider_unregister(struct phy_provider *phy_provider);
284
284
void devm_of_phy_provider_unregister(struct device *dev,
285
285
struct phy_provider *phy_provider);
···
479
479
}
480
480
481
481
static inline struct phy *of_phy_simple_xlate(struct device *dev,
482
-
struct of_phandle_args *args)
482
+
const struct of_phandle_args *args)
483
483
{
484
484
return ERR_PTR(-ENOSYS);
485
485
}
···
509
509
static inline struct phy_provider *__of_phy_provider_register(
510
510
struct device *dev, struct device_node *children, struct module *owner,
511
511
struct phy * (*of_xlate)(struct device *dev,
512
-
struct of_phandle_args *args))
512
+
const struct of_phandle_args *args))
513
513
{
514
514
return ERR_PTR(-ENOSYS);
515
515
}
···
517
517
static inline struct phy_provider *__devm_of_phy_provider_register(struct device
518
518
*dev, struct device_node *children, struct module *owner,
519
519
struct phy * (*of_xlate)(struct device *dev,
520
-
struct of_phandle_args *args))
520
+
const struct of_phandle_args *args))
521
521
{
522
522
return ERR_PTR(-ENOSYS);
523
523
}