Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'ixp4xx-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM ixp4xx bug fixes from Arnd Bergmann:
"These were originally prepared by Krzysztof Halasa but not submitted
in time for v3.7 due to some confusion about how ixp4xx patches should
be handled. Jason Cooper thankfully offered to help out sending the
patches upstream through arm-soc now, but given the timing, we could
as well delay them for 3.8."
* tag 'ixp4xx-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
IXP4xx: use __iomem for MMIO
IXP4xx: map CPU config registers within VMALLOC region.
IXP4xx: Always ioremap() Queue Manager MMIO region at boot.
ixp4xx: Declare MODULE_FIRMWARE usage
IXP4xx crypto: MOD_AES{128,192,256} already include key size.
WAN: Remove redundant HDLC info printed by IXP4xx HSS driver.
IXP4xx: Remove time limit for PCI TRDY to enable use of slow devices.
IXP4xx: ixp4xx_crypto driver requires Queue Manager and NPE drivers.
IXP4xx: HW pseudo-random generator is available on IXP45x/46x only.
IXP4xx: Fix off-by-one bug in Goramo MultiLink platform.
IXP4xx: Fix Goramo MultiLink platform compilation.
+59
-68
+1
arch/arm/mach-ixp4xx/common-pci.c
+1
arch/arm/mach-ixp4xx/common-pci.c
···
410
410
* Enable the IO window to be way up high, at 0xfffffc00
411
411
*/
412
412
local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01);
413
+
local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */
413
414
} else {
414
415
printk("PCI: IXP4xx is target - No bus scan performed\n");
415
416
}
+5
-8
arch/arm/mach-ixp4xx/common.c
+5
-8
arch/arm/mach-ixp4xx/common.c
···
67
67
.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
68
68
.length = IXP4XX_PCI_CFG_REGION_SIZE,
69
69
.type = MT_DEVICE
70
-
},
71
-
#ifdef CONFIG_DEBUG_LL
72
-
{ /* Debug UART mapping */
73
-
.virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
74
-
.pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
75
-
.length = IXP4XX_DEBUG_UART_REGION_SIZE,
70
+
}, { /* Queue Manager */
71
+
.virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
72
+
.pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
73
+
.length = IXP4XX_QMGR_REGION_SIZE,
76
74
.type = MT_DEVICE
77
-
}
78
-
#endif
75
+
},
79
76
};
80
77
81
78
void __init ixp4xx_map_io(void)
+2
-1
arch/arm/mach-ixp4xx/goramo_mlr.c
+2
-1
arch/arm/mach-ixp4xx/goramo_mlr.c
···
15
15
#include <asm/mach/arch.h>
16
16
#include <asm/mach/flash.h>
17
17
#include <asm/mach/pci.h>
18
+
#include <asm/system_info.h>
18
19
19
20
#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
20
21
#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
···
330
329
};
331
330
332
331
333
-
static struct platform_device *device_tab[6] __initdata = {
332
+
static struct platform_device *device_tab[7] __initdata = {
334
333
&device_flash, /* index 0 */
335
334
};
336
335
+2
-2
arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+2
-2
arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+19
-27
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+19
-27
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
···
30
30
*
31
31
* 0x50000000 0x10000000 ioremap'd EXP BUS
32
32
*
33
-
* 0x6000000 0x00004000 ioremap'd QMgr
33
+
* 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
34
34
*
35
-
* 0xC0000000 0x00001000 0xffbff000 PCI CFG
35
+
* 0xC0000000 0x00001000 0xFEF13000 PCI CFG
36
36
*
37
-
* 0xC4000000 0x00001000 0xffbfe000 EXP CFG
37
+
* 0xC4000000 0x00001000 0xFEF14000 EXP CFG
38
38
*
39
-
* 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
39
+
* 0x60000000 0x00004000 0xFEF15000 QMgr
40
40
*/
41
41
42
42
/*
43
43
* Queue Manager
44
44
*/
45
-
#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
46
-
#define IXP4XX_QMGR_REGION_SIZE (0x00004000)
45
+
#define IXP4XX_QMGR_BASE_PHYS 0x60000000
46
+
#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)
47
+
#define IXP4XX_QMGR_REGION_SIZE 0x00004000
47
48
48
49
/*
49
-
* Expansion BUS Configuration registers
50
+
* Peripheral space, including debug UART. Must be section-aligned so that
51
+
* it can be used with the low-level debug code.
50
52
*/
51
-
#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
52
-
#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000)
53
-
#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
53
+
#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
54
+
#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
55
+
#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
54
56
55
57
/*
56
58
* PCI Config registers
57
59
*/
58
-
#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
59
-
#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000)
60
-
#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
60
+
#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
61
+
#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
62
+
#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
61
63
62
64
/*
63
-
* Peripheral space
65
+
* Expansion BUS Configuration registers
64
66
*/
65
-
#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
66
-
#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000)
67
-
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
68
-
69
-
/*
70
-
* Debug UART
71
-
*
72
-
* This is basically a remap of UART1 into a region that is section
73
-
* aligned so that it * can be used with the low-level debug code.
74
-
*/
75
-
#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
76
-
#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000)
77
-
#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
67
+
#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
68
+
#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
69
+
#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
78
70
79
71
#define IXP4XX_EXP_CS0_OFFSET 0x00
80
72
#define IXP4XX_EXP_CS1_OFFSET 0x04
+6
-6
arch/arm/mach-ixp4xx/include/mach/qmgr.h
+6
-6
arch/arm/mach-ixp4xx/include/mach/qmgr.h
···
86
86
87
87
static inline void qmgr_put_entry(unsigned int queue, u32 val)
88
88
{
89
-
extern struct qmgr_regs __iomem *qmgr_regs;
89
+
struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
90
90
#if DEBUG_QMGR
91
91
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
92
92
···
99
99
static inline u32 qmgr_get_entry(unsigned int queue)
100
100
{
101
101
u32 val;
102
-
extern struct qmgr_regs __iomem *qmgr_regs;
102
+
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
103
103
val = __raw_readl(&qmgr_regs->acc[queue][0]);
104
104
#if DEBUG_QMGR
105
105
BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
···
112
112
113
113
static inline int __qmgr_get_stat1(unsigned int queue)
114
114
{
115
-
extern struct qmgr_regs __iomem *qmgr_regs;
115
+
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
116
116
return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
117
117
>> ((queue & 7) << 2)) & 0xF;
118
118
}
119
119
120
120
static inline int __qmgr_get_stat2(unsigned int queue)
121
121
{
122
-
extern struct qmgr_regs __iomem *qmgr_regs;
122
+
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
123
123
BUG_ON(queue >= HALF_QUEUES);
124
124
return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
125
125
>> ((queue & 0xF) << 1)) & 0x3;
···
145
145
*/
146
146
static inline int qmgr_stat_below_low_watermark(unsigned int queue)
147
147
{
148
-
extern struct qmgr_regs __iomem *qmgr_regs;
148
+
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
149
149
if (queue >= HALF_QUEUES)
150
150
return (__raw_readl(&qmgr_regs->statne_h) >>
151
151
(queue - HALF_QUEUES)) & 0x01;
···
172
172
*/
173
173
static inline int qmgr_stat_full(unsigned int queue)
174
174
{
175
-
extern struct qmgr_regs __iomem *qmgr_regs;
175
+
const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
176
176
if (queue >= HALF_QUEUES)
177
177
return (__raw_readl(&qmgr_regs->statf_h) >>
178
178
(queue - HALF_QUEUES)) & 0x01;
+8
-1
arch/arm/mach-ixp4xx/ixp4xx_npe.c
+8
-1
arch/arm/mach-ixp4xx/ixp4xx_npe.c
···
116
116
/* NPE mailbox_status value for reset */
117
117
#define RESET_MBOX_STAT 0x0000F0F0
118
118
119
-
const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
119
+
#define NPE_A_FIRMWARE "NPE-A"
120
+
#define NPE_B_FIRMWARE "NPE-B"
121
+
#define NPE_C_FIRMWARE "NPE-C"
122
+
123
+
const char *npe_names[] = { NPE_A_FIRMWARE, NPE_B_FIRMWARE, NPE_C_FIRMWARE };
120
124
121
125
#define print_npe(pri, npe, fmt, ...) \
122
126
printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
···
728
724
729
725
MODULE_AUTHOR("Krzysztof Halasa");
730
726
MODULE_LICENSE("GPL v2");
727
+
MODULE_FIRMWARE(NPE_A_FIRMWARE);
728
+
MODULE_FIRMWARE(NPE_B_FIRMWARE);
729
+
MODULE_FIRMWARE(NPE_C_FIRMWARE);
731
730
732
731
EXPORT_SYMBOL(npe_names);
733
732
EXPORT_SYMBOL(npe_running);
+1
-11
arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+1
-11
arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
···
14
14
#include <linux/module.h>
15
15
#include <mach/qmgr.h>
16
16
17
-
struct qmgr_regs __iomem *qmgr_regs;
17
+
static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
18
18
static struct resource *mem_res;
19
19
static spinlock_t qmgr_lock;
20
20
static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
···
293
293
if (mem_res == NULL)
294
294
return -EBUSY;
295
295
296
-
qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
297
-
if (qmgr_regs == NULL) {
298
-
err = -ENOMEM;
299
-
goto error_map;
300
-
}
301
-
302
296
/* reset qmgr registers */
303
297
for (i = 0; i < 4; i++) {
304
298
__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
···
341
347
error_irq2:
342
348
free_irq(IRQ_IXP4XX_QM1, NULL);
343
349
error_irq:
344
-
iounmap(qmgr_regs);
345
-
error_map:
346
350
release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
347
351
return err;
348
352
}
···
351
359
free_irq(IRQ_IXP4XX_QM2, NULL);
352
360
synchronize_irq(IRQ_IXP4XX_QM1);
353
361
synchronize_irq(IRQ_IXP4XX_QM2);
354
-
iounmap(qmgr_regs);
355
362
release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
356
363
}
357
364
···
360
369
MODULE_LICENSE("GPL v2");
361
370
MODULE_AUTHOR("Krzysztof Halasa");
362
371
363
-
EXPORT_SYMBOL(qmgr_regs);
364
372
EXPORT_SYMBOL(qmgr_set_irq);
365
373
EXPORT_SYMBOL(qmgr_enable_irq);
366
374
EXPORT_SYMBOL(qmgr_disable_irq);
+3
-3
drivers/char/hw_random/Kconfig
+3
-3
drivers/char/hw_random/Kconfig
···
127
127
If unsure, say Y.
128
128
129
129
config HW_RANDOM_IXP4XX
130
-
tristate "Intel IXP4xx NPU HW Random Number Generator support"
130
+
tristate "Intel IXP4xx NPU HW Pseudo-Random Number Generator support"
131
131
depends on HW_RANDOM && ARCH_IXP4XX
132
132
default HW_RANDOM
133
133
---help---
134
-
This driver provides kernel-side support for the Random
135
-
Number Generator hardware found on the Intel IXP4xx NPU.
134
+
This driver provides kernel-side support for the Pseudo-Random
135
+
Number Generator hardware found on the Intel IXP45x/46x NPU.
136
136
137
137
To compile this driver as a module, choose M here: the
138
138
module will be called ixp4xx-rng.
+4
-1
drivers/char/hw_random/ixp4xx-rng.c
+4
-1
drivers/char/hw_random/ixp4xx-rng.c
···
45
45
void __iomem * rng_base;
46
46
int err;
47
47
48
+
if (!cpu_is_ixp46x()) /* includes IXP455 */
49
+
return -ENOSYS;
50
+
48
51
rng_base = ioremap(0x70002100, 4);
49
52
if (!rng_base)
50
53
return -ENOMEM;
···
71
68
module_exit(ixp4xx_rng_exit);
72
69
73
70
MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
74
-
MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver for IXP4xx");
71
+
MODULE_DESCRIPTION("H/W Pseudo-Random Number Generator (RNG) driver for IXP45x/46x");
75
72
MODULE_LICENSE("GPL");
+1
-1
drivers/crypto/Kconfig
+1
-1
drivers/crypto/Kconfig
+6
-6
drivers/crypto/ixp4xx_crypto.c
+6
-6
drivers/crypto/ixp4xx_crypto.c
···
750
750
}
751
751
if (cipher_cfg & MOD_AES) {
752
752
switch (key_len) {
753
-
case 16: keylen_cfg = MOD_AES128 | KEYLEN_128; break;
754
-
case 24: keylen_cfg = MOD_AES192 | KEYLEN_192; break;
755
-
case 32: keylen_cfg = MOD_AES256 | KEYLEN_256; break;
756
-
default:
757
-
*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
758
-
return -EINVAL;
753
+
case 16: keylen_cfg = MOD_AES128; break;
754
+
case 24: keylen_cfg = MOD_AES192; break;
755
+
case 32: keylen_cfg = MOD_AES256; break;
756
+
default:
757
+
*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
758
+
return -EINVAL;
759
759
}
760
760
cipher_cfg |= keylen_cfg;
761
761
} else if (cipher_cfg & MOD_3DES) {