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phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC

UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 90c64cc0 0d46b98d

+36
+36
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 576 576 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 577 577 }; 578 578 579 + static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 580 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 581 + }; 582 + 583 + static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 584 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 585 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 586 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 587 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 588 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 589 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 590 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 591 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 592 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 593 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 594 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 595 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 596 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 597 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 598 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 599 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 600 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 601 + }; 602 + 603 + static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 604 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 605 + }; 606 + 579 607 struct qmp_ufs_offsets { 580 608 u16 serdes; 581 609 u16 pcs; ··· 909 881 .tbls_hs_b = { 910 882 .serdes = sm8350_ufsphy_hs_b_serdes, 911 883 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 884 + }, 885 + .tbls_hs_g4 = { 886 + .tx = sm8350_ufsphy_g4_tx, 887 + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 888 + .rx = sm8350_ufsphy_g4_rx, 889 + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 890 + .pcs = sm8350_ufsphy_g4_pcs, 891 + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 912 892 }, 913 893 .clk_list = sdm845_ufs_phy_clk_l, 914 894 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),