+1 -1

Documentation/connector/cn_test.c

reviewed

··· 34 34 static struct sock *nls; 35 35 static struct timer_list cn_test_timer; 36 36 37 37 - static void cn_test_callback(struct cn_msg *msg) 37 37 + static void cn_test_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 38 38 { 39 39 pr_info("%s: %lu: idx=%x, val=%x, seq=%u, ack=%u, len=%d: %s.\n", 40 40 __func__, jiffies, msg->id.idx, msg->id.val,

+4 -4

Documentation/connector/connector.txt

reviewed

··· 23 23 netlink based networking for inter-process communication in a significantly 24 24 easier way: 25 25 26 26 - int cn_add_callback(struct cb_id *id, char *name, void (*callback) (void *)); 26 26 + int cn_add_callback(struct cb_id *id, char *name, void (*callback) (struct cn_msg *, struct netlink_skb_parms *)); 27 27 void cn_netlink_send(struct cn_msg *msg, u32 __group, int gfp_mask); 28 28 29 29 struct cb_id ··· 53 53 Connector interfaces. 54 54 /*****************************************/ 55 55 56 56 - int cn_add_callback(struct cb_id *id, char *name, void (*callback) (void *)); 56 56 + int cn_add_callback(struct cb_id *id, char *name, void (*callback) (struct cn_msg *, struct netlink_skb_parms *)); 57 57 58 58 Registers new callback with connector core. 59 59 60 60 struct cb_id *id - unique connector's user identifier. 61 61 It must be registered in connector.h for legal in-kernel users. 62 62 char *name - connector's callback symbolic name. 63 63 - void (*callback) (void *) - connector's callback. 64 64 - Argument must be dereferenced to struct cn_msg *. 63 63 + void (*callback) (struct cn..) - connector's callback. 64 64 + cn_msg and the sender's credentials 65 65 66 66 67 67 void cn_del_callback(struct cb_id *id);

+1 -1

Documentation/networking/timestamping/timestamping.c

reviewed

··· 381 381 memset(&hwtstamp, 0, sizeof(hwtstamp)); 382 382 strncpy(hwtstamp.ifr_name, interface, sizeof(hwtstamp.ifr_name)); 383 383 hwtstamp.ifr_data = (void *)&hwconfig; 384 384 - memset(&hwconfig, 0, sizeof(&hwconfig)); 384 384 + memset(&hwconfig, 0, sizeof(hwconfig)); 385 385 hwconfig.tx_type = 386 386 (so_timestamping_flags & SOF_TIMESTAMPING_TX_HARDWARE) ? 387 387 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;

+7 -5

drivers/connector/cn_queue.c

reviewed

··· 78 78 struct cn_callback_entry *cbq = 79 79 container_of(work, struct cn_callback_entry, work); 80 80 struct cn_callback_data *d = &cbq->data; 81 81 + struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(d->skb)); 82 82 + struct netlink_skb_parms *nsp = &NETLINK_CB(d->skb); 81 83 82 82 - d->callback(d->callback_priv); 84 84 + d->callback(msg, nsp); 83 85 84 84 - d->destruct_data(d->ddata); 85 85 - d->ddata = NULL; 86 86 + kfree_skb(d->skb); 87 87 + d->skb = NULL; 86 88 87 89 kfree(d->free); 88 90 } 89 91 90 92 static struct cn_callback_entry * 91 93 cn_queue_alloc_callback_entry(char *name, struct cb_id *id, 92 92 - void (*callback)(struct cn_msg *)) 94 94 + void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) 93 95 { 94 96 struct cn_callback_entry *cbq; 95 97 ··· 125 123 } 126 124 127 125 int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, 128 128 - void (*callback)(struct cn_msg *)) 126 126 + void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) 129 127 { 130 128 struct cn_callback_entry *cbq, *__cbq; 131 129 int found = 0;

+8 -14

drivers/connector/connector.c

reviewed

··· 129 129 /* 130 130 * Callback helper - queues work and setup destructor for given data. 131 131 */ 132 132 - static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), void *data) 132 132 + static int cn_call_callback(struct sk_buff *skb) 133 133 { 134 134 struct cn_callback_entry *__cbq, *__new_cbq; 135 135 struct cn_dev *dev = &cdev; 136 136 + struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(skb)); 136 137 int err = -ENODEV; 137 138 138 139 spin_lock_bh(&dev->cbdev->queue_lock); 139 140 list_for_each_entry(__cbq, &dev->cbdev->queue_list, callback_entry) { 140 141 if (cn_cb_equal(&__cbq->id.id, &msg->id)) { 141 142 if (likely(!work_pending(&__cbq->work) && 142 142 - __cbq->data.ddata == NULL)) { 143 143 - __cbq->data.callback_priv = msg; 144 144 - 145 145 - __cbq->data.ddata = data; 146 146 - __cbq->data.destruct_data = destruct_data; 143 143 + __cbq->data.skb == NULL)) { 144 144 + __cbq->data.skb = skb; 147 145 148 146 if (queue_cn_work(__cbq, &__cbq->work)) 149 147 err = 0; ··· 154 156 __new_cbq = kzalloc(sizeof(struct cn_callback_entry), GFP_ATOMIC); 155 157 if (__new_cbq) { 156 158 d = &__new_cbq->data; 157 157 - d->callback_priv = msg; 159 159 + d->skb = skb; 158 160 d->callback = __cbq->data.callback; 159 159 - d->ddata = data; 160 160 - d->destruct_data = destruct_data; 161 161 d->free = __new_cbq; 162 162 163 163 __new_cbq->pdev = __cbq->pdev; ··· 187 191 */ 188 192 static void cn_rx_skb(struct sk_buff *__skb) 189 193 { 190 190 - struct cn_msg *msg; 191 194 struct nlmsghdr *nlh; 192 195 int err; 193 196 struct sk_buff *skb; ··· 203 208 return; 204 209 } 205 210 206 206 - msg = NLMSG_DATA(nlh); 207 207 - err = cn_call_callback(msg, (void (*)(void *))kfree_skb, skb); 211 211 + err = cn_call_callback(skb); 208 212 if (err < 0) 209 213 kfree_skb(skb); 210 214 } ··· 264 270 * May sleep. 265 271 */ 266 272 int cn_add_callback(struct cb_id *id, char *name, 267 267 - void (*callback)(struct cn_msg *)) 273 273 + void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) 268 274 { 269 275 int err; 270 276 struct cn_dev *dev = &cdev; ··· 346 352 * 347 353 * Used for notification of a request's processing. 348 354 */ 349 349 - static void cn_callback(struct cn_msg *msg) 355 355 + static void cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 350 356 { 351 357 struct cn_ctl_msg *ctl; 352 358 struct cn_ctl_entry *ent;

+4 -2

drivers/md/dm-log-userspace-transfer.c

reviewed

··· 129 129 * This is the connector callback that delivers data 130 130 * that was sent from userspace. 131 131 */ 132 132 - static void cn_ulog_callback(void *data) 132 132 + static void cn_ulog_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 133 133 { 134 134 - struct cn_msg *msg = (struct cn_msg *)data; 135 134 struct dm_ulog_request *tfr = (struct dm_ulog_request *)(msg + 1); 135 135 + 136 136 + if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) 137 137 + return; 136 138 137 139 spin_lock(&receiving_list_lock); 138 140 if (msg->len == 0)

+38 -39

drivers/net/3c59x.c

reviewed

··· 805 805 806 806 #ifdef CONFIG_PM 807 807 808 808 - static int vortex_suspend(struct pci_dev *pdev, pm_message_t state) 808 808 + static int vortex_suspend(struct device *dev) 809 809 { 810 810 - struct net_device *dev = pci_get_drvdata(pdev); 810 810 + struct pci_dev *pdev = to_pci_dev(dev); 811 811 + struct net_device *ndev = pci_get_drvdata(pdev); 811 812 812 812 - if (dev && netdev_priv(dev)) { 813 813 - if (netif_running(dev)) { 814 814 - netif_device_detach(dev); 815 815 - vortex_down(dev, 1); 816 816 - disable_irq(dev->irq); 817 817 - } 818 818 - pci_save_state(pdev); 819 819 - pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 820 820 - pci_disable_device(pdev); 821 821 - pci_set_power_state(pdev, pci_choose_state(pdev, state)); 822 822 - } 813 813 + if (!ndev || !netif_running(ndev)) 814 814 + return 0; 815 815 + 816 816 + netif_device_detach(ndev); 817 817 + vortex_down(ndev, 1); 818 818 + 823 819 return 0; 824 820 } 825 821 826 826 - static int vortex_resume(struct pci_dev *pdev) 822 822 + static int vortex_resume(struct device *dev) 827 823 { 828 828 - struct net_device *dev = pci_get_drvdata(pdev); 829 829 - struct vortex_private *vp = netdev_priv(dev); 824 824 + struct pci_dev *pdev = to_pci_dev(dev); 825 825 + struct net_device *ndev = pci_get_drvdata(pdev); 830 826 int err; 831 827 832 832 - if (dev && vp) { 833 833 - pci_set_power_state(pdev, PCI_D0); 834 834 - pci_restore_state(pdev); 835 835 - err = pci_enable_device(pdev); 836 836 - if (err) { 837 837 - pr_warning("%s: Could not enable device\n", 838 838 - dev->name); 839 839 - return err; 840 840 - } 841 841 - pci_set_master(pdev); 842 842 - if (netif_running(dev)) { 843 843 - err = vortex_up(dev); 844 844 - if (err) 845 845 - return err; 846 846 - enable_irq(dev->irq); 847 847 - netif_device_attach(dev); 848 848 - } 849 849 - } 828 828 + if (!ndev || !netif_running(ndev)) 829 829 + return 0; 830 830 + 831 831 + err = vortex_up(ndev); 832 832 + if (err) 833 833 + return err; 834 834 + 835 835 + netif_device_attach(ndev); 836 836 + 850 837 return 0; 851 838 } 852 839 853 853 - #endif /* CONFIG_PM */ 840 840 + static struct dev_pm_ops vortex_pm_ops = { 841 841 + .suspend = vortex_suspend, 842 842 + .resume = vortex_resume, 843 843 + .freeze = vortex_suspend, 844 844 + .thaw = vortex_resume, 845 845 + .poweroff = vortex_suspend, 846 846 + .restore = vortex_resume, 847 847 + }; 848 848 + 849 849 + #define VORTEX_PM_OPS (&vortex_pm_ops) 850 850 + 851 851 + #else /* !CONFIG_PM */ 852 852 + 853 853 + #define VORTEX_PM_OPS NULL 854 854 + 855 855 + #endif /* !CONFIG_PM */ 854 856 855 857 #ifdef CONFIG_EISA 856 858 static struct eisa_device_id vortex_eisa_ids[] = { ··· 3201 3199 .probe = vortex_init_one, 3202 3200 .remove = __devexit_p(vortex_remove_one), 3203 3201 .id_table = vortex_pci_tbl, 3204 3204 - #ifdef CONFIG_PM 3205 3205 - .suspend = vortex_suspend, 3206 3206 - .resume = vortex_resume, 3207 3207 - #endif 3202 3202 + .driver.pm = VORTEX_PM_OPS, 3208 3203 }; 3209 3204 3210 3205

+7

drivers/net/Kconfig

reviewed

··· 1738 1738 help 1739 1739 SPI driver for Micrel KS8851 SPI attached network chip. 1740 1740 1741 1741 + config KS8851_MLL 1742 1742 + tristate "Micrel KS8851 MLL" 1743 1743 + depends on HAS_IOMEM 1744 1744 + help 1745 1745 + This platform driver is for Micrel KS8851 Address/data bus 1746 1746 + multiplexed network chip. 1747 1747 + 1741 1748 config VIA_RHINE 1742 1749 tristate "VIA Rhine support" 1743 1750 depends on NET_PCI && PCI

+1

drivers/net/Makefile

reviewed

··· 89 89 obj-$(CONFIG_SKFP) += skfp/ 90 90 obj-$(CONFIG_KS8842) += ks8842.o 91 91 obj-$(CONFIG_KS8851) += ks8851.o 92 92 + obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o 92 93 obj-$(CONFIG_VIA_RHINE) += via-rhine.o 93 94 obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o 94 95 obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o

+1 -1

drivers/net/bcm63xx_enet.c

reviewed

··· 90 90 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) 91 91 break; 92 92 udelay(1); 93 93 - } while (limit-- >= 0); 93 93 + } while (limit-- > 0); 94 94 95 95 return (limit < 0) ? 1 : 0; 96 96 }

+1

drivers/net/benet/be.h

reviewed

··· 258 258 bool link_up; 259 259 u32 port_num; 260 260 bool promiscuous; 261 261 + u32 cap; 261 262 }; 262 263 263 264 extern const struct ethtool_ops be_ethtool_ops;

+2 -1

drivers/net/benet/be_cmds.c

reviewed

··· 1068 1068 } 1069 1069 1070 1070 /* Uses mbox */ 1071 1071 - int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num) 1071 1071 + int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap) 1072 1072 { 1073 1073 struct be_mcc_wrb *wrb; 1074 1074 struct be_cmd_req_query_fw_cfg *req; ··· 1088 1088 if (!status) { 1089 1089 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); 1090 1090 *port_num = le32_to_cpu(resp->phys_port); 1091 1091 + *cap = le32_to_cpu(resp->function_cap); 1091 1092 } 1092 1093 1093 1094 spin_unlock(&adapter->mbox_lock);

+2 -1

drivers/net/benet/be_cmds.h

reviewed

··· 760 760 u32 tx_fc, u32 rx_fc); 761 761 extern int be_cmd_get_flow_control(struct be_adapter *adapter, 762 762 u32 *tx_fc, u32 *rx_fc); 763 763 - extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num); 763 763 + extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, 764 764 + u32 *port_num, u32 *cap); 764 765 extern int be_cmd_reset_function(struct be_adapter *adapter); 765 766 extern int be_process_mcc(struct be_adapter *adapter); 766 767 extern int be_cmd_write_flashrom(struct be_adapter *adapter,

+19 -4

drivers/net/benet/be_main.c

reviewed

··· 747 747 struct be_eth_rx_compl *rxcp) 748 748 { 749 749 struct sk_buff *skb; 750 750 - u32 vtp, vid; 750 750 + u32 vlanf, vid; 751 751 + u8 vtm; 751 752 752 752 - vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); 753 753 + vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); 754 754 + vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); 755 755 + 756 756 + /* vlanf could be wrongly set in some cards. 757 757 + * ignore if vtm is not set */ 758 758 + if ((adapter->cap == 0x400) && !vtm) 759 759 + vlanf = 0; 753 760 754 761 skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN); 755 762 if (!skb) { ··· 779 772 skb->protocol = eth_type_trans(skb, adapter->netdev); 780 773 skb->dev = adapter->netdev; 781 774 782 782 - if (vtp) { 775 775 + if (vlanf) { 783 776 if (!adapter->vlan_grp || adapter->num_vlans == 0) { 784 777 kfree_skb(skb); 785 778 return; ··· 804 797 struct be_eq_obj *eq_obj = &adapter->rx_eq; 805 798 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; 806 799 u16 i, rxq_idx = 0, vid, j; 800 800 + u8 vtm; 807 801 808 802 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); 809 803 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); 810 804 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); 811 805 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); 806 806 + vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); 807 807 + 808 808 + /* vlanf could be wrongly set in some cards. 809 809 + * ignore if vtm is not set */ 810 810 + if ((adapter->cap == 0x400) && !vtm) 811 811 + vlanf = 0; 812 812 813 813 skb = napi_get_frags(&eq_obj->napi); 814 814 if (!skb) { ··· 2059 2045 if (status) 2060 2046 return status; 2061 2047 2062 2062 - status = be_cmd_query_fw_cfg(adapter, &adapter->port_num); 2048 2048 + status = be_cmd_query_fw_cfg(adapter, 2049 2049 + &adapter->port_num, &adapter->cap); 2063 2050 return status; 2064 2051 } 2065 2052

+1

drivers/net/bonding/bond_sysfs.c

reviewed

··· 1182 1182 ": %s: Setting %s as primary slave.\n", 1183 1183 bond->dev->name, slave->dev->name); 1184 1184 bond->primary_slave = slave; 1185 1185 + strcpy(bond->params.primary, slave->dev->name); 1185 1186 bond_select_active_slave(bond); 1186 1187 goto out; 1187 1188 }

+2 -1

drivers/net/cnic.c

reviewed

··· 2733 2733 cnic_ulp_init(dev); 2734 2734 else if (event == NETDEV_UNREGISTER) 2735 2735 cnic_ulp_exit(dev); 2736 2736 - else if (event == NETDEV_UP) { 2736 2736 + 2737 2737 + if (event == NETDEV_UP) { 2737 2738 if (cnic_register_netdev(dev) != 0) { 2738 2739 cnic_put(dev); 2739 2740 goto done;

+2 -2

drivers/net/cnic_if.h

reviewed

··· 12 12 #ifndef CNIC_IF_H 13 13 #define CNIC_IF_H 14 14 15 15 - #define CNIC_MODULE_VERSION "2.0.0" 16 16 - #define CNIC_MODULE_RELDATE "May 21, 2009" 15 15 + #define CNIC_MODULE_VERSION "2.0.1" 16 16 + #define CNIC_MODULE_RELDATE "Oct 01, 2009" 17 17 18 18 #define CNIC_ULP_RDMA 0 19 19 #define CNIC_ULP_ISCSI 1

+2 -11

drivers/net/e1000e/netdev.c

reviewed

··· 4982 4982 goto err_pci_reg; 4983 4983 4984 4984 /* AER (Advanced Error Reporting) hooks */ 4985 4985 - err = pci_enable_pcie_error_reporting(pdev); 4986 4986 - if (err) { 4987 4987 - dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " 4988 4988 - "0x%x\n", err); 4989 4989 - /* non-fatal, continue */ 4990 4990 - } 4985 4985 + pci_enable_pcie_error_reporting(pdev); 4991 4986 4992 4987 pci_set_master(pdev); 4993 4988 /* PCI config space info */ ··· 5258 5263 { 5259 5264 struct net_device *netdev = pci_get_drvdata(pdev); 5260 5265 struct e1000_adapter *adapter = netdev_priv(netdev); 5261 5261 - int err; 5262 5266 5263 5267 /* 5264 5268 * flush_scheduled work may reschedule our watchdog task, so ··· 5293 5299 free_netdev(netdev); 5294 5300 5295 5301 /* AER disable */ 5296 5296 - err = pci_disable_pcie_error_reporting(pdev); 5297 5297 - if (err) 5298 5298 - dev_err(&pdev->dev, 5299 5299 - "pci_disable_pcie_error_reporting failed 0x%x\n", err); 5302 5302 + pci_disable_pcie_error_reporting(pdev); 5300 5303 5301 5304 pci_disable_device(pdev); 5302 5305 }

+2 -2

drivers/net/hamradio/mkiss.c

reviewed

··· 258 258 } 259 259 if (ax->crcmode != CRC_MODE_SMACK && ax->crcauto) { 260 260 printk(KERN_INFO 261 261 - "mkiss: %s: Switchting to crc-smack\n", 261 261 + "mkiss: %s: Switching to crc-smack\n", 262 262 ax->dev->name); 263 263 ax->crcmode = CRC_MODE_SMACK; 264 264 } ··· 272 272 } 273 273 if (ax->crcmode != CRC_MODE_FLEX && ax->crcauto) { 274 274 printk(KERN_INFO 275 275 - "mkiss: %s: Switchting to crc-flexnet\n", 275 275 + "mkiss: %s: Switching to crc-flexnet\n", 276 276 ax->dev->name); 277 277 ax->crcmode = CRC_MODE_FLEX; 278 278 }

+2 -11

drivers/net/igb/igb_main.c

reviewed

··· 1246 1246 if (err) 1247 1247 goto err_pci_reg; 1248 1248 1249 1249 - err = pci_enable_pcie_error_reporting(pdev); 1250 1250 - if (err) { 1251 1251 - dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " 1252 1252 - "0x%x\n", err); 1253 1253 - /* non-fatal, continue */ 1254 1254 - } 1249 1249 + pci_enable_pcie_error_reporting(pdev); 1255 1250 1256 1251 pci_set_master(pdev); 1257 1252 pci_save_state(pdev); ··· 1623 1628 struct net_device *netdev = pci_get_drvdata(pdev); 1624 1629 struct igb_adapter *adapter = netdev_priv(netdev); 1625 1630 struct e1000_hw *hw = &adapter->hw; 1626 1626 - int err; 1627 1631 1628 1632 /* flush_scheduled work may reschedule our watchdog task, so 1629 1633 * explicitly disable watchdog tasks from being rescheduled */ ··· 1676 1682 1677 1683 free_netdev(netdev); 1678 1684 1679 1679 - err = pci_disable_pcie_error_reporting(pdev); 1680 1680 - if (err) 1681 1681 - dev_err(&pdev->dev, 1682 1682 - "pci_disable_pcie_error_reporting failed 0x%x\n", err); 1685 1685 + pci_disable_pcie_error_reporting(pdev); 1683 1686 1684 1687 pci_disable_device(pdev); 1685 1688 }

+1 -1

drivers/net/iseries_veth.c

reviewed

··· 495 495 cnx->remote_lp); 496 496 } else { 497 497 memcpy(&cnx->cap_ack_event, event, 498 498 - sizeof(&cnx->cap_ack_event)); 498 498 + sizeof(cnx->cap_ack_event)); 499 499 cnx->state |= VETH_STATE_GOTCAPACK; 500 500 veth_kick_statemachine(cnx); 501 501 }

+1 -1

drivers/net/ixgbe/ixgbe_82598.c

reviewed

··· 425 425 #endif /* CONFIG_DCB */ 426 426 default: 427 427 hw_dbg(hw, "Flow control param set incorrectly\n"); 428 428 - ret_val = -IXGBE_ERR_CONFIG; 428 428 + ret_val = IXGBE_ERR_CONFIG; 429 429 goto out; 430 430 break; 431 431 }

+178 -54

drivers/net/ixgbe/ixgbe_common.c

reviewed

··· 1355 1355 /** 1356 1356 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1357 1357 * @hw: pointer to hardware structure 1358 1358 - * @addr_list: the list of new addresses 1359 1359 - * @addr_count: number of addresses 1360 1360 - * @next: iterator function to walk the address list 1358 1358 + * @uc_list: the list of new addresses 1361 1359 * 1362 1360 * The given list replaces any existing list. Clears the secondary addrs from 1363 1361 * receive address registers. Uses unused receive address registers for the ··· 1661 1663 #endif /* CONFIG_DCB */ 1662 1664 default: 1663 1665 hw_dbg(hw, "Flow control param set incorrectly\n"); 1664 1664 - ret_val = -IXGBE_ERR_CONFIG; 1666 1666 + ret_val = IXGBE_ERR_CONFIG; 1665 1667 goto out; 1666 1668 break; 1667 1669 } ··· 1732 1734 s32 ret_val = 0; 1733 1735 ixgbe_link_speed speed; 1734 1736 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1737 1737 + u32 links2, anlp1_reg, autoc_reg, links; 1735 1738 bool link_up; 1736 1739 1737 1740 /* 1738 1741 * AN should have completed when the cable was plugged in. 1739 1742 * Look for reasons to bail out. Bail out if: 1740 1743 * - FC autoneg is disabled, or if 1741 1741 - * - we don't have multispeed fiber, or if 1742 1742 - * - we're not running at 1G, or if 1743 1743 - * - link is not up, or if 1744 1744 - * - link is up but AN did not complete, or if 1745 1745 - * - link is up and AN completed but timed out 1744 1744 + * - link is not up. 1746 1745 * 1747 1747 - * Since we're being called from an LSC, link is already know to be up. 1746 1746 + * Since we're being called from an LSC, link is already known to be up. 1748 1747 * So use link_up_wait_to_complete=false. 1749 1748 */ 1750 1749 hw->mac.ops.check_link(hw, &speed, &link_up, false); 1751 1751 - linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1752 1750 1753 1753 - if (hw->fc.disable_fc_autoneg || 1754 1754 - !hw->phy.multispeed_fiber || 1755 1755 - (speed != IXGBE_LINK_SPEED_1GB_FULL) || 1756 1756 - !link_up || 1757 1757 - ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1758 1758 - ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1751 1751 + if (hw->fc.disable_fc_autoneg || (!link_up)) { 1759 1752 hw->fc.fc_was_autonegged = false; 1760 1753 hw->fc.current_mode = hw->fc.requested_mode; 1761 1761 - hw_dbg(hw, "Autoneg FC was skipped.\n"); 1762 1754 goto out; 1755 1755 + } 1756 1756 + 1757 1757 + /* 1758 1758 + * On backplane, bail out if 1759 1759 + * - backplane autoneg was not completed, or if 1760 1760 + * - link partner is not AN enabled 1761 1761 + */ 1762 1762 + if (hw->phy.media_type == ixgbe_media_type_backplane) { 1763 1763 + links = IXGBE_READ_REG(hw, IXGBE_LINKS); 1764 1764 + links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 1765 1765 + if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) || 1766 1766 + ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) { 1767 1767 + hw->fc.fc_was_autonegged = false; 1768 1768 + hw->fc.current_mode = hw->fc.requested_mode; 1769 1769 + goto out; 1770 1770 + } 1771 1771 + } 1772 1772 + 1773 1773 + /* 1774 1774 + * On multispeed fiber at 1g, bail out if 1775 1775 + * - link is up but AN did not complete, or if 1776 1776 + * - link is up and AN completed but timed out 1777 1777 + */ 1778 1778 + if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { 1779 1779 + linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1780 1780 + if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1781 1781 + ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1782 1782 + hw->fc.fc_was_autonegged = false; 1783 1783 + hw->fc.current_mode = hw->fc.requested_mode; 1784 1784 + goto out; 1785 1785 + } 1763 1786 } 1764 1787 1765 1788 /* 1766 1789 * Read the AN advertisement and LP ability registers and resolve 1767 1790 * local flow control settings accordingly 1768 1791 */ 1769 1769 - pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1770 1770 - pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1771 1771 - if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1772 1772 - (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1773 1773 - /* 1774 1774 - * Now we need to check if the user selected Rx ONLY 1775 1775 - * of pause frames. In this case, we had to advertise 1776 1776 - * FULL flow control because we could not advertise RX 1777 1777 - * ONLY. Hence, we must now check to see if we need to 1778 1778 - * turn OFF the TRANSMISSION of PAUSE frames. 1779 1779 - */ 1780 1780 - if (hw->fc.requested_mode == ixgbe_fc_full) { 1781 1781 - hw->fc.current_mode = ixgbe_fc_full; 1782 1782 - hw_dbg(hw, "Flow Control = FULL.\n"); 1783 1783 - } else { 1792 1792 + if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1793 1793 + (hw->phy.media_type != ixgbe_media_type_backplane)) { 1794 1794 + pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1795 1795 + pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1796 1796 + if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1797 1797 + (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1798 1798 + /* 1799 1799 + * Now we need to check if the user selected Rx ONLY 1800 1800 + * of pause frames. In this case, we had to advertise 1801 1801 + * FULL flow control because we could not advertise RX 1802 1802 + * ONLY. Hence, we must now check to see if we need to 1803 1803 + * turn OFF the TRANSMISSION of PAUSE frames. 1804 1804 + */ 1805 1805 + if (hw->fc.requested_mode == ixgbe_fc_full) { 1806 1806 + hw->fc.current_mode = ixgbe_fc_full; 1807 1807 + hw_dbg(hw, "Flow Control = FULL.\n"); 1808 1808 + } else { 1809 1809 + hw->fc.current_mode = ixgbe_fc_rx_pause; 1810 1810 + hw_dbg(hw, "Flow Control=RX PAUSE only\n"); 1811 1811 + } 1812 1812 + } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1813 1813 + (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1814 1814 + (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1815 1815 + (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1816 1816 + hw->fc.current_mode = ixgbe_fc_tx_pause; 1817 1817 + hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 1818 1818 + } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1819 1819 + (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1820 1820 + !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1821 1821 + (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1784 1822 hw->fc.current_mode = ixgbe_fc_rx_pause; 1785 1823 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 1824 1824 + } else { 1825 1825 + hw->fc.current_mode = ixgbe_fc_none; 1826 1826 + hw_dbg(hw, "Flow Control = NONE.\n"); 1786 1827 } 1787 1787 - } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1788 1788 - (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1789 1789 - (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1790 1790 - (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1791 1791 - hw->fc.current_mode = ixgbe_fc_tx_pause; 1792 1792 - hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 1793 1793 - } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1794 1794 - (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1795 1795 - !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1796 1796 - (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1797 1797 - hw->fc.current_mode = ixgbe_fc_rx_pause; 1798 1798 - hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 1799 1799 - } else { 1800 1800 - hw->fc.current_mode = ixgbe_fc_none; 1801 1801 - hw_dbg(hw, "Flow Control = NONE.\n"); 1802 1828 } 1803 1829 1830 1830 + if (hw->phy.media_type == ixgbe_media_type_backplane) { 1831 1831 + /* 1832 1832 + * Read the 10g AN autoc and LP ability registers and resolve 1833 1833 + * local flow control settings accordingly 1834 1834 + */ 1835 1835 + autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1836 1836 + anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1837 1837 + 1838 1838 + if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1839 1839 + (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { 1840 1840 + /* 1841 1841 + * Now we need to check if the user selected Rx ONLY 1842 1842 + * of pause frames. In this case, we had to advertise 1843 1843 + * FULL flow control because we could not advertise RX 1844 1844 + * ONLY. Hence, we must now check to see if we need to 1845 1845 + * turn OFF the TRANSMISSION of PAUSE frames. 1846 1846 + */ 1847 1847 + if (hw->fc.requested_mode == ixgbe_fc_full) { 1848 1848 + hw->fc.current_mode = ixgbe_fc_full; 1849 1849 + hw_dbg(hw, "Flow Control = FULL.\n"); 1850 1850 + } else { 1851 1851 + hw->fc.current_mode = ixgbe_fc_rx_pause; 1852 1852 + hw_dbg(hw, "Flow Control=RX PAUSE only\n"); 1853 1853 + } 1854 1854 + } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1855 1855 + (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1856 1856 + (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1857 1857 + (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1858 1858 + hw->fc.current_mode = ixgbe_fc_tx_pause; 1859 1859 + hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 1860 1860 + } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1861 1861 + (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1862 1862 + !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1863 1863 + (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1864 1864 + hw->fc.current_mode = ixgbe_fc_rx_pause; 1865 1865 + hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 1866 1866 + } else { 1867 1867 + hw->fc.current_mode = ixgbe_fc_none; 1868 1868 + hw_dbg(hw, "Flow Control = NONE.\n"); 1869 1869 + } 1870 1870 + } 1804 1871 /* Record that current_mode is the result of a successful autoneg */ 1805 1872 hw->fc.fc_was_autonegged = true; 1806 1873 ··· 1982 1919 #endif /* CONFIG_DCB */ 1983 1920 default: 1984 1921 hw_dbg(hw, "Flow control param set incorrectly\n"); 1985 1985 - ret_val = -IXGBE_ERR_CONFIG; 1922 1922 + ret_val = IXGBE_ERR_CONFIG; 1986 1923 goto out; 1987 1924 break; 1988 1925 } ··· 1990 1927 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 1991 1928 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 1992 1929 1993 1993 - /* Enable and restart autoneg to inform the link partner */ 1994 1994 - reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; 1995 1995 - 1996 1930 /* Disable AN timeout */ 1997 1931 if (hw->fc.strict_ieee) 1998 1932 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 1999 1933 2000 1934 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2001 1935 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 1936 1936 + 1937 1937 + /* 1938 1938 + * Set up the 10G flow control advertisement registers so the HW 1939 1939 + * can do fc autoneg once the cable is plugged in. If we end up 1940 1940 + * using 1g instead, this is harmless. 1941 1941 + */ 1942 1942 + reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1943 1943 + 1944 1944 + /* 1945 1945 + * The possible values of fc.requested_mode are: 1946 1946 + * 0: Flow control is completely disabled 1947 1947 + * 1: Rx flow control is enabled (we can receive pause frames, 1948 1948 + * but not send pause frames). 1949 1949 + * 2: Tx flow control is enabled (we can send pause frames but 1950 1950 + * we do not support receiving pause frames). 1951 1951 + * 3: Both Rx and Tx flow control (symmetric) are enabled. 1952 1952 + * other: Invalid. 1953 1953 + */ 1954 1954 + switch (hw->fc.requested_mode) { 1955 1955 + case ixgbe_fc_none: 1956 1956 + /* Flow control completely disabled by software override. */ 1957 1957 + reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 1958 1958 + break; 1959 1959 + case ixgbe_fc_rx_pause: 1960 1960 + /* 1961 1961 + * Rx Flow control is enabled and Tx Flow control is 1962 1962 + * disabled by software override. Since there really 1963 1963 + * isn't a way to advertise that we are capable of RX 1964 1964 + * Pause ONLY, we will advertise that we support both 1965 1965 + * symmetric and asymmetric Rx PAUSE. Later, we will 1966 1966 + * disable the adapter's ability to send PAUSE frames. 1967 1967 + */ 1968 1968 + reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 1969 1969 + break; 1970 1970 + case ixgbe_fc_tx_pause: 1971 1971 + /* 1972 1972 + * Tx Flow control is enabled, and Rx Flow control is 1973 1973 + * disabled by software override. 1974 1974 + */ 1975 1975 + reg |= (IXGBE_AUTOC_ASM_PAUSE); 1976 1976 + reg &= ~(IXGBE_AUTOC_SYM_PAUSE); 1977 1977 + break; 1978 1978 + case ixgbe_fc_full: 1979 1979 + /* Flow control (both Rx and Tx) is enabled by SW override. */ 1980 1980 + reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 1981 1981 + break; 1982 1982 + #ifdef CONFIG_DCB 1983 1983 + case ixgbe_fc_pfc: 1984 1984 + goto out; 1985 1985 + break; 1986 1986 + #endif /* CONFIG_DCB */ 1987 1987 + default: 1988 1988 + hw_dbg(hw, "Flow control param set incorrectly\n"); 1989 1989 + ret_val = IXGBE_ERR_CONFIG; 1990 1990 + goto out; 1991 1991 + break; 1992 1992 + } 1993 1993 + /* 1994 1994 + * AUTOC restart handles negotiation of 1G and 10G. There is 1995 1995 + * no need to set the PCS1GCTL register. 1996 1996 + */ 1997 1997 + reg |= IXGBE_AUTOC_AN_RESTART; 1998 1998 + IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); 1999 1999 + hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2002 2000 2003 2001 out: 2004 2002 return ret_val; ··· 2124 2000 2125 2001 while (timeout) { 2126 2002 if (ixgbe_get_eeprom_semaphore(hw)) 2127 2127 - return -IXGBE_ERR_SWFW_SYNC; 2003 2003 + return IXGBE_ERR_SWFW_SYNC; 2128 2004 2129 2005 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2130 2006 if (!(gssr & (fwmask | swmask))) ··· 2141 2017 2142 2018 if (!timeout) { 2143 2019 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); 2144 2144 - return -IXGBE_ERR_SWFW_SYNC; 2020 2020 + return IXGBE_ERR_SWFW_SYNC; 2145 2021 } 2146 2022 2147 2023 gssr |= swmask;

+4

drivers/net/ixgbe/ixgbe_ethtool.c

reviewed

··· 53 53 {"tx_packets", IXGBE_STAT(net_stats.tx_packets)}, 54 54 {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)}, 55 55 {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)}, 56 56 + {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 57 57 + {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 58 58 + {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 59 59 + {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 56 60 {"lsc_int", IXGBE_STAT(lsc_int)}, 57 61 {"tx_busy", IXGBE_STAT(tx_busy)}, 58 62 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},

+28 -24

drivers/net/ixgbe/ixgbe_main.c

reviewed

··· 49 49 static const char ixgbe_driver_string[] = 50 50 "Intel(R) 10 Gigabit PCI Express Network Driver"; 51 51 52 52 - #define DRV_VERSION "2.0.37-k2" 52 52 + #define DRV_VERSION "2.0.44-k2" 53 53 const char ixgbe_driver_version[] = DRV_VERSION; 54 54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; 55 55 ··· 1885 1885 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); 1886 1886 adapter->tx_ring[i].head = IXGBE_TDH(j); 1887 1887 adapter->tx_ring[i].tail = IXGBE_TDT(j); 1888 1888 - /* Disable Tx Head Writeback RO bit, since this hoses 1888 1888 + /* 1889 1889 + * Disable Tx Head Writeback RO bit, since this hoses 1889 1890 * bookkeeping if things aren't delivered in order. 1890 1891 */ 1891 1891 - txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 1892 1892 + switch (hw->mac.type) { 1893 1893 + case ixgbe_mac_82598EB: 1894 1894 + txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); 1895 1895 + break; 1896 1896 + case ixgbe_mac_82599EB: 1897 1897 + default: 1898 1898 + txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); 1899 1899 + break; 1900 1900 + } 1892 1901 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; 1893 1893 - IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 1902 1902 + switch (hw->mac.type) { 1903 1903 + case ixgbe_mac_82598EB: 1904 1904 + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); 1905 1905 + break; 1906 1906 + case ixgbe_mac_82599EB: 1907 1907 + default: 1908 1908 + IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); 1909 1909 + break; 1910 1910 + } 1894 1911 } 1895 1912 if (hw->mac.type == ixgbe_mac_82599EB) { 1896 1913 /* We enable 8 traffic classes, DCB only */ ··· 4449 4432 4450 4433 /* 82598 hardware only has a 32 bit counter in the high register */ 4451 4434 if (hw->mac.type == ixgbe_mac_82599EB) { 4435 4435 + u64 tmp; 4452 4436 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 4453 4453 - IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 4437 4437 + tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ 4438 4438 + adapter->stats.gorc += (tmp << 32); 4454 4439 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 4455 4455 - IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 4440 4440 + tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ 4441 4441 + adapter->stats.gotc += (tmp << 32); 4456 4442 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); 4457 4443 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 4458 4444 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); ··· 5091 5071 /* Right now, we support IPv4 only */ 5092 5072 struct ixgbe_atr_input atr_input; 5093 5073 struct tcphdr *th; 5094 5094 - struct udphdr *uh; 5095 5074 struct iphdr *iph = ip_hdr(skb); 5096 5075 struct ethhdr *eth = (struct ethhdr *)skb->data; 5097 5076 u16 vlan_id, src_port, dst_port, flex_bytes; ··· 5103 5084 src_port = th->source; 5104 5085 dst_port = th->dest; 5105 5086 l4type |= IXGBE_ATR_L4TYPE_TCP; 5106 5106 - /* l4type IPv4 type is 0, no need to assign */ 5107 5107 - } else if(iph->protocol == IPPROTO_UDP) { 5108 5108 - uh = udp_hdr(skb); 5109 5109 - src_port = uh->source; 5110 5110 - dst_port = uh->dest; 5111 5111 - l4type |= IXGBE_ATR_L4TYPE_UDP; 5112 5087 /* l4type IPv4 type is 0, no need to assign */ 5113 5088 } else { 5114 5089 /* Unsupported L4 header, just bail here */ ··· 5507 5494 goto err_pci_reg; 5508 5495 } 5509 5496 5510 5510 - err = pci_enable_pcie_error_reporting(pdev); 5511 5511 - if (err) { 5512 5512 - dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " 5513 5513 - "0x%x\n", err); 5514 5514 - /* non-fatal, continue */ 5515 5515 - } 5497 5497 + pci_enable_pcie_error_reporting(pdev); 5516 5498 5517 5499 pci_set_master(pdev); 5518 5500 pci_save_state(pdev); ··· 5816 5808 { 5817 5809 struct net_device *netdev = pci_get_drvdata(pdev); 5818 5810 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5819 5819 - int err; 5820 5811 5821 5812 set_bit(__IXGBE_DOWN, &adapter->state); 5822 5813 /* clear the module not found bit to make sure the worker won't ··· 5866 5859 5867 5860 free_netdev(netdev); 5868 5861 5869 5869 - err = pci_disable_pcie_error_reporting(pdev); 5870 5870 - if (err) 5871 5871 - dev_err(&pdev->dev, 5872 5872 - "pci_disable_pcie_error_reporting failed 0x%x\n", err); 5862 5862 + pci_disable_pcie_error_reporting(pdev); 5873 5863 5874 5864 pci_disable_device(pdev); 5875 5865 }

+9

drivers/net/ixgbe/ixgbe_type.h

reviewed

··· 1336 1336 #define IXGBE_AUTOC_KX4_SUPP 0x80000000 1337 1337 #define IXGBE_AUTOC_KX_SUPP 0x40000000 1338 1338 #define IXGBE_AUTOC_PAUSE 0x30000000 1339 1339 + #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 1340 1340 + #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 1339 1341 #define IXGBE_AUTOC_RF 0x08000000 1340 1342 #define IXGBE_AUTOC_PD_TMR 0x06000000 1341 1343 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 ··· 1406 1404 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1407 1405 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1408 1406 1407 1407 + #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 1408 1408 + 1409 1409 /* PCS1GLSTA Bit Masks */ 1410 1410 #define IXGBE_PCS1GLSTA_LINK_OK 1 1411 1411 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 ··· 1427 1423 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 1428 1424 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 1429 1425 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 1426 1426 + 1427 1427 + /* ANLP1 Bit Masks */ 1428 1428 + #define IXGBE_ANLP1_PAUSE 0x0C00 1429 1429 + #define IXGBE_ANLP1_SYM_PAUSE 0x0400 1430 1430 + #define IXGBE_ANLP1_ASM_PAUSE 0x0800 1430 1431 1431 1432 /* SW Semaphore Register bitmasks */ 1432 1433 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */

+1697

drivers/net/ks8851_mll.c

reviewed

··· 1 1 + /** 2 2 + * drivers/net/ks8851_mll.c 3 3 + * Copyright (c) 2009 Micrel Inc. 4 4 + * 5 5 + * This program is free software; you can redistribute it and/or modify 6 6 + * it under the terms of the GNU General Public License version 2 as 7 7 + * published by the Free Software Foundation. 8 8 + * 9 9 + * This program is distributed in the hope that it will be useful, 10 10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 12 + * GNU General Public License for more details. 13 13 + * 14 14 + * You should have received a copy of the GNU General Public License 15 15 + * along with this program; if not, write to the Free Software 16 16 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 17 + */ 18 18 + 19 19 + /** 20 20 + * Supports: 21 21 + * KS8851 16bit MLL chip from Micrel Inc. 22 22 + */ 23 23 + 24 24 + #include <linux/module.h> 25 25 + #include <linux/kernel.h> 26 26 + #include <linux/netdevice.h> 27 27 + #include <linux/etherdevice.h> 28 28 + #include <linux/ethtool.h> 29 29 + #include <linux/cache.h> 30 30 + #include <linux/crc32.h> 31 31 + #include <linux/mii.h> 32 32 + #include <linux/platform_device.h> 33 33 + #include <linux/delay.h> 34 34 + 35 35 + #define DRV_NAME "ks8851_mll" 36 36 + 37 37 + static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 }; 38 38 + #define MAX_RECV_FRAMES 32 39 39 + #define MAX_BUF_SIZE 2048 40 40 + #define TX_BUF_SIZE 2000 41 41 + #define RX_BUF_SIZE 2000 42 42 + 43 43 + #define KS_CCR 0x08 44 44 + #define CCR_EEPROM (1 << 9) 45 45 + #define CCR_SPI (1 << 8) 46 46 + #define CCR_8BIT (1 << 7) 47 47 + #define CCR_16BIT (1 << 6) 48 48 + #define CCR_32BIT (1 << 5) 49 49 + #define CCR_SHARED (1 << 4) 50 50 + #define CCR_32PIN (1 << 0) 51 51 + 52 52 + /* MAC address registers */ 53 53 + #define KS_MARL 0x10 54 54 + #define KS_MARM 0x12 55 55 + #define KS_MARH 0x14 56 56 + 57 57 + #define KS_OBCR 0x20 58 58 + #define OBCR_ODS_16MA (1 << 6) 59 59 + 60 60 + #define KS_EEPCR 0x22 61 61 + #define EEPCR_EESA (1 << 4) 62 62 + #define EEPCR_EESB (1 << 3) 63 63 + #define EEPCR_EEDO (1 << 2) 64 64 + #define EEPCR_EESCK (1 << 1) 65 65 + #define EEPCR_EECS (1 << 0) 66 66 + 67 67 + #define KS_MBIR 0x24 68 68 + #define MBIR_TXMBF (1 << 12) 69 69 + #define MBIR_TXMBFA (1 << 11) 70 70 + #define MBIR_RXMBF (1 << 4) 71 71 + #define MBIR_RXMBFA (1 << 3) 72 72 + 73 73 + #define KS_GRR 0x26 74 74 + #define GRR_QMU (1 << 1) 75 75 + #define GRR_GSR (1 << 0) 76 76 + 77 77 + #define KS_WFCR 0x2A 78 78 + #define WFCR_MPRXE (1 << 7) 79 79 + #define WFCR_WF3E (1 << 3) 80 80 + #define WFCR_WF2E (1 << 2) 81 81 + #define WFCR_WF1E (1 << 1) 82 82 + #define WFCR_WF0E (1 << 0) 83 83 + 84 84 + #define KS_WF0CRC0 0x30 85 85 + #define KS_WF0CRC1 0x32 86 86 + #define KS_WF0BM0 0x34 87 87 + #define KS_WF0BM1 0x36 88 88 + #define KS_WF0BM2 0x38 89 89 + #define KS_WF0BM3 0x3A 90 90 + 91 91 + #define KS_WF1CRC0 0x40 92 92 + #define KS_WF1CRC1 0x42 93 93 + #define KS_WF1BM0 0x44 94 94 + #define KS_WF1BM1 0x46 95 95 + #define KS_WF1BM2 0x48 96 96 + #define KS_WF1BM3 0x4A 97 97 + 98 98 + #define KS_WF2CRC0 0x50 99 99 + #define KS_WF2CRC1 0x52 100 100 + #define KS_WF2BM0 0x54 101 101 + #define KS_WF2BM1 0x56 102 102 + #define KS_WF2BM2 0x58 103 103 + #define KS_WF2BM3 0x5A 104 104 + 105 105 + #define KS_WF3CRC0 0x60 106 106 + #define KS_WF3CRC1 0x62 107 107 + #define KS_WF3BM0 0x64 108 108 + #define KS_WF3BM1 0x66 109 109 + #define KS_WF3BM2 0x68 110 110 + #define KS_WF3BM3 0x6A 111 111 + 112 112 + #define KS_TXCR 0x70 113 113 + #define TXCR_TCGICMP (1 << 8) 114 114 + #define TXCR_TCGUDP (1 << 7) 115 115 + #define TXCR_TCGTCP (1 << 6) 116 116 + #define TXCR_TCGIP (1 << 5) 117 117 + #define TXCR_FTXQ (1 << 4) 118 118 + #define TXCR_TXFCE (1 << 3) 119 119 + #define TXCR_TXPE (1 << 2) 120 120 + #define TXCR_TXCRC (1 << 1) 121 121 + #define TXCR_TXE (1 << 0) 122 122 + 123 123 + #define KS_TXSR 0x72 124 124 + #define TXSR_TXLC (1 << 13) 125 125 + #define TXSR_TXMC (1 << 12) 126 126 + #define TXSR_TXFID_MASK (0x3f << 0) 127 127 + #define TXSR_TXFID_SHIFT (0) 128 128 + #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) 129 129 + 130 130 + 131 131 + #define KS_RXCR1 0x74 132 132 + #define RXCR1_FRXQ (1 << 15) 133 133 + #define RXCR1_RXUDPFCC (1 << 14) 134 134 + #define RXCR1_RXTCPFCC (1 << 13) 135 135 + #define RXCR1_RXIPFCC (1 << 12) 136 136 + #define RXCR1_RXPAFMA (1 << 11) 137 137 + #define RXCR1_RXFCE (1 << 10) 138 138 + #define RXCR1_RXEFE (1 << 9) 139 139 + #define RXCR1_RXMAFMA (1 << 8) 140 140 + #define RXCR1_RXBE (1 << 7) 141 141 + #define RXCR1_RXME (1 << 6) 142 142 + #define RXCR1_RXUE (1 << 5) 143 143 + #define RXCR1_RXAE (1 << 4) 144 144 + #define RXCR1_RXINVF (1 << 1) 145 145 + #define RXCR1_RXE (1 << 0) 146 146 + #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ 147 147 + RXCR1_RXMAFMA | RXCR1_RXPAFMA) 148 148 + 149 149 + #define KS_RXCR2 0x76 150 150 + #define RXCR2_SRDBL_MASK (0x7 << 5) 151 151 + #define RXCR2_SRDBL_SHIFT (5) 152 152 + #define RXCR2_SRDBL_4B (0x0 << 5) 153 153 + #define RXCR2_SRDBL_8B (0x1 << 5) 154 154 + #define RXCR2_SRDBL_16B (0x2 << 5) 155 155 + #define RXCR2_SRDBL_32B (0x3 << 5) 156 156 + /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ 157 157 + #define RXCR2_IUFFP (1 << 4) 158 158 + #define RXCR2_RXIUFCEZ (1 << 3) 159 159 + #define RXCR2_UDPLFE (1 << 2) 160 160 + #define RXCR2_RXICMPFCC (1 << 1) 161 161 + #define RXCR2_RXSAF (1 << 0) 162 162 + 163 163 + #define KS_TXMIR 0x78 164 164 + 165 165 + #define KS_RXFHSR 0x7C 166 166 + #define RXFSHR_RXFV (1 << 15) 167 167 + #define RXFSHR_RXICMPFCS (1 << 13) 168 168 + #define RXFSHR_RXIPFCS (1 << 12) 169 169 + #define RXFSHR_RXTCPFCS (1 << 11) 170 170 + #define RXFSHR_RXUDPFCS (1 << 10) 171 171 + #define RXFSHR_RXBF (1 << 7) 172 172 + #define RXFSHR_RXMF (1 << 6) 173 173 + #define RXFSHR_RXUF (1 << 5) 174 174 + #define RXFSHR_RXMR (1 << 4) 175 175 + #define RXFSHR_RXFT (1 << 3) 176 176 + #define RXFSHR_RXFTL (1 << 2) 177 177 + #define RXFSHR_RXRF (1 << 1) 178 178 + #define RXFSHR_RXCE (1 << 0) 179 179 + #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ 180 180 + RXFSHR_RXFTL | RXFSHR_RXMR |\ 181 181 + RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\ 182 182 + RXFSHR_RXTCPFCS) 183 183 + #define KS_RXFHBCR 0x7E 184 184 + #define RXFHBCR_CNT_MASK 0x0FFF 185 185 + 186 186 + #define KS_TXQCR 0x80 187 187 + #define TXQCR_AETFE (1 << 2) 188 188 + #define TXQCR_TXQMAM (1 << 1) 189 189 + #define TXQCR_METFE (1 << 0) 190 190 + 191 191 + #define KS_RXQCR 0x82 192 192 + #define RXQCR_RXDTTS (1 << 12) 193 193 + #define RXQCR_RXDBCTS (1 << 11) 194 194 + #define RXQCR_RXFCTS (1 << 10) 195 195 + #define RXQCR_RXIPHTOE (1 << 9) 196 196 + #define RXQCR_RXDTTE (1 << 7) 197 197 + #define RXQCR_RXDBCTE (1 << 6) 198 198 + #define RXQCR_RXFCTE (1 << 5) 199 199 + #define RXQCR_ADRFE (1 << 4) 200 200 + #define RXQCR_SDA (1 << 3) 201 201 + #define RXQCR_RRXEF (1 << 0) 202 202 + #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) 203 203 + 204 204 + #define KS_TXFDPR 0x84 205 205 + #define TXFDPR_TXFPAI (1 << 14) 206 206 + #define TXFDPR_TXFP_MASK (0x7ff << 0) 207 207 + #define TXFDPR_TXFP_SHIFT (0) 208 208 + 209 209 + #define KS_RXFDPR 0x86 210 210 + #define RXFDPR_RXFPAI (1 << 14) 211 211 + 212 212 + #define KS_RXDTTR 0x8C 213 213 + #define KS_RXDBCTR 0x8E 214 214 + 215 215 + #define KS_IER 0x90 216 216 + #define KS_ISR 0x92 217 217 + #define IRQ_LCI (1 << 15) 218 218 + #define IRQ_TXI (1 << 14) 219 219 + #define IRQ_RXI (1 << 13) 220 220 + #define IRQ_RXOI (1 << 11) 221 221 + #define IRQ_TXPSI (1 << 9) 222 222 + #define IRQ_RXPSI (1 << 8) 223 223 + #define IRQ_TXSAI (1 << 6) 224 224 + #define IRQ_RXWFDI (1 << 5) 225 225 + #define IRQ_RXMPDI (1 << 4) 226 226 + #define IRQ_LDI (1 << 3) 227 227 + #define IRQ_EDI (1 << 2) 228 228 + #define IRQ_SPIBEI (1 << 1) 229 229 + #define IRQ_DEDI (1 << 0) 230 230 + 231 231 + #define KS_RXFCTR 0x9C 232 232 + #define RXFCTR_THRESHOLD_MASK 0x00FF 233 233 + 234 234 + #define KS_RXFC 0x9D 235 235 + #define RXFCTR_RXFC_MASK (0xff << 8) 236 236 + #define RXFCTR_RXFC_SHIFT (8) 237 237 + #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff) 238 238 + #define RXFCTR_RXFCT_MASK (0xff << 0) 239 239 + #define RXFCTR_RXFCT_SHIFT (0) 240 240 + 241 241 + #define KS_TXNTFSR 0x9E 242 242 + 243 243 + #define KS_MAHTR0 0xA0 244 244 + #define KS_MAHTR1 0xA2 245 245 + #define KS_MAHTR2 0xA4 246 246 + #define KS_MAHTR3 0xA6 247 247 + 248 248 + #define KS_FCLWR 0xB0 249 249 + #define KS_FCHWR 0xB2 250 250 + #define KS_FCOWR 0xB4 251 251 + 252 252 + #define KS_CIDER 0xC0 253 253 + #define CIDER_ID 0x8870 254 254 + #define CIDER_REV_MASK (0x7 << 1) 255 255 + #define CIDER_REV_SHIFT (1) 256 256 + #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7) 257 257 + 258 258 + #define KS_CGCR 0xC6 259 259 + #define KS_IACR 0xC8 260 260 + #define IACR_RDEN (1 << 12) 261 261 + #define IACR_TSEL_MASK (0x3 << 10) 262 262 + #define IACR_TSEL_SHIFT (10) 263 263 + #define IACR_TSEL_MIB (0x3 << 10) 264 264 + #define IACR_ADDR_MASK (0x1f << 0) 265 265 + #define IACR_ADDR_SHIFT (0) 266 266 + 267 267 + #define KS_IADLR 0xD0 268 268 + #define KS_IAHDR 0xD2 269 269 + 270 270 + #define KS_PMECR 0xD4 271 271 + #define PMECR_PME_DELAY (1 << 14) 272 272 + #define PMECR_PME_POL (1 << 12) 273 273 + #define PMECR_WOL_WAKEUP (1 << 11) 274 274 + #define PMECR_WOL_MAGICPKT (1 << 10) 275 275 + #define PMECR_WOL_LINKUP (1 << 9) 276 276 + #define PMECR_WOL_ENERGY (1 << 8) 277 277 + #define PMECR_AUTO_WAKE_EN (1 << 7) 278 278 + #define PMECR_WAKEUP_NORMAL (1 << 6) 279 279 + #define PMECR_WKEVT_MASK (0xf << 2) 280 280 + #define PMECR_WKEVT_SHIFT (2) 281 281 + #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) 282 282 + #define PMECR_WKEVT_ENERGY (0x1 << 2) 283 283 + #define PMECR_WKEVT_LINK (0x2 << 2) 284 284 + #define PMECR_WKEVT_MAGICPKT (0x4 << 2) 285 285 + #define PMECR_WKEVT_FRAME (0x8 << 2) 286 286 + #define PMECR_PM_MASK (0x3 << 0) 287 287 + #define PMECR_PM_SHIFT (0) 288 288 + #define PMECR_PM_NORMAL (0x0 << 0) 289 289 + #define PMECR_PM_ENERGY (0x1 << 0) 290 290 + #define PMECR_PM_SOFTDOWN (0x2 << 0) 291 291 + #define PMECR_PM_POWERSAVE (0x3 << 0) 292 292 + 293 293 + /* Standard MII PHY data */ 294 294 + #define KS_P1MBCR 0xE4 295 295 + #define P1MBCR_FORCE_FDX (1 << 8) 296 296 + 297 297 + #define KS_P1MBSR 0xE6 298 298 + #define P1MBSR_AN_COMPLETE (1 << 5) 299 299 + #define P1MBSR_AN_CAPABLE (1 << 3) 300 300 + #define P1MBSR_LINK_UP (1 << 2) 301 301 + 302 302 + #define KS_PHY1ILR 0xE8 303 303 + #define KS_PHY1IHR 0xEA 304 304 + #define KS_P1ANAR 0xEC 305 305 + #define KS_P1ANLPR 0xEE 306 306 + 307 307 + #define KS_P1SCLMD 0xF4 308 308 + #define P1SCLMD_LEDOFF (1 << 15) 309 309 + #define P1SCLMD_TXIDS (1 << 14) 310 310 + #define P1SCLMD_RESTARTAN (1 << 13) 311 311 + #define P1SCLMD_DISAUTOMDIX (1 << 10) 312 312 + #define P1SCLMD_FORCEMDIX (1 << 9) 313 313 + #define P1SCLMD_AUTONEGEN (1 << 7) 314 314 + #define P1SCLMD_FORCE100 (1 << 6) 315 315 + #define P1SCLMD_FORCEFDX (1 << 5) 316 316 + #define P1SCLMD_ADV_FLOW (1 << 4) 317 317 + #define P1SCLMD_ADV_100BT_FDX (1 << 3) 318 318 + #define P1SCLMD_ADV_100BT_HDX (1 << 2) 319 319 + #define P1SCLMD_ADV_10BT_FDX (1 << 1) 320 320 + #define P1SCLMD_ADV_10BT_HDX (1 << 0) 321 321 + 322 322 + #define KS_P1CR 0xF6 323 323 + #define P1CR_HP_MDIX (1 << 15) 324 324 + #define P1CR_REV_POL (1 << 13) 325 325 + #define P1CR_OP_100M (1 << 10) 326 326 + #define P1CR_OP_FDX (1 << 9) 327 327 + #define P1CR_OP_MDI (1 << 7) 328 328 + #define P1CR_AN_DONE (1 << 6) 329 329 + #define P1CR_LINK_GOOD (1 << 5) 330 330 + #define P1CR_PNTR_FLOW (1 << 4) 331 331 + #define P1CR_PNTR_100BT_FDX (1 << 3) 332 332 + #define P1CR_PNTR_100BT_HDX (1 << 2) 333 333 + #define P1CR_PNTR_10BT_FDX (1 << 1) 334 334 + #define P1CR_PNTR_10BT_HDX (1 << 0) 335 335 + 336 336 + /* TX Frame control */ 337 337 + 338 338 + #define TXFR_TXIC (1 << 15) 339 339 + #define TXFR_TXFID_MASK (0x3f << 0) 340 340 + #define TXFR_TXFID_SHIFT (0) 341 341 + 342 342 + #define KS_P1SR 0xF8 343 343 + #define P1SR_HP_MDIX (1 << 15) 344 344 + #define P1SR_REV_POL (1 << 13) 345 345 + #define P1SR_OP_100M (1 << 10) 346 346 + #define P1SR_OP_FDX (1 << 9) 347 347 + #define P1SR_OP_MDI (1 << 7) 348 348 + #define P1SR_AN_DONE (1 << 6) 349 349 + #define P1SR_LINK_GOOD (1 << 5) 350 350 + #define P1SR_PNTR_FLOW (1 << 4) 351 351 + #define P1SR_PNTR_100BT_FDX (1 << 3) 352 352 + #define P1SR_PNTR_100BT_HDX (1 << 2) 353 353 + #define P1SR_PNTR_10BT_FDX (1 << 1) 354 354 + #define P1SR_PNTR_10BT_HDX (1 << 0) 355 355 + 356 356 + #define ENUM_BUS_NONE 0 357 357 + #define ENUM_BUS_8BIT 1 358 358 + #define ENUM_BUS_16BIT 2 359 359 + #define ENUM_BUS_32BIT 3 360 360 + 361 361 + #define MAX_MCAST_LST 32 362 362 + #define HW_MCAST_SIZE 8 363 363 + #define MAC_ADDR_LEN 6 364 364 + 365 365 + /** 366 366 + * union ks_tx_hdr - tx header data 367 367 + * @txb: The header as bytes 368 368 + * @txw: The header as 16bit, little-endian words 369 369 + * 370 370 + * A dual representation of the tx header data to allow 371 371 + * access to individual bytes, and to allow 16bit accesses 372 372 + * with 16bit alignment. 373 373 + */ 374 374 + union ks_tx_hdr { 375 375 + u8 txb[4]; 376 376 + __le16 txw[2]; 377 377 + }; 378 378 + 379 379 + /** 380 380 + * struct ks_net - KS8851 driver private data 381 381 + * @net_device : The network device we're bound to 382 382 + * @hw_addr : start address of data register. 383 383 + * @hw_addr_cmd : start address of command register. 384 384 + * @txh : temporaly buffer to save status/length. 385 385 + * @lock : Lock to ensure that the device is not accessed when busy. 386 386 + * @pdev : Pointer to platform device. 387 387 + * @mii : The MII state information for the mii calls. 388 388 + * @frame_head_info : frame header information for multi-pkt rx. 389 389 + * @statelock : Lock on this structure for tx list. 390 390 + * @msg_enable : The message flags controlling driver output (see ethtool). 391 391 + * @frame_cnt : number of frames received. 392 392 + * @bus_width : i/o bus width. 393 393 + * @irq : irq number assigned to this device. 394 394 + * @rc_rxqcr : Cached copy of KS_RXQCR. 395 395 + * @rc_txcr : Cached copy of KS_TXCR. 396 396 + * @rc_ier : Cached copy of KS_IER. 397 397 + * @sharedbus : Multipex(addr and data bus) mode indicator. 398 398 + * @cmd_reg_cache : command register cached. 399 399 + * @cmd_reg_cache_int : command register cached. Used in the irq handler. 400 400 + * @promiscuous : promiscuous mode indicator. 401 401 + * @all_mcast : mutlicast indicator. 402 402 + * @mcast_lst_size : size of multicast list. 403 403 + * @mcast_lst : multicast list. 404 404 + * @mcast_bits : multicast enabed. 405 405 + * @mac_addr : MAC address assigned to this device. 406 406 + * @fid : frame id. 407 407 + * @extra_byte : number of extra byte prepended rx pkt. 408 408 + * @enabled : indicator this device works. 409 409 + * 410 410 + * The @lock ensures that the chip is protected when certain operations are 411 411 + * in progress. When the read or write packet transfer is in progress, most 412 412 + * of the chip registers are not accessible until the transfer is finished and 413 413 + * the DMA has been de-asserted. 414 414 + * 415 415 + * The @statelock is used to protect information in the structure which may 416 416 + * need to be accessed via several sources, such as the network driver layer 417 417 + * or one of the work queues. 418 418 + * 419 419 + */ 420 420 + 421 421 + /* Receive multiplex framer header info */ 422 422 + struct type_frame_head { 423 423 + u16 sts; /* Frame status */ 424 424 + u16 len; /* Byte count */ 425 425 + }; 426 426 + 427 427 + struct ks_net { 428 428 + struct net_device *netdev; 429 429 + void __iomem *hw_addr; 430 430 + void __iomem *hw_addr_cmd; 431 431 + union ks_tx_hdr txh ____cacheline_aligned; 432 432 + struct mutex lock; /* spinlock to be interrupt safe */ 433 433 + struct platform_device *pdev; 434 434 + struct mii_if_info mii; 435 435 + struct type_frame_head *frame_head_info; 436 436 + spinlock_t statelock; 437 437 + u32 msg_enable; 438 438 + u32 frame_cnt; 439 439 + int bus_width; 440 440 + int irq; 441 441 + 442 442 + u16 rc_rxqcr; 443 443 + u16 rc_txcr; 444 444 + u16 rc_ier; 445 445 + u16 sharedbus; 446 446 + u16 cmd_reg_cache; 447 447 + u16 cmd_reg_cache_int; 448 448 + u16 promiscuous; 449 449 + u16 all_mcast; 450 450 + u16 mcast_lst_size; 451 451 + u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN]; 452 452 + u8 mcast_bits[HW_MCAST_SIZE]; 453 453 + u8 mac_addr[6]; 454 454 + u8 fid; 455 455 + u8 extra_byte; 456 456 + u8 enabled; 457 457 + }; 458 458 + 459 459 + static int msg_enable; 460 460 + 461 461 + #define ks_info(_ks, _msg...) dev_info(&(_ks)->pdev->dev, _msg) 462 462 + #define ks_warn(_ks, _msg...) dev_warn(&(_ks)->pdev->dev, _msg) 463 463 + #define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->pdev->dev, _msg) 464 464 + #define ks_err(_ks, _msg...) dev_err(&(_ks)->pdev->dev, _msg) 465 465 + 466 466 + #define BE3 0x8000 /* Byte Enable 3 */ 467 467 + #define BE2 0x4000 /* Byte Enable 2 */ 468 468 + #define BE1 0x2000 /* Byte Enable 1 */ 469 469 + #define BE0 0x1000 /* Byte Enable 0 */ 470 470 + 471 471 + /** 472 472 + * register read/write calls. 473 473 + * 474 474 + * All these calls issue transactions to access the chip's registers. They 475 475 + * all require that the necessary lock is held to prevent accesses when the 476 476 + * chip is busy transfering packet data (RX/TX FIFO accesses). 477 477 + */ 478 478 + 479 479 + /** 480 480 + * ks_rdreg8 - read 8 bit register from device 481 481 + * @ks : The chip information 482 482 + * @offset: The register address 483 483 + * 484 484 + * Read a 8bit register from the chip, returning the result 485 485 + */ 486 486 + static u8 ks_rdreg8(struct ks_net *ks, int offset) 487 487 + { 488 488 + u16 data; 489 489 + u8 shift_bit = offset & 0x03; 490 490 + u8 shift_data = (offset & 1) << 3; 491 491 + ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit); 492 492 + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); 493 493 + data = ioread16(ks->hw_addr); 494 494 + return (u8)(data >> shift_data); 495 495 + } 496 496 + 497 497 + /** 498 498 + * ks_rdreg16 - read 16 bit register from device 499 499 + * @ks : The chip information 500 500 + * @offset: The register address 501 501 + * 502 502 + * Read a 16bit register from the chip, returning the result 503 503 + */ 504 504 + 505 505 + static u16 ks_rdreg16(struct ks_net *ks, int offset) 506 506 + { 507 507 + ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); 508 508 + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); 509 509 + return ioread16(ks->hw_addr); 510 510 + } 511 511 + 512 512 + /** 513 513 + * ks_wrreg8 - write 8bit register value to chip 514 514 + * @ks: The chip information 515 515 + * @offset: The register address 516 516 + * @value: The value to write 517 517 + * 518 518 + */ 519 519 + static void ks_wrreg8(struct ks_net *ks, int offset, u8 value) 520 520 + { 521 521 + u8 shift_bit = (offset & 0x03); 522 522 + u16 value_write = (u16)(value << ((offset & 1) << 3)); 523 523 + ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit); 524 524 + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); 525 525 + iowrite16(value_write, ks->hw_addr); 526 526 + } 527 527 + 528 528 + /** 529 529 + * ks_wrreg16 - write 16bit register value to chip 530 530 + * @ks: The chip information 531 531 + * @offset: The register address 532 532 + * @value: The value to write 533 533 + * 534 534 + */ 535 535 + 536 536 + static void ks_wrreg16(struct ks_net *ks, int offset, u16 value) 537 537 + { 538 538 + ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); 539 539 + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); 540 540 + iowrite16(value, ks->hw_addr); 541 541 + } 542 542 + 543 543 + /** 544 544 + * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled. 545 545 + * @ks: The chip state 546 546 + * @wptr: buffer address to save data 547 547 + * @len: length in byte to read 548 548 + * 549 549 + */ 550 550 + static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) 551 551 + { 552 552 + len >>= 1; 553 553 + while (len--) 554 554 + *wptr++ = (u16)ioread16(ks->hw_addr); 555 555 + } 556 556 + 557 557 + /** 558 558 + * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled. 559 559 + * @ks: The chip information 560 560 + * @wptr: buffer address 561 561 + * @len: length in byte to write 562 562 + * 563 563 + */ 564 564 + static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) 565 565 + { 566 566 + len >>= 1; 567 567 + while (len--) 568 568 + iowrite16(*wptr++, ks->hw_addr); 569 569 + } 570 570 + 571 571 + /** 572 572 + * ks_tx_fifo_space - return the available hardware buffer size. 573 573 + * @ks: The chip information 574 574 + * 575 575 + */ 576 576 + static inline u16 ks_tx_fifo_space(struct ks_net *ks) 577 577 + { 578 578 + return ks_rdreg16(ks, KS_TXMIR) & 0x1fff; 579 579 + } 580 580 + 581 581 + /** 582 582 + * ks_save_cmd_reg - save the command register from the cache. 583 583 + * @ks: The chip information 584 584 + * 585 585 + */ 586 586 + static inline void ks_save_cmd_reg(struct ks_net *ks) 587 587 + { 588 588 + /*ks8851 MLL has a bug to read back the command register. 589 589 + * So rely on software to save the content of command register. 590 590 + */ 591 591 + ks->cmd_reg_cache_int = ks->cmd_reg_cache; 592 592 + } 593 593 + 594 594 + /** 595 595 + * ks_restore_cmd_reg - restore the command register from the cache and 596 596 + * write to hardware register. 597 597 + * @ks: The chip information 598 598 + * 599 599 + */ 600 600 + static inline void ks_restore_cmd_reg(struct ks_net *ks) 601 601 + { 602 602 + ks->cmd_reg_cache = ks->cmd_reg_cache_int; 603 603 + iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); 604 604 + } 605 605 + 606 606 + /** 607 607 + * ks_set_powermode - set power mode of the device 608 608 + * @ks: The chip information 609 609 + * @pwrmode: The power mode value to write to KS_PMECR. 610 610 + * 611 611 + * Change the power mode of the chip. 612 612 + */ 613 613 + static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode) 614 614 + { 615 615 + unsigned pmecr; 616 616 + 617 617 + if (netif_msg_hw(ks)) 618 618 + ks_dbg(ks, "setting power mode %d\n", pwrmode); 619 619 + 620 620 + ks_rdreg16(ks, KS_GRR); 621 621 + pmecr = ks_rdreg16(ks, KS_PMECR); 622 622 + pmecr &= ~PMECR_PM_MASK; 623 623 + pmecr |= pwrmode; 624 624 + 625 625 + ks_wrreg16(ks, KS_PMECR, pmecr); 626 626 + } 627 627 + 628 628 + /** 629 629 + * ks_read_config - read chip configuration of bus width. 630 630 + * @ks: The chip information 631 631 + * 632 632 + */ 633 633 + static void ks_read_config(struct ks_net *ks) 634 634 + { 635 635 + u16 reg_data = 0; 636 636 + 637 637 + /* Regardless of bus width, 8 bit read should always work.*/ 638 638 + reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF; 639 639 + reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8; 640 640 + 641 641 + /* addr/data bus are multiplexed */ 642 642 + ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; 643 643 + 644 644 + /* There are garbage data when reading data from QMU, 645 645 + depending on bus-width. 646 646 + */ 647 647 + 648 648 + if (reg_data & CCR_8BIT) { 649 649 + ks->bus_width = ENUM_BUS_8BIT; 650 650 + ks->extra_byte = 1; 651 651 + } else if (reg_data & CCR_16BIT) { 652 652 + ks->bus_width = ENUM_BUS_16BIT; 653 653 + ks->extra_byte = 2; 654 654 + } else { 655 655 + ks->bus_width = ENUM_BUS_32BIT; 656 656 + ks->extra_byte = 4; 657 657 + } 658 658 + } 659 659 + 660 660 + /** 661 661 + * ks_soft_reset - issue one of the soft reset to the device 662 662 + * @ks: The device state. 663 663 + * @op: The bit(s) to set in the GRR 664 664 + * 665 665 + * Issue the relevant soft-reset command to the device's GRR register 666 666 + * specified by @op. 667 667 + * 668 668 + * Note, the delays are in there as a caution to ensure that the reset 669 669 + * has time to take effect and then complete. Since the datasheet does 670 670 + * not currently specify the exact sequence, we have chosen something 671 671 + * that seems to work with our device. 672 672 + */ 673 673 + static void ks_soft_reset(struct ks_net *ks, unsigned op) 674 674 + { 675 675 + /* Disable interrupt first */ 676 676 + ks_wrreg16(ks, KS_IER, 0x0000); 677 677 + ks_wrreg16(ks, KS_GRR, op); 678 678 + mdelay(10); /* wait a short time to effect reset */ 679 679 + ks_wrreg16(ks, KS_GRR, 0); 680 680 + mdelay(1); /* wait for condition to clear */ 681 681 + } 682 682 + 683 683 + 684 684 + /** 685 685 + * ks_read_qmu - read 1 pkt data from the QMU. 686 686 + * @ks: The chip information 687 687 + * @buf: buffer address to save 1 pkt 688 688 + * @len: Pkt length 689 689 + * Here is the sequence to read 1 pkt: 690 690 + * 1. set sudo DMA mode 691 691 + * 2. read prepend data 692 692 + * 3. read pkt data 693 693 + * 4. reset sudo DMA Mode 694 694 + */ 695 695 + static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len) 696 696 + { 697 697 + u32 r = ks->extra_byte & 0x1 ; 698 698 + u32 w = ks->extra_byte - r; 699 699 + 700 700 + /* 1. set sudo DMA mode */ 701 701 + ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI); 702 702 + ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); 703 703 + 704 704 + /* 2. read prepend data */ 705 705 + /** 706 706 + * read 4 + extra bytes and discard them. 707 707 + * extra bytes for dummy, 2 for status, 2 for len 708 708 + */ 709 709 + 710 710 + /* use likely(r) for 8 bit access for performance */ 711 711 + if (unlikely(r)) 712 712 + ioread8(ks->hw_addr); 713 713 + ks_inblk(ks, buf, w + 2 + 2); 714 714 + 715 715 + /* 3. read pkt data */ 716 716 + ks_inblk(ks, buf, ALIGN(len, 4)); 717 717 + 718 718 + /* 4. reset sudo DMA Mode */ 719 719 + ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr); 720 720 + } 721 721 + 722 722 + /** 723 723 + * ks_rcv - read multiple pkts data from the QMU. 724 724 + * @ks: The chip information 725 725 + * @netdev: The network device being opened. 726 726 + * 727 727 + * Read all of header information before reading pkt content. 728 728 + * It is not allowed only port of pkts in QMU after issuing 729 729 + * interrupt ack. 730 730 + */ 731 731 + static void ks_rcv(struct ks_net *ks, struct net_device *netdev) 732 732 + { 733 733 + u32 i; 734 734 + struct type_frame_head *frame_hdr = ks->frame_head_info; 735 735 + struct sk_buff *skb; 736 736 + 737 737 + ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8; 738 738 + 739 739 + /* read all header information */ 740 740 + for (i = 0; i < ks->frame_cnt; i++) { 741 741 + /* Checking Received packet status */ 742 742 + frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR); 743 743 + /* Get packet len from hardware */ 744 744 + frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR); 745 745 + frame_hdr++; 746 746 + } 747 747 + 748 748 + frame_hdr = ks->frame_head_info; 749 749 + while (ks->frame_cnt--) { 750 750 + skb = dev_alloc_skb(frame_hdr->len + 16); 751 751 + if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) && 752 752 + (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) { 753 753 + skb_reserve(skb, 2); 754 754 + /* read data block including CRC 4 bytes */ 755 755 + ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len + 4); 756 756 + skb_put(skb, frame_hdr->len); 757 757 + skb->dev = netdev; 758 758 + skb->protocol = eth_type_trans(skb, netdev); 759 759 + netif_rx(skb); 760 760 + } else { 761 761 + printk(KERN_ERR "%s: err:skb alloc\n", __func__); 762 762 + ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF)); 763 763 + if (skb) 764 764 + dev_kfree_skb_irq(skb); 765 765 + } 766 766 + frame_hdr++; 767 767 + } 768 768 + } 769 769 + 770 770 + /** 771 771 + * ks_update_link_status - link status update. 772 772 + * @netdev: The network device being opened. 773 773 + * @ks: The chip information 774 774 + * 775 775 + */ 776 776 + 777 777 + static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks) 778 778 + { 779 779 + /* check the status of the link */ 780 780 + u32 link_up_status; 781 781 + if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) { 782 782 + netif_carrier_on(netdev); 783 783 + link_up_status = true; 784 784 + } else { 785 785 + netif_carrier_off(netdev); 786 786 + link_up_status = false; 787 787 + } 788 788 + if (netif_msg_link(ks)) 789 789 + ks_dbg(ks, "%s: %s\n", 790 790 + __func__, link_up_status ? "UP" : "DOWN"); 791 791 + } 792 792 + 793 793 + /** 794 794 + * ks_irq - device interrupt handler 795 795 + * @irq: Interrupt number passed from the IRQ hnalder. 796 796 + * @pw: The private word passed to register_irq(), our struct ks_net. 797 797 + * 798 798 + * This is the handler invoked to find out what happened 799 799 + * 800 800 + * Read the interrupt status, work out what needs to be done and then clear 801 801 + * any of the interrupts that are not needed. 802 802 + */ 803 803 + 804 804 + static irqreturn_t ks_irq(int irq, void *pw) 805 805 + { 806 806 + struct ks_net *ks = pw; 807 807 + struct net_device *netdev = ks->netdev; 808 808 + u16 status; 809 809 + 810 810 + /*this should be the first in IRQ handler */ 811 811 + ks_save_cmd_reg(ks); 812 812 + 813 813 + status = ks_rdreg16(ks, KS_ISR); 814 814 + if (unlikely(!status)) { 815 815 + ks_restore_cmd_reg(ks); 816 816 + return IRQ_NONE; 817 817 + } 818 818 + 819 819 + ks_wrreg16(ks, KS_ISR, status); 820 820 + 821 821 + if (likely(status & IRQ_RXI)) 822 822 + ks_rcv(ks, netdev); 823 823 + 824 824 + if (unlikely(status & IRQ_LCI)) 825 825 + ks_update_link_status(netdev, ks); 826 826 + 827 827 + if (unlikely(status & IRQ_TXI)) 828 828 + netif_wake_queue(netdev); 829 829 + 830 830 + if (unlikely(status & IRQ_LDI)) { 831 831 + 832 832 + u16 pmecr = ks_rdreg16(ks, KS_PMECR); 833 833 + pmecr &= ~PMECR_WKEVT_MASK; 834 834 + ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK); 835 835 + } 836 836 + 837 837 + /* this should be the last in IRQ handler*/ 838 838 + ks_restore_cmd_reg(ks); 839 839 + return IRQ_HANDLED; 840 840 + } 841 841 + 842 842 + 843 843 + /** 844 844 + * ks_net_open - open network device 845 845 + * @netdev: The network device being opened. 846 846 + * 847 847 + * Called when the network device is marked active, such as a user executing 848 848 + * 'ifconfig up' on the device. 849 849 + */ 850 850 + static int ks_net_open(struct net_device *netdev) 851 851 + { 852 852 + struct ks_net *ks = netdev_priv(netdev); 853 853 + int err; 854 854 + 855 855 + #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW) 856 856 + /* lock the card, even if we may not actually do anything 857 857 + * else at the moment. 858 858 + */ 859 859 + 860 860 + if (netif_msg_ifup(ks)) 861 861 + ks_dbg(ks, "%s - entry\n", __func__); 862 862 + 863 863 + /* reset the HW */ 864 864 + err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, ks); 865 865 + 866 866 + if (err) { 867 867 + printk(KERN_ERR "Failed to request IRQ: %d: %d\n", 868 868 + ks->irq, err); 869 869 + return err; 870 870 + } 871 871 + 872 872 + if (netif_msg_ifup(ks)) 873 873 + ks_dbg(ks, "network device %s up\n", netdev->name); 874 874 + 875 875 + return 0; 876 876 + } 877 877 + 878 878 + /** 879 879 + * ks_net_stop - close network device 880 880 + * @netdev: The device being closed. 881 881 + * 882 882 + * Called to close down a network device which has been active. Cancell any 883 883 + * work, shutdown the RX and TX process and then place the chip into a low 884 884 + * power state whilst it is not being used. 885 885 + */ 886 886 + static int ks_net_stop(struct net_device *netdev) 887 887 + { 888 888 + struct ks_net *ks = netdev_priv(netdev); 889 889 + 890 890 + if (netif_msg_ifdown(ks)) 891 891 + ks_info(ks, "%s: shutting down\n", netdev->name); 892 892 + 893 893 + netif_stop_queue(netdev); 894 894 + 895 895 + kfree(ks->frame_head_info); 896 896 + 897 897 + mutex_lock(&ks->lock); 898 898 + 899 899 + /* turn off the IRQs and ack any outstanding */ 900 900 + ks_wrreg16(ks, KS_IER, 0x0000); 901 901 + ks_wrreg16(ks, KS_ISR, 0xffff); 902 902 + 903 903 + /* shutdown RX process */ 904 904 + ks_wrreg16(ks, KS_RXCR1, 0x0000); 905 905 + 906 906 + /* shutdown TX process */ 907 907 + ks_wrreg16(ks, KS_TXCR, 0x0000); 908 908 + 909 909 + /* set powermode to soft power down to save power */ 910 910 + ks_set_powermode(ks, PMECR_PM_SOFTDOWN); 911 911 + free_irq(ks->irq, netdev); 912 912 + mutex_unlock(&ks->lock); 913 913 + return 0; 914 914 + } 915 915 + 916 916 + 917 917 + /** 918 918 + * ks_write_qmu - write 1 pkt data to the QMU. 919 919 + * @ks: The chip information 920 920 + * @pdata: buffer address to save 1 pkt 921 921 + * @len: Pkt length in byte 922 922 + * Here is the sequence to write 1 pkt: 923 923 + * 1. set sudo DMA mode 924 924 + * 2. write status/length 925 925 + * 3. write pkt data 926 926 + * 4. reset sudo DMA Mode 927 927 + * 5. reset sudo DMA mode 928 928 + * 6. Wait until pkt is out 929 929 + */ 930 930 + static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len) 931 931 + { 932 932 + unsigned fid = ks->fid; 933 933 + 934 934 + fid = ks->fid; 935 935 + ks->fid = (ks->fid + 1) & TXFR_TXFID_MASK; 936 936 + 937 937 + /* reduce the tx interrupt occurrances. */ 938 938 + if (!fid) 939 939 + fid |= TXFR_TXIC; /* irq on completion */ 940 940 + 941 941 + /* start header at txb[0] to align txw entries */ 942 942 + ks->txh.txw[0] = cpu_to_le16(fid); 943 943 + ks->txh.txw[1] = cpu_to_le16(len); 944 944 + 945 945 + /* 1. set sudo-DMA mode */ 946 946 + ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); 947 947 + /* 2. write status/lenth info */ 948 948 + ks_outblk(ks, ks->txh.txw, 4); 949 949 + /* 3. write pkt data */ 950 950 + ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4)); 951 951 + /* 4. reset sudo-DMA mode */ 952 952 + ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr); 953 953 + /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */ 954 954 + ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE); 955 955 + /* 6. wait until TXQCR_METFE is auto-cleared */ 956 956 + while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE) 957 957 + ; 958 958 + } 959 959 + 960 960 + static void ks_disable_int(struct ks_net *ks) 961 961 + { 962 962 + ks_wrreg16(ks, KS_IER, 0x0000); 963 963 + } /* ks_disable_int */ 964 964 + 965 965 + static void ks_enable_int(struct ks_net *ks) 966 966 + { 967 967 + ks_wrreg16(ks, KS_IER, ks->rc_ier); 968 968 + } /* ks_enable_int */ 969 969 + 970 970 + /** 971 971 + * ks_start_xmit - transmit packet 972 972 + * @skb : The buffer to transmit 973 973 + * @netdev : The device used to transmit the packet. 974 974 + * 975 975 + * Called by the network layer to transmit the @skb. 976 976 + * spin_lock_irqsave is required because tx and rx should be mutual exclusive. 977 977 + * So while tx is in-progress, prevent IRQ interrupt from happenning. 978 978 + */ 979 979 + static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev) 980 980 + { 981 981 + int retv = NETDEV_TX_OK; 982 982 + struct ks_net *ks = netdev_priv(netdev); 983 983 + 984 984 + disable_irq(netdev->irq); 985 985 + ks_disable_int(ks); 986 986 + spin_lock(&ks->statelock); 987 987 + 988 988 + /* Extra space are required: 989 989 + * 4 byte for alignment, 4 for status/length, 4 for CRC 990 990 + */ 991 991 + 992 992 + if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) { 993 993 + ks_write_qmu(ks, skb->data, skb->len); 994 994 + dev_kfree_skb(skb); 995 995 + } else 996 996 + retv = NETDEV_TX_BUSY; 997 997 + spin_unlock(&ks->statelock); 998 998 + ks_enable_int(ks); 999 999 + enable_irq(netdev->irq); 1000 1000 + return retv; 1001 1001 + } 1002 1002 + 1003 1003 + /** 1004 1004 + * ks_start_rx - ready to serve pkts 1005 1005 + * @ks : The chip information 1006 1006 + * 1007 1007 + */ 1008 1008 + static void ks_start_rx(struct ks_net *ks) 1009 1009 + { 1010 1010 + u16 cntl; 1011 1011 + 1012 1012 + /* Enables QMU Receive (RXCR1). */ 1013 1013 + cntl = ks_rdreg16(ks, KS_RXCR1); 1014 1014 + cntl |= RXCR1_RXE ; 1015 1015 + ks_wrreg16(ks, KS_RXCR1, cntl); 1016 1016 + } /* ks_start_rx */ 1017 1017 + 1018 1018 + /** 1019 1019 + * ks_stop_rx - stop to serve pkts 1020 1020 + * @ks : The chip information 1021 1021 + * 1022 1022 + */ 1023 1023 + static void ks_stop_rx(struct ks_net *ks) 1024 1024 + { 1025 1025 + u16 cntl; 1026 1026 + 1027 1027 + /* Disables QMU Receive (RXCR1). */ 1028 1028 + cntl = ks_rdreg16(ks, KS_RXCR1); 1029 1029 + cntl &= ~RXCR1_RXE ; 1030 1030 + ks_wrreg16(ks, KS_RXCR1, cntl); 1031 1031 + 1032 1032 + } /* ks_stop_rx */ 1033 1033 + 1034 1034 + static unsigned long const ethernet_polynomial = 0x04c11db7U; 1035 1035 + 1036 1036 + static unsigned long ether_gen_crc(int length, u8 *data) 1037 1037 + { 1038 1038 + long crc = -1; 1039 1039 + while (--length >= 0) { 1040 1040 + u8 current_octet = *data++; 1041 1041 + int bit; 1042 1042 + 1043 1043 + for (bit = 0; bit < 8; bit++, current_octet >>= 1) { 1044 1044 + crc = (crc << 1) ^ 1045 1045 + ((crc < 0) ^ (current_octet & 1) ? 1046 1046 + ethernet_polynomial : 0); 1047 1047 + } 1048 1048 + } 1049 1049 + return (unsigned long)crc; 1050 1050 + } /* ether_gen_crc */ 1051 1051 + 1052 1052 + /** 1053 1053 + * ks_set_grpaddr - set multicast information 1054 1054 + * @ks : The chip information 1055 1055 + */ 1056 1056 + 1057 1057 + static void ks_set_grpaddr(struct ks_net *ks) 1058 1058 + { 1059 1059 + u8 i; 1060 1060 + u32 index, position, value; 1061 1061 + 1062 1062 + memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE); 1063 1063 + 1064 1064 + for (i = 0; i < ks->mcast_lst_size; i++) { 1065 1065 + position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f; 1066 1066 + index = position >> 3; 1067 1067 + value = 1 << (position & 7); 1068 1068 + ks->mcast_bits[index] |= (u8)value; 1069 1069 + } 1070 1070 + 1071 1071 + for (i = 0; i < HW_MCAST_SIZE; i++) { 1072 1072 + if (i & 1) { 1073 1073 + ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1), 1074 1074 + (ks->mcast_bits[i] << 8) | 1075 1075 + ks->mcast_bits[i - 1]); 1076 1076 + } 1077 1077 + } 1078 1078 + } /* ks_set_grpaddr */ 1079 1079 + 1080 1080 + /* 1081 1081 + * ks_clear_mcast - clear multicast information 1082 1082 + * 1083 1083 + * @ks : The chip information 1084 1084 + * This routine removes all mcast addresses set in the hardware. 1085 1085 + */ 1086 1086 + 1087 1087 + static void ks_clear_mcast(struct ks_net *ks) 1088 1088 + { 1089 1089 + u16 i, mcast_size; 1090 1090 + for (i = 0; i < HW_MCAST_SIZE; i++) 1091 1091 + ks->mcast_bits[i] = 0; 1092 1092 + 1093 1093 + mcast_size = HW_MCAST_SIZE >> 2; 1094 1094 + for (i = 0; i < mcast_size; i++) 1095 1095 + ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0); 1096 1096 + } 1097 1097 + 1098 1098 + static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode) 1099 1099 + { 1100 1100 + u16 cntl; 1101 1101 + ks->promiscuous = promiscuous_mode; 1102 1102 + ks_stop_rx(ks); /* Stop receiving for reconfiguration */ 1103 1103 + cntl = ks_rdreg16(ks, KS_RXCR1); 1104 1104 + 1105 1105 + cntl &= ~RXCR1_FILTER_MASK; 1106 1106 + if (promiscuous_mode) 1107 1107 + /* Enable Promiscuous mode */ 1108 1108 + cntl |= RXCR1_RXAE | RXCR1_RXINVF; 1109 1109 + else 1110 1110 + /* Disable Promiscuous mode (default normal mode) */ 1111 1111 + cntl |= RXCR1_RXPAFMA; 1112 1112 + 1113 1113 + ks_wrreg16(ks, KS_RXCR1, cntl); 1114 1114 + 1115 1115 + if (ks->enabled) 1116 1116 + ks_start_rx(ks); 1117 1117 + 1118 1118 + } /* ks_set_promis */ 1119 1119 + 1120 1120 + static void ks_set_mcast(struct ks_net *ks, u16 mcast) 1121 1121 + { 1122 1122 + u16 cntl; 1123 1123 + 1124 1124 + ks->all_mcast = mcast; 1125 1125 + ks_stop_rx(ks); /* Stop receiving for reconfiguration */ 1126 1126 + cntl = ks_rdreg16(ks, KS_RXCR1); 1127 1127 + cntl &= ~RXCR1_FILTER_MASK; 1128 1128 + if (mcast) 1129 1129 + /* Enable "Perfect with Multicast address passed mode" */ 1130 1130 + cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA); 1131 1131 + else 1132 1132 + /** 1133 1133 + * Disable "Perfect with Multicast address passed 1134 1134 + * mode" (normal mode). 1135 1135 + */ 1136 1136 + cntl |= RXCR1_RXPAFMA; 1137 1137 + 1138 1138 + ks_wrreg16(ks, KS_RXCR1, cntl); 1139 1139 + 1140 1140 + if (ks->enabled) 1141 1141 + ks_start_rx(ks); 1142 1142 + } /* ks_set_mcast */ 1143 1143 + 1144 1144 + static void ks_set_rx_mode(struct net_device *netdev) 1145 1145 + { 1146 1146 + struct ks_net *ks = netdev_priv(netdev); 1147 1147 + struct dev_mc_list *ptr; 1148 1148 + 1149 1149 + /* Turn on/off promiscuous mode. */ 1150 1150 + if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC) 1151 1151 + ks_set_promis(ks, 1152 1152 + (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC)); 1153 1153 + /* Turn on/off all mcast mode. */ 1154 1154 + else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI) 1155 1155 + ks_set_mcast(ks, 1156 1156 + (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)); 1157 1157 + else 1158 1158 + ks_set_promis(ks, false); 1159 1159 + 1160 1160 + if ((netdev->flags & IFF_MULTICAST) && netdev->mc_count) { 1161 1161 + if (netdev->mc_count <= MAX_MCAST_LST) { 1162 1162 + int i = 0; 1163 1163 + for (ptr = netdev->mc_list; ptr; ptr = ptr->next) { 1164 1164 + if (!(*ptr->dmi_addr & 1)) 1165 1165 + continue; 1166 1166 + if (i >= MAX_MCAST_LST) 1167 1167 + break; 1168 1168 + memcpy(ks->mcast_lst[i++], ptr->dmi_addr, 1169 1169 + MAC_ADDR_LEN); 1170 1170 + } 1171 1171 + ks->mcast_lst_size = (u8)i; 1172 1172 + ks_set_grpaddr(ks); 1173 1173 + } else { 1174 1174 + /** 1175 1175 + * List too big to support so 1176 1176 + * turn on all mcast mode. 1177 1177 + */ 1178 1178 + ks->mcast_lst_size = MAX_MCAST_LST; 1179 1179 + ks_set_mcast(ks, true); 1180 1180 + } 1181 1181 + } else { 1182 1182 + ks->mcast_lst_size = 0; 1183 1183 + ks_clear_mcast(ks); 1184 1184 + } 1185 1185 + } /* ks_set_rx_mode */ 1186 1186 + 1187 1187 + static void ks_set_mac(struct ks_net *ks, u8 *data) 1188 1188 + { 1189 1189 + u16 *pw = (u16 *)data; 1190 1190 + u16 w, u; 1191 1191 + 1192 1192 + ks_stop_rx(ks); /* Stop receiving for reconfiguration */ 1193 1193 + 1194 1194 + u = *pw++; 1195 1195 + w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); 1196 1196 + ks_wrreg16(ks, KS_MARH, w); 1197 1197 + 1198 1198 + u = *pw++; 1199 1199 + w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); 1200 1200 + ks_wrreg16(ks, KS_MARM, w); 1201 1201 + 1202 1202 + u = *pw; 1203 1203 + w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); 1204 1204 + ks_wrreg16(ks, KS_MARL, w); 1205 1205 + 1206 1206 + memcpy(ks->mac_addr, data, 6); 1207 1207 + 1208 1208 + if (ks->enabled) 1209 1209 + ks_start_rx(ks); 1210 1210 + } 1211 1211 + 1212 1212 + static int ks_set_mac_address(struct net_device *netdev, void *paddr) 1213 1213 + { 1214 1214 + struct ks_net *ks = netdev_priv(netdev); 1215 1215 + struct sockaddr *addr = paddr; 1216 1216 + u8 *da; 1217 1217 + 1218 1218 + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 1219 1219 + 1220 1220 + da = (u8 *)netdev->dev_addr; 1221 1221 + 1222 1222 + ks_set_mac(ks, da); 1223 1223 + return 0; 1224 1224 + } 1225 1225 + 1226 1226 + static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 1227 1227 + { 1228 1228 + struct ks_net *ks = netdev_priv(netdev); 1229 1229 + 1230 1230 + if (!netif_running(netdev)) 1231 1231 + return -EINVAL; 1232 1232 + 1233 1233 + return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL); 1234 1234 + } 1235 1235 + 1236 1236 + static const struct net_device_ops ks_netdev_ops = { 1237 1237 + .ndo_open = ks_net_open, 1238 1238 + .ndo_stop = ks_net_stop, 1239 1239 + .ndo_do_ioctl = ks_net_ioctl, 1240 1240 + .ndo_start_xmit = ks_start_xmit, 1241 1241 + .ndo_set_mac_address = ks_set_mac_address, 1242 1242 + .ndo_set_rx_mode = ks_set_rx_mode, 1243 1243 + .ndo_change_mtu = eth_change_mtu, 1244 1244 + .ndo_validate_addr = eth_validate_addr, 1245 1245 + }; 1246 1246 + 1247 1247 + /* ethtool support */ 1248 1248 + 1249 1249 + static void ks_get_drvinfo(struct net_device *netdev, 1250 1250 + struct ethtool_drvinfo *di) 1251 1251 + { 1252 1252 + strlcpy(di->driver, DRV_NAME, sizeof(di->driver)); 1253 1253 + strlcpy(di->version, "1.00", sizeof(di->version)); 1254 1254 + strlcpy(di->bus_info, dev_name(netdev->dev.parent), 1255 1255 + sizeof(di->bus_info)); 1256 1256 + } 1257 1257 + 1258 1258 + static u32 ks_get_msglevel(struct net_device *netdev) 1259 1259 + { 1260 1260 + struct ks_net *ks = netdev_priv(netdev); 1261 1261 + return ks->msg_enable; 1262 1262 + } 1263 1263 + 1264 1264 + static void ks_set_msglevel(struct net_device *netdev, u32 to) 1265 1265 + { 1266 1266 + struct ks_net *ks = netdev_priv(netdev); 1267 1267 + ks->msg_enable = to; 1268 1268 + } 1269 1269 + 1270 1270 + static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 1271 1271 + { 1272 1272 + struct ks_net *ks = netdev_priv(netdev); 1273 1273 + return mii_ethtool_gset(&ks->mii, cmd); 1274 1274 + } 1275 1275 + 1276 1276 + static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd) 1277 1277 + { 1278 1278 + struct ks_net *ks = netdev_priv(netdev); 1279 1279 + return mii_ethtool_sset(&ks->mii, cmd); 1280 1280 + } 1281 1281 + 1282 1282 + static u32 ks_get_link(struct net_device *netdev) 1283 1283 + { 1284 1284 + struct ks_net *ks = netdev_priv(netdev); 1285 1285 + return mii_link_ok(&ks->mii); 1286 1286 + } 1287 1287 + 1288 1288 + static int ks_nway_reset(struct net_device *netdev) 1289 1289 + { 1290 1290 + struct ks_net *ks = netdev_priv(netdev); 1291 1291 + return mii_nway_restart(&ks->mii); 1292 1292 + } 1293 1293 + 1294 1294 + static const struct ethtool_ops ks_ethtool_ops = { 1295 1295 + .get_drvinfo = ks_get_drvinfo, 1296 1296 + .get_msglevel = ks_get_msglevel, 1297 1297 + .set_msglevel = ks_set_msglevel, 1298 1298 + .get_settings = ks_get_settings, 1299 1299 + .set_settings = ks_set_settings, 1300 1300 + .get_link = ks_get_link, 1301 1301 + .nway_reset = ks_nway_reset, 1302 1302 + }; 1303 1303 + 1304 1304 + /* MII interface controls */ 1305 1305 + 1306 1306 + /** 1307 1307 + * ks_phy_reg - convert MII register into a KS8851 register 1308 1308 + * @reg: MII register number. 1309 1309 + * 1310 1310 + * Return the KS8851 register number for the corresponding MII PHY register 1311 1311 + * if possible. Return zero if the MII register has no direct mapping to the 1312 1312 + * KS8851 register set. 1313 1313 + */ 1314 1314 + static int ks_phy_reg(int reg) 1315 1315 + { 1316 1316 + switch (reg) { 1317 1317 + case MII_BMCR: 1318 1318 + return KS_P1MBCR; 1319 1319 + case MII_BMSR: 1320 1320 + return KS_P1MBSR; 1321 1321 + case MII_PHYSID1: 1322 1322 + return KS_PHY1ILR; 1323 1323 + case MII_PHYSID2: 1324 1324 + return KS_PHY1IHR; 1325 1325 + case MII_ADVERTISE: 1326 1326 + return KS_P1ANAR; 1327 1327 + case MII_LPA: 1328 1328 + return KS_P1ANLPR; 1329 1329 + } 1330 1330 + 1331 1331 + return 0x0; 1332 1332 + } 1333 1333 + 1334 1334 + /** 1335 1335 + * ks_phy_read - MII interface PHY register read. 1336 1336 + * @netdev: The network device the PHY is on. 1337 1337 + * @phy_addr: Address of PHY (ignored as we only have one) 1338 1338 + * @reg: The register to read. 1339 1339 + * 1340 1340 + * This call reads data from the PHY register specified in @reg. Since the 1341 1341 + * device does not support all the MII registers, the non-existant values 1342 1342 + * are always returned as zero. 1343 1343 + * 1344 1344 + * We return zero for unsupported registers as the MII code does not check 1345 1345 + * the value returned for any error status, and simply returns it to the 1346 1346 + * caller. The mii-tool that the driver was tested with takes any -ve error 1347 1347 + * as real PHY capabilities, thus displaying incorrect data to the user. 1348 1348 + */ 1349 1349 + static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg) 1350 1350 + { 1351 1351 + struct ks_net *ks = netdev_priv(netdev); 1352 1352 + int ksreg; 1353 1353 + int result; 1354 1354 + 1355 1355 + ksreg = ks_phy_reg(reg); 1356 1356 + if (!ksreg) 1357 1357 + return 0x0; /* no error return allowed, so use zero */ 1358 1358 + 1359 1359 + mutex_lock(&ks->lock); 1360 1360 + result = ks_rdreg16(ks, ksreg); 1361 1361 + mutex_unlock(&ks->lock); 1362 1362 + 1363 1363 + return result; 1364 1364 + } 1365 1365 + 1366 1366 + static void ks_phy_write(struct net_device *netdev, 1367 1367 + int phy, int reg, int value) 1368 1368 + { 1369 1369 + struct ks_net *ks = netdev_priv(netdev); 1370 1370 + int ksreg; 1371 1371 + 1372 1372 + ksreg = ks_phy_reg(reg); 1373 1373 + if (ksreg) { 1374 1374 + mutex_lock(&ks->lock); 1375 1375 + ks_wrreg16(ks, ksreg, value); 1376 1376 + mutex_unlock(&ks->lock); 1377 1377 + } 1378 1378 + } 1379 1379 + 1380 1380 + /** 1381 1381 + * ks_read_selftest - read the selftest memory info. 1382 1382 + * @ks: The device state 1383 1383 + * 1384 1384 + * Read and check the TX/RX memory selftest information. 1385 1385 + */ 1386 1386 + static int ks_read_selftest(struct ks_net *ks) 1387 1387 + { 1388 1388 + unsigned both_done = MBIR_TXMBF | MBIR_RXMBF; 1389 1389 + int ret = 0; 1390 1390 + unsigned rd; 1391 1391 + 1392 1392 + rd = ks_rdreg16(ks, KS_MBIR); 1393 1393 + 1394 1394 + if ((rd & both_done) != both_done) { 1395 1395 + ks_warn(ks, "Memory selftest not finished\n"); 1396 1396 + return 0; 1397 1397 + } 1398 1398 + 1399 1399 + if (rd & MBIR_TXMBFA) { 1400 1400 + ks_err(ks, "TX memory selftest fails\n"); 1401 1401 + ret |= 1; 1402 1402 + } 1403 1403 + 1404 1404 + if (rd & MBIR_RXMBFA) { 1405 1405 + ks_err(ks, "RX memory selftest fails\n"); 1406 1406 + ret |= 2; 1407 1407 + } 1408 1408 + 1409 1409 + ks_info(ks, "the selftest passes\n"); 1410 1410 + return ret; 1411 1411 + } 1412 1412 + 1413 1413 + static void ks_disable(struct ks_net *ks) 1414 1414 + { 1415 1415 + u16 w; 1416 1416 + 1417 1417 + w = ks_rdreg16(ks, KS_TXCR); 1418 1418 + 1419 1419 + /* Disables QMU Transmit (TXCR). */ 1420 1420 + w &= ~TXCR_TXE; 1421 1421 + ks_wrreg16(ks, KS_TXCR, w); 1422 1422 + 1423 1423 + /* Disables QMU Receive (RXCR1). */ 1424 1424 + w = ks_rdreg16(ks, KS_RXCR1); 1425 1425 + w &= ~RXCR1_RXE ; 1426 1426 + ks_wrreg16(ks, KS_RXCR1, w); 1427 1427 + 1428 1428 + ks->enabled = false; 1429 1429 + 1430 1430 + } /* ks_disable */ 1431 1431 + 1432 1432 + static void ks_setup(struct ks_net *ks) 1433 1433 + { 1434 1434 + u16 w; 1435 1435 + 1436 1436 + /** 1437 1437 + * Configure QMU Transmit 1438 1438 + */ 1439 1439 + 1440 1440 + /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */ 1441 1441 + ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI); 1442 1442 + 1443 1443 + /* Setup Receive Frame Data Pointer Auto-Increment */ 1444 1444 + ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI); 1445 1445 + 1446 1446 + /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */ 1447 1447 + ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK); 1448 1448 + 1449 1449 + /* Setup RxQ Command Control (RXQCR) */ 1450 1450 + ks->rc_rxqcr = RXQCR_CMD_CNTL; 1451 1451 + ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr); 1452 1452 + 1453 1453 + /** 1454 1454 + * set the force mode to half duplex, default is full duplex 1455 1455 + * because if the auto-negotiation fails, most switch uses 1456 1456 + * half-duplex. 1457 1457 + */ 1458 1458 + 1459 1459 + w = ks_rdreg16(ks, KS_P1MBCR); 1460 1460 + w &= ~P1MBCR_FORCE_FDX; 1461 1461 + ks_wrreg16(ks, KS_P1MBCR, w); 1462 1462 + 1463 1463 + w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP; 1464 1464 + ks_wrreg16(ks, KS_TXCR, w); 1465 1465 + 1466 1466 + w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE; 1467 1467 + 1468 1468 + if (ks->promiscuous) /* bPromiscuous */ 1469 1469 + w |= (RXCR1_RXAE | RXCR1_RXINVF); 1470 1470 + else if (ks->all_mcast) /* Multicast address passed mode */ 1471 1471 + w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA); 1472 1472 + else /* Normal mode */ 1473 1473 + w |= RXCR1_RXPAFMA; 1474 1474 + 1475 1475 + ks_wrreg16(ks, KS_RXCR1, w); 1476 1476 + } /*ks_setup */ 1477 1477 + 1478 1478 + 1479 1479 + static void ks_setup_int(struct ks_net *ks) 1480 1480 + { 1481 1481 + ks->rc_ier = 0x00; 1482 1482 + /* Clear the interrupts status of the hardware. */ 1483 1483 + ks_wrreg16(ks, KS_ISR, 0xffff); 1484 1484 + 1485 1485 + /* Enables the interrupts of the hardware. */ 1486 1486 + ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI); 1487 1487 + } /* ks_setup_int */ 1488 1488 + 1489 1489 + void ks_enable(struct ks_net *ks) 1490 1490 + { 1491 1491 + u16 w; 1492 1492 + 1493 1493 + w = ks_rdreg16(ks, KS_TXCR); 1494 1494 + /* Enables QMU Transmit (TXCR). */ 1495 1495 + ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE); 1496 1496 + 1497 1497 + /* 1498 1498 + * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame 1499 1499 + * Enable 1500 1500 + */ 1501 1501 + 1502 1502 + w = ks_rdreg16(ks, KS_RXQCR); 1503 1503 + ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE); 1504 1504 + 1505 1505 + /* Enables QMU Receive (RXCR1). */ 1506 1506 + w = ks_rdreg16(ks, KS_RXCR1); 1507 1507 + ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE); 1508 1508 + ks->enabled = true; 1509 1509 + } /* ks_enable */ 1510 1510 + 1511 1511 + static int ks_hw_init(struct ks_net *ks) 1512 1512 + { 1513 1513 + #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES) 1514 1514 + ks->promiscuous = 0; 1515 1515 + ks->all_mcast = 0; 1516 1516 + ks->mcast_lst_size = 0; 1517 1517 + 1518 1518 + ks->frame_head_info = (struct type_frame_head *) \ 1519 1519 + kmalloc(MHEADER_SIZE, GFP_KERNEL); 1520 1520 + if (!ks->frame_head_info) { 1521 1521 + printk(KERN_ERR "Error: Fail to allocate frame memory\n"); 1522 1522 + return false; 1523 1523 + } 1524 1524 + 1525 1525 + ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS); 1526 1526 + return true; 1527 1527 + } 1528 1528 + 1529 1529 + 1530 1530 + static int __devinit ks8851_probe(struct platform_device *pdev) 1531 1531 + { 1532 1532 + int err = -ENOMEM; 1533 1533 + struct resource *io_d, *io_c; 1534 1534 + struct net_device *netdev; 1535 1535 + struct ks_net *ks; 1536 1536 + u16 id, data; 1537 1537 + 1538 1538 + io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1539 1539 + io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1540 1540 + 1541 1541 + if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME)) 1542 1542 + goto err_mem_region; 1543 1543 + 1544 1544 + if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME)) 1545 1545 + goto err_mem_region1; 1546 1546 + 1547 1547 + netdev = alloc_etherdev(sizeof(struct ks_net)); 1548 1548 + if (!netdev) 1549 1549 + goto err_alloc_etherdev; 1550 1550 + 1551 1551 + SET_NETDEV_DEV(netdev, &pdev->dev); 1552 1552 + 1553 1553 + ks = netdev_priv(netdev); 1554 1554 + ks->netdev = netdev; 1555 1555 + ks->hw_addr = ioremap(io_d->start, resource_size(io_d)); 1556 1556 + 1557 1557 + if (!ks->hw_addr) 1558 1558 + goto err_ioremap; 1559 1559 + 1560 1560 + ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c)); 1561 1561 + if (!ks->hw_addr_cmd) 1562 1562 + goto err_ioremap1; 1563 1563 + 1564 1564 + ks->irq = platform_get_irq(pdev, 0); 1565 1565 + 1566 1566 + if (ks->irq < 0) { 1567 1567 + err = ks->irq; 1568 1568 + goto err_get_irq; 1569 1569 + } 1570 1570 + 1571 1571 + ks->pdev = pdev; 1572 1572 + 1573 1573 + mutex_init(&ks->lock); 1574 1574 + spin_lock_init(&ks->statelock); 1575 1575 + 1576 1576 + netdev->netdev_ops = &ks_netdev_ops; 1577 1577 + netdev->ethtool_ops = &ks_ethtool_ops; 1578 1578 + 1579 1579 + /* setup mii state */ 1580 1580 + ks->mii.dev = netdev; 1581 1581 + ks->mii.phy_id = 1, 1582 1582 + ks->mii.phy_id_mask = 1; 1583 1583 + ks->mii.reg_num_mask = 0xf; 1584 1584 + ks->mii.mdio_read = ks_phy_read; 1585 1585 + ks->mii.mdio_write = ks_phy_write; 1586 1586 + 1587 1587 + ks_info(ks, "message enable is %d\n", msg_enable); 1588 1588 + /* set the default message enable */ 1589 1589 + ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV | 1590 1590 + NETIF_MSG_PROBE | 1591 1591 + NETIF_MSG_LINK)); 1592 1592 + ks_read_config(ks); 1593 1593 + 1594 1594 + /* simple check for a valid chip being connected to the bus */ 1595 1595 + if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) { 1596 1596 + ks_err(ks, "failed to read device ID\n"); 1597 1597 + err = -ENODEV; 1598 1598 + goto err_register; 1599 1599 + } 1600 1600 + 1601 1601 + if (ks_read_selftest(ks)) { 1602 1602 + ks_err(ks, "failed to read device ID\n"); 1603 1603 + err = -ENODEV; 1604 1604 + goto err_register; 1605 1605 + } 1606 1606 + 1607 1607 + err = register_netdev(netdev); 1608 1608 + if (err) 1609 1609 + goto err_register; 1610 1610 + 1611 1611 + platform_set_drvdata(pdev, netdev); 1612 1612 + 1613 1613 + ks_soft_reset(ks, GRR_GSR); 1614 1614 + ks_hw_init(ks); 1615 1615 + ks_disable(ks); 1616 1616 + ks_setup(ks); 1617 1617 + ks_setup_int(ks); 1618 1618 + ks_enable_int(ks); 1619 1619 + ks_enable(ks); 1620 1620 + memcpy(netdev->dev_addr, ks->mac_addr, 6); 1621 1621 + 1622 1622 + data = ks_rdreg16(ks, KS_OBCR); 1623 1623 + ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA); 1624 1624 + 1625 1625 + /** 1626 1626 + * If you want to use the default MAC addr, 1627 1627 + * comment out the 2 functions below. 1628 1628 + */ 1629 1629 + 1630 1630 + random_ether_addr(netdev->dev_addr); 1631 1631 + ks_set_mac(ks, netdev->dev_addr); 1632 1632 + 1633 1633 + id = ks_rdreg16(ks, KS_CIDER); 1634 1634 + 1635 1635 + printk(KERN_INFO DRV_NAME 1636 1636 + " Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n", 1637 1637 + (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7); 1638 1638 + return 0; 1639 1639 + 1640 1640 + err_register: 1641 1641 + err_get_irq: 1642 1642 + iounmap(ks->hw_addr_cmd); 1643 1643 + err_ioremap1: 1644 1644 + iounmap(ks->hw_addr); 1645 1645 + err_ioremap: 1646 1646 + free_netdev(netdev); 1647 1647 + err_alloc_etherdev: 1648 1648 + release_mem_region(io_c->start, resource_size(io_c)); 1649 1649 + err_mem_region1: 1650 1650 + release_mem_region(io_d->start, resource_size(io_d)); 1651 1651 + err_mem_region: 1652 1652 + return err; 1653 1653 + } 1654 1654 + 1655 1655 + static int __devexit ks8851_remove(struct platform_device *pdev) 1656 1656 + { 1657 1657 + struct net_device *netdev = platform_get_drvdata(pdev); 1658 1658 + struct ks_net *ks = netdev_priv(netdev); 1659 1659 + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1660 1660 + 1661 1661 + unregister_netdev(netdev); 1662 1662 + iounmap(ks->hw_addr); 1663 1663 + free_netdev(netdev); 1664 1664 + release_mem_region(iomem->start, resource_size(iomem)); 1665 1665 + platform_set_drvdata(pdev, NULL); 1666 1666 + return 0; 1667 1667 + 1668 1668 + } 1669 1669 + 1670 1670 + static struct platform_driver ks8851_platform_driver = { 1671 1671 + .driver = { 1672 1672 + .name = DRV_NAME, 1673 1673 + .owner = THIS_MODULE, 1674 1674 + }, 1675 1675 + .probe = ks8851_probe, 1676 1676 + .remove = __devexit_p(ks8851_remove), 1677 1677 + }; 1678 1678 + 1679 1679 + static int __init ks8851_init(void) 1680 1680 + { 1681 1681 + return platform_driver_register(&ks8851_platform_driver); 1682 1682 + } 1683 1683 + 1684 1684 + static void __exit ks8851_exit(void) 1685 1685 + { 1686 1686 + platform_driver_unregister(&ks8851_platform_driver); 1687 1687 + } 1688 1688 + 1689 1689 + module_init(ks8851_init); 1690 1690 + module_exit(ks8851_exit); 1691 1691 + 1692 1692 + MODULE_DESCRIPTION("KS8851 MLL Network driver"); 1693 1693 + MODULE_AUTHOR("David Choi <david.choi@micrel.com>"); 1694 1694 + MODULE_LICENSE("GPL"); 1695 1695 + module_param_named(message, msg_enable, int, 0); 1696 1696 + MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)"); 1697 1697 +

+1 -1

drivers/net/meth.c

reviewed

··· 828 828 829 829 static struct platform_driver meth_driver = { 830 830 .probe = meth_probe, 831 831 - .remove = __devexit_p(meth_remove), 831 831 + .remove = __exit_p(meth_remove), 832 832 .driver = { 833 833 .name = "meth", 834 834 .owner = THIS_MODULE,

+9 -9

drivers/net/qlge/qlge.h

reviewed

··· 1381 1381 1382 1382 /* adapter flags definitions. */ 1383 1383 enum { 1384 1384 - QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */ 1385 1385 - QL_LEGACY_ENABLED = (1 << 3), 1386 1386 - QL_MSI_ENABLED = (1 << 3), 1387 1387 - QL_MSIX_ENABLED = (1 << 4), 1388 1388 - QL_DMA64 = (1 << 5), 1389 1389 - QL_PROMISCUOUS = (1 << 6), 1390 1390 - QL_ALLMULTI = (1 << 7), 1391 1391 - QL_PORT_CFG = (1 << 8), 1392 1392 - QL_CAM_RT_SET = (1 << 9), 1384 1384 + QL_ADAPTER_UP = 0, /* Adapter has been brought up. */ 1385 1385 + QL_LEGACY_ENABLED = 1, 1386 1386 + QL_MSI_ENABLED = 2, 1387 1387 + QL_MSIX_ENABLED = 3, 1388 1388 + QL_DMA64 = 4, 1389 1389 + QL_PROMISCUOUS = 5, 1390 1390 + QL_ALLMULTI = 6, 1391 1391 + QL_PORT_CFG = 7, 1392 1392 + QL_CAM_RT_SET = 8, 1393 1393 }; 1394 1394 1395 1395 /* link_status bit definitions */

+13 -15

drivers/net/qlge/qlge_main.c

reviewed

··· 3142 3142 { 3143 3143 int status = 0; 3144 3144 3145 3145 - status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); 3146 3146 - if (status) 3147 3147 - return status; 3148 3148 - 3149 3145 /* Clear all the entries in the routing table. */ 3150 3146 status = ql_clear_routing_entries(qdev); 3151 3147 if (status) 3152 3152 - goto exit; 3148 3148 + return status; 3149 3149 + 3150 3150 + status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); 3151 3151 + if (status) 3152 3152 + return status; 3153 3153 3154 3154 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1); 3155 3155 if (status) { ··· 3380 3380 3381 3381 ql_free_rx_buffers(qdev); 3382 3382 3383 3383 - spin_lock(&qdev->hw_lock); 3384 3383 status = ql_adapter_reset(qdev); 3385 3384 if (status) 3386 3385 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n", 3387 3386 qdev->func); 3388 3388 - spin_unlock(&qdev->hw_lock); 3389 3387 return status; 3390 3388 } 3391 3389 ··· 3703 3705 struct ql_adapter *qdev = 3704 3706 container_of(work, struct ql_adapter, asic_reset_work.work); 3705 3707 int status; 3706 3706 - 3708 3708 + rtnl_lock(); 3707 3709 status = ql_adapter_down(qdev); 3708 3710 if (status) 3709 3711 goto error; ··· 3711 3713 status = ql_adapter_up(qdev); 3712 3714 if (status) 3713 3715 goto error; 3714 3714 - 3716 3716 + rtnl_unlock(); 3715 3717 return; 3716 3718 error: 3717 3719 QPRINTK(qdev, IFUP, ALERT, 3718 3720 "Driver up/down cycle failed, closing device\n"); 3719 3719 - rtnl_lock(); 3721 3721 + 3720 3722 set_bit(QL_ADAPTER_UP, &qdev->flags); 3721 3723 dev_close(qdev->ndev); 3722 3724 rtnl_unlock(); ··· 3832 3834 return err; 3833 3835 } 3834 3836 3837 3837 + qdev->ndev = ndev; 3838 3838 + qdev->pdev = pdev; 3839 3839 + pci_set_drvdata(pdev, ndev); 3835 3840 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 3836 3841 if (pos <= 0) { 3837 3842 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " 3838 3843 "aborting.\n"); 3839 3839 - goto err_out; 3844 3844 + return pos; 3840 3845 } else { 3841 3846 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); 3842 3847 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; ··· 3852 3851 err = pci_request_regions(pdev, DRV_NAME); 3853 3852 if (err) { 3854 3853 dev_err(&pdev->dev, "PCI region request failed.\n"); 3855 3855 - goto err_out; 3854 3854 + return err; 3856 3855 } 3857 3856 3858 3857 pci_set_master(pdev); ··· 3870 3869 goto err_out; 3871 3870 } 3872 3871 3873 3873 - pci_set_drvdata(pdev, ndev); 3874 3872 qdev->reg_base = 3875 3873 ioremap_nocache(pci_resource_start(pdev, 1), 3876 3874 pci_resource_len(pdev, 1)); ··· 3889 3889 goto err_out; 3890 3890 } 3891 3891 3892 3892 - qdev->ndev = ndev; 3893 3893 - qdev->pdev = pdev; 3894 3892 err = ql_get_board_info(qdev); 3895 3893 if (err) { 3896 3894 dev_err(&pdev->dev, "Register access failed.\n");

+1 -1

drivers/net/sgiseeq.c

reviewed

··· 826 826 827 827 static struct platform_driver sgiseeq_driver = { 828 828 .probe = sgiseeq_probe, 829 829 - .remove = __devexit_p(sgiseeq_remove), 829 829 + .remove = __exit_p(sgiseeq_remove), 830 830 .driver = { 831 831 .name = "sgiseeq", 832 832 .owner = THIS_MODULE,

+11 -5

drivers/net/skge.c

reviewed

··· 3935 3935 #endif 3936 3936 3937 3937 err = -ENOMEM; 3938 3938 - hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3938 3938 + /* space for skge@pci:0000:04:00.0 */ 3939 3939 + hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" ) 3940 3940 + + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 3939 3941 if (!hw) { 3940 3942 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 3941 3943 goto err_out_free_regions; 3942 3944 } 3945 3945 + sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 3943 3946 3944 3947 hw->pdev = pdev; 3945 3948 spin_lock_init(&hw->hw_lock); ··· 3977 3974 goto err_out_free_netdev; 3978 3975 } 3979 3976 3980 3980 - err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw); 3977 3977 + err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw); 3981 3978 if (err) { 3982 3979 dev_err(&pdev->dev, "%s: cannot assign irq %d\n", 3983 3980 dev->name, pdev->irq); ··· 3985 3982 } 3986 3983 skge_show_addr(dev); 3987 3984 3988 3988 - if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { 3989 3989 - if (register_netdev(dev1) == 0) 3985 3985 + if (hw->ports > 1) { 3986 3986 + dev1 = skge_devinit(hw, 1, using_dac); 3987 3987 + if (dev1 && register_netdev(dev1) == 0) 3990 3988 skge_show_addr(dev1); 3991 3989 else { 3992 3990 /* Failure to register second port need not be fatal */ 3993 3991 dev_warn(&pdev->dev, "register of second port failed\n"); 3994 3992 hw->dev[1] = NULL; 3995 3995 - free_netdev(dev1); 3993 3993 + hw->ports = 1; 3994 3994 + if (dev1) 3995 3995 + free_netdev(dev1); 3996 3996 } 3997 3997 } 3998 3998 pci_set_drvdata(pdev, hw);

+2

drivers/net/skge.h

reviewed

··· 2423 2423 u16 phy_addr; 2424 2424 spinlock_t phy_lock; 2425 2425 struct tasklet_struct phy_task; 2426 2426 + 2427 2427 + char irq_name[0]; /* skge@pci:000:04:00.0 */ 2426 2428 }; 2427 2429 2428 2430 enum pause_control {

+5 -2

drivers/net/sky2.c

reviewed

··· 4487 4487 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4488 4488 4489 4489 err = -ENOMEM; 4490 4490 - hw = kzalloc(sizeof(*hw), GFP_KERNEL); 4490 4490 + 4491 4491 + hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4492 4492 + + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4491 4493 if (!hw) { 4492 4494 dev_err(&pdev->dev, "cannot allocate hardware struct\n"); 4493 4495 goto err_out_free_regions; 4494 4496 } 4495 4497 4496 4498 hw->pdev = pdev; 4499 4499 + sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4497 4500 4498 4501 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4499 4502 if (!hw->regs) { ··· 4542 4539 4543 4540 err = request_irq(pdev->irq, sky2_intr, 4544 4541 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 4545 4545 - dev->name, hw); 4542 4542 + hw->irq_name, hw); 4546 4543 if (err) { 4547 4544 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4548 4545 goto err_out_unregister;

+2

drivers/net/sky2.h

reviewed

··· 2085 2085 struct timer_list watchdog_timer; 2086 2086 struct work_struct restart_work; 2087 2087 wait_queue_head_t msi_wait; 2088 2088 + 2089 2089 + char irq_name[0]; 2088 2090 }; 2089 2091 2090 2092 static inline int sky2_is_copper(const struct sky2_hw *hw)

-1

drivers/net/tg3.h

reviewed

··· 2412 2412 2413 2413 struct tx_ring_info { 2414 2414 struct sk_buff *skb; 2415 2415 - u32 prev_vlan_tag; 2416 2415 }; 2417 2416 2418 2417 struct tg3_config_info {

+1 -1

drivers/net/virtio_net.c

reviewed

··· 948 948 return err; 949 949 } 950 950 951 951 - static void virtnet_remove(struct virtio_device *vdev) 951 951 + static void __devexit virtnet_remove(struct virtio_device *vdev) 952 952 { 953 953 struct virtnet_info *vi = vdev->priv; 954 954 struct sk_buff *skb;

+6 -7

drivers/net/wireless/Kconfig

reviewed

··· 31 31 ---help--- 32 32 Say Y if you have a Metricom radio and intend to use Starmode Radio 33 33 IP. STRIP is a radio protocol developed for the MosquitoNet project 34 34 - (on the WWW at <http://mosquitonet.stanford.edu/>) to send Internet 35 35 - traffic using Metricom radios. Metricom radios are small, battery 36 36 - powered, 100kbit/sec packet radio transceivers, about the size and 37 37 - weight of a cellular telephone. (You may also have heard them called 38 38 - "Metricom modems" but we avoid the term "modem" because it misleads 39 39 - many people into thinking that you can plug a Metricom modem into a 40 40 - phone line and use it as a modem.) 34 34 + to send Internet traffic using Metricom radios. Metricom radios are 35 35 + small, battery powered, 100kbit/sec packet radio transceivers, about 36 36 + the size and weight of a cellular telephone. (You may also have heard 37 37 + them called "Metricom modems" but we avoid the term "modem" because 38 38 + it misleads many people into thinking that you can plug a Metricom 39 39 + modem into a phone line and use it as a modem.) 41 40 42 41 You can use STRIP on any Linux machine with a serial port, although 43 42 it is obviously most useful for people with laptop computers. If you

+2 -4

drivers/net/wireless/ath/ar9170/phy.c

reviewed

··· 1141 1141 u8 vpds[2][AR5416_PD_GAIN_ICEPTS]; 1142 1142 u8 pwrs[2][AR5416_PD_GAIN_ICEPTS]; 1143 1143 int chain, idx, i; 1144 1144 - u8 f; 1144 1144 + u32 phy_data = 0; 1145 1145 + u8 f, tmp; 1145 1146 1146 1147 switch (channel->band) { 1147 1148 case IEEE80211_BAND_2GHZ: ··· 1209 1208 } 1210 1209 1211 1210 for (i = 0; i < 76; i++) { 1212 1212 - u32 phy_data; 1213 1213 - u8 tmp; 1214 1214 - 1215 1211 if (i < 25) { 1216 1212 tmp = ar9170_interpolate_val(i, &pwrs[0][0], 1217 1213 &vpds[0][0]);

+38 -22

drivers/net/wireless/b43/pio.c

reviewed

··· 340 340 q->mmio_base + B43_PIO_TXDATA, 341 341 sizeof(u16)); 342 342 if (data_len & 1) { 343 343 + u8 tail[2] = { 0, }; 344 344 + 343 345 /* Write the last byte. */ 344 346 ctl &= ~B43_PIO_TXCTL_WRITEHI; 345 347 b43_piotx_write16(q, B43_PIO_TXCTL, ctl); 346 346 - b43_piotx_write16(q, B43_PIO_TXDATA, data[data_len - 1]); 348 348 + tail[0] = data[data_len - 1]; 349 349 + ssb_block_write(dev->dev, tail, 2, 350 350 + q->mmio_base + B43_PIO_TXDATA, 351 351 + sizeof(u16)); 347 352 } 348 353 349 354 return ctl; ··· 391 386 q->mmio_base + B43_PIO8_TXDATA, 392 387 sizeof(u32)); 393 388 if (data_len & 3) { 394 394 - u32 value = 0; 389 389 + u8 tail[4] = { 0, }; 395 390 396 391 /* Write the last few bytes. */ 397 392 ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 | 398 393 B43_PIO8_TXCTL_24_31); 399 399 - data = &(data[data_len - 1]); 400 394 switch (data_len & 3) { 401 395 case 3: 402 402 - ctl |= B43_PIO8_TXCTL_16_23; 403 403 - value |= (u32)(*data) << 16; 404 404 - data--; 396 396 + ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15; 397 397 + tail[0] = data[data_len - 3]; 398 398 + tail[1] = data[data_len - 2]; 399 399 + tail[2] = data[data_len - 1]; 400 400 + break; 405 401 case 2: 406 402 ctl |= B43_PIO8_TXCTL_8_15; 407 407 - value |= (u32)(*data) << 8; 408 408 - data--; 403 403 + tail[0] = data[data_len - 2]; 404 404 + tail[1] = data[data_len - 1]; 405 405 + break; 409 406 case 1: 410 410 - value |= (u32)(*data); 407 407 + tail[0] = data[data_len - 1]; 408 408 + break; 411 409 } 412 410 b43_piotx_write32(q, B43_PIO8_TXCTL, ctl); 413 413 - b43_piotx_write32(q, B43_PIO8_TXDATA, value); 411 411 + ssb_block_write(dev->dev, tail, 4, 412 412 + q->mmio_base + B43_PIO8_TXDATA, 413 413 + sizeof(u32)); 414 414 } 415 415 416 416 return ctl; ··· 703 693 q->mmio_base + B43_PIO8_RXDATA, 704 694 sizeof(u32)); 705 695 if (len & 3) { 706 706 - u32 value; 707 707 - char *data; 696 696 + u8 tail[4] = { 0, }; 708 697 709 698 /* Read the last few bytes. */ 710 710 - value = b43_piorx_read32(q, B43_PIO8_RXDATA); 711 711 - data = &(skb->data[len + padding - 1]); 699 699 + ssb_block_read(dev->dev, tail, 4, 700 700 + q->mmio_base + B43_PIO8_RXDATA, 701 701 + sizeof(u32)); 712 702 switch (len & 3) { 713 703 case 3: 714 714 - *data = (value >> 16); 715 715 - data--; 704 704 + skb->data[len + padding - 3] = tail[0]; 705 705 + skb->data[len + padding - 2] = tail[1]; 706 706 + skb->data[len + padding - 1] = tail[2]; 707 707 + break; 716 708 case 2: 717 717 - *data = (value >> 8); 718 718 - data--; 709 709 + skb->data[len + padding - 2] = tail[0]; 710 710 + skb->data[len + padding - 1] = tail[1]; 711 711 + break; 719 712 case 1: 720 720 - *data = value; 713 713 + skb->data[len + padding - 1] = tail[0]; 714 714 + break; 721 715 } 722 716 } 723 717 } else { ··· 729 715 q->mmio_base + B43_PIO_RXDATA, 730 716 sizeof(u16)); 731 717 if (len & 1) { 732 732 - u16 value; 718 718 + u8 tail[2] = { 0, }; 733 719 734 720 /* Read the last byte. */ 735 735 - value = b43_piorx_read16(q, B43_PIO_RXDATA); 736 736 - skb->data[len + padding - 1] = value; 721 721 + ssb_block_read(dev->dev, tail, 2, 722 722 + q->mmio_base + B43_PIO_RXDATA, 723 723 + sizeof(u16)); 724 724 + skb->data[len + padding - 1] = tail[0]; 737 725 } 738 726 } 739 727

+3

drivers/net/wireless/mac80211_hwsim.c

reviewed

··· 631 631 data->beacon_int = 1024 * info->beacon_int / 1000 * HZ / 1000; 632 632 if (WARN_ON(!data->beacon_int)) 633 633 data->beacon_int = 1; 634 634 + if (data->started) 635 635 + mod_timer(&data->beacon_timer, 636 636 + jiffies + data->beacon_int); 634 637 } 635 638 636 639 if (changed & BSS_CHANGED_ERP_CTS_PROT) {

+1

drivers/net/wireless/rt2x00/rt73usb.c

reviewed

··· 2381 2381 /* Huawei-3Com */ 2382 2382 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, 2383 2383 /* Hercules */ 2384 2384 + { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) }, 2384 2385 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, 2385 2386 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, 2386 2387 /* Linksys */

+6 -1

drivers/staging/dst/dcore.c

reviewed

··· 847 847 /* 848 848 * Configuration parser. 849 849 */ 850 850 - static void cn_dst_callback(struct cn_msg *msg) 850 850 + static void cn_dst_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 851 851 { 852 852 struct dst_ctl *ctl; 853 853 int err; 854 854 struct dst_ctl_ack ack; 855 855 struct dst_node *n = NULL, *tmp; 856 856 unsigned int hash; 857 857 + 858 858 + if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) { 859 859 + err = -EPERM; 860 860 + goto out; 861 861 + } 857 862 858 863 if (msg->len < sizeof(struct dst_ctl)) { 859 864 err = -EBADMSG;

+4 -1

drivers/staging/pohmelfs/config.c

reviewed

··· 527 527 return err; 528 528 } 529 529 530 530 - static void pohmelfs_cn_callback(struct cn_msg *msg) 530 530 + static void pohmelfs_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 531 531 { 532 532 int err; 533 533 + 534 534 + if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) 535 535 + return; 533 536 534 537 switch (msg->flags) { 535 538 case POHMELFS_FLAGS_ADD:

+4 -1

drivers/video/uvesafb.c

reviewed

··· 67 67 * find the kernel part of the task struct, copy the registers and 68 68 * the buffer contents and then complete the task. 69 69 */ 70 70 - static void uvesafb_cn_callback(struct cn_msg *msg) 70 70 + static void uvesafb_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 71 71 { 72 72 struct uvesafb_task *utask; 73 73 struct uvesafb_ktask *task; 74 74 + 75 75 + if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) 76 76 + return; 74 77 75 78 if (msg->seq >= UVESAFB_TASKS_MAX) 76 79 return;

+1 -1

drivers/w1/w1_netlink.c

reviewed

··· 306 306 return error; 307 307 } 308 308 309 309 - static void w1_cn_callback(struct cn_msg *msg) 309 309 + static void w1_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) 310 310 { 311 311 struct w1_netlink_msg *m = (struct w1_netlink_msg *)(msg + 1); 312 312 struct w1_netlink_cmd *cmd;

+4 -7

include/linux/connector.h

reviewed

··· 132 132 }; 133 133 134 134 struct cn_callback_data { 135 135 - void (*destruct_data) (void *); 136 136 - void *ddata; 137 137 - 138 138 - void *callback_priv; 139 139 - void (*callback) (struct cn_msg *); 135 135 + struct sk_buff *skb; 136 136 + void (*callback) (struct cn_msg *, struct netlink_skb_parms *); 140 137 141 138 void *free; 142 139 }; ··· 164 167 struct cn_queue_dev *cbdev; 165 168 }; 166 169 167 167 - int cn_add_callback(struct cb_id *, char *, void (*callback) (struct cn_msg *)); 170 170 + int cn_add_callback(struct cb_id *, char *, void (*callback) (struct cn_msg *, struct netlink_skb_parms *)); 168 171 void cn_del_callback(struct cb_id *); 169 172 int cn_netlink_send(struct cn_msg *, u32, gfp_t); 170 173 171 171 - int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, void (*callback)(struct cn_msg *)); 174 174 + int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, void (*callback)(struct cn_msg *, struct netlink_skb_parms *)); 172 175 void cn_queue_del_callback(struct cn_queue_dev *dev, struct cb_id *id); 173 176 174 177 int queue_cn_work(struct cn_callback_entry *cbq, struct work_struct *work);

+4 -2

net/core/pktgen.c

reviewed

··· 2105 2105 static void spin(struct pktgen_dev *pkt_dev, ktime_t spin_until) 2106 2106 { 2107 2107 ktime_t start_time, end_time; 2108 2108 - s32 remaining; 2108 2108 + s64 remaining; 2109 2109 struct hrtimer_sleeper t; 2110 2110 2111 2111 hrtimer_init_on_stack(&t.timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 2112 2112 hrtimer_set_expires(&t.timer, spin_until); 2113 2113 2114 2114 remaining = ktime_to_us(hrtimer_expires_remaining(&t.timer)); 2115 2115 - if (remaining <= 0) 2115 2115 + if (remaining <= 0) { 2116 2116 + pkt_dev->next_tx = ktime_add_ns(spin_until, pkt_dev->delay); 2116 2117 return; 2118 2118 + } 2117 2119 2118 2120 start_time = ktime_now(); 2119 2121 if (remaining < 100)

+1

net/ipv4/af_inet.c

reviewed

··· 1119 1119 { 1120 1120 struct flowi fl = { 1121 1121 .oif = sk->sk_bound_dev_if, 1122 1122 + .mark = sk->sk_mark, 1122 1123 .nl_u = { 1123 1124 .ip4_u = { 1124 1125 .daddr = daddr,

+1

net/ipv4/ip_output.c

reviewed

··· 335 335 336 336 { 337 337 struct flowi fl = { .oif = sk->sk_bound_dev_if, 338 338 + .mark = sk->sk_mark, 338 339 .nl_u = { .ip4_u = 339 340 { .daddr = daddr, 340 341 .saddr = inet->saddr,

+2 -2

net/ipv4/tcp.c

reviewed

··· 580 580 581 581 lock_sock(sk); 582 582 583 583 - timeo = sock_rcvtimeo(sk, flags & SPLICE_F_NONBLOCK); 583 583 + timeo = sock_rcvtimeo(sk, sock->file->f_flags & O_NONBLOCK); 584 584 while (tss.len) { 585 585 ret = __tcp_splice_read(sk, &tss); 586 586 if (ret < 0) ··· 2047 2047 return -EINVAL; 2048 2048 2049 2049 val = strncpy_from_user(name, optval, 2050 2050 - min(TCP_CA_NAME_MAX-1, optlen)); 2050 2050 + min_t(long, TCP_CA_NAME_MAX-1, optlen)); 2051 2051 if (val < 0) 2052 2052 return -EFAULT; 2053 2053 name[val] = 0;

+6 -5

net/ipv4/tcp_output.c

reviewed

··· 361 361 #define OPTION_SACK_ADVERTISE (1 << 0) 362 362 #define OPTION_TS (1 << 1) 363 363 #define OPTION_MD5 (1 << 2) 364 364 + #define OPTION_WSCALE (1 << 3) 364 365 365 366 struct tcp_out_options { 366 367 u8 options; /* bit field of OPTION_* */ ··· 428 427 TCPOLEN_SACK_PERM); 429 428 } 430 429 431 431 - if (unlikely(opts->ws)) { 430 430 + if (unlikely(OPTION_WSCALE & opts->options)) { 432 431 *ptr++ = htonl((TCPOPT_NOP << 24) | 433 432 (TCPOPT_WINDOW << 16) | 434 433 (TCPOLEN_WINDOW << 8) | ··· 495 494 } 496 495 if (likely(sysctl_tcp_window_scaling)) { 497 496 opts->ws = tp->rx_opt.rcv_wscale; 498 498 - if (likely(opts->ws)) 499 499 - size += TCPOLEN_WSCALE_ALIGNED; 497 497 + opts->options |= OPTION_WSCALE; 498 498 + size += TCPOLEN_WSCALE_ALIGNED; 500 499 } 501 500 if (likely(sysctl_tcp_sack)) { 502 501 opts->options |= OPTION_SACK_ADVERTISE; ··· 538 537 539 538 if (likely(ireq->wscale_ok)) { 540 539 opts->ws = ireq->rcv_wscale; 541 541 - if (likely(opts->ws)) 542 542 - size += TCPOLEN_WSCALE_ALIGNED; 540 540 + opts->options |= OPTION_WSCALE; 541 541 + size += TCPOLEN_WSCALE_ALIGNED; 543 542 } 544 543 if (likely(doing_ts)) { 545 544 opts->options |= OPTION_TS;

+1

net/ipv4/udp.c

reviewed

··· 696 696 697 697 if (rt == NULL) { 698 698 struct flowi fl = { .oif = ipc.oif, 699 699 + .mark = sk->sk_mark, 699 700 .nl_u = { .ip4_u = 700 701 { .daddr = faddr, 701 702 .saddr = saddr,

+4 -1

net/mac80211/tx.c

reviewed

··· 367 367 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data; 368 368 u32 staflags; 369 369 370 370 - if (unlikely(!sta || ieee80211_is_probe_resp(hdr->frame_control))) 370 370 + if (unlikely(!sta || ieee80211_is_probe_resp(hdr->frame_control) 371 371 + || ieee80211_is_auth(hdr->frame_control) 372 372 + || ieee80211_is_assoc_resp(hdr->frame_control) 373 373 + || ieee80211_is_reassoc_resp(hdr->frame_control))) 371 374 return TX_CONTINUE; 372 375 373 376 staflags = get_sta_flags(sta);