Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- Fixes for HSDK platform
- module build error for !LLSC config
* tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: unbork module link errors with !CONFIG_ARC_HAS_LLSC
ARC: [plat-hsdk] Increase SDIO CIU frequency to 50000000Hz
ARC: [plat-hsdk] select CONFIG_RESET_HSDK from Kconfig
+22
-6
+6
-5
arch/arc/boot/dts/hsdk.dts
+6
-5
arch/arc/boot/dts/hsdk.dts
···
137
137
/*
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* DW sdio controller has external ciu clock divider
139
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* controlled via register in SDIO IP. Due to its
140
-
* unexpected default value (it should devide by 1
141
-
* but it devides by 8) SDIO IP uses wrong clock and
140
+
* unexpected default value (it should divide by 1
141
+
* but it divides by 8) SDIO IP uses wrong clock and
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* works unstable (see STAR 9001204800)
143
+
* We switched to the minimum possible value of the
144
+
* divisor (div-by-2) in HSDK platform code.
143
145
* So add temporary fix and change clock frequency
144
-
* from 100000000 to 12500000 Hz until we fix dw sdio
145
-
* driver itself.
146
+
* to 50000000 Hz until we fix dw sdio driver itself.
146
147
*/
147
-
clock-frequency = <12500000>;
148
+
clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
150
151
-1
arch/arc/configs/hsdk_defconfig
-1
arch/arc/configs/hsdk_defconfig
+5
arch/arc/kernel/smp.c
+5
arch/arc/kernel/smp.c
···
23
23
#include <linux/cpumask.h>
24
24
#include <linux/reboot.h>
25
25
#include <linux/irqdomain.h>
26
+
#include <linux/export.h>
27
+
26
28
#include <asm/processor.h>
27
29
#include <asm/setup.h>
28
30
#include <asm/mach_desc.h>
···
32
30
#ifndef CONFIG_ARC_HAS_LLSC
33
31
arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
34
32
arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;
33
+
34
+
EXPORT_SYMBOL_GPL(smp_atomic_ops_lock);
35
+
EXPORT_SYMBOL_GPL(smp_bitops_lock);
35
36
#endif
36
37
37
38
struct plat_smp_ops __weak plat_smp_ops;
+1
arch/arc/plat-hsdk/Kconfig
+1
arch/arc/plat-hsdk/Kconfig
+10
arch/arc/plat-hsdk/platform.c
+10
arch/arc/plat-hsdk/platform.c
···
74
74
pr_err("Failed to setup CPU frequency to 1GHz!");
75
75
}
76
76
77
+
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
78
+
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
79
+
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
80
+
77
81
static void __init hsdk_init_early(void)
78
82
{
79
83
/*
···
92
88
93
89
/* Really apply settings made above */
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90
writel(1, (void __iomem *) CREG_PAE_UPDATE);
91
+
92
+
/*
93
+
* Switch SDIO external ciu clock divider from default div-by-8 to
94
+
* minimum possible div-by-2.
95
+
*/
96
+
iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
95
97
96
98
/*
97
99
* Setup CPU frequency to 1GHz.