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phy: qcom: qmp-pcie: restore compatibility with existing DTs

Existing device trees specify only a single clock-output-name for the
PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
that property. When it doesn't find it, it returns an error, thus
failing the probe of the PHY and thus breaking support for the
corresponding PCIe host.

Follow the approach of the combo USB+DT PHY and generate the name for
the AUX clocks instead of requiring it in DT.

Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 912cee11 8e97ddd5

+3 -6
+3 -6
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 4033 4033 { 4034 4034 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 4035 4035 struct clk_init_data init = { }; 4036 - int ret; 4036 + char name[64]; 4037 4037 4038 - ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); 4039 - if (ret) { 4040 - dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); 4041 - return ret; 4042 - } 4038 + snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); 4043 4039 4040 + init.name = name; 4044 4041 init.ops = &clk_fixed_rate_ops; 4045 4042 4046 4043 fixed->fixed_rate = qmp->cfg->aux_clock_rate;