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phy: qcom: edp: Introduce aux_cfg array for version specific aux settings

In order to support different HW versions, introduce aux_cfg array
to move v4 specific aux configuration settings.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Link: https://lore.kernel.org/r/20241004103046.22209-3-quic_mukhopad@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Soutrik Mukhopadhyay and committed by
Vinod Koul
91346358 7adb3d22

+17 -24
+17 -24
drivers/phy/qualcomm/phy-qcom-edp.c
··· 32 32 #define DP_PHY_PD_CTL 0x001c 33 33 #define DP_PHY_MODE 0x0020 34 34 35 - #define DP_PHY_AUX_CFG0 0x0024 36 - #define DP_PHY_AUX_CFG1 0x0028 37 - #define DP_PHY_AUX_CFG2 0x002C 38 - #define DP_PHY_AUX_CFG3 0x0030 39 - #define DP_PHY_AUX_CFG4 0x0034 40 - #define DP_PHY_AUX_CFG5 0x0038 41 - #define DP_PHY_AUX_CFG6 0x003C 42 - #define DP_PHY_AUX_CFG7 0x0040 43 - #define DP_PHY_AUX_CFG8 0x0044 44 - #define DP_PHY_AUX_CFG9 0x0048 35 + #define DP_AUX_CFG_SIZE 10 36 + #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n))) 45 37 46 38 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 47 39 ··· 82 90 83 91 struct qcom_edp_phy_cfg { 84 92 bool is_edp; 93 + const u8 *aux_cfg; 85 94 const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; 86 95 const struct phy_ver_ops *ver_ops; 87 96 }; ··· 179 186 .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, 180 187 }; 181 188 189 + static const u8 edp_phy_aux_cfg_v4[10] = { 190 + 0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03 191 + }; 192 + 182 193 static int qcom_edp_phy_init(struct phy *phy) 183 194 { 184 195 struct qcom_edp *edp = phy_get_drvdata(phy); 196 + u8 aux_cfg[DP_AUX_CFG_SIZE]; 185 197 int ret; 186 - u8 cfg8; 187 198 188 199 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); 189 200 if (ret) ··· 196 199 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); 197 200 if (ret) 198 201 goto out_disable_supplies; 202 + 203 + memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); 199 204 200 205 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 201 206 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, ··· 221 222 * even needed. 222 223 */ 223 224 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) 224 - cfg8 = 0xb7; 225 - else 226 - cfg8 = 0x37; 225 + aux_cfg[8] = 0xb7; 227 226 228 227 writel(0xfc, edp->edp + DP_PHY_MODE); 229 228 230 - writel(0x00, edp->edp + DP_PHY_AUX_CFG0); 231 - writel(0x13, edp->edp + DP_PHY_AUX_CFG1); 232 - writel(0x24, edp->edp + DP_PHY_AUX_CFG2); 233 - writel(0x00, edp->edp + DP_PHY_AUX_CFG3); 234 - writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); 235 - writel(0x26, edp->edp + DP_PHY_AUX_CFG5); 236 - writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); 237 - writel(0x03, edp->edp + DP_PHY_AUX_CFG7); 238 - writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); 239 - writel(0x03, edp->edp + DP_PHY_AUX_CFG9); 229 + for (int i = 0; i < DP_AUX_CFG_SIZE; i++) 230 + writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); 240 231 241 232 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 242 233 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | ··· 508 519 }; 509 520 510 521 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { 522 + .aux_cfg = edp_phy_aux_cfg_v4, 511 523 .ver_ops = &qcom_edp_phy_ops_v4, 512 524 }; 513 525 514 526 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = { 527 + .aux_cfg = edp_phy_aux_cfg_v4, 515 528 .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, 516 529 .ver_ops = &qcom_edp_phy_ops_v4, 517 530 }; 518 531 519 532 static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { 520 533 .is_edp = true, 534 + .aux_cfg = edp_phy_aux_cfg_v4, 521 535 .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, 522 536 .ver_ops = &qcom_edp_phy_ops_v4, 523 537 }; ··· 699 707 }; 700 708 701 709 static struct qcom_edp_phy_cfg x1e80100_phy_cfg = { 710 + .aux_cfg = edp_phy_aux_cfg_v4, 702 711 .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, 703 712 .ver_ops = &qcom_edp_phy_ops_v6, 704 713 };