Merge tag 'iommu-fixes-v6.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

+12 -26

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c

··· 292 292 struct mm_struct *mm) 293 293 { 294 294 int ret; 295 - unsigned long flags; 296 295 struct arm_smmu_ctx_desc *cd; 297 296 struct arm_smmu_mmu_notifier *smmu_mn; 298 - struct arm_smmu_master *master; 299 297 300 298 list_for_each_entry(smmu_mn, &smmu_domain->mmu_notifiers, list) { 301 299 if (smmu_mn->mn.mm == mm) { ··· 323 325 goto err_free_cd; 324 326 } 325 327 326 - spin_lock_irqsave(&smmu_domain->devices_lock, flags); 327 - list_for_each_entry(master, &smmu_domain->devices, domain_head) { 328 - ret = arm_smmu_write_ctx_desc(master, mm_get_enqcmd_pasid(mm), 329 - cd); 330 - if (ret) { 331 - list_for_each_entry_from_reverse( 332 - master, &smmu_domain->devices, domain_head) 333 - arm_smmu_write_ctx_desc( 334 - master, mm_get_enqcmd_pasid(mm), NULL); 335 - break; 336 - } 337 - } 338 - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); 339 - if (ret) 340 - goto err_put_notifier; 341 - 342 328 list_add(&smmu_mn->list, &smmu_domain->mmu_notifiers); 343 329 return smmu_mn; 344 330 345 - err_put_notifier: 346 - /* Frees smmu_mn */ 347 - mmu_notifier_put(&smmu_mn->mn); 348 331 err_free_cd: 349 332 arm_smmu_free_shared_cd(cd); 350 333 return ERR_PTR(ret); ··· 342 363 343 364 list_del(&smmu_mn->list); 344 365 345 - arm_smmu_update_ctx_desc_devices(smmu_domain, mm_get_enqcmd_pasid(mm), 346 - NULL); 347 - 348 366 /* 349 367 * If we went through clear(), we've already invalidated, and no 350 368 * new TLB entry can have been formed. ··· 357 381 arm_smmu_free_shared_cd(cd); 358 382 } 359 383 360 - static int __arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm) 384 + static int __arm_smmu_sva_bind(struct device *dev, ioasid_t pasid, 385 + struct mm_struct *mm) 361 386 { 362 387 int ret; 363 388 struct arm_smmu_bond *bond; ··· 381 404 goto err_free_bond; 382 405 } 383 406 407 + ret = arm_smmu_write_ctx_desc(master, pasid, bond->smmu_mn->cd); 408 + if (ret) 409 + goto err_put_notifier; 410 + 384 411 list_add(&bond->list, &master->bonds); 385 412 return 0; 386 413 414 + err_put_notifier: 415 + arm_smmu_mmu_notifier_put(bond->smmu_mn); 387 416 err_free_bond: 388 417 kfree(bond); 389 418 return ret; ··· 551 568 struct arm_smmu_master *master = dev_iommu_priv_get(dev); 552 569 553 570 mutex_lock(&sva_lock); 571 + 572 + arm_smmu_write_ctx_desc(master, id, NULL); 573 + 554 574 list_for_each_entry(t, &master->bonds, list) { 555 575 if (t->mm == mm) { 556 576 bond = t; ··· 576 590 struct mm_struct *mm = domain->mm; 577 591 578 592 mutex_lock(&sva_lock); 579 - ret = __arm_smmu_sva_bind(dev, mm); 593 + ret = __arm_smmu_sva_bind(dev, id, mm); 580 594 mutex_unlock(&sva_lock); 581 595 582 596 return ret;

+6 -11

drivers/iommu/arm/arm-smmu/arm-smmu.c

··· 859 859 arm_smmu_rpm_put(smmu); 860 860 } 861 861 862 - static struct iommu_domain *arm_smmu_domain_alloc_paging(struct device *dev) 862 + static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) 863 863 { 864 864 struct arm_smmu_domain *smmu_domain; 865 865 866 + if (type != IOMMU_DOMAIN_UNMANAGED) { 867 + if (using_legacy_binding || type != IOMMU_DOMAIN_DMA) 868 + return NULL; 869 + } 866 870 /* 867 871 * Allocate the domain and initialise some of its data structures. 868 872 * We can't really do anything meaningful until we've added a ··· 878 874 879 875 mutex_init(&smmu_domain->init_mutex); 880 876 spin_lock_init(&smmu_domain->cb_lock); 881 - 882 - if (dev) { 883 - struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); 884 - 885 - if (arm_smmu_init_domain_context(smmu_domain, cfg->smmu, dev)) { 886 - kfree(smmu_domain); 887 - return NULL; 888 - } 889 - } 890 877 891 878 return &smmu_domain->domain; 892 879 } ··· 1595 1600 .identity_domain = &arm_smmu_identity_domain, 1596 1601 .blocked_domain = &arm_smmu_blocked_domain, 1597 1602 .capable = arm_smmu_capable, 1598 - .domain_alloc_paging = arm_smmu_domain_alloc_paging, 1603 + .domain_alloc = arm_smmu_domain_alloc, 1599 1604 .probe_device = arm_smmu_probe_device, 1600 1605 .release_device = arm_smmu_release_device, 1601 1606 .probe_finalize = arm_smmu_probe_finalize,

+163 -51

drivers/iommu/intel/iommu.c

··· 396 396 return nid; 397 397 } 398 398 399 - static void domain_update_iotlb(struct dmar_domain *domain); 400 - 401 399 /* Return the super pagesize bitmap if supported. */ 402 400 static unsigned long domain_super_pgsize_bitmap(struct dmar_domain *domain) 403 401 { ··· 1216 1218 return NULL; 1217 1219 } 1218 1220 1219 - static void domain_update_iotlb(struct dmar_domain *domain) 1221 + void domain_update_iotlb(struct dmar_domain *domain) 1220 1222 { 1221 1223 struct dev_pasid_info *dev_pasid; 1222 1224 struct device_domain_info *info; ··· 1366 1368 spin_unlock_irqrestore(&domain->lock, flags); 1367 1369 } 1368 1370 1371 + static void __iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, 1372 + unsigned long pfn, unsigned int pages, 1373 + int ih) 1374 + { 1375 + unsigned int aligned_pages = __roundup_pow_of_two(pages); 1376 + unsigned long bitmask = aligned_pages - 1; 1377 + unsigned int mask = ilog2(aligned_pages); 1378 + u64 addr = (u64)pfn << VTD_PAGE_SHIFT; 1379 + 1380 + /* 1381 + * PSI masks the low order bits of the base address. If the 1382 + * address isn't aligned to the mask, then compute a mask value 1383 + * needed to ensure the target range is flushed. 1384 + */ 1385 + if (unlikely(bitmask & pfn)) { 1386 + unsigned long end_pfn = pfn + pages - 1, shared_bits; 1387 + 1388 + /* 1389 + * Since end_pfn <= pfn + bitmask, the only way bits 1390 + * higher than bitmask can differ in pfn and end_pfn is 1391 + * by carrying. This means after masking out bitmask, 1392 + * high bits starting with the first set bit in 1393 + * shared_bits are all equal in both pfn and end_pfn. 1394 + */ 1395 + shared_bits = ~(pfn ^ end_pfn) & ~bitmask; 1396 + mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; 1397 + } 1398 + 1399 + /* 1400 + * Fallback to domain selective flush if no PSI support or 1401 + * the size is too big. 1402 + */ 1403 + if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) 1404 + iommu->flush.flush_iotlb(iommu, did, 0, 0, 1405 + DMA_TLB_DSI_FLUSH); 1406 + else 1407 + iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, 1408 + DMA_TLB_PSI_FLUSH); 1409 + } 1410 + 1369 1411 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, 1370 1412 struct dmar_domain *domain, 1371 1413 unsigned long pfn, unsigned int pages, ··· 1422 1384 if (ih) 1423 1385 ih = 1 << 6; 1424 1386 1425 - if (domain->use_first_level) { 1387 + if (domain->use_first_level) 1426 1388 domain_flush_pasid_iotlb(iommu, domain, addr, pages, ih); 1427 - } else { 1428 - unsigned long bitmask = aligned_pages - 1; 1429 - 1430 - /* 1431 - * PSI masks the low order bits of the base address. If the 1432 - * address isn't aligned to the mask, then compute a mask value 1433 - * needed to ensure the target range is flushed. 1434 - */ 1435 - if (unlikely(bitmask & pfn)) { 1436 - unsigned long end_pfn = pfn + pages - 1, shared_bits; 1437 - 1438 - /* 1439 - * Since end_pfn <= pfn + bitmask, the only way bits 1440 - * higher than bitmask can differ in pfn and end_pfn is 1441 - * by carrying. This means after masking out bitmask, 1442 - * high bits starting with the first set bit in 1443 - * shared_bits are all equal in both pfn and end_pfn. 1444 - */ 1445 - shared_bits = ~(pfn ^ end_pfn) & ~bitmask; 1446 - mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; 1447 - } 1448 - 1449 - /* 1450 - * Fallback to domain selective flush if no PSI support or 1451 - * the size is too big. 1452 - */ 1453 - if (!cap_pgsel_inv(iommu->cap) || 1454 - mask > cap_max_amask_val(iommu->cap)) 1455 - iommu->flush.flush_iotlb(iommu, did, 0, 0, 1456 - DMA_TLB_DSI_FLUSH); 1457 - else 1458 - iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, 1459 - DMA_TLB_PSI_FLUSH); 1460 - } 1389 + else 1390 + __iommu_flush_iotlb_psi(iommu, did, pfn, pages, ih); 1461 1391 1462 1392 /* 1463 1393 * In caching mode, changes of pages from non-present to present require ··· 1449 1443 iommu_flush_write_buffer(iommu); 1450 1444 } 1451 1445 1446 + /* 1447 + * Flush the relevant caches in nested translation if the domain 1448 + * also serves as a parent 1449 + */ 1450 + static void parent_domain_flush(struct dmar_domain *domain, 1451 + unsigned long pfn, 1452 + unsigned long pages, int ih) 1453 + { 1454 + struct dmar_domain *s1_domain; 1455 + 1456 + spin_lock(&domain->s1_lock); 1457 + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { 1458 + struct device_domain_info *device_info; 1459 + struct iommu_domain_info *info; 1460 + unsigned long flags; 1461 + unsigned long i; 1462 + 1463 + xa_for_each(&s1_domain->iommu_array, i, info) 1464 + __iommu_flush_iotlb_psi(info->iommu, info->did, 1465 + pfn, pages, ih); 1466 + 1467 + if (!s1_domain->has_iotlb_device) 1468 + continue; 1469 + 1470 + spin_lock_irqsave(&s1_domain->lock, flags); 1471 + list_for_each_entry(device_info, &s1_domain->devices, link) 1472 + /* 1473 + * Address translation cache in device side caches the 1474 + * result of nested translation. There is no easy way 1475 + * to identify the exact set of nested translations 1476 + * affected by a change in S2. So just flush the entire 1477 + * device cache. 1478 + */ 1479 + __iommu_flush_dev_iotlb(device_info, 0, 1480 + MAX_AGAW_PFN_WIDTH); 1481 + spin_unlock_irqrestore(&s1_domain->lock, flags); 1482 + } 1483 + spin_unlock(&domain->s1_lock); 1484 + } 1485 + 1452 1486 static void intel_flush_iotlb_all(struct iommu_domain *domain) 1453 1487 { 1454 1488 struct dmar_domain *dmar_domain = to_dmar_domain(domain); ··· 1508 1462 if (!cap_caching_mode(iommu->cap)) 1509 1463 iommu_flush_dev_iotlb(dmar_domain, 0, MAX_AGAW_PFN_WIDTH); 1510 1464 } 1465 + 1466 + if (dmar_domain->nested_parent) 1467 + parent_domain_flush(dmar_domain, 0, -1, 0); 1511 1468 } 1512 1469 1513 1470 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) ··· 2034 1985 iommu_flush_iotlb_psi(info->iommu, domain, 2035 1986 start_pfn, lvl_pages, 2036 1987 0, 0); 1988 + if (domain->nested_parent) 1989 + parent_domain_flush(domain, start_pfn, 1990 + lvl_pages, 0); 2037 1991 } 2038 1992 2039 1993 pte++; ··· 3935 3883 bool dirty_tracking = flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; 3936 3884 bool nested_parent = flags & IOMMU_HWPT_ALLOC_NEST_PARENT; 3937 3885 struct intel_iommu *iommu = info->iommu; 3886 + struct dmar_domain *dmar_domain; 3938 3887 struct iommu_domain *domain; 3939 3888 3940 3889 /* Must be NESTING domain */ ··· 3961 3908 if (!domain) 3962 3909 return ERR_PTR(-ENOMEM); 3963 3910 3964 - if (nested_parent) 3965 - to_dmar_domain(domain)->nested_parent = true; 3911 + dmar_domain = to_dmar_domain(domain); 3912 + 3913 + if (nested_parent) { 3914 + dmar_domain->nested_parent = true; 3915 + INIT_LIST_HEAD(&dmar_domain->s1_domains); 3916 + spin_lock_init(&dmar_domain->s1_lock); 3917 + } 3966 3918 3967 3919 if (dirty_tracking) { 3968 - if (to_dmar_domain(domain)->use_first_level) { 3920 + if (dmar_domain->use_first_level) { 3969 3921 iommu_domain_free(domain); 3970 3922 return ERR_PTR(-EOPNOTSUPP); 3971 3923 } ··· 3982 3924 3983 3925 static void intel_iommu_domain_free(struct iommu_domain *domain) 3984 3926 { 3927 + struct dmar_domain *dmar_domain = to_dmar_domain(domain); 3928 + 3929 + WARN_ON(dmar_domain->nested_parent && 3930 + !list_empty(&dmar_domain->s1_domains)); 3985 3931 if (domain != &si_domain->domain) 3986 - domain_exit(to_dmar_domain(domain)); 3932 + domain_exit(dmar_domain); 3987 3933 } 3988 3934 3989 3935 int prepare_domain_attach_device(struct iommu_domain *domain, ··· 4169 4107 start_pfn, nrpages, 4170 4108 list_empty(&gather->freelist), 0); 4171 4109 4110 + if (dmar_domain->nested_parent) 4111 + parent_domain_flush(dmar_domain, start_pfn, nrpages, 4112 + list_empty(&gather->freelist)); 4172 4113 put_pages_list(&gather->freelist); 4173 4114 } 4174 4115 ··· 4729 4664 return vtd; 4730 4665 } 4731 4666 4667 + /* 4668 + * Set dirty tracking for the device list of a domain. The caller must 4669 + * hold the domain->lock when calling it. 4670 + */ 4671 + static int device_set_dirty_tracking(struct list_head *devices, bool enable) 4672 + { 4673 + struct device_domain_info *info; 4674 + int ret = 0; 4675 + 4676 + list_for_each_entry(info, devices, link) { 4677 + ret = intel_pasid_setup_dirty_tracking(info->iommu, info->dev, 4678 + IOMMU_NO_PASID, enable); 4679 + if (ret) 4680 + break; 4681 + } 4682 + 4683 + return ret; 4684 + } 4685 + 4686 + static int parent_domain_set_dirty_tracking(struct dmar_domain *domain, 4687 + bool enable) 4688 + { 4689 + struct dmar_domain *s1_domain; 4690 + unsigned long flags; 4691 + int ret; 4692 + 4693 + spin_lock(&domain->s1_lock); 4694 + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { 4695 + spin_lock_irqsave(&s1_domain->lock, flags); 4696 + ret = device_set_dirty_tracking(&s1_domain->devices, enable); 4697 + spin_unlock_irqrestore(&s1_domain->lock, flags); 4698 + if (ret) 4699 + goto err_unwind; 4700 + } 4701 + spin_unlock(&domain->s1_lock); 4702 + return 0; 4703 + 4704 + err_unwind: 4705 + list_for_each_entry(s1_domain, &domain->s1_domains, s2_link) { 4706 + spin_lock_irqsave(&s1_domain->lock, flags); 4707 + device_set_dirty_tracking(&s1_domain->devices, 4708 + domain->dirty_tracking); 4709 + spin_unlock_irqrestore(&s1_domain->lock, flags); 4710 + } 4711 + spin_unlock(&domain->s1_lock); 4712 + return ret; 4713 + } 4714 + 4732 4715 static int intel_iommu_set_dirty_tracking(struct iommu_domain *domain, 4733 4716 bool enable) 4734 4717 { 4735 4718 struct dmar_domain *dmar_domain = to_dmar_domain(domain); 4736 - struct device_domain_info *info; 4737 4719 int ret; 4738 4720 4739 4721 spin_lock(&dmar_domain->lock); 4740 4722 if (dmar_domain->dirty_tracking == enable) 4741 4723 goto out_unlock; 4742 4724 4743 - list_for_each_entry(info, &dmar_domain->devices, link) { 4744 - ret = intel_pasid_setup_dirty_tracking(info->iommu, 4745 - info->domain, info->dev, 4746 - IOMMU_NO_PASID, enable); 4725 + ret = device_set_dirty_tracking(&dmar_domain->devices, enable); 4726 + if (ret) 4727 + goto err_unwind; 4728 + 4729 + if (dmar_domain->nested_parent) { 4730 + ret = parent_domain_set_dirty_tracking(dmar_domain, enable); 4747 4731 if (ret) 4748 4732 goto err_unwind; 4749 4733 } ··· 4804 4690 return 0; 4805 4691 4806 4692 err_unwind: 4807 - list_for_each_entry(info, &dmar_domain->devices, link) 4808 - intel_pasid_setup_dirty_tracking(info->iommu, dmar_domain, 4809 - info->dev, IOMMU_NO_PASID, 4810 - dmar_domain->dirty_tracking); 4693 + device_set_dirty_tracking(&dmar_domain->devices, 4694 + dmar_domain->dirty_tracking); 4811 4695 spin_unlock(&dmar_domain->lock); 4812 4696 return ret; 4813 4697 }

+7

drivers/iommu/intel/iommu.h

··· 627 627 int agaw; 628 628 /* maximum mapped address */ 629 629 u64 max_addr; 630 + /* Protect the s1_domains list */ 631 + spinlock_t s1_lock; 632 + /* Track s1_domains nested on this domain */ 633 + struct list_head s1_domains; 630 634 }; 631 635 632 636 /* Nested user domain */ ··· 641 637 unsigned long s1_pgtbl; 642 638 /* page table attributes */ 643 639 struct iommu_hwpt_vtd_s1 s1_cfg; 640 + /* link to parent domain siblings */ 641 + struct list_head s2_link; 644 642 }; 645 643 }; 646 644 ··· 1066 1060 */ 1067 1061 #define QI_OPT_WAIT_DRAIN BIT(0) 1068 1062 1063 + void domain_update_iotlb(struct dmar_domain *domain); 1069 1064 int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); 1070 1065 void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu); 1071 1066 void device_block_translation(struct device *dev);

+14 -2

drivers/iommu/intel/nested.c

··· 65 65 list_add(&info->link, &dmar_domain->devices); 66 66 spin_unlock_irqrestore(&dmar_domain->lock, flags); 67 67 68 + domain_update_iotlb(dmar_domain); 69 + 68 70 return 0; 69 71 } 70 72 71 73 static void intel_nested_domain_free(struct iommu_domain *domain) 72 74 { 73 - kfree(to_dmar_domain(domain)); 75 + struct dmar_domain *dmar_domain = to_dmar_domain(domain); 76 + struct dmar_domain *s2_domain = dmar_domain->s2_domain; 77 + 78 + spin_lock(&s2_domain->s1_lock); 79 + list_del(&dmar_domain->s2_link); 80 + spin_unlock(&s2_domain->s1_lock); 81 + kfree(dmar_domain); 74 82 } 75 83 76 84 static void nested_flush_dev_iotlb(struct dmar_domain *domain, u64 addr, ··· 103 95 } 104 96 105 97 static void intel_nested_flush_cache(struct dmar_domain *domain, u64 addr, 106 - unsigned long npages, bool ih) 98 + u64 npages, bool ih) 107 99 { 108 100 struct iommu_domain_info *info; 109 101 unsigned int mask; ··· 208 200 INIT_LIST_HEAD(&domain->dev_pasids); 209 201 spin_lock_init(&domain->lock); 210 202 xa_init(&domain->iommu_array); 203 + 204 + spin_lock(&s2_domain->s1_lock); 205 + list_add(&domain->s2_link, &s2_domain->s1_domains); 206 + spin_unlock(&s2_domain->s1_lock); 211 207 212 208 return &domain->domain; 213 209 }

+3 -2

drivers/iommu/intel/pasid.c

··· 428 428 * Set up dirty tracking on a second only or nested translation type. 429 429 */ 430 430 int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, 431 - struct dmar_domain *domain, 432 431 struct device *dev, u32 pasid, 433 432 bool enabled) 434 433 { ··· 444 445 return -ENODEV; 445 446 } 446 447 447 - did = domain_id_iommu(domain, iommu); 448 + did = pasid_get_domain_id(pte); 448 449 pgtt = pasid_pte_get_pgtt(pte); 449 450 if (pgtt != PASID_ENTRY_PGTT_SL_ONLY && 450 451 pgtt != PASID_ENTRY_PGTT_NESTED) { ··· 657 658 pasid_set_domain_id(pte, did); 658 659 pasid_set_address_width(pte, s2_domain->agaw); 659 660 pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); 661 + if (s2_domain->dirty_tracking) 662 + pasid_set_ssade(pte); 660 663 pasid_set_translation_type(pte, PASID_ENTRY_PGTT_NESTED); 661 664 pasid_set_present(pte); 662 665 spin_unlock(&iommu->lock);

-1

drivers/iommu/intel/pasid.h

··· 307 307 struct dmar_domain *domain, 308 308 struct device *dev, u32 pasid); 309 309 int intel_pasid_setup_dirty_tracking(struct intel_iommu *iommu, 310 - struct dmar_domain *domain, 311 310 struct device *dev, u32 pasid, 312 311 bool enabled); 313 312 int intel_pasid_setup_pass_through(struct intel_iommu *iommu,

+17

drivers/iommu/iommu-sva.c

··· 41 41 } 42 42 iommu_mm->pasid = pasid; 43 43 INIT_LIST_HEAD(&iommu_mm->sva_domains); 44 + INIT_LIST_HEAD(&iommu_mm->sva_handles); 44 45 /* 45 46 * Make sure the write to mm->iommu_mm is not reordered in front of 46 47 * initialization to iommu_mm fields. If it does, readers may see a ··· 83 82 goto out_unlock; 84 83 } 85 84 85 + list_for_each_entry(handle, &mm->iommu_mm->sva_handles, handle_item) { 86 + if (handle->dev == dev) { 87 + refcount_inc(&handle->users); 88 + mutex_unlock(&iommu_sva_lock); 89 + return handle; 90 + } 91 + } 92 + 86 93 handle = kzalloc(sizeof(*handle), GFP_KERNEL); 87 94 if (!handle) { 88 95 ret = -ENOMEM; ··· 117 108 if (ret) 118 109 goto out_free_domain; 119 110 domain->users = 1; 111 + refcount_set(&handle->users, 1); 120 112 list_add(&domain->next, &mm->iommu_mm->sva_domains); 113 + list_add(&handle->handle_item, &mm->iommu_mm->sva_handles); 121 114 122 115 out: 123 116 mutex_unlock(&iommu_sva_lock); ··· 152 141 struct device *dev = handle->dev; 153 142 154 143 mutex_lock(&iommu_sva_lock); 144 + if (!refcount_dec_and_test(&handle->users)) { 145 + mutex_unlock(&iommu_sva_lock); 146 + return; 147 + } 148 + list_del(&handle->handle_item); 149 + 155 150 iommu_detach_device_pasid(domain, dev, iommu_mm->pasid); 156 151 if (--domain->users == 0) { 157 152 list_del(&domain->next);

+3

include/linux/iommu.h

··· 892 892 struct iommu_sva { 893 893 struct device *dev; 894 894 struct iommu_domain *domain; 895 + struct list_head handle_item; 896 + refcount_t users; 895 897 }; 896 898 897 899 struct iommu_mm_data { 898 900 u32 pasid; 899 901 struct list_head sva_domains; 902 + struct list_head sva_handles; 900 903 }; 901 904 902 905 int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,

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