Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Samsung S2MPG10 regulator and S2MPG11 PMIC drivers
Merge series from André Draszik <andre.draszik@linaro.org>:
This series extends the existing S2MPG10 PMIC driver to add support for
the regulators, and adds new S2MPG11 core and regulator drivers.
The patches are kept together in one series, due to S2MPG11 and its
regulators being very similar to S2MPG10.
The Samsung S2MPG11 PMIC is a Power Management IC for mobile
applications with buck converters, various LDOs, power meters, and
additional GPIO interfaces. It typically complements an S2MPG10 PMIC in
a main/sub configuration as the sub-PMIC and both are used on the
Google Pixel 6 and 6 Pro (oriole / raven).
A DT update for Oriole / Raven to enable these is required which I will
send out separately.
+2550
-221
+2
-2
Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml
+2
-2
Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml
···
75
75
interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
76
76
77
77
regulators {
78
-
LDO1 {
78
+
ldo1m {
79
79
regulator-name = "vdd_ldo1";
80
80
regulator-min-microvolt = <700000>;
81
81
regulator-max-microvolt = <1300000>;
···
84
84
85
85
// ...
86
86
87
-
BUCK1 {
87
+
buck8m {
88
88
regulator-name = "vdd_mif";
89
89
regulator-min-microvolt = <450000>;
90
90
regulator-max-microvolt = <1300000>;
+120
Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml
+120
Documentation/devicetree/bindings/mfd/samsung,s2mpg10-pmic.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/samsung,s2mpg10-pmic.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung S2MPG10 Power Management IC
8
+
9
+
maintainers:
10
+
- André Draszik <andre.draszik@linaro.org>
11
+
12
+
description: |
13
+
This is part of the device tree bindings for the S2MPG10 Power Management IC
14
+
(PMIC).
15
+
16
+
The Samsung S2MPG10 is a Power Management IC for mobile applications with buck
17
+
converters, various LDOs, power meters, RTC, clock outputs, and additional
18
+
GPIO interfaces and is typically complemented by S2MPG10 PMIC in a main/sub
19
+
configuration as the main PMIC.
20
+
21
+
properties:
22
+
compatible:
23
+
const: samsung,s2mpg10-pmic
24
+
25
+
clocks:
26
+
$ref: /schemas/clock/samsung,s2mps11.yaml
27
+
description:
28
+
Child node describing clock provider.
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
regulators:
34
+
type: object
35
+
$ref: /schemas/regulator/samsung,s2mpg10-regulator.yaml
36
+
description:
37
+
List of child nodes that specify the regulators.
38
+
39
+
system-power-controller: true
40
+
41
+
wakeup-source: true
42
+
43
+
patternProperties:
44
+
"^vinb([1-9]|10)m-supply$":
45
+
description:
46
+
Phandle to the power supply for each buck rail of this PMIC. There is a
47
+
1:1 mapping of supply to rail, e.g. vinb1m-supply supplies buck1m.
48
+
49
+
"^vinl([1-9]|1[0-5])m-supply$":
50
+
description: |
51
+
Phandle to the power supply for one or multiple LDO rails of this PMIC.
52
+
The mapping of supply to rail(s) is as follows:
53
+
vinl1m - ldo13m
54
+
vinl2m - ldo15m
55
+
vinl3m - ldo1m, ldo5m, ldo7m
56
+
vinl4m - ldo3m, ldo8m
57
+
vinl5m - ldo16m
58
+
vinl6m - ldo17m
59
+
vinl7m - ldo6m, ldo11m, ldo24m, ldo28m
60
+
vinl8m - ldo12m
61
+
vinl9m - ldo2m, ldo4m
62
+
vinl10m - ldo9m, ldo14m, ldo18m, 19m, ldo20m, ldo25m
63
+
vinl11m - ldo23m, ldo31m
64
+
vinl12m - ldo29m
65
+
vinl13m - ldo30m
66
+
vinl14m - ldo21m
67
+
vinl15m - ldo10m, ldo22m, ldo26m, ldo27m
68
+
69
+
required:
70
+
- compatible
71
+
- interrupts
72
+
- regulators
73
+
74
+
additionalProperties: false
75
+
76
+
examples:
77
+
- |
78
+
#include <dt-bindings/gpio/gpio.h>
79
+
#include <dt-bindings/interrupt-controller/irq.h>
80
+
#include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
81
+
82
+
pmic {
83
+
compatible = "samsung,s2mpg10-pmic";
84
+
interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
85
+
pinctrl-names = "default";
86
+
pinctrl-0 = <&pmic_int>;
87
+
system-power-controller;
88
+
wakeup-source;
89
+
90
+
vinl3m-supply = <&buck8m>;
91
+
92
+
clocks {
93
+
compatible = "samsung,s2mpg10-clk";
94
+
#clock-cells = <1>;
95
+
clock-output-names = "rtc32k_ap", "peri32k1", "peri32k2";
96
+
};
97
+
98
+
regulators {
99
+
buck8m {
100
+
regulator-name = "vdd_mif";
101
+
regulator-min-microvolt = <450000>;
102
+
regulator-max-microvolt = <1300000>;
103
+
regulator-ramp-delay = <6250>;
104
+
};
105
+
106
+
ldo1m {
107
+
regulator-name = "vdd_ldo1";
108
+
regulator-min-microvolt = <700000>;
109
+
regulator-max-microvolt = <1300000>;
110
+
};
111
+
112
+
ldo20m {
113
+
regulator-name = "vdd_dmics";
114
+
regulator-min-microvolt = <700000>;
115
+
regulator-max-microvolt = <1300000>;
116
+
regulator-always-on;
117
+
samsung,ext-control = <S2MPG10_EXTCTRL_LDO20M_EN2>;
118
+
};
119
+
};
120
+
};
+88
Documentation/devicetree/bindings/mfd/samsung,s2mpg11-pmic.yaml
+88
Documentation/devicetree/bindings/mfd/samsung,s2mpg11-pmic.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/samsung,s2mpg11-pmic.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung S2MPG11 Power Management IC
8
+
9
+
maintainers:
10
+
- André Draszik <andre.draszik@linaro.org>
11
+
12
+
description: |
13
+
This is part of the device tree bindings for the S2MPG11 Power Management IC
14
+
(PMIC).
15
+
16
+
The Samsung S2MPG11 is a Power Management IC for mobile applications with buck
17
+
converters, various LDOs, power meters, NTC thermistor inputs, and additional
18
+
GPIO interfaces and typically complements an S2MPG10 PMIC in a main/sub
19
+
configuration as the sub-PMIC.
20
+
21
+
properties:
22
+
compatible:
23
+
const: samsung,s2mpg11-pmic
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
regulators:
29
+
type: object
30
+
$ref: /schemas/regulator/samsung,s2mpg11-regulator.yaml
31
+
description:
32
+
List of child nodes that specify the regulators.
33
+
34
+
wakeup-source: true
35
+
36
+
patternProperties:
37
+
"^vinb(([1-9]|10)s|[abd])-supply$":
38
+
description:
39
+
Phandle to the power supply for each buck rail of this PMIC. There is a
40
+
1:1 mapping of numbered supply to rail, e.g. vinb1s-supply supplies
41
+
buck1s. The remaining mapping is as follows
42
+
vinba - bucka
43
+
vinbb - buck boost
44
+
vinbd - buckd
45
+
46
+
"^vinl[1-6]s-supply$":
47
+
description: |
48
+
Phandle to the power supply for one or multiple LDO rails of this PMIC.
49
+
The mapping of supply to rail(s) is as follows
50
+
vinl1s - ldo1s, ldo2s
51
+
vinl2s - ldo8s, ldo9s
52
+
vinl3s - ldo3s, ldo5s, ldo7s, ldo15s
53
+
vinl4s - ldo10s, ldo11s, ldo12s, ldo14s
54
+
vinl5s - ldo4s, ldo6s
55
+
vinl6s - ldo13s
56
+
57
+
required:
58
+
- compatible
59
+
- interrupts
60
+
- regulators
61
+
62
+
additionalProperties: false
63
+
64
+
examples:
65
+
- |
66
+
#include <dt-bindings/gpio/gpio.h>
67
+
#include <dt-bindings/interrupt-controller/irq.h>
68
+
#include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
69
+
70
+
pmic {
71
+
compatible = "samsung,s2mpg11-pmic";
72
+
interrupts-extended = <&gpa0 7 IRQ_TYPE_LEVEL_LOW>;
73
+
pinctrl-names = "default";
74
+
pinctrl-0 = <&pmic_int>;
75
+
wakeup-source;
76
+
77
+
vinl1s-supply = <&buck8m>;
78
+
vinl2s-supply = <&buck6s>;
79
+
80
+
regulators {
81
+
buckd {
82
+
regulator-name = "vcc_ufs";
83
+
regulator-ramp-delay = <6250>;
84
+
enable-gpios = <&gpp0 1 GPIO_ACTIVE_HIGH>;
85
+
samsung,ext-control = <S2MPG11_EXTCTRL_UFS_EN>;
86
+
};
87
+
};
88
+
};
+1
-28
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
+1
-28
Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml
···
20
20
properties:
21
21
compatible:
22
22
enum:
23
-
- samsung,s2mpg10-pmic
24
23
- samsung,s2mps11-pmic
25
24
- samsung,s2mps13-pmic
26
25
- samsung,s2mps14-pmic
···
58
59
reset (setting buck voltages to default values).
59
60
type: boolean
60
61
61
-
system-power-controller: true
62
-
63
62
wakeup-source: true
64
63
65
64
required:
66
65
- compatible
66
+
- reg
67
67
- regulators
68
68
69
69
additionalProperties: false
70
70
71
71
allOf:
72
-
- if:
73
-
properties:
74
-
compatible:
75
-
contains:
76
-
const: samsung,s2mpg10-pmic
77
-
then:
78
-
properties:
79
-
reg: false
80
-
samsung,s2mps11-acokb-ground: false
81
-
samsung,s2mps11-wrstbi-ground: false
82
-
83
-
# oneOf is required, because dtschema's fixups.py doesn't handle this
84
-
# nesting here. Its special treatment to allow either interrupt property
85
-
# when only one is specified in the binding works at the top level only.
86
-
oneOf:
87
-
- required: [interrupts]
88
-
- required: [interrupts-extended]
89
-
90
-
else:
91
-
properties:
92
-
system-power-controller: false
93
-
94
-
required:
95
-
- reg
96
-
97
72
- if:
98
73
properties:
99
74
compatible:
+158
Documentation/devicetree/bindings/regulator/samsung,s2mpg10-regulator.yaml
+158
Documentation/devicetree/bindings/regulator/samsung,s2mpg10-regulator.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/samsung,s2mpg10-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung S2MPG10 Power Management IC regulators
8
+
9
+
maintainers:
10
+
- André Draszik <andre.draszik@linaro.org>
11
+
12
+
description: |
13
+
This is part of the device tree bindings for the S2MG10 Power Management IC
14
+
(PMIC).
15
+
16
+
The S2MPG10 PMIC provides 10 buck and 31 LDO regulators.
17
+
18
+
See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
19
+
additional information and example.
20
+
21
+
properties:
22
+
# 1 LDO with possible (but limited) external control
23
+
ldo20m:
24
+
type: object
25
+
$ref: regulator.yaml#
26
+
unevaluatedProperties: false
27
+
description:
28
+
Properties for a single LDO regulator.
29
+
30
+
allOf:
31
+
- $ref: "#/$defs/s2mpg10-ext-control"
32
+
33
+
properties:
34
+
regulator-ramp-delay: false
35
+
36
+
samsung,ext-control:
37
+
minimum: 11
38
+
39
+
patternProperties:
40
+
# 10 bucks
41
+
"^buck([1-9]|10)m$":
42
+
type: object
43
+
$ref: regulator.yaml#
44
+
unevaluatedProperties: false
45
+
description:
46
+
Properties for a single buck regulator.
47
+
48
+
allOf:
49
+
- $ref: "#/$defs/s2mpg10-ext-control"
50
+
51
+
properties:
52
+
regulator-ramp-delay:
53
+
enum: [6250, 12500, 25000]
54
+
default: 6250
55
+
56
+
samsung,ext-control:
57
+
maximum: 10
58
+
59
+
# 12 standard LDOs
60
+
"^ldo(2[1-9]?|3[0-1])m$":
61
+
type: object
62
+
$ref: regulator.yaml#
63
+
unevaluatedProperties: false
64
+
description:
65
+
Properties for single LDO regulator.
66
+
67
+
properties:
68
+
regulator-ramp-delay: false
69
+
70
+
# 12 LDOs with possible external control
71
+
"^ldo([3-689]|1[046-9])m$":
72
+
type: object
73
+
$ref: regulator.yaml#
74
+
unevaluatedProperties: false
75
+
description:
76
+
Properties for a single LDO regulator.
77
+
78
+
allOf:
79
+
- $ref: "#/$defs/s2mpg10-ext-control"
80
+
81
+
properties:
82
+
regulator-ramp-delay: false
83
+
84
+
samsung,ext-control:
85
+
maximum: 10
86
+
87
+
# 6 LDOs with ramp support, 5 out of those with possible external control
88
+
"^ldo(1[1235]?|7)m$":
89
+
type: object
90
+
$ref: regulator.yaml#
91
+
unevaluatedProperties: false
92
+
description:
93
+
Properties for a single LDO regulator.
94
+
95
+
allOf:
96
+
- $ref: "#/$defs/s2mpg10-ext-control"
97
+
98
+
properties:
99
+
regulator-ramp-delay:
100
+
enum: [6250, 12500]
101
+
default: 6250
102
+
103
+
samsung,ext-control:
104
+
maximum: 10
105
+
106
+
$defs:
107
+
s2mpg10-ext-control:
108
+
properties:
109
+
samsung,ext-control:
110
+
description: |
111
+
These rails can be controlled via one of several possible external
112
+
(hardware) signals. If so, this property configures the signal the PMIC
113
+
should monitor. For S2MPG10 rails where external control is possible other
114
+
than ldo20m, the following values generally corresponding to the
115
+
respective on-chip pin are valid:
116
+
- 0 # S2MPG10_EXTCTRL_PWREN - PWREN pin
117
+
- 1 # S2MPG10_EXTCTRL_PWREN_MIF - PWREN_MIF pin
118
+
- 2 # S2MPG10_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin
119
+
- 3 # S2MPG10_EXTCTRL_CPUCL1_EN - CPUCL1_EN pin
120
+
- 4 # S2MPG10_EXTCTRL_CPUCL1_EN2 - CPUCL1_EN & PWREN pins
121
+
- 5 # S2MPG10_EXTCTRL_CPUCL2_EN - CPUCL2_EN pin
122
+
- 6 # S2MPG10_EXTCTRL_CPUCL2_EN2 - CPUCL2_E2 & PWREN pins
123
+
- 7 # S2MPG10_EXTCTRL_TPU_EN - TPU_EN pin
124
+
- 8 # S2MPG10_EXTCTRL_TPU_EN2 - TPU_EN & ~AP_ACTIVE_N pins
125
+
- 9 # S2MPG10_EXTCTRL_TCXO_ON - TCXO_ON pin
126
+
- 10 # S2MPG10_EXTCTRL_TCXO_ON2 - TCXO_ON & ~AP_ACTIVE_N pins
127
+
128
+
For S2MPG10 ldo20m, the following values are valid
129
+
- 11 # S2MPG10_EXTCTRL_LDO20M_EN2 - VLDO20M_EN & LDO20M_SFR
130
+
- 12 # S2MPG10_EXTCTRL_LDO20M_EN - VLDO20M_EN pin
131
+
132
+
$ref: /schemas/types.yaml#/definitions/uint32
133
+
minimum: 0
134
+
maximum: 12
135
+
136
+
enable-gpios:
137
+
description:
138
+
For rails where external control is done via a GPIO, this optional
139
+
property describes the GPIO line used.
140
+
141
+
dependentRequired:
142
+
enable-gpios: [ "samsung,ext-control" ]
143
+
144
+
allOf:
145
+
# Bucks 8, 9, and LDO 1 can not be controlled externally - above definition
146
+
# allows it and we deny it here. This approach reduces repetition.
147
+
- if:
148
+
anyOf:
149
+
- required: [buck8m]
150
+
- required: [buck9m]
151
+
- required: [ldo1m]
152
+
then:
153
+
patternProperties:
154
+
"^(buck[8-9]|ldo1)m$":
155
+
properties:
156
+
samsung,ext-control: false
157
+
158
+
additionalProperties: false
+136
Documentation/devicetree/bindings/regulator/samsung,s2mpg11-regulator.yaml
+136
Documentation/devicetree/bindings/regulator/samsung,s2mpg11-regulator.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/samsung,s2mpg11-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung S2MPG11 Power Management IC regulators
8
+
9
+
maintainers:
10
+
- André Draszik <andre.draszik@linaro.org>
11
+
12
+
description: |
13
+
This is part of the device tree bindings for the S2MG11 Power Management IC
14
+
(PMIC).
15
+
16
+
The S2MPG11 PMIC provides 12 buck, 1 buck-boost, and 15 LDO regulators.
17
+
18
+
See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
19
+
additional information and example.
20
+
21
+
properties:
22
+
buckboost:
23
+
type: object
24
+
$ref: regulator.yaml#
25
+
unevaluatedProperties: false
26
+
description:
27
+
Properties for the buck-boost regulator.
28
+
29
+
properties:
30
+
regulator-ramp-delay: false
31
+
32
+
patternProperties:
33
+
# 12 bucks
34
+
"^buck(([1-9]|10)s|[ad])$":
35
+
type: object
36
+
$ref: regulator.yaml#
37
+
unevaluatedProperties: false
38
+
description:
39
+
Properties for a single buck regulator.
40
+
41
+
allOf:
42
+
- $ref: "#/$defs/s2mpg11-ext-control"
43
+
44
+
properties:
45
+
regulator-ramp-delay:
46
+
enum: [6250, 12500, 25000]
47
+
default: 6250
48
+
49
+
# 11 standard LDOs
50
+
"^ldo([3-79]|1[01245])s$":
51
+
type: object
52
+
$ref: regulator.yaml#
53
+
unevaluatedProperties: false
54
+
description:
55
+
Properties for a single LDO regulator.
56
+
57
+
properties:
58
+
regulator-ramp-delay: false
59
+
60
+
# 2 LDOs with possible external control
61
+
"^ldo(8|13)s$":
62
+
type: object
63
+
$ref: regulator.yaml#
64
+
unevaluatedProperties: false
65
+
description:
66
+
Properties for single LDO regulator.
67
+
68
+
allOf:
69
+
- $ref: "#/$defs/s2mpg11-ext-control"
70
+
71
+
properties:
72
+
regulator-ramp-delay: false
73
+
74
+
# 2 LDOs with ramp support and possible external control
75
+
"^ldo[12]s$":
76
+
type: object
77
+
$ref: regulator.yaml#
78
+
unevaluatedProperties: false
79
+
description:
80
+
Properties for a single LDO regulator.
81
+
82
+
allOf:
83
+
- $ref: "#/$defs/s2mpg11-ext-control"
84
+
85
+
properties:
86
+
regulator-ramp-delay:
87
+
enum: [6250, 12500]
88
+
default: 6250
89
+
90
+
$defs:
91
+
s2mpg11-ext-control:
92
+
properties:
93
+
samsung,ext-control:
94
+
description: |
95
+
These rails can be controlled via one of several possible external
96
+
(hardware) signals. If so, this property configures the signal the PMIC
97
+
should monitor. The following values generally corresponding to the
98
+
respective on-chip pin are valid:
99
+
- 0 # S2MPG11_EXTCTRL_PWREN - PWREN pin
100
+
- 1 # S2MPG11_EXTCTRL_PWREN_MIF - PWREN_MIF pin
101
+
- 2 # S2MPG11_EXTCTRL_AP_ACTIVE_N - ~AP_ACTIVE_N pin
102
+
- 3 # S2MPG11_EXTCTRL_G3D_EN - G3D_EN pin
103
+
- 4 # S2MPG11_EXTCTRL_G3D_EN2 - G3D_EN & ~AP_ACTIVE_N pins
104
+
- 5 # S2MPG11_EXTCTRL_AOC_VDD - AOC_VDD pin
105
+
- 6 # S2MPG11_EXTCTRL_AOC_RET - AOC_RET pin
106
+
- 7 # S2MPG11_EXTCTRL_UFS_EN - UFS_EN pin
107
+
- 8 # S2MPG11_EXTCTRL_LDO13S_EN - VLDO13S_EN pin
108
+
109
+
$ref: /schemas/types.yaml#/definitions/uint32
110
+
minimum: 0
111
+
maximum: 8
112
+
113
+
enable-gpios:
114
+
description:
115
+
For rails where external control is done via a GPIO, this optional
116
+
property describes the GPIO line used.
117
+
118
+
dependentRequired:
119
+
enable-gpios: [ "samsung,ext-control" ]
120
+
121
+
allOf:
122
+
# Bucks 4, 6, 7 and 10 can not be controlled externally - above definition
123
+
# allows it and we deny it here. This approach reduces repetition.
124
+
- if:
125
+
anyOf:
126
+
- required: [buck4s]
127
+
- required: [buck6s]
128
+
- required: [buck7s]
129
+
- required: [buck10s]
130
+
then:
131
+
patternProperties:
132
+
"^buck([467]|10)s$":
133
+
properties:
134
+
samsung,ext-control: false
135
+
136
+
additionalProperties: false
+1
MAINTAINERS
+1
MAINTAINERS
+167
-4
drivers/mfd/sec-acpm.c
+167
-4
drivers/mfd/sec-acpm.c
···
13
13
#include <linux/mfd/samsung/core.h>
14
14
#include <linux/mfd/samsung/rtc.h>
15
15
#include <linux/mfd/samsung/s2mpg10.h>
16
+
#include <linux/mfd/samsung/s2mpg11.h>
16
17
#include <linux/mod_devicetable.h>
17
18
#include <linux/module.h>
18
19
#include <linux/of.h>
···
217
216
.cache_type = REGCACHE_FLAT,
218
217
};
219
218
219
+
static const struct regmap_range s2mpg11_common_registers[] = {
220
+
regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */
221
+
regmap_reg_range(0x0a, 0x0c), /* Speedy control */
222
+
regmap_reg_range(0x1a, 0x27), /* Debug */
223
+
};
224
+
225
+
static const struct regmap_range s2mpg11_common_ro_registers[] = {
226
+
regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */
227
+
regmap_reg_range(0x25, 0x27), /* Debug */
228
+
};
229
+
230
+
static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = {
231
+
regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */
232
+
regmap_reg_range(0x02, 0x02), /* INT_MASK */
233
+
regmap_reg_range(0x0a, 0x0c), /* Speedy control */
234
+
};
235
+
236
+
static const struct regmap_range s2mpg11_common_precious_registers[] = {
237
+
regmap_reg_range(0x01, 0x01), /* INT */
238
+
};
239
+
240
+
static const struct regmap_access_table s2mpg11_common_wr_table = {
241
+
.yes_ranges = s2mpg11_common_registers,
242
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),
243
+
.no_ranges = s2mpg11_common_ro_registers,
244
+
.n_no_ranges = ARRAY_SIZE(s2mpg11_common_ro_registers),
245
+
};
246
+
247
+
static const struct regmap_access_table s2mpg11_common_rd_table = {
248
+
.yes_ranges = s2mpg11_common_registers,
249
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_registers),
250
+
};
251
+
252
+
static const struct regmap_access_table s2mpg11_common_volatile_table = {
253
+
.no_ranges = s2mpg11_common_nonvolatile_registers,
254
+
.n_no_ranges = ARRAY_SIZE(s2mpg11_common_nonvolatile_registers),
255
+
};
256
+
257
+
static const struct regmap_access_table s2mpg11_common_precious_table = {
258
+
.yes_ranges = s2mpg11_common_precious_registers,
259
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_common_precious_registers),
260
+
};
261
+
262
+
static const struct regmap_config s2mpg11_regmap_config_common = {
263
+
.name = "common",
264
+
.reg_bits = ACPM_ADDR_BITS,
265
+
.val_bits = 8,
266
+
.max_register = S2MPG11_COMMON_SPD_DEBUG4,
267
+
.wr_table = &s2mpg11_common_wr_table,
268
+
.rd_table = &s2mpg11_common_rd_table,
269
+
.volatile_table = &s2mpg11_common_volatile_table,
270
+
.precious_table = &s2mpg11_common_precious_table,
271
+
.num_reg_defaults_raw = S2MPG11_COMMON_SPD_DEBUG4 + 1,
272
+
.cache_type = REGCACHE_FLAT,
273
+
};
274
+
275
+
static const struct regmap_range s2mpg11_pmic_registers[] = {
276
+
regmap_reg_range(0x00, 0x5a), /* All PMIC registers */
277
+
regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */
278
+
};
279
+
280
+
static const struct regmap_range s2mpg11_pmic_ro_registers[] = {
281
+
regmap_reg_range(0x00, 0x05), /* INTx */
282
+
regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */
283
+
regmap_reg_range(0x98, 0x98), /* GPIO input */
284
+
};
285
+
286
+
static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] = {
287
+
regmap_reg_range(0x06, 0x0b), /* INTxM */
288
+
};
289
+
290
+
static const struct regmap_range s2mpg11_pmic_precious_registers[] = {
291
+
regmap_reg_range(0x00, 0x05), /* INTx */
292
+
};
293
+
294
+
static const struct regmap_access_table s2mpg11_pmic_wr_table = {
295
+
.yes_ranges = s2mpg11_pmic_registers,
296
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),
297
+
.no_ranges = s2mpg11_pmic_ro_registers,
298
+
.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_ro_registers),
299
+
};
300
+
301
+
static const struct regmap_access_table s2mpg11_pmic_rd_table = {
302
+
.yes_ranges = s2mpg11_pmic_registers,
303
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_registers),
304
+
};
305
+
306
+
static const struct regmap_access_table s2mpg11_pmic_volatile_table = {
307
+
.no_ranges = s2mpg11_pmic_nonvolatile_registers,
308
+
.n_no_ranges = ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers),
309
+
};
310
+
311
+
static const struct regmap_access_table s2mpg11_pmic_precious_table = {
312
+
.yes_ranges = s2mpg11_pmic_precious_registers,
313
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_pmic_precious_registers),
314
+
};
315
+
316
+
static const struct regmap_config s2mpg11_regmap_config_pmic = {
317
+
.name = "pmic",
318
+
.reg_bits = ACPM_ADDR_BITS,
319
+
.val_bits = 8,
320
+
.max_register = S2MPG11_PMIC_LDO_SENSE2,
321
+
.wr_table = &s2mpg11_pmic_wr_table,
322
+
.rd_table = &s2mpg11_pmic_rd_table,
323
+
.volatile_table = &s2mpg11_pmic_volatile_table,
324
+
.precious_table = &s2mpg11_pmic_precious_table,
325
+
.num_reg_defaults_raw = S2MPG11_PMIC_LDO_SENSE2 + 1,
326
+
.cache_type = REGCACHE_FLAT,
327
+
};
328
+
329
+
static const struct regmap_range s2mpg11_meter_registers[] = {
330
+
regmap_reg_range(0x00, 0x3e), /* Meter config */
331
+
regmap_reg_range(0x40, 0x8a), /* Meter data */
332
+
regmap_reg_range(0x8d, 0x9c), /* Meter data */
333
+
};
334
+
335
+
static const struct regmap_range s2mpg11_meter_ro_registers[] = {
336
+
regmap_reg_range(0x40, 0x9c), /* Meter data */
337
+
};
338
+
339
+
static const struct regmap_access_table s2mpg11_meter_wr_table = {
340
+
.yes_ranges = s2mpg11_meter_registers,
341
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),
342
+
.no_ranges = s2mpg11_meter_ro_registers,
343
+
.n_no_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),
344
+
};
345
+
346
+
static const struct regmap_access_table s2mpg11_meter_rd_table = {
347
+
.yes_ranges = s2mpg11_meter_registers,
348
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_registers),
349
+
};
350
+
351
+
static const struct regmap_access_table s2mpg11_meter_volatile_table = {
352
+
.yes_ranges = s2mpg11_meter_ro_registers,
353
+
.n_yes_ranges = ARRAY_SIZE(s2mpg11_meter_ro_registers),
354
+
};
355
+
356
+
static const struct regmap_config s2mpg11_regmap_config_meter = {
357
+
.name = "meter",
358
+
.reg_bits = ACPM_ADDR_BITS,
359
+
.val_bits = 8,
360
+
.max_register = S2MPG11_METER_LPF_DATA_NTC7_2,
361
+
.wr_table = &s2mpg11_meter_wr_table,
362
+
.rd_table = &s2mpg11_meter_rd_table,
363
+
.volatile_table = &s2mpg11_meter_volatile_table,
364
+
.num_reg_defaults_raw = S2MPG11_METER_LPF_DATA_NTC7_2 + 1,
365
+
.cache_type = REGCACHE_FLAT,
366
+
};
367
+
220
368
struct sec_pmic_acpm_shared_bus_context {
221
369
const struct acpm_handle *acpm;
222
370
unsigned int acpm_chan_id;
···
514
364
if (IS_ERR(regmap_pmic))
515
365
return PTR_ERR(regmap_pmic);
516
366
517
-
regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC,
518
-
pdata->regmap_cfg_rtc, true);
519
-
if (IS_ERR(regmap))
520
-
return PTR_ERR(regmap);
367
+
if (pdata->regmap_cfg_rtc) {
368
+
regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_RTC,
369
+
pdata->regmap_cfg_rtc, true);
370
+
if (IS_ERR(regmap))
371
+
return PTR_ERR(regmap);
372
+
}
521
373
522
374
regmap = sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCESSTYPE_METER,
523
375
pdata->regmap_cfg_meter, true);
···
551
399
.regmap_cfg_meter = &s2mpg10_regmap_config_meter,
552
400
};
553
401
402
+
static const struct sec_pmic_acpm_platform_data s2mpg11_data = {
403
+
.device_type = S2MPG11,
404
+
.acpm_chan_id = 2,
405
+
.speedy_channel = 1,
406
+
.regmap_cfg_common = &s2mpg11_regmap_config_common,
407
+
.regmap_cfg_pmic = &s2mpg11_regmap_config_pmic,
408
+
.regmap_cfg_meter = &s2mpg11_regmap_config_meter,
409
+
};
410
+
554
411
static const struct of_device_id sec_pmic_acpm_of_match[] = {
555
412
{ .compatible = "samsung,s2mpg10-pmic", .data = &s2mpg10_data, },
413
+
{ .compatible = "samsung,s2mpg11-pmic", .data = &s2mpg11_data, },
556
414
{ },
557
415
};
558
416
MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match);
···
570
408
static struct platform_driver sec_pmic_acpm_driver = {
571
409
.driver = {
572
410
.name = "sec-pmic-acpm",
411
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
573
412
.pm = pm_sleep_ptr(&sec_pmic_pm_ops),
574
413
.of_match_table = sec_pmic_acpm_of_match,
575
414
},
+49
-13
drivers/mfd/sec-common.c
+49
-13
drivers/mfd/sec-common.c
···
23
23
#include <linux/regmap.h>
24
24
#include "sec-core.h"
25
25
26
+
static const struct resource s5m8767_rtc_resources[] = {
27
+
DEFINE_RES_IRQ_NAMED(S5M8767_IRQ_RTCA1, "alarm"),
28
+
};
29
+
26
30
static const struct mfd_cell s5m8767_devs[] = {
27
31
MFD_CELL_NAME("s5m8767-pmic"),
28
-
MFD_CELL_NAME("s5m-rtc"),
32
+
MFD_CELL_RES("s5m-rtc", s5m8767_rtc_resources),
29
33
MFD_CELL_OF("s5m8767-clk", NULL, NULL, 0, 0, "samsung,s5m8767-clk"),
30
34
};
31
35
···
37
33
MFD_CELL_NAME("s2dos05-regulator"),
38
34
};
39
35
36
+
static const struct resource s2mpg10_rtc_resources[] = {
37
+
DEFINE_RES_IRQ_NAMED(S2MPG10_IRQ_RTCA0, "alarm"),
38
+
};
39
+
40
40
static const struct mfd_cell s2mpg10_devs[] = {
41
41
MFD_CELL_NAME("s2mpg10-meter"),
42
42
MFD_CELL_NAME("s2mpg10-regulator"),
43
-
MFD_CELL_NAME("s2mpg10-rtc"),
43
+
MFD_CELL_RES("s2mpg10-rtc", s2mpg10_rtc_resources),
44
44
MFD_CELL_OF("s2mpg10-clk", NULL, NULL, 0, 0, "samsung,s2mpg10-clk"),
45
45
MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"),
46
46
};
47
47
48
+
static const struct mfd_cell s2mpg11_devs[] = {
49
+
MFD_CELL_NAME("s2mpg11-meter"),
50
+
MFD_CELL_NAME("s2mpg11-regulator"),
51
+
MFD_CELL_OF("s2mpg11-gpio", NULL, NULL, 0, 0, "samsung,s2mpg11-gpio"),
52
+
};
53
+
54
+
static const struct resource s2mps11_rtc_resources[] = {
55
+
DEFINE_RES_IRQ_NAMED(S2MPS11_IRQ_RTCA0, "alarm"),
56
+
};
57
+
48
58
static const struct mfd_cell s2mps11_devs[] = {
49
59
MFD_CELL_NAME("s2mps11-regulator"),
50
-
MFD_CELL_NAME("s2mps14-rtc"),
60
+
MFD_CELL_RES("s2mps14-rtc", s2mps11_rtc_resources),
51
61
MFD_CELL_OF("s2mps11-clk", NULL, NULL, 0, 0, "samsung,s2mps11-clk"),
62
+
};
63
+
64
+
static const struct resource s2mps14_rtc_resources[] = {
65
+
DEFINE_RES_IRQ_NAMED(S2MPS14_IRQ_RTCA0, "alarm"),
52
66
};
53
67
54
68
static const struct mfd_cell s2mps13_devs[] = {
55
69
MFD_CELL_NAME("s2mps13-regulator"),
56
-
MFD_CELL_NAME("s2mps13-rtc"),
70
+
MFD_CELL_RES("s2mps13-rtc", s2mps14_rtc_resources),
57
71
MFD_CELL_OF("s2mps13-clk", NULL, NULL, 0, 0, "samsung,s2mps13-clk"),
58
72
};
59
73
60
74
static const struct mfd_cell s2mps14_devs[] = {
61
75
MFD_CELL_NAME("s2mps14-regulator"),
62
-
MFD_CELL_NAME("s2mps14-rtc"),
76
+
MFD_CELL_RES("s2mps14-rtc", s2mps14_rtc_resources),
63
77
MFD_CELL_OF("s2mps14-clk", NULL, NULL, 0, 0, "samsung,s2mps14-clk"),
64
78
};
65
79
66
80
static const struct mfd_cell s2mps15_devs[] = {
67
81
MFD_CELL_NAME("s2mps15-regulator"),
68
-
MFD_CELL_NAME("s2mps15-rtc"),
82
+
MFD_CELL_RES("s2mps15-rtc", s2mps14_rtc_resources),
69
83
MFD_CELL_OF("s2mps13-clk", NULL, NULL, 0, 0, "samsung,s2mps13-clk"),
70
84
};
71
85
72
86
static const struct mfd_cell s2mpa01_devs[] = {
73
87
MFD_CELL_NAME("s2mpa01-pmic"),
74
-
MFD_CELL_NAME("s2mps14-rtc"),
88
+
MFD_CELL_RES("s2mps14-rtc", s2mps14_rtc_resources),
75
89
};
76
90
77
91
static const struct mfd_cell s2mpu02_devs[] = {
78
92
MFD_CELL_NAME("s2mpu02-regulator"),
79
93
};
80
94
95
+
static const struct resource s2mpu05_rtc_resources[] = {
96
+
DEFINE_RES_IRQ_NAMED(S2MPU05_IRQ_RTCA0, "alarm"),
97
+
};
98
+
81
99
static const struct mfd_cell s2mpu05_devs[] = {
82
100
MFD_CELL_NAME("s2mpu05-regulator"),
83
-
MFD_CELL_NAME("s2mps15-rtc"),
101
+
MFD_CELL_RES("s2mps15-rtc", s2mpu05_rtc_resources),
84
102
};
85
103
86
104
static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic)
···
110
84
unsigned int val;
111
85
112
86
/* For s2mpg1x, the revision is in a different regmap */
113
-
if (sec_pmic->device_type == S2MPG10)
87
+
switch (sec_pmic->device_type) {
88
+
case S2MPG10:
89
+
case S2MPG11:
114
90
return;
91
+
default:
92
+
break;
93
+
}
115
94
116
95
/* For each device type, the REG_ID is always the first register */
117
96
if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val))
···
174
143
int sec_pmic_probe(struct device *dev, int device_type, unsigned int irq,
175
144
struct regmap *regmap, struct i2c_client *client)
176
145
{
146
+
struct regmap_irq_chip_data *irq_data;
177
147
struct sec_platform_data *pdata;
178
148
const struct mfd_cell *sec_devs;
179
149
struct sec_pmic_dev *sec_pmic;
···
199
167
200
168
sec_pmic->pdata = pdata;
201
169
202
-
ret = sec_irq_init(sec_pmic);
203
-
if (ret)
204
-
return ret;
170
+
irq_data = sec_irq_init(sec_pmic);
171
+
if (IS_ERR(irq_data))
172
+
return PTR_ERR(irq_data);
205
173
206
174
pm_runtime_set_active(sec_pmic->dev);
207
175
···
221
189
case S2MPG10:
222
190
sec_devs = s2mpg10_devs;
223
191
num_sec_devs = ARRAY_SIZE(s2mpg10_devs);
192
+
break;
193
+
case S2MPG11:
194
+
sec_devs = s2mpg11_devs;
195
+
num_sec_devs = ARRAY_SIZE(s2mpg11_devs);
224
196
break;
225
197
case S2MPS11X:
226
198
sec_devs = s2mps11_devs;
···
256
220
sec_pmic->device_type);
257
221
}
258
222
ret = devm_mfd_add_devices(sec_pmic->dev, -1, sec_devs, num_sec_devs,
259
-
NULL, 0, NULL);
223
+
NULL, 0, regmap_irq_get_domain(irq_data));
260
224
if (ret)
261
225
return ret;
262
226
+1
-1
drivers/mfd/sec-core.h
+1
-1
drivers/mfd/sec-core.h
+114
-36
drivers/mfd/sec-irq.c
+114
-36
drivers/mfd/sec-irq.c
···
11
11
#include <linux/mfd/samsung/core.h>
12
12
#include <linux/mfd/samsung/irq.h>
13
13
#include <linux/mfd/samsung/s2mpg10.h>
14
+
#include <linux/mfd/samsung/s2mpg11.h>
14
15
#include <linux/mfd/samsung/s2mps11.h>
15
16
#include <linux/mfd/samsung/s2mps14.h>
16
17
#include <linux/mfd/samsung/s2mpu02.h>
···
78
77
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK),
79
78
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK),
80
79
REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK),
80
+
};
81
+
82
+
static const struct regmap_irq s2mpg11_irqs[] = {
83
+
REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_PMIC, 0, S2MPG11_COMMON_INT_SRC_PMIC),
84
+
/* No documentation or other reference for remaining bits */
85
+
REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)),
86
+
};
87
+
88
+
static const struct regmap_irq s2mpg11_pmic_irqs[] = {
89
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK),
90
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK),
91
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK),
92
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK),
93
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK),
94
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK),
95
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_MASK),
96
+
97
+
REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK),
98
+
REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK),
99
+
REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK),
100
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK),
101
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_MASK),
102
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK),
103
+
104
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK),
105
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK),
106
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK),
107
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK),
108
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK),
109
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK),
110
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK),
111
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK),
112
+
113
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK),
114
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK),
115
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK),
116
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK),
117
+
REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK),
118
+
REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK),
119
+
REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK),
120
+
121
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK),
122
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK),
123
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK),
124
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK),
125
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK),
126
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK),
127
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK),
128
+
REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK),
129
+
130
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK),
131
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK),
132
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK),
133
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK),
134
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK),
135
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK),
136
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK),
137
+
REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK),
81
138
};
82
139
83
140
static const struct regmap_irq s2mps11_irqs[] = {
···
245
186
REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
246
187
};
247
188
248
-
/* All S2MPG10 interrupt sources are read-only and don't require clearing */
189
+
/* All S2MPG1x interrupt sources are read-only and don't require clearing */
249
190
static const struct regmap_irq_chip s2mpg10_irq_chip = {
250
191
.name = "s2mpg10",
251
192
.status_base = S2MPG10_COMMON_INT,
···
262
203
.num_regs = 6,
263
204
.irqs = s2mpg10_pmic_irqs,
264
205
.num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs),
206
+
};
207
+
208
+
static const struct regmap_irq_chip s2mpg11_irq_chip = {
209
+
.name = "s2mpg11",
210
+
.status_base = S2MPG11_COMMON_INT,
211
+
.mask_base = S2MPG11_COMMON_INT_MASK,
212
+
.num_regs = 1,
213
+
.irqs = s2mpg11_irqs,
214
+
.num_irqs = ARRAY_SIZE(s2mpg11_irqs),
215
+
};
216
+
217
+
static const struct regmap_irq_chip s2mpg11_irq_chip_pmic = {
218
+
.name = "s2mpg11-pmic",
219
+
.domain_suffix = "pmic",
220
+
.status_base = S2MPG11_PMIC_INT1,
221
+
.mask_base = S2MPG11_PMIC_INT1M,
222
+
.num_regs = 6,
223
+
.irqs = s2mpg11_pmic_irqs,
224
+
.num_irqs = ARRAY_SIZE(s2mpg11_pmic_irqs),
265
225
};
266
226
267
227
static const struct regmap_irq_chip s2mps11_irq_chip = {
···
346
268
.ack_base = S5M8767_REG_INT1,
347
269
};
348
270
349
-
static int s2mpg1x_add_chained_irq_chip(struct device *dev, struct regmap *regmap, int pirq,
350
-
struct regmap_irq_chip_data *parent,
351
-
const struct regmap_irq_chip *chip,
352
-
struct regmap_irq_chip_data **data)
271
+
static struct regmap_irq_chip_data *
272
+
s2mpg1x_add_chained_pmic(struct sec_pmic_dev *sec_pmic, int pirq,
273
+
struct regmap_irq_chip_data *parent, const struct regmap_irq_chip *chip)
353
274
{
275
+
struct device *dev = sec_pmic->dev;
276
+
struct regmap_irq_chip_data *data;
354
277
int irq, ret;
355
278
356
279
irq = regmap_irq_get_virq(parent, pirq);
357
280
if (irq < 0)
358
-
return dev_err_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n", pirq,
359
-
chip->name);
281
+
return dev_err_ptr_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
282
+
pirq, chip->name);
360
283
361
-
ret = devm_regmap_add_irq_chip(dev, regmap, irq, IRQF_ONESHOT | IRQF_SHARED, 0, chip, data);
284
+
ret = devm_regmap_add_irq_chip(dev, sec_pmic->regmap_pmic, irq,
285
+
IRQF_ONESHOT | IRQF_SHARED, 0, chip, &data);
362
286
if (ret)
363
-
return dev_err_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
287
+
return dev_err_ptr_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name);
364
288
365
-
return 0;
289
+
return data;
366
290
}
367
291
368
-
static int sec_irq_init_s2mpg1x(struct sec_pmic_dev *sec_pmic)
292
+
static struct regmap_irq_chip_data *sec_irq_init_s2mpg1x(struct sec_pmic_dev *sec_pmic)
369
293
{
370
294
const struct regmap_irq_chip *irq_chip, *chained_irq_chip;
371
295
struct regmap_irq_chip_data *irq_data;
···
381
301
chained_irq_chip = &s2mpg10_irq_chip_pmic;
382
302
chained_pirq = S2MPG10_COMMON_IRQ_PMIC;
383
303
break;
304
+
case S2MPG11:
305
+
irq_chip = &s2mpg11_irq_chip;
306
+
chained_irq_chip = &s2mpg11_irq_chip_pmic;
307
+
chained_pirq = S2MPG11_COMMON_IRQ_PMIC;
308
+
break;
384
309
default:
385
-
return dev_err_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",
386
-
sec_pmic->device_type);
310
+
return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",
311
+
sec_pmic->device_type);
387
312
}
388
313
389
314
regmap_common = dev_get_regmap(sec_pmic->dev, "common");
390
315
if (!regmap_common)
391
-
return dev_err_probe(sec_pmic->dev, -EINVAL, "No 'common' regmap %d\n",
392
-
sec_pmic->device_type);
316
+
return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "No 'common' regmap %d\n",
317
+
sec_pmic->device_type);
393
318
394
319
ret = devm_regmap_add_irq_chip(sec_pmic->dev, regmap_common, sec_pmic->irq, IRQF_ONESHOT, 0,
395
320
irq_chip, &irq_data);
396
321
if (ret)
397
-
return dev_err_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n",
398
-
irq_chip->name);
322
+
return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n",
323
+
irq_chip->name);
399
324
400
-
return s2mpg1x_add_chained_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, chained_pirq,
401
-
irq_data, chained_irq_chip, &sec_pmic->irq_data);
325
+
return s2mpg1x_add_chained_pmic(sec_pmic, chained_pirq, irq_data, chained_irq_chip);
402
326
}
403
327
404
-
int sec_irq_init(struct sec_pmic_dev *sec_pmic)
328
+
struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic)
405
329
{
330
+
struct regmap_irq_chip_data *sec_irq_chip_data;
406
331
const struct regmap_irq_chip *sec_irq_chip;
407
332
int ret;
408
333
···
416
331
sec_irq_chip = &s5m8767_irq_chip;
417
332
break;
418
333
case S2DOS05:
419
-
return 0;
334
+
return NULL;
420
335
case S2MPA01:
421
336
sec_irq_chip = &s2mps14_irq_chip;
422
337
break;
423
338
case S2MPG10:
339
+
case S2MPG11:
424
340
return sec_irq_init_s2mpg1x(sec_pmic);
425
341
case S2MPS11X:
426
342
sec_irq_chip = &s2mps11_irq_chip;
···
442
356
sec_irq_chip = &s2mpu05_irq_chip;
443
357
break;
444
358
default:
445
-
return dev_err_probe(sec_pmic->dev, -EINVAL,
446
-
"Unsupported device type %d\n",
447
-
sec_pmic->device_type);
359
+
return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n",
360
+
sec_pmic->device_type);
448
361
}
449
362
450
363
if (!sec_pmic->irq) {
451
364
dev_warn(sec_pmic->dev,
452
365
"No interrupt specified, no interrupts\n");
453
-
return 0;
366
+
return NULL;
454
367
}
455
368
456
369
ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
457
370
sec_pmic->irq, IRQF_ONESHOT,
458
-
0, sec_irq_chip, &sec_pmic->irq_data);
371
+
0, sec_irq_chip, &sec_irq_chip_data);
459
372
if (ret)
460
-
return dev_err_probe(sec_pmic->dev, ret,
461
-
"Failed to add %s IRQ chip\n",
462
-
sec_irq_chip->name);
373
+
return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n",
374
+
sec_irq_chip->name);
463
375
464
-
/*
465
-
* The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
466
-
* so the interrupt number must be consistent.
467
-
*/
468
-
BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
469
-
470
-
return 0;
376
+
return sec_irq_chip_data;
471
377
}
+1073
-113
drivers/regulator/s2mps11.c
+1073
-113
drivers/regulator/s2mps11.c
···
3
3
// Copyright (c) 2012-2014 Samsung Electronics Co., Ltd
4
4
// http://www.samsung.com
5
5
6
+
#include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
6
7
#include <linux/bug.h>
7
8
#include <linux/cleanup.h>
8
9
#include <linux/err.h>
···
17
16
#include <linux/regulator/machine.h>
18
17
#include <linux/regulator/of_regulator.h>
19
18
#include <linux/mfd/samsung/core.h>
19
+
#include <linux/mfd/samsung/s2mpg10.h>
20
+
#include <linux/mfd/samsung/s2mpg11.h>
20
21
#include <linux/mfd/samsung/s2mps11.h>
21
22
#include <linux/mfd/samsung/s2mps13.h>
22
23
#include <linux/mfd/samsung/s2mps14.h>
23
24
#include <linux/mfd/samsung/s2mps15.h>
24
25
#include <linux/mfd/samsung/s2mpu02.h>
25
26
#include <linux/mfd/samsung/s2mpu05.h>
27
+
28
+
enum {
29
+
S2MPG10_REGULATOR_OPS_STD,
30
+
S2MPG10_REGULATOR_OPS_EXTCONTROL,
31
+
};
26
32
27
33
/* The highest number of possible regulators for supported devices. */
28
34
#define S2MPS_REGULATOR_MAX S2MPS13_REGULATOR_MAX
···
48
40
* the suspend mode was enabled.
49
41
*/
50
42
DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX);
43
+
};
51
44
52
-
/*
53
-
* Array (size: number of regulators) with GPIO-s for external
54
-
* sleep control.
55
-
*/
56
-
struct gpio_desc **ext_control_gpiod;
45
+
#define to_s2mpg10_regulator_desc(x) container_of((x), struct s2mpg10_regulator_desc, desc)
46
+
47
+
struct s2mpg10_regulator_desc {
48
+
struct regulator_desc desc;
49
+
50
+
/* Ramp rate during enable, valid for bucks only. */
51
+
unsigned int enable_ramp_rate;
52
+
53
+
/* Registers for external control of rail. */
54
+
unsigned int pctrlsel_reg;
55
+
unsigned int pctrlsel_mask;
56
+
/* Populated from DT. */
57
+
unsigned int pctrlsel_val;
57
58
};
58
59
59
60
static int get_ramp_delay(int ramp_delay)
···
261
244
case S2MPS14X:
262
245
if (test_bit(rdev_id, s2mps11->suspend_state))
263
246
val = S2MPS14_ENABLE_SUSPEND;
264
-
else if (s2mps11->ext_control_gpiod[rdev_id])
247
+
else if (rdev->ena_pin)
265
248
val = S2MPS14_ENABLE_EXT_CONTROL;
266
249
else
267
250
val = rdev->desc->enable_mask;
···
351
334
rdev->desc->enable_mask, state);
352
335
}
353
336
337
+
static int s2mps11_of_parse_gpiod(struct device_node *np,
338
+
const char *con_id, bool optional,
339
+
const struct regulator_desc *desc,
340
+
struct regulator_config *config)
341
+
{
342
+
struct gpio_desc *ena_gpiod;
343
+
int ret;
344
+
345
+
ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), con_id, 0,
346
+
GPIOD_OUT_HIGH |
347
+
GPIOD_FLAGS_BIT_NONEXCLUSIVE,
348
+
desc->name
349
+
? : dev_name(config->dev));
350
+
if (IS_ERR(ena_gpiod)) {
351
+
ret = PTR_ERR(ena_gpiod);
352
+
353
+
/* Ignore all errors except probe defer. */
354
+
if (ret == -EPROBE_DEFER)
355
+
return ret;
356
+
357
+
if (ret == -ENOENT) {
358
+
if (optional)
359
+
return 0;
360
+
361
+
dev_info(config->dev,
362
+
"No entry for control GPIO for %d/%s in node %pOF\n",
363
+
desc->id, desc->name, np);
364
+
} else {
365
+
dev_warn_probe(config->dev, ret,
366
+
"Failed to get control GPIO for %d/%s in node %pOF\n",
367
+
desc->id, desc->name, np);
368
+
}
369
+
370
+
return 0;
371
+
}
372
+
373
+
dev_info(config->dev, "Using GPIO for ext-control over %d/%s\n",
374
+
desc->id, desc->name);
375
+
376
+
config->ena_gpiod = ena_gpiod;
377
+
378
+
return 0;
379
+
}
380
+
381
+
static int s2mps11_of_parse_cb(struct device_node *np,
382
+
const struct regulator_desc *desc,
383
+
struct regulator_config *config)
384
+
{
385
+
const struct s2mps11_info *s2mps11 = config->driver_data;
386
+
387
+
if (s2mps11->dev_type == S2MPS14X)
388
+
switch (desc->id) {
389
+
case S2MPS14_LDO10:
390
+
case S2MPS14_LDO11:
391
+
case S2MPS14_LDO12:
392
+
break;
393
+
394
+
default:
395
+
return 0;
396
+
}
397
+
else
398
+
return 0;
399
+
400
+
return s2mps11_of_parse_gpiod(np, "samsung,ext-control", false, desc,
401
+
config);
402
+
}
403
+
404
+
static int s2mpg10_of_parse_cb(struct device_node *np,
405
+
const struct regulator_desc *desc,
406
+
struct regulator_config *config)
407
+
{
408
+
const struct s2mps11_info *s2mps11 = config->driver_data;
409
+
struct s2mpg10_regulator_desc *s2mpg10_desc = to_s2mpg10_regulator_desc(desc);
410
+
static const u32 ext_control_s2mpg10[] = {
411
+
[S2MPG10_EXTCTRL_PWREN] = S2MPG10_PCTRLSEL_PWREN,
412
+
[S2MPG10_EXTCTRL_PWREN_MIF] = S2MPG10_PCTRLSEL_PWREN_MIF,
413
+
[S2MPG10_EXTCTRL_AP_ACTIVE_N] = S2MPG10_PCTRLSEL_AP_ACTIVE_N,
414
+
[S2MPG10_EXTCTRL_CPUCL1_EN] = S2MPG10_PCTRLSEL_CPUCL1_EN,
415
+
[S2MPG10_EXTCTRL_CPUCL1_EN2] = S2MPG10_PCTRLSEL_CPUCL1_EN2,
416
+
[S2MPG10_EXTCTRL_CPUCL2_EN] = S2MPG10_PCTRLSEL_CPUCL2_EN,
417
+
[S2MPG10_EXTCTRL_CPUCL2_EN2] = S2MPG10_PCTRLSEL_CPUCL2_EN2,
418
+
[S2MPG10_EXTCTRL_TPU_EN] = S2MPG10_PCTRLSEL_TPU_EN,
419
+
[S2MPG10_EXTCTRL_TPU_EN2] = S2MPG10_PCTRLSEL_TPU_EN2,
420
+
[S2MPG10_EXTCTRL_TCXO_ON] = S2MPG10_PCTRLSEL_TCXO_ON,
421
+
[S2MPG10_EXTCTRL_TCXO_ON2] = S2MPG10_PCTRLSEL_TCXO_ON2,
422
+
[S2MPG10_EXTCTRL_LDO20M_EN2] = S2MPG10_PCTRLSEL_LDO20M_EN2,
423
+
[S2MPG10_EXTCTRL_LDO20M_EN] = S2MPG10_PCTRLSEL_LDO20M_EN,
424
+
};
425
+
static const u32 ext_control_s2mpg11[] = {
426
+
[S2MPG11_EXTCTRL_PWREN] = S2MPG10_PCTRLSEL_PWREN,
427
+
[S2MPG11_EXTCTRL_PWREN_MIF] = S2MPG10_PCTRLSEL_PWREN_MIF,
428
+
[S2MPG11_EXTCTRL_AP_ACTIVE_N] = S2MPG10_PCTRLSEL_AP_ACTIVE_N,
429
+
[S2MPG11_EXTCTRL_G3D_EN] = S2MPG10_PCTRLSEL_CPUCL1_EN,
430
+
[S2MPG11_EXTCTRL_G3D_EN2] = S2MPG10_PCTRLSEL_CPUCL1_EN2,
431
+
[S2MPG11_EXTCTRL_AOC_VDD] = S2MPG10_PCTRLSEL_CPUCL2_EN,
432
+
[S2MPG11_EXTCTRL_AOC_RET] = S2MPG10_PCTRLSEL_CPUCL2_EN2,
433
+
[S2MPG11_EXTCTRL_UFS_EN] = S2MPG10_PCTRLSEL_TPU_EN,
434
+
[S2MPG11_EXTCTRL_LDO13S_EN] = S2MPG10_PCTRLSEL_TPU_EN2,
435
+
};
436
+
u32 ext_control;
437
+
438
+
if (s2mps11->dev_type != S2MPG10 && s2mps11->dev_type != S2MPG11)
439
+
return 0;
440
+
441
+
if (of_property_read_u32(np, "samsung,ext-control", &ext_control))
442
+
return 0;
443
+
444
+
switch (s2mps11->dev_type) {
445
+
case S2MPG10:
446
+
switch (desc->id) {
447
+
case S2MPG10_BUCK1 ... S2MPG10_BUCK7:
448
+
case S2MPG10_BUCK10:
449
+
case S2MPG10_LDO3 ... S2MPG10_LDO19:
450
+
if (ext_control > S2MPG10_EXTCTRL_TCXO_ON2)
451
+
return -EINVAL;
452
+
break;
453
+
454
+
case S2MPG10_LDO20:
455
+
if (ext_control < S2MPG10_EXTCTRL_LDO20M_EN2 ||
456
+
ext_control > S2MPG10_EXTCTRL_LDO20M_EN)
457
+
return -EINVAL;
458
+
break;
459
+
460
+
default:
461
+
return -EINVAL;
462
+
}
463
+
464
+
if (ext_control > ARRAY_SIZE(ext_control_s2mpg10))
465
+
return -EINVAL;
466
+
ext_control = ext_control_s2mpg10[ext_control];
467
+
break;
468
+
469
+
case S2MPG11:
470
+
switch (desc->id) {
471
+
case S2MPG11_BUCK1 ... S2MPG11_BUCK3:
472
+
case S2MPG11_BUCK5:
473
+
case S2MPG11_BUCK8:
474
+
case S2MPG11_BUCK9:
475
+
case S2MPG11_BUCKD:
476
+
case S2MPG11_BUCKA:
477
+
case S2MPG11_LDO1:
478
+
case S2MPG11_LDO2:
479
+
case S2MPG11_LDO8:
480
+
case S2MPG11_LDO13:
481
+
if (ext_control > S2MPG11_EXTCTRL_LDO13S_EN)
482
+
return -EINVAL;
483
+
break;
484
+
485
+
default:
486
+
return -EINVAL;
487
+
}
488
+
489
+
if (ext_control > ARRAY_SIZE(ext_control_s2mpg11))
490
+
return -EINVAL;
491
+
ext_control = ext_control_s2mpg11[ext_control];
492
+
break;
493
+
494
+
default:
495
+
return -EINVAL;
496
+
}
497
+
498
+
/*
499
+
* If the regulator should be configured for external control, then:
500
+
* 1) the PCTRLSELx register needs to be set accordingly
501
+
* 2) regulator_desc::enable_val needs to be:
502
+
* a) updated and
503
+
* b) written to the hardware
504
+
* 3) we switch to the ::ops that provide an empty ::enable() and no
505
+
* ::disable() implementations
506
+
*
507
+
* Points 1) and 2b) will be handled in _probe(), after
508
+
* devm_regulator_register() returns, so that we can properly act on
509
+
* failures, since the regulator core ignores most return values from
510
+
* this parse callback.
511
+
*/
512
+
s2mpg10_desc->pctrlsel_val = ext_control;
513
+
s2mpg10_desc->pctrlsel_val <<= (ffs(s2mpg10_desc->pctrlsel_mask) - 1);
514
+
515
+
s2mpg10_desc->desc.enable_val = S2MPG10_PMIC_CTRL_ENABLE_EXT;
516
+
s2mpg10_desc->desc.enable_val <<= (ffs(desc->enable_mask) - 1);
517
+
518
+
++s2mpg10_desc->desc.ops;
519
+
520
+
return s2mps11_of_parse_gpiod(np, "enable", true, desc, config);
521
+
}
522
+
523
+
static int s2mpg10_enable_ext_control(struct s2mps11_info *s2mps11,
524
+
struct regulator_dev *rdev)
525
+
{
526
+
const struct s2mpg10_regulator_desc *s2mpg10_desc;
527
+
int ret;
528
+
529
+
switch (s2mps11->dev_type) {
530
+
case S2MPG10:
531
+
case S2MPG11:
532
+
s2mpg10_desc = to_s2mpg10_regulator_desc(rdev->desc);
533
+
break;
534
+
535
+
default:
536
+
return 0;
537
+
}
538
+
539
+
ret = regmap_update_bits(rdev_get_regmap(rdev),
540
+
s2mpg10_desc->pctrlsel_reg,
541
+
s2mpg10_desc->pctrlsel_mask,
542
+
s2mpg10_desc->pctrlsel_val);
543
+
if (ret)
544
+
return dev_err_probe(rdev_get_dev(rdev), ret,
545
+
"failed to configure pctrlsel for %s\n",
546
+
rdev->desc->name);
547
+
548
+
/*
549
+
* When using external control, the enable bit of the regulator still
550
+
* needs to be set. The actual state will still be determined by the
551
+
* external signal.
552
+
*/
553
+
ret = regulator_enable_regmap(rdev);
554
+
if (ret)
555
+
return dev_err_probe(rdev_get_dev(rdev), ret,
556
+
"failed to enable regulator %s\n",
557
+
rdev->desc->name);
558
+
559
+
return 0;
560
+
}
561
+
562
+
static int s2mpg10_regulator_enable_nop(struct regulator_dev *rdev)
563
+
{
564
+
/*
565
+
* We need to provide this, otherwise the regulator core's enable on
566
+
* this regulator will return a failure and subsequently disable our
567
+
* parent regulator.
568
+
*/
569
+
return 0;
570
+
}
571
+
572
+
static int s2mpg10_regulator_buck_enable_time(struct regulator_dev *rdev)
573
+
{
574
+
const struct s2mpg10_regulator_desc * const s2mpg10_desc =
575
+
to_s2mpg10_regulator_desc(rdev->desc);
576
+
const struct regulator_ops * const ops = rdev->desc->ops;
577
+
int vsel, curr_uV;
578
+
579
+
vsel = ops->get_voltage_sel(rdev);
580
+
if (vsel < 0)
581
+
return vsel;
582
+
583
+
curr_uV = ops->list_voltage(rdev, vsel);
584
+
if (curr_uV < 0)
585
+
return curr_uV;
586
+
587
+
return (rdev->desc->enable_time
588
+
+ DIV_ROUND_UP(curr_uV, s2mpg10_desc->enable_ramp_rate));
589
+
}
590
+
591
+
static int s2mpg1x_regulator_buck_set_voltage_time(struct regulator_dev *rdev,
592
+
int old_uV, int new_uV,
593
+
unsigned int ramp_reg,
594
+
unsigned int ramp_mask)
595
+
{
596
+
unsigned int ramp_sel, ramp_rate;
597
+
int ret;
598
+
599
+
if (old_uV == new_uV)
600
+
return 0;
601
+
602
+
ret = regmap_read(rdev->regmap, ramp_reg, &ramp_sel);
603
+
if (ret)
604
+
return ret;
605
+
606
+
ramp_sel &= ramp_mask;
607
+
ramp_sel >>= ffs(ramp_mask) - 1;
608
+
if (ramp_sel >= rdev->desc->n_ramp_values ||
609
+
!rdev->desc->ramp_delay_table)
610
+
return -EINVAL;
611
+
612
+
ramp_rate = rdev->desc->ramp_delay_table[ramp_sel];
613
+
614
+
return DIV_ROUND_UP(abs(new_uV - old_uV), ramp_rate);
615
+
}
616
+
617
+
static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *rdev,
618
+
int old_uV, int new_uV)
619
+
{
620
+
unsigned int ramp_reg;
621
+
622
+
ramp_reg = rdev->desc->ramp_reg;
623
+
if (old_uV > new_uV)
624
+
/* The downwards ramp is at a different offset. */
625
+
ramp_reg += S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1;
626
+
627
+
return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV,
628
+
ramp_reg,
629
+
rdev->desc->ramp_mask);
630
+
}
631
+
632
+
static int s2mpg11_regulator_buck_set_voltage_time(struct regulator_dev *rdev,
633
+
int old_uV, int new_uV)
634
+
{
635
+
unsigned int ramp_mask;
636
+
637
+
ramp_mask = rdev->desc->ramp_mask;
638
+
if (old_uV > new_uV)
639
+
/* The downwards mask is at a different position. */
640
+
ramp_mask >>= 2;
641
+
642
+
return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV,
643
+
rdev->desc->ramp_reg,
644
+
ramp_mask);
645
+
}
646
+
647
+
/*
648
+
* We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), because
649
+
* only if the latter is != NULL, the regulator core will call neither during
650
+
* DVS if the regulator is disabled. If the latter is NULL, the core always
651
+
* calls the ::set_voltage_time() callback, which would give incorrect results
652
+
* if the regulator is off.
653
+
* At the same time, we do need ::set_voltage_time() due to differing upwards
654
+
* and downwards ramps and we can not make that code dependent on the regulator
655
+
* enable state, as that would break regulator_set_voltage_time() which
656
+
* expects a correct result no matter the enable state.
657
+
*/
658
+
static const struct regulator_ops s2mpg10_reg_buck_ops[] = {
659
+
[S2MPG10_REGULATOR_OPS_STD] = {
660
+
.list_voltage = regulator_list_voltage_linear_range,
661
+
.map_voltage = regulator_map_voltage_linear_range,
662
+
.is_enabled = regulator_is_enabled_regmap,
663
+
.enable = regulator_enable_regmap,
664
+
.disable = regulator_disable_regmap,
665
+
.enable_time = s2mpg10_regulator_buck_enable_time,
666
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
667
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
668
+
.set_voltage_time = s2mpg10_regulator_buck_set_voltage_time,
669
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
670
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
671
+
},
672
+
[S2MPG10_REGULATOR_OPS_EXTCONTROL] = {
673
+
.list_voltage = regulator_list_voltage_linear_range,
674
+
.map_voltage = regulator_map_voltage_linear_range,
675
+
.enable = s2mpg10_regulator_enable_nop,
676
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
677
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
678
+
.set_voltage_time = s2mpg10_regulator_buck_set_voltage_time,
679
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
680
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
681
+
}
682
+
};
683
+
684
+
#define s2mpg10_buck_to_ramp_mask(n) (GENMASK(1, 0) << (((n) % 4) * 2))
685
+
686
+
/*
687
+
* The ramp_delay during enable is fixed (12.5mV/μs), while the ramp during
688
+
* DVS can be adjusted. Linux can adjust the ramp delay via DT, in which case
689
+
* the regulator core will modify the regulator's constraints and call our
690
+
* .set_ramp_delay() which updates the DVS ramp in ramp_reg.
691
+
* For enable, our .enable_time() unconditionally uses enable_ramp_rate
692
+
* (12.5mV/μs) while our ::set_voltage_time() takes the value in ramp_reg
693
+
* into account.
694
+
*/
695
+
#define regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, _ops, \
696
+
_vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \
697
+
_r_reg, _r_mask, _r_table, _r_table_sz, \
698
+
_en_time) { \
699
+
.name = "buck" _name, \
700
+
.supply_name = _supply, \
701
+
.of_match = of_match_ptr("buck" _name), \
702
+
.regulators_node = of_match_ptr("regulators"), \
703
+
.of_parse_cb = s2mpg10_of_parse_cb, \
704
+
.id = _id, \
705
+
.ops = &(_ops)[0], \
706
+
.type = REGULATOR_VOLTAGE, \
707
+
.owner = THIS_MODULE, \
708
+
.linear_ranges = _vrange, \
709
+
.n_linear_ranges = ARRAY_SIZE(_vrange), \
710
+
.n_voltages = _vrange##_count, \
711
+
.vsel_reg = _vsel_reg, \
712
+
.vsel_mask = _vsel_mask, \
713
+
.enable_reg = _en_reg, \
714
+
.enable_mask = _en_mask, \
715
+
.ramp_reg = _r_reg, \
716
+
.ramp_mask = _r_mask, \
717
+
.ramp_delay_table = _r_table, \
718
+
.n_ramp_values = _r_table_sz, \
719
+
.enable_time = _en_time, /* + V/enable_ramp_rate */ \
720
+
}
721
+
722
+
#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) \
723
+
regulator_desc_s2mpg1x_buck_cmn(#_num "m", S2MPG10_BUCK##_num, \
724
+
"vinb"#_num "m", s2mpg10_reg_buck_ops, _vrange, \
725
+
S2MPG10_PMIC_B##_num##M_OUT1, GENMASK(7, 0), \
726
+
S2MPG10_PMIC_B##_num##M_CTRL, GENMASK(7, 6), \
727
+
S2MPG10_PMIC_##_r_reg, \
728
+
s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \
729
+
- S2MPG10_BUCK1), \
730
+
s2mpg10_buck_ramp_table, \
731
+
ARRAY_SIZE(s2mpg10_buck_ramp_table), 30)
732
+
733
+
#define s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg) \
734
+
.desc = regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg), \
735
+
.enable_ramp_rate = 12500
736
+
737
+
#define s2mpg10_regulator_desc_buck_gpio(_num, _vrange, _r_reg, \
738
+
_pc_reg, _pc_mask) \
739
+
[S2MPG10_BUCK##_num] = { \
740
+
s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \
741
+
.pctrlsel_reg = S2MPG10_PMIC_##_pc_reg, \
742
+
.pctrlsel_mask = _pc_mask, \
743
+
}
744
+
745
+
#define s2mpg10_regulator_desc_buck(_num, _vrange, _r_reg) \
746
+
[S2MPG10_BUCK##_num] = { \
747
+
s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \
748
+
}
749
+
750
+
/* ops for S2MPG1x LDO regulators without ramp control */
751
+
static const struct regulator_ops s2mpg10_reg_ldo_ops[] = {
752
+
[S2MPG10_REGULATOR_OPS_STD] = {
753
+
.list_voltage = regulator_list_voltage_linear_range,
754
+
.map_voltage = regulator_map_voltage_linear_range,
755
+
.is_enabled = regulator_is_enabled_regmap,
756
+
.enable = regulator_enable_regmap,
757
+
.disable = regulator_disable_regmap,
758
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
759
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
760
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
761
+
},
762
+
[S2MPG10_REGULATOR_OPS_EXTCONTROL] = {
763
+
.list_voltage = regulator_list_voltage_linear_range,
764
+
.map_voltage = regulator_map_voltage_linear_range,
765
+
.enable = s2mpg10_regulator_enable_nop,
766
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
767
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
768
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
769
+
}
770
+
};
771
+
772
+
/* ops for S2MPG1x LDO regulators that have ramp control */
773
+
static const struct regulator_ops s2mpg10_reg_ldo_ramp_ops[] = {
774
+
[S2MPG10_REGULATOR_OPS_STD] = {
775
+
.list_voltage = regulator_list_voltage_linear_range,
776
+
.map_voltage = regulator_map_voltage_linear_range,
777
+
.is_enabled = regulator_is_enabled_regmap,
778
+
.enable = regulator_enable_regmap,
779
+
.disable = regulator_disable_regmap,
780
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
781
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
782
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
783
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
784
+
},
785
+
[S2MPG10_REGULATOR_OPS_EXTCONTROL] = {
786
+
.list_voltage = regulator_list_voltage_linear_range,
787
+
.map_voltage = regulator_map_voltage_linear_range,
788
+
.enable = s2mpg10_regulator_enable_nop,
789
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
790
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
791
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
792
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
793
+
}
794
+
};
795
+
796
+
#define regulator_desc_s2mpg1x_ldo_cmn(_name, _id, _supply, _ops, \
797
+
_vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \
798
+
_ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz) { \
799
+
.name = "ldo" _name, \
800
+
.supply_name = _supply, \
801
+
.of_match = of_match_ptr("ldo" _name), \
802
+
.regulators_node = of_match_ptr("regulators"), \
803
+
.of_parse_cb = s2mpg10_of_parse_cb, \
804
+
.id = _id, \
805
+
.ops = &(_ops)[0], \
806
+
.type = REGULATOR_VOLTAGE, \
807
+
.owner = THIS_MODULE, \
808
+
.linear_ranges = _vrange, \
809
+
.n_linear_ranges = ARRAY_SIZE(_vrange), \
810
+
.n_voltages = _vrange##_count, \
811
+
.vsel_reg = _vsel_reg, \
812
+
.vsel_mask = _vsel_mask, \
813
+
.enable_reg = _en_reg, \
814
+
.enable_mask = _en_mask, \
815
+
.ramp_delay = _ramp_delay, \
816
+
.ramp_reg = _r_reg, \
817
+
.ramp_mask = _r_mask, \
818
+
.ramp_delay_table = _r_table, \
819
+
.n_ramp_values = _r_table_sz, \
820
+
.enable_time = 130, /* startup 20+-10 + ramp 30..100μs */ \
821
+
}
822
+
823
+
#define s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _ops, _vrange, \
824
+
_vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \
825
+
_ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \
826
+
_pc_reg, _pc_mask) \
827
+
[S2MPG10_LDO##_num] = { \
828
+
.desc = regulator_desc_s2mpg1x_ldo_cmn(#_num "m", \
829
+
S2MPG10_LDO##_num, _supply, _ops, \
830
+
_vrange, \
831
+
S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \
832
+
_vsel_mask, \
833
+
S2MPG10_PMIC_##_en_reg, _en_mask, \
834
+
_ramp_delay, _r_reg, _r_mask, _r_table, \
835
+
_r_table_sz), \
836
+
.pctrlsel_reg = _pc_reg, \
837
+
.pctrlsel_mask = _pc_mask, \
838
+
}
839
+
840
+
/* standard LDO via LxM_CTRL */
841
+
#define s2mpg10_regulator_desc_ldo(_num, _supply, _vrange) \
842
+
s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \
843
+
s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \
844
+
L##_num##M_CTRL, BIT(7), \
845
+
0, 0, 0, NULL, 0, \
846
+
0, 0)
847
+
848
+
/* standard LDO but possibly GPIO controlled */
849
+
#define s2mpg10_regulator_desc_ldo_gpio(_num, _supply, _vrange, \
850
+
_pc_reg, _pc_mask) \
851
+
s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \
852
+
s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \
853
+
L##_num##M_CTRL, GENMASK(7, 6), \
854
+
0, 0, 0, NULL, 0, \
855
+
S2MPG10_PMIC_##_pc_reg, _pc_mask)
856
+
857
+
/* LDO with ramp support and possibly GPIO controlled */
858
+
#define s2mpg10_regulator_desc_ldo_ramp(_num, _supply, _vrange, \
859
+
_en_mask, _r_reg, _pc_reg, _pc_mask) \
860
+
s2mpg10_regulator_desc_ldo_cmn(_num, _supply, \
861
+
s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \
862
+
LDO_CTRL2, _en_mask, \
863
+
6250, S2MPG10_PMIC_##_r_reg, GENMASK(1, 0), \
864
+
s2mpg10_ldo_ramp_table, \
865
+
ARRAY_SIZE(s2mpg10_ldo_ramp_table), \
866
+
S2MPG10_PMIC_##_pc_reg, _pc_mask)
867
+
868
+
#define S2MPG10_VOLTAGE_RANGE(_prefix, _idx, _offs_uV, _min_uV, \
869
+
_max_uV, _step_uV) \
870
+
static const struct linear_range _prefix##_vranges##_idx[] = { \
871
+
REGULATOR_LINEAR_VRANGE(_offs_uV, _min_uV, _max_uV, _step_uV) \
872
+
}; \
873
+
static const unsigned int _prefix##_vranges##_idx##_count = \
874
+
((((_max_uV) - (_offs_uV)) / (_step_uV)) + 1)
875
+
876
+
/* voltage range for s2mpg10 BUCK 1, 2, 3, 4, 5, 7, 8, 9, 10 */
877
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 1, 200000, 450000, 1300000, STEP_6_25_MV);
878
+
879
+
/* voltage range for s2mpg10 BUCK 6 */
880
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 6, 200000, 450000, 1350000, STEP_6_25_MV);
881
+
882
+
static const unsigned int s2mpg10_buck_ramp_table[] = {
883
+
6250, 12500, 25000
884
+
};
885
+
886
+
/* voltage range for s2mpg10 LDO 1, 11, 12 */
887
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 1, 300000, 700000, 1300000, STEP_12_5_MV);
888
+
889
+
/* voltage range for s2mpg10 LDO 2, 4, 9, 14, 18, 19, 20, 23, 25, 29, 30, 31 */
890
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 2, 700000, 1600000, 1950000, STEP_25_MV);
891
+
892
+
/* voltage range for s2mpg10 LDO 3, 5, 6, 8, 16, 17, 24, 28 */
893
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 3, 725000, 725000, 1300000, STEP_12_5_MV);
894
+
895
+
/* voltage range for s2mpg10 LDO 7 */
896
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 7, 300000, 450000, 1300000, STEP_12_5_MV);
897
+
898
+
/* voltage range for s2mpg10 LDO 13, 15 */
899
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 13, 300000, 450000, 950000, STEP_12_5_MV);
900
+
901
+
/* voltage range for s2mpg10 LDO 10 */
902
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 10, 1800000, 1800000, 3350000, STEP_25_MV);
903
+
904
+
/* voltage range for s2mpg10 LDO 21, 22, 26, 27 */
905
+
S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 21, 1800000, 2500000, 3300000, STEP_25_MV);
906
+
907
+
/* possible ramp values for s2mpg10 LDO 1, 7, 11, 12, 13, 15 */
908
+
static const unsigned int s2mpg10_ldo_ramp_table[] = {
909
+
6250, 12500
910
+
};
911
+
912
+
static const struct s2mpg10_regulator_desc s2mpg10_regulators[] = {
913
+
s2mpg10_regulator_desc_buck_gpio(1, s2mpg10_buck_vranges1, DVS_RAMP1,
914
+
PCTRLSEL1, GENMASK(3, 0)),
915
+
s2mpg10_regulator_desc_buck_gpio(2, s2mpg10_buck_vranges1, DVS_RAMP1,
916
+
PCTRLSEL1, GENMASK(7, 4)),
917
+
s2mpg10_regulator_desc_buck_gpio(3, s2mpg10_buck_vranges1, DVS_RAMP1,
918
+
PCTRLSEL2, GENMASK(3, 0)),
919
+
s2mpg10_regulator_desc_buck_gpio(4, s2mpg10_buck_vranges1, DVS_RAMP1,
920
+
PCTRLSEL2, GENMASK(7, 4)),
921
+
s2mpg10_regulator_desc_buck_gpio(5, s2mpg10_buck_vranges1, DVS_RAMP2,
922
+
PCTRLSEL3, GENMASK(3, 0)),
923
+
s2mpg10_regulator_desc_buck_gpio(6, s2mpg10_buck_vranges6, DVS_RAMP2,
924
+
PCTRLSEL3, GENMASK(7, 4)),
925
+
s2mpg10_regulator_desc_buck_gpio(7, s2mpg10_buck_vranges1, DVS_RAMP2,
926
+
PCTRLSEL4, GENMASK(3, 0)),
927
+
s2mpg10_regulator_desc_buck(8, s2mpg10_buck_vranges1, DVS_RAMP2),
928
+
s2mpg10_regulator_desc_buck(9, s2mpg10_buck_vranges1, DVS_RAMP3),
929
+
s2mpg10_regulator_desc_buck_gpio(10, s2mpg10_buck_vranges1, DVS_RAMP3,
930
+
PCTRLSEL4, GENMASK(7, 4)),
931
+
/*
932
+
* Standard LDO via LxM_CTRL but non-standard (greater) V-range and with
933
+
* ramp support.
934
+
*/
935
+
s2mpg10_regulator_desc_ldo_cmn(1, "vinl3m", s2mpg10_reg_ldo_ramp_ops,
936
+
s2mpg10_ldo_vranges1,
937
+
CTRL, GENMASK(6, 0),
938
+
L1M_CTRL, BIT(7),
939
+
6250, S2MPG10_PMIC_DVS_RAMP6,
940
+
GENMASK(5, 4), s2mpg10_ldo_ramp_table,
941
+
ARRAY_SIZE(s2mpg10_ldo_ramp_table),
942
+
0, 0),
943
+
s2mpg10_regulator_desc_ldo(2, "vinl9m", s2mpg10_ldo_vranges2),
944
+
s2mpg10_regulator_desc_ldo_gpio(3, "vinl4m", s2mpg10_ldo_vranges3,
945
+
PCTRLSEL5, GENMASK(3, 0)),
946
+
s2mpg10_regulator_desc_ldo_gpio(4, "vinl9m", s2mpg10_ldo_vranges2,
947
+
PCTRLSEL5, GENMASK(7, 4)),
948
+
s2mpg10_regulator_desc_ldo_gpio(5, "vinl3m", s2mpg10_ldo_vranges3,
949
+
PCTRLSEL6, GENMASK(3, 0)),
950
+
s2mpg10_regulator_desc_ldo_gpio(6, "vinl7m", s2mpg10_ldo_vranges3,
951
+
PCTRLSEL6, GENMASK(7, 4)),
952
+
/*
953
+
* Ramp support, possibly GPIO controlled, non-standard (greater) V-
954
+
* range and enable reg & mask.
955
+
*/
956
+
s2mpg10_regulator_desc_ldo_cmn(7, "vinl3m", s2mpg10_reg_ldo_ramp_ops,
957
+
s2mpg10_ldo_vranges7,
958
+
CTRL, GENMASK(6, 0),
959
+
LDO_CTRL1, GENMASK(4, 3),
960
+
6250, S2MPG10_PMIC_DVS_RAMP6,
961
+
GENMASK(7, 6), s2mpg10_ldo_ramp_table,
962
+
ARRAY_SIZE(s2mpg10_ldo_ramp_table),
963
+
S2MPG10_PMIC_PCTRLSEL7, GENMASK(3, 0)),
964
+
s2mpg10_regulator_desc_ldo_gpio(8, "vinl4m", s2mpg10_ldo_vranges3,
965
+
PCTRLSEL7, GENMASK(7, 4)),
966
+
s2mpg10_regulator_desc_ldo_gpio(9, "vinl10m", s2mpg10_ldo_vranges2,
967
+
PCTRLSEL8, GENMASK(3, 0)),
968
+
s2mpg10_regulator_desc_ldo_gpio(10, "vinl15m", s2mpg10_ldo_vranges10,
969
+
PCTRLSEL8, GENMASK(7, 4)),
970
+
s2mpg10_regulator_desc_ldo_ramp(11, "vinl7m", s2mpg10_ldo_vranges1,
971
+
GENMASK(1, 0), DVS_SYNC_CTRL3,
972
+
PCTRLSEL9, GENMASK(3, 0)),
973
+
s2mpg10_regulator_desc_ldo_ramp(12, "vinl8m", s2mpg10_ldo_vranges1,
974
+
GENMASK(3, 2), DVS_SYNC_CTRL4,
975
+
PCTRLSEL9, GENMASK(7, 4)),
976
+
s2mpg10_regulator_desc_ldo_ramp(13, "vinl1m", s2mpg10_ldo_vranges13,
977
+
GENMASK(5, 4), DVS_SYNC_CTRL5,
978
+
PCTRLSEL10, GENMASK(3, 0)),
979
+
s2mpg10_regulator_desc_ldo_gpio(14, "vinl10m", s2mpg10_ldo_vranges2,
980
+
PCTRLSEL10, GENMASK(7, 4)),
981
+
s2mpg10_regulator_desc_ldo_ramp(15, "vinl2m", s2mpg10_ldo_vranges13,
982
+
GENMASK(7, 6), DVS_SYNC_CTRL6,
983
+
PCTRLSEL11, GENMASK(3, 0)),
984
+
s2mpg10_regulator_desc_ldo_gpio(16, "vinl5m", s2mpg10_ldo_vranges3,
985
+
PCTRLSEL11, GENMASK(7, 4)),
986
+
s2mpg10_regulator_desc_ldo_gpio(17, "vinl6m", s2mpg10_ldo_vranges3,
987
+
PCTRLSEL12, GENMASK(3, 0)),
988
+
s2mpg10_regulator_desc_ldo_gpio(18, "vinl10m", s2mpg10_ldo_vranges2,
989
+
PCTRLSEL12, GENMASK(7, 4)),
990
+
s2mpg10_regulator_desc_ldo_gpio(19, "vinl10m", s2mpg10_ldo_vranges2,
991
+
PCTRLSEL13, GENMASK(3, 0)),
992
+
s2mpg10_regulator_desc_ldo_gpio(20, "vinl10m", s2mpg10_ldo_vranges2,
993
+
PCTRLSEL13, GENMASK(7, 4)),
994
+
s2mpg10_regulator_desc_ldo(21, "vinl14m", s2mpg10_ldo_vranges21),
995
+
s2mpg10_regulator_desc_ldo(22, "vinl15m", s2mpg10_ldo_vranges21),
996
+
s2mpg10_regulator_desc_ldo(23, "vinl11m", s2mpg10_ldo_vranges2),
997
+
s2mpg10_regulator_desc_ldo(24, "vinl7m", s2mpg10_ldo_vranges3),
998
+
s2mpg10_regulator_desc_ldo(25, "vinl10m", s2mpg10_ldo_vranges2),
999
+
s2mpg10_regulator_desc_ldo(26, "vinl15m", s2mpg10_ldo_vranges21),
1000
+
s2mpg10_regulator_desc_ldo(27, "vinl15m", s2mpg10_ldo_vranges21),
1001
+
s2mpg10_regulator_desc_ldo(28, "vinl7m", s2mpg10_ldo_vranges3),
1002
+
s2mpg10_regulator_desc_ldo(29, "vinl12m", s2mpg10_ldo_vranges2),
1003
+
s2mpg10_regulator_desc_ldo(30, "vinl13m", s2mpg10_ldo_vranges2),
1004
+
s2mpg10_regulator_desc_ldo(31, "vinl11m", s2mpg10_ldo_vranges2)
1005
+
};
1006
+
1007
+
static const struct regulator_ops s2mpg11_reg_buck_ops[] = {
1008
+
[S2MPG10_REGULATOR_OPS_STD] = {
1009
+
.list_voltage = regulator_list_voltage_linear_range,
1010
+
.map_voltage = regulator_map_voltage_linear_range,
1011
+
.is_enabled = regulator_is_enabled_regmap,
1012
+
.enable = regulator_enable_regmap,
1013
+
.disable = regulator_disable_regmap,
1014
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
1015
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
1016
+
.set_voltage_time = s2mpg11_regulator_buck_set_voltage_time,
1017
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
1018
+
.enable_time = s2mpg10_regulator_buck_enable_time,
1019
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
1020
+
},
1021
+
[S2MPG10_REGULATOR_OPS_EXTCONTROL] = {
1022
+
.list_voltage = regulator_list_voltage_linear_range,
1023
+
.map_voltage = regulator_map_voltage_linear_range,
1024
+
.enable = s2mpg10_regulator_enable_nop,
1025
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
1026
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
1027
+
.set_voltage_time = s2mpg11_regulator_buck_set_voltage_time,
1028
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
1029
+
.enable_time = s2mpg10_regulator_buck_enable_time,
1030
+
.set_ramp_delay = regulator_set_ramp_delay_regmap,
1031
+
}
1032
+
};
1033
+
1034
+
#define s2mpg11_buck_to_ramp_mask(n) (GENMASK(3, 2) << (((n) % 2) * 4))
1035
+
1036
+
#define regulator_desc_s2mpg11_buckx(_name, _id, _supply, _vrange, \
1037
+
_vsel_reg, _en_reg, _en_mask, _r_reg) \
1038
+
regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, \
1039
+
s2mpg11_reg_buck_ops, _vrange, \
1040
+
S2MPG11_PMIC_##_vsel_reg, GENMASK(7, 0), \
1041
+
S2MPG11_PMIC_##_en_reg, _en_mask, \
1042
+
S2MPG11_PMIC_##_r_reg, \
1043
+
s2mpg11_buck_to_ramp_mask(_id - S2MPG11_BUCK1), \
1044
+
s2mpg10_buck_ramp_table, \
1045
+
ARRAY_SIZE(s2mpg10_buck_ramp_table), 30)
1046
+
1047
+
#define s2mpg11_regulator_desc_buck_xm(_num, _vrange, _vsel_reg_sfx, \
1048
+
_en_mask, _r_reg, _en_rrate) \
1049
+
.desc = regulator_desc_s2mpg11_buckx(#_num"s", \
1050
+
S2MPG11_BUCK##_num, "vinb"#_num"s", \
1051
+
_vrange, \
1052
+
B##_num##S_##_vsel_reg_sfx, \
1053
+
B##_num##S_CTRL, _en_mask, \
1054
+
_r_reg), \
1055
+
.enable_ramp_rate = _en_rrate
1056
+
1057
+
#define s2mpg11_regulator_desc_buck_cm(_num, _vrange, _vsel_reg_sfx, \
1058
+
_en_mask, _r_reg) \
1059
+
[S2MPG11_BUCK##_num] = { \
1060
+
s2mpg11_regulator_desc_buck_xm(_num, _vrange, \
1061
+
_vsel_reg_sfx, _en_mask, _r_reg, 12500), \
1062
+
}
1063
+
1064
+
#define s2mpg11_regulator_desc_buckn_cm_gpio(_num, _vrange, \
1065
+
_vsel_reg_sfx, _en_mask, _r_reg, _pc_reg, _pc_mask) \
1066
+
[S2MPG11_BUCK##_num] = { \
1067
+
s2mpg11_regulator_desc_buck_xm(_num, _vrange, \
1068
+
_vsel_reg_sfx, _en_mask, _r_reg, 12500), \
1069
+
.pctrlsel_reg = S2MPG11_PMIC_##_pc_reg, \
1070
+
.pctrlsel_mask = _pc_mask, \
1071
+
}
1072
+
1073
+
#define s2mpg11_regulator_desc_buck_vm(_num, _vrange, _vsel_reg_sfx, \
1074
+
_en_mask, _r_reg) \
1075
+
[S2MPG11_BUCK##_num] = { \
1076
+
s2mpg11_regulator_desc_buck_xm(_num, _vrange, \
1077
+
_vsel_reg_sfx, _en_mask, _r_reg, 25000), \
1078
+
}
1079
+
1080
+
#define s2mpg11_regulator_desc_bucka(_num, _num_lower, _r_reg, \
1081
+
_pc_reg, _pc_mask) \
1082
+
[S2MPG11_BUCK##_num] = { \
1083
+
.desc = regulator_desc_s2mpg11_buckx(#_num_lower, \
1084
+
S2MPG11_BUCK##_num, "vinb"#_num_lower, \
1085
+
s2mpg11_buck_vranges##_num_lower, \
1086
+
BUCK##_num##_OUT, \
1087
+
BUCK##_num##_CTRL, GENMASK(7, 6), \
1088
+
_r_reg), \
1089
+
.enable_ramp_rate = 25000, \
1090
+
.pctrlsel_reg = S2MPG11_PMIC_##_pc_reg, \
1091
+
.pctrlsel_mask = _pc_mask, \
1092
+
}
1093
+
1094
+
#define s2mpg11_regulator_desc_buckboost() \
1095
+
[S2MPG11_BUCKBOOST] = { \
1096
+
.desc = regulator_desc_s2mpg1x_buck_cmn("boost", \
1097
+
S2MPG11_BUCKBOOST, "vinbb", \
1098
+
s2mpg10_reg_ldo_ops, \
1099
+
s2mpg11_buck_vrangesboost, \
1100
+
S2MPG11_PMIC_BB_OUT1, GENMASK(6, 0), \
1101
+
S2MPG11_PMIC_BB_CTRL, BIT(7), \
1102
+
0, 0, NULL, 0, 35), \
1103
+
.enable_ramp_rate = 17500, \
1104
+
}
1105
+
1106
+
#define s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _ops, \
1107
+
_vrange, _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \
1108
+
_ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \
1109
+
_pc_reg, _pc_mask) \
1110
+
[S2MPG11_LDO##_num] = { \
1111
+
.desc = regulator_desc_s2mpg1x_ldo_cmn(#_num "s", \
1112
+
S2MPG11_LDO##_num, _supply, _ops, \
1113
+
_vrange, \
1114
+
S2MPG11_PMIC_L##_num##S_##_vsel_reg_sfx, \
1115
+
_vsel_mask, \
1116
+
S2MPG11_PMIC_##_en_reg, _en_mask, \
1117
+
_ramp_delay, _r_reg, _r_mask, _r_table, \
1118
+
_r_table_sz), \
1119
+
.pctrlsel_reg = _pc_reg, \
1120
+
.pctrlsel_mask = _pc_mask, \
1121
+
}
1122
+
1123
+
/* standard LDO via LxM_CTRL */
1124
+
#define s2mpg11_regulator_desc_ldo(_num, _supply, _vrange) \
1125
+
s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \
1126
+
s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \
1127
+
L##_num##S_CTRL, BIT(7), \
1128
+
0, 0, 0, NULL, 0, \
1129
+
0, 0)
1130
+
1131
+
/* standard LDO but possibly GPIO controlled */
1132
+
#define s2mpg11_regulator_desc_ldo_gpio(_num, _supply, _vrange, \
1133
+
_pc_reg, _pc_mask) \
1134
+
s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \
1135
+
s2mpg10_reg_ldo_ops, _vrange, CTRL, GENMASK(5, 0), \
1136
+
L##_num##S_CTRL, GENMASK(7, 6), \
1137
+
0, 0, 0, NULL, 0, \
1138
+
S2MPG11_PMIC_##_pc_reg, _pc_mask)
1139
+
1140
+
/* LDO with ramp support and possibly GPIO controlled */
1141
+
#define s2mpg11_regulator_desc_ldo_ramp(_num, _supply, _vrange, \
1142
+
_en_mask, _r_reg, _pc_reg, _pc_mask) \
1143
+
s2mpg11_regulator_desc_ldo_cmn(_num, _supply, \
1144
+
s2mpg10_reg_ldo_ramp_ops, _vrange, CTRL1, GENMASK(6, 0), \
1145
+
LDO_CTRL1, _en_mask, \
1146
+
6250, S2MPG11_PMIC_##_r_reg, GENMASK(1, 0), \
1147
+
s2mpg10_ldo_ramp_table, \
1148
+
ARRAY_SIZE(s2mpg10_ldo_ramp_table), \
1149
+
S2MPG11_PMIC_##_pc_reg, _pc_mask)
1150
+
1151
+
/* voltage range for s2mpg11 BUCK 1, 2, 3, 4, 8, 9, 10 */
1152
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 1, 200000, 450000, 1300000, STEP_6_25_MV);
1153
+
1154
+
/* voltage range for s2mpg11 BUCK 5 */
1155
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 5, 200000, 400000, 1300000, STEP_6_25_MV);
1156
+
1157
+
/* voltage range for s2mpg11 BUCK 6 */
1158
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 6, 200000, 1000000, 1500000, STEP_6_25_MV);
1159
+
1160
+
/* voltage range for s2mpg11 BUCK 7 */
1161
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 7, 600000, 1500000, 2200000, STEP_12_5_MV);
1162
+
1163
+
/* voltage range for s2mpg11 BUCK D */
1164
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, d, 600000, 2400000, 3300000, STEP_12_5_MV);
1165
+
1166
+
/* voltage range for s2mpg11 BUCK A */
1167
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, a, 600000, 1700000, 2100000, STEP_12_5_MV);
1168
+
1169
+
/* voltage range for s2mpg11 BUCK BOOST */
1170
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, boost,
1171
+
2600000, 3000000, 3600000, STEP_12_5_MV);
1172
+
1173
+
/* voltage range for s2mpg11 LDO 1, 2 */
1174
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 1, 300000, 450000, 950000, STEP_12_5_MV);
1175
+
1176
+
/* voltage range for s2mpg11 LDO 3, 7, 10, 11, 12, 14, 15 */
1177
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 3, 700000, 1600000, 1950000, STEP_25_MV);
1178
+
1179
+
/* voltage range for s2mpg11 LDO 4, 6 */
1180
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 4, 1800000, 2500000, 3300000, STEP_25_MV);
1181
+
1182
+
/* voltage range for s2mpg11 LDO 5 */
1183
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 5, 1600000, 1600000, 1950000, STEP_12_5_MV);
1184
+
1185
+
/* voltage range for s2mpg11 LDO 8 */
1186
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 8, 979600, 1130400, 1281200, 5800);
1187
+
1188
+
/* voltage range for s2mpg11 LDO 9 */
1189
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 9, 725000, 725000, 1300000, STEP_12_5_MV);
1190
+
1191
+
/* voltage range for s2mpg11 LDO 13 */
1192
+
S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 13, 1800000, 1800000, 3350000, STEP_25_MV);
1193
+
1194
+
static const struct s2mpg10_regulator_desc s2mpg11_regulators[] = {
1195
+
s2mpg11_regulator_desc_buckboost(),
1196
+
s2mpg11_regulator_desc_buckn_cm_gpio(1, s2mpg11_buck_vranges1,
1197
+
OUT1, GENMASK(7, 6), DVS_RAMP1,
1198
+
PCTRLSEL1, GENMASK(3, 0)),
1199
+
s2mpg11_regulator_desc_buckn_cm_gpio(2, s2mpg11_buck_vranges1,
1200
+
OUT1, GENMASK(7, 6), DVS_RAMP1,
1201
+
PCTRLSEL1, GENMASK(7, 4)),
1202
+
s2mpg11_regulator_desc_buckn_cm_gpio(3, s2mpg11_buck_vranges1,
1203
+
OUT1, GENMASK(7, 6), DVS_RAMP2,
1204
+
PCTRLSEL2, GENMASK(3, 0)),
1205
+
s2mpg11_regulator_desc_buck_cm(4, s2mpg11_buck_vranges1,
1206
+
OUT, BIT(7), DVS_RAMP2),
1207
+
s2mpg11_regulator_desc_buckn_cm_gpio(5, s2mpg11_buck_vranges5,
1208
+
OUT, GENMASK(7, 6), DVS_RAMP3,
1209
+
PCTRLSEL2, GENMASK(7, 4)),
1210
+
s2mpg11_regulator_desc_buck_cm(6, s2mpg11_buck_vranges6,
1211
+
OUT1, BIT(7), DVS_RAMP3),
1212
+
s2mpg11_regulator_desc_buck_vm(7, s2mpg11_buck_vranges7,
1213
+
OUT1, BIT(7), DVS_RAMP4),
1214
+
s2mpg11_regulator_desc_buckn_cm_gpio(8, s2mpg11_buck_vranges1,
1215
+
OUT1, GENMASK(7, 6), DVS_RAMP4,
1216
+
PCTRLSEL3, GENMASK(3, 0)),
1217
+
s2mpg11_regulator_desc_buckn_cm_gpio(9, s2mpg11_buck_vranges1,
1218
+
OUT1, GENMASK(7, 6), DVS_RAMP5,
1219
+
PCTRLSEL3, GENMASK(7, 4)),
1220
+
s2mpg11_regulator_desc_buck_cm(10, s2mpg11_buck_vranges1,
1221
+
OUT, BIT(7), DVS_RAMP5),
1222
+
s2mpg11_regulator_desc_bucka(D, d, DVS_RAMP6, PCTRLSEL4, GENMASK(3, 0)),
1223
+
s2mpg11_regulator_desc_bucka(A, a, DVS_RAMP6, PCTRLSEL4, GENMASK(7, 4)),
1224
+
s2mpg11_regulator_desc_ldo_ramp(1, "vinl1s", s2mpg11_ldo_vranges1,
1225
+
GENMASK(5, 4), DVS_SYNC_CTRL1,
1226
+
PCTRLSEL5, GENMASK(3, 0)),
1227
+
s2mpg11_regulator_desc_ldo_ramp(2, "vinl1s", s2mpg11_ldo_vranges1,
1228
+
GENMASK(7, 6), DVS_SYNC_CTRL2,
1229
+
PCTRLSEL5, GENMASK(7, 4)),
1230
+
s2mpg11_regulator_desc_ldo(3, "vinl3s", s2mpg11_ldo_vranges3),
1231
+
s2mpg11_regulator_desc_ldo(4, "vinl5s", s2mpg11_ldo_vranges4),
1232
+
s2mpg11_regulator_desc_ldo(5, "vinl3s", s2mpg11_ldo_vranges5),
1233
+
s2mpg11_regulator_desc_ldo(6, "vinl5s", s2mpg11_ldo_vranges4),
1234
+
s2mpg11_regulator_desc_ldo(7, "vinl3s", s2mpg11_ldo_vranges3),
1235
+
s2mpg11_regulator_desc_ldo_gpio(8, "vinl2s", s2mpg11_ldo_vranges8,
1236
+
PCTRLSEL6, GENMASK(3, 0)),
1237
+
s2mpg11_regulator_desc_ldo(9, "vinl2s", s2mpg11_ldo_vranges9),
1238
+
s2mpg11_regulator_desc_ldo(10, "vinl4s", s2mpg11_ldo_vranges3),
1239
+
s2mpg11_regulator_desc_ldo(11, "vinl4s", s2mpg11_ldo_vranges3),
1240
+
s2mpg11_regulator_desc_ldo(12, "vinl4s", s2mpg11_ldo_vranges3),
1241
+
s2mpg11_regulator_desc_ldo_gpio(13, "vinl6s", s2mpg11_ldo_vranges13,
1242
+
PCTRLSEL6, GENMASK(7, 4)),
1243
+
s2mpg11_regulator_desc_ldo(14, "vinl4s", s2mpg11_ldo_vranges3),
1244
+
s2mpg11_regulator_desc_ldo(15, "vinl3s", s2mpg11_ldo_vranges3)
1245
+
};
1246
+
354
1247
static const struct regulator_ops s2mps11_ldo_ops = {
355
1248
.list_voltage = regulator_list_voltage_linear,
356
1249
.map_voltage = regulator_map_voltage_linear,
···
1289
362
#define regulator_desc_s2mps11_ldo(num, step) { \
1290
363
.name = "LDO"#num, \
1291
364
.id = S2MPS11_LDO##num, \
365
+
.of_match = of_match_ptr("LDO"#num), \
366
+
.regulators_node = of_match_ptr("regulators"), \
1292
367
.ops = &s2mps11_ldo_ops, \
1293
368
.type = REGULATOR_VOLTAGE, \
1294
369
.owner = THIS_MODULE, \
···
1307
378
#define regulator_desc_s2mps11_buck1_4(num) { \
1308
379
.name = "BUCK"#num, \
1309
380
.id = S2MPS11_BUCK##num, \
381
+
.of_match = of_match_ptr("BUCK"#num), \
382
+
.regulators_node = of_match_ptr("regulators"), \
1310
383
.ops = &s2mps11_buck_ops, \
1311
384
.type = REGULATOR_VOLTAGE, \
1312
385
.owner = THIS_MODULE, \
···
1326
395
#define regulator_desc_s2mps11_buck5 { \
1327
396
.name = "BUCK5", \
1328
397
.id = S2MPS11_BUCK5, \
398
+
.of_match = of_match_ptr("BUCK5"), \
399
+
.regulators_node = of_match_ptr("regulators"), \
1329
400
.ops = &s2mps11_buck_ops, \
1330
401
.type = REGULATOR_VOLTAGE, \
1331
402
.owner = THIS_MODULE, \
···
1345
412
#define regulator_desc_s2mps11_buck67810(num, min, step, min_sel, voltages) { \
1346
413
.name = "BUCK"#num, \
1347
414
.id = S2MPS11_BUCK##num, \
415
+
.of_match = of_match_ptr("BUCK"#num), \
416
+
.regulators_node = of_match_ptr("regulators"), \
1348
417
.ops = &s2mps11_buck_ops, \
1349
418
.type = REGULATOR_VOLTAGE, \
1350
419
.owner = THIS_MODULE, \
···
1364
429
#define regulator_desc_s2mps11_buck9 { \
1365
430
.name = "BUCK9", \
1366
431
.id = S2MPS11_BUCK9, \
432
+
.of_match = of_match_ptr("BUCK9"), \
433
+
.regulators_node = of_match_ptr("regulators"), \
1367
434
.ops = &s2mps11_buck_ops, \
1368
435
.type = REGULATOR_VOLTAGE, \
1369
436
.owner = THIS_MODULE, \
···
1439
502
#define regulator_desc_s2mps13_ldo(num, min, step, min_sel) { \
1440
503
.name = "LDO"#num, \
1441
504
.id = S2MPS13_LDO##num, \
505
+
.of_match = of_match_ptr("LDO"#num), \
506
+
.regulators_node = of_match_ptr("regulators"), \
1442
507
.ops = &s2mps14_reg_ops, \
1443
508
.type = REGULATOR_VOLTAGE, \
1444
509
.owner = THIS_MODULE, \
···
1457
518
#define regulator_desc_s2mps13_buck(num, min, step, min_sel) { \
1458
519
.name = "BUCK"#num, \
1459
520
.id = S2MPS13_BUCK##num, \
521
+
.of_match = of_match_ptr("BUCK"#num), \
522
+
.regulators_node = of_match_ptr("regulators"), \
1460
523
.ops = &s2mps14_reg_ops, \
1461
524
.type = REGULATOR_VOLTAGE, \
1462
525
.owner = THIS_MODULE, \
···
1476
535
#define regulator_desc_s2mps13_buck7(num, min, step, min_sel) { \
1477
536
.name = "BUCK"#num, \
1478
537
.id = S2MPS13_BUCK##num, \
538
+
.of_match = of_match_ptr("BUCK"#num), \
539
+
.regulators_node = of_match_ptr("regulators"), \
1479
540
.ops = &s2mps14_reg_ops, \
1480
541
.type = REGULATOR_VOLTAGE, \
1481
542
.owner = THIS_MODULE, \
···
1495
552
#define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) { \
1496
553
.name = "BUCK"#num, \
1497
554
.id = S2MPS13_BUCK##num, \
555
+
.of_match = of_match_ptr("BUCK"#num), \
556
+
.regulators_node = of_match_ptr("regulators"), \
1498
557
.ops = &s2mps14_reg_ops, \
1499
558
.type = REGULATOR_VOLTAGE, \
1500
559
.owner = THIS_MODULE, \
···
1579
634
#define regulator_desc_s2mps14_ldo(num, min, step) { \
1580
635
.name = "LDO"#num, \
1581
636
.id = S2MPS14_LDO##num, \
637
+
.of_match = of_match_ptr("LDO"#num), \
638
+
.regulators_node = of_match_ptr("regulators"), \
639
+
.of_parse_cb = s2mps11_of_parse_cb, \
1582
640
.ops = &s2mps14_reg_ops, \
1583
641
.type = REGULATOR_VOLTAGE, \
1584
642
.owner = THIS_MODULE, \
···
1597
649
#define regulator_desc_s2mps14_buck(num, min, step, min_sel) { \
1598
650
.name = "BUCK"#num, \
1599
651
.id = S2MPS14_BUCK##num, \
652
+
.of_match = of_match_ptr("BUCK"#num), \
653
+
.regulators_node = of_match_ptr("regulators"), \
654
+
.of_parse_cb = s2mps11_of_parse_cb, \
1600
655
.ops = &s2mps14_reg_ops, \
1601
656
.type = REGULATOR_VOLTAGE, \
1602
657
.owner = THIS_MODULE, \
···
1676
725
#define regulator_desc_s2mps15_ldo(num, range) { \
1677
726
.name = "LDO"#num, \
1678
727
.id = S2MPS15_LDO##num, \
728
+
.of_match = of_match_ptr("LDO"#num), \
729
+
.regulators_node = of_match_ptr("regulators"), \
1679
730
.ops = &s2mps15_reg_ldo_ops, \
1680
731
.type = REGULATOR_VOLTAGE, \
1681
732
.owner = THIS_MODULE, \
···
1693
740
#define regulator_desc_s2mps15_buck(num, range) { \
1694
741
.name = "BUCK"#num, \
1695
742
.id = S2MPS15_BUCK##num, \
743
+
.of_match = of_match_ptr("BUCK"#num), \
744
+
.regulators_node = of_match_ptr("regulators"), \
1696
745
.ops = &s2mps15_reg_buck_ops, \
1697
746
.type = REGULATOR_VOLTAGE, \
1698
747
.owner = THIS_MODULE, \
···
1784
829
};
1785
830
1786
831
static int s2mps14_pmic_enable_ext_control(struct s2mps11_info *s2mps11,
1787
-
struct regulator_dev *rdev)
832
+
struct regulator_dev *rdev)
1788
833
{
1789
-
return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
1790
-
rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL);
1791
-
}
1792
-
1793
-
static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device *pdev,
1794
-
struct of_regulator_match *rdata, struct s2mps11_info *s2mps11)
1795
-
{
1796
-
struct gpio_desc **gpio = s2mps11->ext_control_gpiod;
1797
-
unsigned int i;
1798
-
unsigned int valid_regulators[3] = { S2MPS14_LDO10, S2MPS14_LDO11,
1799
-
S2MPS14_LDO12 };
1800
-
1801
-
for (i = 0; i < ARRAY_SIZE(valid_regulators); i++) {
1802
-
unsigned int reg = valid_regulators[i];
1803
-
1804
-
if (!rdata[reg].init_data || !rdata[reg].of_node)
1805
-
continue;
1806
-
1807
-
gpio[reg] = devm_fwnode_gpiod_get(&pdev->dev,
1808
-
of_fwnode_handle(rdata[reg].of_node),
1809
-
"samsung,ext-control",
1810
-
GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
1811
-
"s2mps11-regulator");
1812
-
if (PTR_ERR(gpio[reg]) == -ENOENT)
1813
-
gpio[reg] = NULL;
1814
-
else if (IS_ERR(gpio[reg])) {
1815
-
dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n",
1816
-
reg, rdata[reg].name);
1817
-
gpio[reg] = NULL;
1818
-
continue;
1819
-
}
1820
-
if (gpio[reg])
1821
-
dev_dbg(&pdev->dev, "Using GPIO for ext-control over %d/%s\n",
1822
-
reg, rdata[reg].name);
1823
-
}
1824
-
}
1825
-
1826
-
static int s2mps11_pmic_dt_parse(struct platform_device *pdev,
1827
-
struct of_regulator_match *rdata, struct s2mps11_info *s2mps11,
1828
-
unsigned int rdev_num)
1829
-
{
1830
-
struct device_node *reg_np;
1831
-
1832
-
reg_np = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
1833
-
if (!reg_np) {
1834
-
dev_err(&pdev->dev, "could not find regulators sub-node\n");
1835
-
return -EINVAL;
1836
-
}
1837
-
1838
-
of_regulator_match(&pdev->dev, reg_np, rdata, rdev_num);
1839
-
if (s2mps11->dev_type == S2MPS14X)
1840
-
s2mps14_pmic_dt_parse_ext_control_gpio(pdev, rdata, s2mps11);
1841
-
1842
-
of_node_put(reg_np);
1843
-
834
+
int ret = regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
835
+
rdev->desc->enable_mask,
836
+
S2MPS14_ENABLE_EXT_CONTROL);
837
+
if (ret < 0)
838
+
return dev_err_probe(rdev_get_dev(rdev), ret,
839
+
"failed to enable GPIO control over %d/%s\n",
840
+
rdev->desc->id, rdev->desc->name);
1844
841
return 0;
1845
842
}
1846
843
···
1853
946
#define regulator_desc_s2mpu02_ldo1(num) { \
1854
947
.name = "LDO"#num, \
1855
948
.id = S2MPU02_LDO##num, \
949
+
.of_match = of_match_ptr("LDO"#num), \
950
+
.regulators_node = of_match_ptr("regulators"), \
1856
951
.ops = &s2mpu02_ldo_ops, \
1857
952
.type = REGULATOR_VOLTAGE, \
1858
953
.owner = THIS_MODULE, \
···
1870
961
#define regulator_desc_s2mpu02_ldo2(num) { \
1871
962
.name = "LDO"#num, \
1872
963
.id = S2MPU02_LDO##num, \
964
+
.of_match = of_match_ptr("LDO"#num), \
965
+
.regulators_node = of_match_ptr("regulators"), \
1873
966
.ops = &s2mpu02_ldo_ops, \
1874
967
.type = REGULATOR_VOLTAGE, \
1875
968
.owner = THIS_MODULE, \
···
1887
976
#define regulator_desc_s2mpu02_ldo3(num) { \
1888
977
.name = "LDO"#num, \
1889
978
.id = S2MPU02_LDO##num, \
979
+
.of_match = of_match_ptr("LDO"#num), \
980
+
.regulators_node = of_match_ptr("regulators"), \
1890
981
.ops = &s2mpu02_ldo_ops, \
1891
982
.type = REGULATOR_VOLTAGE, \
1892
983
.owner = THIS_MODULE, \
···
1904
991
#define regulator_desc_s2mpu02_ldo4(num) { \
1905
992
.name = "LDO"#num, \
1906
993
.id = S2MPU02_LDO##num, \
994
+
.of_match = of_match_ptr("LDO"#num), \
995
+
.regulators_node = of_match_ptr("regulators"), \
1907
996
.ops = &s2mpu02_ldo_ops, \
1908
997
.type = REGULATOR_VOLTAGE, \
1909
998
.owner = THIS_MODULE, \
···
1921
1006
#define regulator_desc_s2mpu02_ldo5(num) { \
1922
1007
.name = "LDO"#num, \
1923
1008
.id = S2MPU02_LDO##num, \
1009
+
.of_match = of_match_ptr("LDO"#num), \
1010
+
.regulators_node = of_match_ptr("regulators"), \
1924
1011
.ops = &s2mpu02_ldo_ops, \
1925
1012
.type = REGULATOR_VOLTAGE, \
1926
1013
.owner = THIS_MODULE, \
···
1939
1022
#define regulator_desc_s2mpu02_buck1234(num) { \
1940
1023
.name = "BUCK"#num, \
1941
1024
.id = S2MPU02_BUCK##num, \
1025
+
.of_match = of_match_ptr("BUCK"#num), \
1026
+
.regulators_node = of_match_ptr("regulators"), \
1942
1027
.ops = &s2mpu02_buck_ops, \
1943
1028
.type = REGULATOR_VOLTAGE, \
1944
1029
.owner = THIS_MODULE, \
···
1957
1038
#define regulator_desc_s2mpu02_buck5(num) { \
1958
1039
.name = "BUCK"#num, \
1959
1040
.id = S2MPU02_BUCK##num, \
1041
+
.of_match = of_match_ptr("BUCK"#num), \
1042
+
.regulators_node = of_match_ptr("regulators"), \
1960
1043
.ops = &s2mpu02_ldo_ops, \
1961
1044
.type = REGULATOR_VOLTAGE, \
1962
1045
.owner = THIS_MODULE, \
···
1975
1054
#define regulator_desc_s2mpu02_buck6(num) { \
1976
1055
.name = "BUCK"#num, \
1977
1056
.id = S2MPU02_BUCK##num, \
1057
+
.of_match = of_match_ptr("BUCK"#num), \
1058
+
.regulators_node = of_match_ptr("regulators"), \
1978
1059
.ops = &s2mpu02_ldo_ops, \
1979
1060
.type = REGULATOR_VOLTAGE, \
1980
1061
.owner = THIS_MODULE, \
···
1993
1070
#define regulator_desc_s2mpu02_buck7(num) { \
1994
1071
.name = "BUCK"#num, \
1995
1072
.id = S2MPU02_BUCK##num, \
1073
+
.of_match = of_match_ptr("BUCK"#num), \
1074
+
.regulators_node = of_match_ptr("regulators"), \
1996
1075
.ops = &s2mpu02_ldo_ops, \
1997
1076
.type = REGULATOR_VOLTAGE, \
1998
1077
.owner = THIS_MODULE, \
···
2050
1125
#define regulator_desc_s2mpu05_ldo_reg(num, min, step, reg) { \
2051
1126
.name = "ldo"#num, \
2052
1127
.id = S2MPU05_LDO##num, \
1128
+
.of_match = of_match_ptr("ldo"#num), \
1129
+
.regulators_node = of_match_ptr("regulators"), \
2053
1130
.ops = &s2mpu02_ldo_ops, \
2054
1131
.type = REGULATOR_VOLTAGE, \
2055
1132
.owner = THIS_MODULE, \
···
2083
1156
#define regulator_desc_s2mpu05_buck(num, which) { \
2084
1157
.name = "buck"#num, \
2085
1158
.id = S2MPU05_BUCK##num, \
1159
+
.of_match = of_match_ptr("buck"#num), \
1160
+
.regulators_node = of_match_ptr("regulators"), \
2086
1161
.ops = &s2mpu02_buck_ops, \
2087
1162
.type = REGULATOR_VOLTAGE, \
2088
1163
.owner = THIS_MODULE, \
···
2131
1202
regulator_desc_s2mpu05_buck45(5),
2132
1203
};
2133
1204
1205
+
static int s2mps11_handle_ext_control(struct s2mps11_info *s2mps11,
1206
+
struct regulator_dev *rdev)
1207
+
{
1208
+
int ret;
1209
+
1210
+
switch (s2mps11->dev_type) {
1211
+
case S2MPS14X:
1212
+
if (!rdev->ena_pin)
1213
+
return 0;
1214
+
1215
+
ret = s2mps14_pmic_enable_ext_control(s2mps11, rdev);
1216
+
break;
1217
+
1218
+
case S2MPG10:
1219
+
case S2MPG11:
1220
+
/*
1221
+
* If desc.enable_val is != 0, then external control was
1222
+
* requested. We can not test s2mpg10_desc::ext_control,
1223
+
* because 0 is a valid value.
1224
+
*/
1225
+
if (!rdev->desc->enable_val)
1226
+
return 0;
1227
+
1228
+
ret = s2mpg10_enable_ext_control(s2mps11, rdev);
1229
+
break;
1230
+
1231
+
default:
1232
+
return 0;
1233
+
}
1234
+
1235
+
return ret;
1236
+
}
1237
+
2134
1238
static int s2mps11_pmic_probe(struct platform_device *pdev)
2135
1239
{
2136
1240
struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
2137
1241
struct regulator_config config = { };
2138
1242
struct s2mps11_info *s2mps11;
2139
-
unsigned int rdev_num = 0;
2140
-
int i, ret = 0;
1243
+
unsigned int rdev_num;
1244
+
int i, ret;
2141
1245
const struct regulator_desc *regulators;
1246
+
const struct s2mpg10_regulator_desc *s2mpg1x_regulators = NULL;
2142
1247
2143
1248
s2mps11 = devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info),
2144
1249
GFP_KERNEL);
···
2181
1218
2182
1219
s2mps11->dev_type = platform_get_device_id(pdev)->driver_data;
2183
1220
switch (s2mps11->dev_type) {
1221
+
case S2MPG10:
1222
+
rdev_num = ARRAY_SIZE(s2mpg10_regulators);
1223
+
s2mpg1x_regulators = s2mpg10_regulators;
1224
+
BUILD_BUG_ON(ARRAY_SIZE(s2mpg10_regulators) > S2MPS_REGULATOR_MAX);
1225
+
break;
1226
+
case S2MPG11:
1227
+
rdev_num = ARRAY_SIZE(s2mpg11_regulators);
1228
+
s2mpg1x_regulators = s2mpg11_regulators;
1229
+
BUILD_BUG_ON(ARRAY_SIZE(s2mpg11_regulators) > S2MPS_REGULATOR_MAX);
1230
+
break;
2184
1231
case S2MPS11X:
2185
1232
rdev_num = ARRAY_SIZE(s2mps11_regulators);
2186
1233
regulators = s2mps11_regulators;
2187
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps11_regulators));
1234
+
BUILD_BUG_ON(ARRAY_SIZE(s2mps11_regulators) > S2MPS_REGULATOR_MAX);
2188
1235
break;
2189
1236
case S2MPS13X:
2190
1237
rdev_num = ARRAY_SIZE(s2mps13_regulators);
2191
1238
regulators = s2mps13_regulators;
2192
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps13_regulators));
1239
+
BUILD_BUG_ON(ARRAY_SIZE(s2mps13_regulators) > S2MPS_REGULATOR_MAX);
2193
1240
break;
2194
1241
case S2MPS14X:
2195
1242
rdev_num = ARRAY_SIZE(s2mps14_regulators);
2196
1243
regulators = s2mps14_regulators;
2197
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps14_regulators));
1244
+
BUILD_BUG_ON(ARRAY_SIZE(s2mps14_regulators) > S2MPS_REGULATOR_MAX);
2198
1245
break;
2199
1246
case S2MPS15X:
2200
1247
rdev_num = ARRAY_SIZE(s2mps15_regulators);
2201
1248
regulators = s2mps15_regulators;
2202
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps15_regulators));
1249
+
BUILD_BUG_ON(ARRAY_SIZE(s2mps15_regulators) > S2MPS_REGULATOR_MAX);
2203
1250
break;
2204
1251
case S2MPU02:
2205
1252
rdev_num = ARRAY_SIZE(s2mpu02_regulators);
2206
1253
regulators = s2mpu02_regulators;
2207
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu02_regulators));
1254
+
BUILD_BUG_ON(ARRAY_SIZE(s2mpu02_regulators) > S2MPS_REGULATOR_MAX);
2208
1255
break;
2209
1256
case S2MPU05:
2210
1257
rdev_num = ARRAY_SIZE(s2mpu05_regulators);
2211
1258
regulators = s2mpu05_regulators;
2212
-
BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu05_regulators));
1259
+
BUILD_BUG_ON(ARRAY_SIZE(s2mpu05_regulators) > S2MPS_REGULATOR_MAX);
2213
1260
break;
2214
1261
default:
2215
-
dev_err(&pdev->dev, "Invalid device type: %u\n",
2216
-
s2mps11->dev_type);
2217
-
return -EINVAL;
1262
+
return dev_err_probe(&pdev->dev, -ENODEV,
1263
+
"Unsupported device type %d\n",
1264
+
s2mps11->dev_type);
2218
1265
}
2219
1266
2220
-
s2mps11->ext_control_gpiod = devm_kcalloc(&pdev->dev, rdev_num,
2221
-
sizeof(*s2mps11->ext_control_gpiod), GFP_KERNEL);
2222
-
if (!s2mps11->ext_control_gpiod)
2223
-
return -ENOMEM;
1267
+
if (s2mpg1x_regulators) {
1268
+
size_t regulators_sz = rdev_num * sizeof(*s2mpg1x_regulators);
2224
1269
2225
-
struct of_regulator_match *rdata __free(kfree) =
2226
-
kcalloc(rdev_num, sizeof(*rdata), GFP_KERNEL);
2227
-
if (!rdata)
2228
-
return -ENOMEM;
1270
+
s2mpg1x_regulators = devm_kmemdup(&pdev->dev,
1271
+
s2mpg1x_regulators,
1272
+
regulators_sz,
1273
+
GFP_KERNEL);
1274
+
if (!s2mpg1x_regulators)
1275
+
return -ENOMEM;
1276
+
}
2229
1277
2230
-
for (i = 0; i < rdev_num; i++)
2231
-
rdata[i].name = regulators[i].name;
2232
-
2233
-
ret = s2mps11_pmic_dt_parse(pdev, rdata, s2mps11, rdev_num);
2234
-
if (ret)
2235
-
return ret;
1278
+
device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent);
2236
1279
2237
1280
platform_set_drvdata(pdev, s2mps11);
2238
1281
···
2246
1277
config.regmap = iodev->regmap_pmic;
2247
1278
config.driver_data = s2mps11;
2248
1279
for (i = 0; i < rdev_num; i++) {
1280
+
const struct regulator_desc *rdesc;
2249
1281
struct regulator_dev *regulator;
2250
1282
2251
-
config.init_data = rdata[i].init_data;
2252
-
config.of_node = rdata[i].of_node;
2253
-
config.ena_gpiod = s2mps11->ext_control_gpiod[i];
2254
-
/*
2255
-
* Hand the GPIO descriptor management over to the regulator
2256
-
* core, remove it from devres management.
2257
-
*/
2258
-
if (config.ena_gpiod)
2259
-
devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod);
2260
-
regulator = devm_regulator_register(&pdev->dev,
2261
-
®ulators[i], &config);
2262
-
if (IS_ERR(regulator)) {
2263
-
dev_err(&pdev->dev, "regulator init failed for %d\n",
2264
-
i);
2265
-
return PTR_ERR(regulator);
2266
-
}
1283
+
if (s2mpg1x_regulators)
1284
+
rdesc = &s2mpg1x_regulators[i].desc;
1285
+
else
1286
+
rdesc = ®ulators[i];
2267
1287
2268
-
if (config.ena_gpiod) {
2269
-
ret = s2mps14_pmic_enable_ext_control(s2mps11,
2270
-
regulator);
2271
-
if (ret < 0) {
2272
-
dev_err(&pdev->dev,
2273
-
"failed to enable GPIO control over %s: %d\n",
2274
-
regulator->desc->name, ret);
2275
-
return ret;
2276
-
}
2277
-
}
1288
+
regulator = devm_regulator_register(&pdev->dev,
1289
+
rdesc, &config);
1290
+
if (IS_ERR(regulator))
1291
+
return dev_err_probe(&pdev->dev, PTR_ERR(regulator),
1292
+
"regulator init failed for %d/%s\n",
1293
+
rdesc->id, rdesc->name);
1294
+
1295
+
ret = s2mps11_handle_ext_control(s2mps11, regulator);
1296
+
if (ret < 0)
1297
+
return ret;
2278
1298
}
2279
1299
2280
1300
return 0;
2281
1301
}
2282
1302
2283
1303
static const struct platform_device_id s2mps11_pmic_id[] = {
1304
+
{ "s2mpg10-regulator", S2MPG10},
1305
+
{ "s2mpg11-regulator", S2MPG11},
2284
1306
{ "s2mps11-regulator", S2MPS11X},
2285
1307
{ "s2mps13-regulator", S2MPS13X},
2286
1308
{ "s2mps14-regulator", S2MPS14X},
+8
-13
drivers/rtc/rtc-s5m.c
+8
-13
drivers/rtc/rtc-s5m.c
···
15
15
#include <linux/rtc.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/mfd/samsung/core.h>
18
-
#include <linux/mfd/samsung/irq.h>
19
18
#include <linux/mfd/samsung/rtc.h>
20
19
#include <linux/mfd/samsung/s2mps14.h>
21
20
···
682
683
case S2MPS15X:
683
684
regmap_cfg = &s2mps14_rtc_regmap_config;
684
685
info->regs = &s2mps15_rtc_regs;
685
-
alarm_irq = S2MPS14_IRQ_RTCA0;
686
686
break;
687
687
case S2MPS14X:
688
688
regmap_cfg = &s2mps14_rtc_regmap_config;
689
689
info->regs = &s2mps14_rtc_regs;
690
-
alarm_irq = S2MPS14_IRQ_RTCA0;
691
690
break;
692
691
case S2MPS13X:
693
692
regmap_cfg = &s2mps14_rtc_regmap_config;
694
693
info->regs = &s2mps13_rtc_regs;
695
-
alarm_irq = S2MPS14_IRQ_RTCA0;
696
694
break;
697
695
case S5M8767X:
698
696
regmap_cfg = &s5m_rtc_regmap_config;
699
697
info->regs = &s5m_rtc_regs;
700
-
alarm_irq = S5M8767_IRQ_RTCA1;
701
698
break;
702
699
default:
703
700
return dev_err_probe(&pdev->dev, -ENODEV,
···
714
719
"Failed to allocate regmap\n");
715
720
} else if (device_type == S2MPG10) {
716
721
info->regs = &s2mpg10_rtc_regs;
717
-
alarm_irq = S2MPG10_IRQ_RTCA0;
718
722
} else {
719
723
return dev_err_probe(&pdev->dev, -ENODEV,
720
724
"Unsupported device type %d\n",
···
724
730
info->s5m87xx = s5m87xx;
725
731
info->device_type = device_type;
726
732
727
-
if (s5m87xx->irq_data) {
728
-
info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
729
-
if (info->irq <= 0)
730
-
return dev_err_probe(&pdev->dev, -EINVAL,
731
-
"Failed to get virtual IRQ %d\n",
732
-
alarm_irq);
733
-
}
733
+
alarm_irq = platform_get_irq_byname_optional(pdev, "alarm");
734
+
if (alarm_irq > 0)
735
+
info->irq = alarm_irq;
736
+
else if (alarm_irq == -ENXIO)
737
+
info->irq = 0;
738
+
else
739
+
return dev_err_probe(&pdev->dev, alarm_irq ? : -EINVAL,
740
+
"IRQ 'alarm' not found\n");
734
741
735
742
platform_set_drvdata(pdev, info);
736
743
+53
include/dt-bindings/regulator/samsung,s2mpg10-regulator.h
+53
include/dt-bindings/regulator/samsung,s2mpg10-regulator.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright 2021 Google LLC
4
+
* Copyright 2025 Linaro Ltd.
5
+
*
6
+
* Device Tree binding constants for the Samsung S2MPG1x PMIC regulators
7
+
*/
8
+
9
+
#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
10
+
#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
11
+
12
+
/*
13
+
* Several regulators may be controlled via external signals instead of via
14
+
* software. These constants describe the possible signals for such regulators
15
+
* and generally correspond to the respecitve on-chip pins.
16
+
*
17
+
* S2MPG10 regulators supporting these are:
18
+
* - buck1m .. buck7m buck10m
19
+
* - ldo3m .. ldo19m
20
+
*
21
+
* ldo20m supports external control, but using a different set of control
22
+
* signals.
23
+
*
24
+
* S2MPG11 regulators supporting these are:
25
+
* - buck1s .. buck3s buck5s buck8s buck9s bucka buckd
26
+
* - ldo1s ldo2s ldo8s ldo13s
27
+
*/
28
+
#define S2MPG10_EXTCTRL_PWREN 0 /* PWREN pin */
29
+
#define S2MPG10_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */
30
+
#define S2MPG10_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
31
+
#define S2MPG10_EXTCTRL_CPUCL1_EN 3 /* CPUCL1_EN pin */
32
+
#define S2MPG10_EXTCTRL_CPUCL1_EN2 4 /* CPUCL1_EN & PWREN pins */
33
+
#define S2MPG10_EXTCTRL_CPUCL2_EN 5 /* CPUCL2_EN pin */
34
+
#define S2MPG10_EXTCTRL_CPUCL2_EN2 6 /* CPUCL2_E2 & PWREN pins */
35
+
#define S2MPG10_EXTCTRL_TPU_EN 7 /* TPU_EN pin */
36
+
#define S2MPG10_EXTCTRL_TPU_EN2 8 /* TPU_EN & ~AP_ACTIVE_N pins */
37
+
#define S2MPG10_EXTCTRL_TCXO_ON 9 /* TCXO_ON pin */
38
+
#define S2MPG10_EXTCTRL_TCXO_ON2 10 /* TCXO_ON & ~AP_ACTIVE_N pins */
39
+
40
+
#define S2MPG10_EXTCTRL_LDO20M_EN2 11 /* VLDO20M_EN & LDO20M_SFR */
41
+
#define S2MPG10_EXTCTRL_LDO20M_EN 12 /* VLDO20M_EN pin */
42
+
43
+
#define S2MPG11_EXTCTRL_PWREN 0 /* PWREN pin */
44
+
#define S2MPG11_EXTCTRL_PWREN_MIF 1 /* PWREN_MIF pin */
45
+
#define S2MPG11_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
46
+
#define S2MPG11_EXTCTRL_G3D_EN 3 /* G3D_EN pin */
47
+
#define S2MPG11_EXTCTRL_G3D_EN2 4 /* G3D_EN & ~AP_ACTIVE_N pins */
48
+
#define S2MPG11_EXTCTRL_AOC_VDD 5 /* AOC_VDD pin */
49
+
#define S2MPG11_EXTCTRL_AOC_RET 6 /* AOC_RET pin */
50
+
#define S2MPG11_EXTCTRL_UFS_EN 7 /* UFS_EN pin */
51
+
#define S2MPG11_EXTCTRL_LDO13S_EN 8 /* VLDO13S_EN pin */
52
+
53
+
#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */
+1
-1
include/linux/mfd/samsung/core.h
+1
-1
include/linux/mfd/samsung/core.h
+105
include/linux/mfd/samsung/irq.h
+105
include/linux/mfd/samsung/irq.h
···
166
166
S2MPG10_IRQ_NR,
167
167
};
168
168
169
+
enum s2mpg11_common_irq {
170
+
/* Top-level (common) block */
171
+
S2MPG11_COMMON_IRQ_PMIC,
172
+
S2MPG11_COMMON_IRQ_UNUSED,
173
+
};
174
+
175
+
enum s2mpg11_irq {
176
+
/* PMIC */
177
+
S2MPG11_IRQ_PWRONF,
178
+
S2MPG11_IRQ_PWRONR,
179
+
S2MPG11_IRQ_PIF_TIMEOUT_MIF,
180
+
S2MPG11_IRQ_PIF_TIMEOUTS,
181
+
S2MPG11_IRQ_WTSR,
182
+
S2MPG11_IRQ_SPD_ABNORMAL_STOP,
183
+
S2MPG11_IRQ_SPD_PARITY_ERR,
184
+
#define S2MPG11_IRQ_PWRONF_MASK BIT(0)
185
+
#define S2MPG11_IRQ_PWRONR_MASK BIT(1)
186
+
#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3)
187
+
#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4)
188
+
#define S2MPG11_IRQ_WTSR_MASK BIT(5)
189
+
#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
190
+
#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7)
191
+
192
+
S2MPG11_IRQ_140C,
193
+
S2MPG11_IRQ_120C,
194
+
S2MPG11_IRQ_TSD,
195
+
S2MPG11_IRQ_WRST,
196
+
S2MPG11_IRQ_NTC_CYCLE_DONE,
197
+
S2MPG11_IRQ_PMETER_OVERF,
198
+
#define S2MPG11_IRQ_INT140C_MASK BIT(0)
199
+
#define S2MPG11_IRQ_INT120C_MASK BIT(1)
200
+
#define S2MPG11_IRQ_TSD_MASK BIT(2)
201
+
#define S2MPG11_IRQ_WRST_MASK BIT(5)
202
+
#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6)
203
+
#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7)
204
+
205
+
S2MPG11_IRQ_OCP_B1S,
206
+
S2MPG11_IRQ_OCP_B2S,
207
+
S2MPG11_IRQ_OCP_B3S,
208
+
S2MPG11_IRQ_OCP_B4S,
209
+
S2MPG11_IRQ_OCP_B5S,
210
+
S2MPG11_IRQ_OCP_B6S,
211
+
S2MPG11_IRQ_OCP_B7S,
212
+
S2MPG11_IRQ_OCP_B8S,
213
+
#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0)
214
+
#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1)
215
+
#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2)
216
+
#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3)
217
+
#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4)
218
+
#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5)
219
+
#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6)
220
+
#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7)
221
+
222
+
S2MPG11_IRQ_OCP_B9S,
223
+
S2MPG11_IRQ_OCP_B10S,
224
+
S2MPG11_IRQ_OCP_BDS,
225
+
S2MPG11_IRQ_OCP_BAS,
226
+
S2MPG11_IRQ_OCP_BBS,
227
+
S2MPG11_IRQ_WLWP_ACC,
228
+
S2MPG11_IRQ_SPD_SRP_PKT_RST,
229
+
#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0)
230
+
#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1)
231
+
#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2)
232
+
#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3)
233
+
#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4)
234
+
#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5)
235
+
#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
236
+
237
+
S2MPG11_IRQ_PWR_WARN_CH0,
238
+
S2MPG11_IRQ_PWR_WARN_CH1,
239
+
S2MPG11_IRQ_PWR_WARN_CH2,
240
+
S2MPG11_IRQ_PWR_WARN_CH3,
241
+
S2MPG11_IRQ_PWR_WARN_CH4,
242
+
S2MPG11_IRQ_PWR_WARN_CH5,
243
+
S2MPG11_IRQ_PWR_WARN_CH6,
244
+
S2MPG11_IRQ_PWR_WARN_CH7,
245
+
#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0)
246
+
#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1)
247
+
#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2)
248
+
#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3)
249
+
#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4)
250
+
#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5)
251
+
#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6)
252
+
#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7)
253
+
254
+
S2MPG11_IRQ_NTC_WARN_CH0,
255
+
S2MPG11_IRQ_NTC_WARN_CH1,
256
+
S2MPG11_IRQ_NTC_WARN_CH2,
257
+
S2MPG11_IRQ_NTC_WARN_CH3,
258
+
S2MPG11_IRQ_NTC_WARN_CH4,
259
+
S2MPG11_IRQ_NTC_WARN_CH5,
260
+
S2MPG11_IRQ_NTC_WARN_CH6,
261
+
S2MPG11_IRQ_NTC_WARN_CH7,
262
+
#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0)
263
+
#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1)
264
+
#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2)
265
+
#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3)
266
+
#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4)
267
+
#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5)
268
+
#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6)
269
+
#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7)
270
+
271
+
S2MPG11_IRQ_NR,
272
+
};
273
+
169
274
enum s2mps11_irq {
170
275
S2MPS11_IRQ_PWRONF,
171
276
S2MPS11_IRQ_PWRONR,
+34
-10
include/linux/mfd/samsung/s2mpg10.h
+34
-10
include/linux/mfd/samsung/s2mpg10.h
···
290
290
S2MPG10_PMIC_LDO_SENSE4,
291
291
};
292
292
293
+
/* Rail controlled externally, based on PCTRLSELx */
294
+
#define S2MPG10_PMIC_CTRL_ENABLE_EXT BIT(0)
295
+
296
+
/* For S2MPG10_PMIC_PCTRLSELx */
297
+
#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */
298
+
#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
299
+
#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
300
+
#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
301
+
#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
302
+
#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
303
+
#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */
304
+
#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */
305
+
#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */
306
+
#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */
307
+
#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */
308
+
#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pins */
309
+
#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */
310
+
#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pins */
311
+
312
+
/* For S2MPG10_PMIC_PCTRLSELx of LDO20M */
313
+
#define S2MPG10_PCTRLSEL_LDO20M_EN2 0x1 /* VLDO20M_EN & LDO20M_SFR */
314
+
#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */
315
+
#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTRL1 register */
316
+
293
317
/* Meter registers (type 0xa00) */
294
318
enum s2mpg10_meter_reg {
295
319
S2MPG10_METER_CTRL1,
···
431
407
432
408
/* S2MPG10 regulator IDs */
433
409
enum s2mpg10_regulators {
410
+
S2MPG10_BUCK1,
411
+
S2MPG10_BUCK2,
412
+
S2MPG10_BUCK3,
413
+
S2MPG10_BUCK4,
414
+
S2MPG10_BUCK5,
415
+
S2MPG10_BUCK6,
416
+
S2MPG10_BUCK7,
417
+
S2MPG10_BUCK8,
418
+
S2MPG10_BUCK9,
419
+
S2MPG10_BUCK10,
434
420
S2MPG10_LDO1,
435
421
S2MPG10_LDO2,
436
422
S2MPG10_LDO3,
···
472
438
S2MPG10_LDO29,
473
439
S2MPG10_LDO30,
474
440
S2MPG10_LDO31,
475
-
S2MPG10_BUCK1,
476
-
S2MPG10_BUCK2,
477
-
S2MPG10_BUCK3,
478
-
S2MPG10_BUCK4,
479
-
S2MPG10_BUCK5,
480
-
S2MPG10_BUCK6,
481
-
S2MPG10_BUCK7,
482
-
S2MPG10_BUCK8,
483
-
S2MPG10_BUCK9,
484
-
S2MPG10_BUCK10,
485
441
S2MPG10_REGULATOR_MAX,
486
442
};
487
443
+434
include/linux/mfd/samsung/s2mpg11.h
+434
include/linux/mfd/samsung/s2mpg11.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Copyright 2015 Samsung Electronics
4
+
* Copyright 2020 Google Inc
5
+
* Copyright 2025 Linaro Ltd.
6
+
*/
7
+
8
+
#ifndef __LINUX_MFD_S2MPG11_H
9
+
#define __LINUX_MFD_S2MPG11_H
10
+
11
+
/* Common registers (type 0x000) */
12
+
enum s2mpg11_common_reg {
13
+
S2MPG11_COMMON_CHIPID,
14
+
S2MPG11_COMMON_INT,
15
+
S2MPG11_COMMON_INT_MASK,
16
+
S2MPG11_COMMON_SPD_CTRL1 = 0x0a,
17
+
S2MPG11_COMMON_SPD_CTRL2,
18
+
S2MPG11_COMMON_SPD_CTRL3,
19
+
S2MPG11_COMMON_MON1SEL = 0x1a,
20
+
S2MPG11_COMMON_MON2SEL,
21
+
S2MPG11_COMMON_MONR,
22
+
S2MPG11_COMMON_DEBUG_CTRL1,
23
+
S2MPG11_COMMON_DEBUG_CTRL2,
24
+
S2MPG11_COMMON_DEBUG_CTRL3,
25
+
S2MPG11_COMMON_DEBUG_CTRL4,
26
+
S2MPG11_COMMON_DEBUG_CTRL5,
27
+
S2MPG11_COMMON_DEBUG_CTRL6,
28
+
S2MPG11_COMMON_TEST_MODE1,
29
+
S2MPG11_COMMON_SPD_DEBUG1,
30
+
S2MPG11_COMMON_SPD_DEBUG2,
31
+
S2MPG11_COMMON_SPD_DEBUG3,
32
+
S2MPG11_COMMON_SPD_DEBUG4,
33
+
};
34
+
35
+
/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */
36
+
#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0)
37
+
#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0)
38
+
39
+
/* PMIC registers (type 0x100) */
40
+
enum s2mpg11_pmic_reg {
41
+
S2MPG11_PMIC_INT1,
42
+
S2MPG11_PMIC_INT2,
43
+
S2MPG11_PMIC_INT3,
44
+
S2MPG11_PMIC_INT4,
45
+
S2MPG11_PMIC_INT5,
46
+
S2MPG11_PMIC_INT6,
47
+
S2MPG11_PMIC_INT1M,
48
+
S2MPG11_PMIC_INT2M,
49
+
S2MPG11_PMIC_INT3M,
50
+
S2MPG11_PMIC_INT4M,
51
+
S2MPG11_PMIC_INT5M,
52
+
S2MPG11_PMIC_INT6M,
53
+
S2MPG11_PMIC_STATUS1,
54
+
S2MPG11_PMIC_OFFSRC,
55
+
S2MPG11_PMIC_COMMON_CTRL1,
56
+
S2MPG11_PMIC_COMMON_CTRL2,
57
+
S2MPG11_PMIC_COMMON_CTRL3,
58
+
S2MPG11_PMIC_MIMICKING_CTRL,
59
+
S2MPG11_PMIC_B1S_CTRL,
60
+
S2MPG11_PMIC_B1S_OUT1,
61
+
S2MPG11_PMIC_B1S_OUT2,
62
+
S2MPG11_PMIC_B2S_CTRL,
63
+
S2MPG11_PMIC_B2S_OUT1,
64
+
S2MPG11_PMIC_B2S_OUT2,
65
+
S2MPG11_PMIC_B3S_CTRL,
66
+
S2MPG11_PMIC_B3S_OUT1,
67
+
S2MPG11_PMIC_B3S_OUT2,
68
+
S2MPG11_PMIC_B4S_CTRL,
69
+
S2MPG11_PMIC_B4S_OUT,
70
+
S2MPG11_PMIC_B5S_CTRL,
71
+
S2MPG11_PMIC_B5S_OUT,
72
+
S2MPG11_PMIC_B6S_CTRL,
73
+
S2MPG11_PMIC_B6S_OUT1,
74
+
S2MPG11_PMIC_B6S_OUT2,
75
+
S2MPG11_PMIC_B7S_CTRL,
76
+
S2MPG11_PMIC_B7S_OUT1,
77
+
S2MPG11_PMIC_B7S_OUT2,
78
+
S2MPG11_PMIC_B8S_CTRL,
79
+
S2MPG11_PMIC_B8S_OUT1,
80
+
S2MPG11_PMIC_B8S_OUT2,
81
+
S2MPG11_PMIC_B9S_CTRL,
82
+
S2MPG11_PMIC_B9S_OUT1,
83
+
S2MPG11_PMIC_B9S_OUT2,
84
+
S2MPG11_PMIC_B10S_CTRL,
85
+
S2MPG11_PMIC_B10S_OUT,
86
+
S2MPG11_PMIC_BUCKD_CTRL,
87
+
S2MPG11_PMIC_BUCKD_OUT,
88
+
S2MPG11_PMIC_BUCKA_CTRL,
89
+
S2MPG11_PMIC_BUCKA_OUT,
90
+
S2MPG11_PMIC_BB_CTRL,
91
+
S2MPG11_PMIC_BB_OUT1,
92
+
S2MPG11_PMIC_BB_OUT2,
93
+
S2MPG11_PMIC_BUCK1S_USONIC,
94
+
S2MPG11_PMIC_BUCK2S_USONIC,
95
+
S2MPG11_PMIC_BUCK3S_USONIC,
96
+
S2MPG11_PMIC_BUCK4S_USONIC,
97
+
S2MPG11_PMIC_BUCK5S_USONIC,
98
+
S2MPG11_PMIC_BUCK6S_USONIC,
99
+
S2MPG11_PMIC_BUCK7S_USONIC,
100
+
S2MPG11_PMIC_BUCK8S_USONIC,
101
+
S2MPG11_PMIC_BUCK9S_USONIC,
102
+
S2MPG11_PMIC_BUCK10S_USONIC,
103
+
S2MPG11_PMIC_BUCKD_USONIC,
104
+
S2MPG11_PMIC_BUCKA_USONIC,
105
+
S2MPG11_PMIC_BB_USONIC,
106
+
S2MPG11_PMIC_L1S_CTRL1,
107
+
S2MPG11_PMIC_L1S_CTRL2,
108
+
S2MPG11_PMIC_L2S_CTRL1,
109
+
S2MPG11_PMIC_L2S_CTRL2,
110
+
S2MPG11_PMIC_L3S_CTRL,
111
+
S2MPG11_PMIC_L4S_CTRL,
112
+
S2MPG11_PMIC_L5S_CTRL,
113
+
S2MPG11_PMIC_L6S_CTRL,
114
+
S2MPG11_PMIC_L7S_CTRL,
115
+
S2MPG11_PMIC_L8S_CTRL,
116
+
S2MPG11_PMIC_L9S_CTRL,
117
+
S2MPG11_PMIC_L10S_CTRL,
118
+
S2MPG11_PMIC_L11S_CTRL,
119
+
S2MPG11_PMIC_L12S_CTRL,
120
+
S2MPG11_PMIC_L13S_CTRL,
121
+
S2MPG11_PMIC_L14S_CTRL,
122
+
S2MPG11_PMIC_L15S_CTRL,
123
+
S2MPG11_PMIC_LDO_CTRL1,
124
+
S2MPG11_PMIC_LDO_DSCH1,
125
+
S2MPG11_PMIC_LDO_DSCH2,
126
+
S2MPG11_PMIC_DVS_RAMP1,
127
+
S2MPG11_PMIC_DVS_RAMP2,
128
+
S2MPG11_PMIC_DVS_RAMP3,
129
+
S2MPG11_PMIC_DVS_RAMP4,
130
+
S2MPG11_PMIC_DVS_RAMP5,
131
+
S2MPG11_PMIC_DVS_RAMP6,
132
+
/* Nothing @ 0x5a */
133
+
S2MPG11_PMIC_DVS_SYNC_CTRL1 = 0x5c,
134
+
S2MPG11_PMIC_DVS_SYNC_CTRL2,
135
+
S2MPG11_PMIC_OFF_CTRL1,
136
+
S2MPG11_PMIC_OFF_CTRL2,
137
+
S2MPG11_PMIC_OFF_CTRL3,
138
+
S2MPG11_PMIC_SEQ_CTRL1,
139
+
S2MPG11_PMIC_SEQ_CTRL2,
140
+
S2MPG11_PMIC_SEQ_CTRL3,
141
+
S2MPG11_PMIC_SEQ_CTRL4,
142
+
S2MPG11_PMIC_SEQ_CTRL5,
143
+
S2MPG11_PMIC_SEQ_CTRL6,
144
+
S2MPG11_PMIC_SEQ_CTRL7,
145
+
S2MPG11_PMIC_SEQ_CTRL8,
146
+
S2MPG11_PMIC_SEQ_CTRL9,
147
+
S2MPG11_PMIC_SEQ_CTRL10,
148
+
S2MPG11_PMIC_SEQ_CTRL11,
149
+
S2MPG11_PMIC_SEQ_CTRL12,
150
+
S2MPG11_PMIC_SEQ_CTRL13,
151
+
S2MPG11_PMIC_SEQ_CTRL14,
152
+
S2MPG11_PMIC_SEQ_CTRL15,
153
+
S2MPG11_PMIC_SEQ_CTRL16,
154
+
S2MPG11_PMIC_SEQ_CTRL17,
155
+
S2MPG11_PMIC_SEQ_CTRL18,
156
+
S2MPG11_PMIC_SEQ_CTRL19,
157
+
S2MPG11_PMIC_SEQ_CTRL20,
158
+
S2MPG11_PMIC_SEQ_CTRL21,
159
+
S2MPG11_PMIC_SEQ_CTRL22,
160
+
S2MPG11_PMIC_SEQ_CTRL23,
161
+
S2MPG11_PMIC_SEQ_CTRL24,
162
+
S2MPG11_PMIC_SEQ_CTRL25,
163
+
S2MPG11_PMIC_SEQ_CTRL26,
164
+
S2MPG11_PMIC_SEQ_CTRL27,
165
+
S2MPG11_PMIC_OFF_SEQ_CTRL1,
166
+
S2MPG11_PMIC_OFF_SEQ_CTRL2,
167
+
S2MPG11_PMIC_OFF_SEQ_CTRL3,
168
+
S2MPG11_PMIC_OFF_SEQ_CTRL4,
169
+
S2MPG11_PMIC_OFF_SEQ_CTRL5,
170
+
S2MPG11_PMIC_OFF_SEQ_CTRL6,
171
+
S2MPG11_PMIC_OFF_SEQ_CTRL7,
172
+
S2MPG11_PMIC_OFF_SEQ_CTRL8,
173
+
S2MPG11_PMIC_OFF_SEQ_CTRL9,
174
+
S2MPG11_PMIC_OFF_SEQ_CTRL10,
175
+
S2MPG11_PMIC_OFF_SEQ_CTRL11,
176
+
S2MPG11_PMIC_OFF_SEQ_CTRL12,
177
+
S2MPG11_PMIC_OFF_SEQ_CTRL13,
178
+
S2MPG11_PMIC_OFF_SEQ_CTRL14,
179
+
S2MPG11_PMIC_OFF_SEQ_CTRL15,
180
+
S2MPG11_PMIC_OFF_SEQ_CTRL16,
181
+
S2MPG11_PMIC_OFF_SEQ_CTRL17,
182
+
S2MPG11_PMIC_PCTRLSEL1,
183
+
S2MPG11_PMIC_PCTRLSEL2,
184
+
S2MPG11_PMIC_PCTRLSEL3,
185
+
S2MPG11_PMIC_PCTRLSEL4,
186
+
S2MPG11_PMIC_PCTRLSEL5,
187
+
S2MPG11_PMIC_PCTRLSEL6,
188
+
S2MPG11_PMIC_DCTRLSEL1,
189
+
S2MPG11_PMIC_DCTRLSEL2,
190
+
S2MPG11_PMIC_DCTRLSEL3,
191
+
S2MPG11_PMIC_DCTRLSEL4,
192
+
S2MPG11_PMIC_DCTRLSEL5,
193
+
S2MPG11_PMIC_GPIO_CTRL1,
194
+
S2MPG11_PMIC_GPIO_CTRL2,
195
+
S2MPG11_PMIC_GPIO_CTRL3,
196
+
S2MPG11_PMIC_GPIO_CTRL4,
197
+
S2MPG11_PMIC_GPIO_CTRL5,
198
+
S2MPG11_PMIC_GPIO_CTRL6,
199
+
S2MPG11_PMIC_GPIO_CTRL7,
200
+
S2MPG11_PMIC_B2S_OCP_WARN,
201
+
S2MPG11_PMIC_B2S_OCP_WARN_X,
202
+
S2MPG11_PMIC_B2S_OCP_WARN_Y,
203
+
S2MPG11_PMIC_B2S_OCP_WARN_Z,
204
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN,
205
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X,
206
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y,
207
+
S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z,
208
+
S2MPG11_PMIC_BUCK_OCP_EN1,
209
+
S2MPG11_PMIC_BUCK_OCP_EN2,
210
+
S2MPG11_PMIC_BUCK_OCP_PD_EN1,
211
+
S2MPG11_PMIC_BUCK_OCP_PD_EN2,
212
+
S2MPG11_PMIC_BUCK_OCP_CTRL1,
213
+
S2MPG11_PMIC_BUCK_OCP_CTRL2,
214
+
S2MPG11_PMIC_BUCK_OCP_CTRL3,
215
+
S2MPG11_PMIC_BUCK_OCP_CTRL4,
216
+
S2MPG11_PMIC_BUCK_OCP_CTRL5,
217
+
S2MPG11_PMIC_BUCK_OCP_CTRL6,
218
+
S2MPG11_PMIC_BUCK_OCP_CTRL7,
219
+
S2MPG11_PMIC_PIF_CTRL,
220
+
S2MPG11_PMIC_BUCK_HR_MODE1,
221
+
S2MPG11_PMIC_BUCK_HR_MODE2,
222
+
S2MPG11_PMIC_FAULTOUT_CTRL,
223
+
S2MPG11_PMIC_LDO_SENSE1,
224
+
S2MPG11_PMIC_LDO_SENSE2,
225
+
};
226
+
227
+
/* For S2MPG11_PMIC_PCTRLSELx */
228
+
#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */
229
+
#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKING_CTRL */
230
+
#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */
231
+
#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMICKING_CTRL */
232
+
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */
233
+
#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in MIMICKING_CTRL */
234
+
#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */
235
+
#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pins */
236
+
#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */
237
+
#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */
238
+
#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */
239
+
#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */
240
+
241
+
/* Meter registers (type 0xa00) */
242
+
enum s2mpg11_meter_reg {
243
+
S2MPG11_METER_CTRL1,
244
+
S2MPG11_METER_CTRL2,
245
+
S2MPG11_METER_CTRL3,
246
+
S2MPG11_METER_CTRL4,
247
+
S2MPG11_METER_CTRL5,
248
+
S2MPG11_METER_BUCKEN1,
249
+
S2MPG11_METER_BUCKEN2,
250
+
S2MPG11_METER_MUXSEL0,
251
+
S2MPG11_METER_MUXSEL1,
252
+
S2MPG11_METER_MUXSEL2,
253
+
S2MPG11_METER_MUXSEL3,
254
+
S2MPG11_METER_MUXSEL4,
255
+
S2MPG11_METER_MUXSEL5,
256
+
S2MPG11_METER_MUXSEL6,
257
+
S2MPG11_METER_MUXSEL7,
258
+
S2MPG11_METER_LPF_C0_0,
259
+
S2MPG11_METER_LPF_C0_1,
260
+
S2MPG11_METER_LPF_C0_2,
261
+
S2MPG11_METER_LPF_C0_3,
262
+
S2MPG11_METER_LPF_C0_4,
263
+
S2MPG11_METER_LPF_C0_5,
264
+
S2MPG11_METER_LPF_C0_6,
265
+
S2MPG11_METER_LPF_C0_7,
266
+
S2MPG11_METER_NTC_LPF_C0_0,
267
+
S2MPG11_METER_NTC_LPF_C0_1,
268
+
S2MPG11_METER_NTC_LPF_C0_2,
269
+
S2MPG11_METER_NTC_LPF_C0_3,
270
+
S2MPG11_METER_NTC_LPF_C0_4,
271
+
S2MPG11_METER_NTC_LPF_C0_5,
272
+
S2MPG11_METER_NTC_LPF_C0_6,
273
+
S2MPG11_METER_NTC_LPF_C0_7,
274
+
S2MPG11_METER_PWR_WARN0,
275
+
S2MPG11_METER_PWR_WARN1,
276
+
S2MPG11_METER_PWR_WARN2,
277
+
S2MPG11_METER_PWR_WARN3,
278
+
S2MPG11_METER_PWR_WARN4,
279
+
S2MPG11_METER_PWR_WARN5,
280
+
S2MPG11_METER_PWR_WARN6,
281
+
S2MPG11_METER_PWR_WARN7,
282
+
S2MPG11_METER_NTC_L_WARN0,
283
+
S2MPG11_METER_NTC_L_WARN1,
284
+
S2MPG11_METER_NTC_L_WARN2,
285
+
S2MPG11_METER_NTC_L_WARN3,
286
+
S2MPG11_METER_NTC_L_WARN4,
287
+
S2MPG11_METER_NTC_L_WARN5,
288
+
S2MPG11_METER_NTC_L_WARN6,
289
+
S2MPG11_METER_NTC_L_WARN7,
290
+
S2MPG11_METER_NTC_H_WARN0,
291
+
S2MPG11_METER_NTC_H_WARN1,
292
+
S2MPG11_METER_NTC_H_WARN2,
293
+
S2MPG11_METER_NTC_H_WARN3,
294
+
S2MPG11_METER_NTC_H_WARN4,
295
+
S2MPG11_METER_NTC_H_WARN5,
296
+
S2MPG11_METER_NTC_H_WARN6,
297
+
S2MPG11_METER_NTC_H_WARN7,
298
+
S2MPG11_METER_PWR_HYS1,
299
+
S2MPG11_METER_PWR_HYS2,
300
+
S2MPG11_METER_PWR_HYS3,
301
+
S2MPG11_METER_PWR_HYS4,
302
+
S2MPG11_METER_NTC_HYS1,
303
+
S2MPG11_METER_NTC_HYS2,
304
+
S2MPG11_METER_NTC_HYS3,
305
+
S2MPG11_METER_NTC_HYS4,
306
+
/* Nothing @ 0x3f */
307
+
S2MPG11_METER_ACC_DATA_CH0_1 = 0x40,
308
+
S2MPG11_METER_ACC_DATA_CH0_2,
309
+
S2MPG11_METER_ACC_DATA_CH0_3,
310
+
S2MPG11_METER_ACC_DATA_CH0_4,
311
+
S2MPG11_METER_ACC_DATA_CH0_5,
312
+
S2MPG11_METER_ACC_DATA_CH0_6,
313
+
S2MPG11_METER_ACC_DATA_CH1_1,
314
+
S2MPG11_METER_ACC_DATA_CH1_2,
315
+
S2MPG11_METER_ACC_DATA_CH1_3,
316
+
S2MPG11_METER_ACC_DATA_CH1_4,
317
+
S2MPG11_METER_ACC_DATA_CH1_5,
318
+
S2MPG11_METER_ACC_DATA_CH1_6,
319
+
S2MPG11_METER_ACC_DATA_CH2_1,
320
+
S2MPG11_METER_ACC_DATA_CH2_2,
321
+
S2MPG11_METER_ACC_DATA_CH2_3,
322
+
S2MPG11_METER_ACC_DATA_CH2_4,
323
+
S2MPG11_METER_ACC_DATA_CH2_5,
324
+
S2MPG11_METER_ACC_DATA_CH2_6,
325
+
S2MPG11_METER_ACC_DATA_CH3_1,
326
+
S2MPG11_METER_ACC_DATA_CH3_2,
327
+
S2MPG11_METER_ACC_DATA_CH3_3,
328
+
S2MPG11_METER_ACC_DATA_CH3_4,
329
+
S2MPG11_METER_ACC_DATA_CH3_5,
330
+
S2MPG11_METER_ACC_DATA_CH3_6,
331
+
S2MPG11_METER_ACC_DATA_CH4_1,
332
+
S2MPG11_METER_ACC_DATA_CH4_2,
333
+
S2MPG11_METER_ACC_DATA_CH4_3,
334
+
S2MPG11_METER_ACC_DATA_CH4_4,
335
+
S2MPG11_METER_ACC_DATA_CH4_5,
336
+
S2MPG11_METER_ACC_DATA_CH4_6,
337
+
S2MPG11_METER_ACC_DATA_CH5_1,
338
+
S2MPG11_METER_ACC_DATA_CH5_2,
339
+
S2MPG11_METER_ACC_DATA_CH5_3,
340
+
S2MPG11_METER_ACC_DATA_CH5_4,
341
+
S2MPG11_METER_ACC_DATA_CH5_5,
342
+
S2MPG11_METER_ACC_DATA_CH5_6,
343
+
S2MPG11_METER_ACC_DATA_CH6_1,
344
+
S2MPG11_METER_ACC_DATA_CH6_2,
345
+
S2MPG11_METER_ACC_DATA_CH6_3,
346
+
S2MPG11_METER_ACC_DATA_CH6_4,
347
+
S2MPG11_METER_ACC_DATA_CH6_5,
348
+
S2MPG11_METER_ACC_DATA_CH6_6,
349
+
S2MPG11_METER_ACC_DATA_CH7_1,
350
+
S2MPG11_METER_ACC_DATA_CH7_2,
351
+
S2MPG11_METER_ACC_DATA_CH7_3,
352
+
S2MPG11_METER_ACC_DATA_CH7_4,
353
+
S2MPG11_METER_ACC_DATA_CH7_5,
354
+
S2MPG11_METER_ACC_DATA_CH7_6,
355
+
S2MPG11_METER_ACC_COUNT_1,
356
+
S2MPG11_METER_ACC_COUNT_2,
357
+
S2MPG11_METER_ACC_COUNT_3,
358
+
S2MPG11_METER_LPF_DATA_CH0_1,
359
+
S2MPG11_METER_LPF_DATA_CH0_2,
360
+
S2MPG11_METER_LPF_DATA_CH0_3,
361
+
S2MPG11_METER_LPF_DATA_CH1_1,
362
+
S2MPG11_METER_LPF_DATA_CH1_2,
363
+
S2MPG11_METER_LPF_DATA_CH1_3,
364
+
S2MPG11_METER_LPF_DATA_CH2_1,
365
+
S2MPG11_METER_LPF_DATA_CH2_2,
366
+
S2MPG11_METER_LPF_DATA_CH2_3,
367
+
S2MPG11_METER_LPF_DATA_CH3_1,
368
+
S2MPG11_METER_LPF_DATA_CH3_2,
369
+
S2MPG11_METER_LPF_DATA_CH3_3,
370
+
S2MPG11_METER_LPF_DATA_CH4_1,
371
+
S2MPG11_METER_LPF_DATA_CH4_2,
372
+
S2MPG11_METER_LPF_DATA_CH4_3,
373
+
S2MPG11_METER_LPF_DATA_CH5_1,
374
+
S2MPG11_METER_LPF_DATA_CH5_2,
375
+
S2MPG11_METER_LPF_DATA_CH5_3,
376
+
S2MPG11_METER_LPF_DATA_CH6_1,
377
+
S2MPG11_METER_LPF_DATA_CH6_2,
378
+
S2MPG11_METER_LPF_DATA_CH6_3,
379
+
S2MPG11_METER_LPF_DATA_CH7_1,
380
+
S2MPG11_METER_LPF_DATA_CH7_2,
381
+
S2MPG11_METER_LPF_DATA_CH7_3,
382
+
/* Nothing @ 0x8b 0x8c */
383
+
S2MPG11_METER_LPF_DATA_NTC0_1 = 0x8d,
384
+
S2MPG11_METER_LPF_DATA_NTC0_2,
385
+
S2MPG11_METER_LPF_DATA_NTC1_1,
386
+
S2MPG11_METER_LPF_DATA_NTC1_2,
387
+
S2MPG11_METER_LPF_DATA_NTC2_1,
388
+
S2MPG11_METER_LPF_DATA_NTC2_2,
389
+
S2MPG11_METER_LPF_DATA_NTC3_1,
390
+
S2MPG11_METER_LPF_DATA_NTC3_2,
391
+
S2MPG11_METER_LPF_DATA_NTC4_1,
392
+
S2MPG11_METER_LPF_DATA_NTC4_2,
393
+
S2MPG11_METER_LPF_DATA_NTC5_1,
394
+
S2MPG11_METER_LPF_DATA_NTC5_2,
395
+
S2MPG11_METER_LPF_DATA_NTC6_1,
396
+
S2MPG11_METER_LPF_DATA_NTC6_2,
397
+
S2MPG11_METER_LPF_DATA_NTC7_1,
398
+
S2MPG11_METER_LPF_DATA_NTC7_2,
399
+
};
400
+
401
+
/* S2MPG11 regulator IDs */
402
+
enum s2mpg11_regulators {
403
+
S2MPG11_BUCKBOOST,
404
+
S2MPG11_BUCK1,
405
+
S2MPG11_BUCK2,
406
+
S2MPG11_BUCK3,
407
+
S2MPG11_BUCK4,
408
+
S2MPG11_BUCK5,
409
+
S2MPG11_BUCK6,
410
+
S2MPG11_BUCK7,
411
+
S2MPG11_BUCK8,
412
+
S2MPG11_BUCK9,
413
+
S2MPG11_BUCK10,
414
+
S2MPG11_BUCKD,
415
+
S2MPG11_BUCKA,
416
+
S2MPG11_LDO1,
417
+
S2MPG11_LDO2,
418
+
S2MPG11_LDO3,
419
+
S2MPG11_LDO4,
420
+
S2MPG11_LDO5,
421
+
S2MPG11_LDO6,
422
+
S2MPG11_LDO7,
423
+
S2MPG11_LDO8,
424
+
S2MPG11_LDO9,
425
+
S2MPG11_LDO10,
426
+
S2MPG11_LDO11,
427
+
S2MPG11_LDO12,
428
+
S2MPG11_LDO13,
429
+
S2MPG11_LDO14,
430
+
S2MPG11_LDO15,
431
+
S2MPG11_REGULATOR_MAX,
432
+
};
433
+
434
+
#endif /* __LINUX_MFD_S2MPG11_H */
+5
include/linux/regulator/driver.h
+5
include/linux/regulator/driver.h
···
53
53
#define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \
54
54
LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV)
55
55
56
+
/* Initialize struct linear_range using voltages, not selectors */
57
+
#define REGULATOR_LINEAR_VRANGE(_offs_uV, _min_uV, _max_uV, _step_uV) \
58
+
LINEAR_RANGE(_min_uV, ((_min_uV) - (_offs_uV)) / (_step_uV), \
59
+
((_max_uV) - (_offs_uV)) / (_step_uV), _step_uV)
60
+
56
61
/**
57
62
* struct regulator_ops - regulator operations.
58
63
*