Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
- Fix a case of rescheduling with user access unlocked, when preempt is
enabled.
- A follow-up fix for a recent fix, which could lead to IRQ state
assertions firing incorrectly.
- Two fixes for lockdep warnings seen when using kfence with the Hash
MMU.
- Two fixes for preempt warnings seen when using the Hash MMU.
- Two fixes for the VAS coprocessor mechanism used on pseries.
- Prevent building some of our older KVM backends when
CONTEXT_TRACKING_USER is enabled, as it's known to cause crashes.
- A couple of fixes for issues seen with PMU NMIs.
Thanks to Nicholas Piggin, Guenter Roeck, Frederic Barrat Haren Myneni,
Sachin Sant, and Samuel Holland.
* tag 'powerpc-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/64s/interrupt: Fix clear of PACA_IRQS_HARD_DIS when returning to soft-masked context
powerpc/64s/interrupt: Perf NMI should not take normal exit path
powerpc/64/interrupt: Prevent NMI PMI causing a dangerous warning
KVM: PPC: BookS PR-KVM and BookE do not support context tracking
powerpc: Fix reschedule bug in KUAP-unlocked user copy
powerpc/64s: Fix hash__change_memory_range preemption warning
powerpc/64s: Disable preemption in hash lazy mmu mode
powerpc/64s: make linear_map_hash_lock a raw spinlock
powerpc/64s: make HPTE lock and native_tlbie_lock irq-safe
powerpc/64s: Add lockdep for HPTE lock
powerpc/pseries: Use lparcfg to reconfig VAS windows for DLPAR CPU
powerpc/pseries/vas: Add VAS IRQ primary handler
+212
-45
+6
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h
+6
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h
···
32
32
33
33
if (radix_enabled())
34
34
return;
35
+
/*
36
+
* apply_to_page_range can call us this preempt enabled when
37
+
* operating on kernel page tables.
38
+
*/
39
+
preempt_disable();
35
40
batch = this_cpu_ptr(&ppc64_tlb_batch);
36
41
batch->active = 1;
37
42
}
···
52
47
if (batch->index)
53
48
__flush_tlb_pending(batch);
54
49
batch->active = 0;
50
+
preempt_enable();
55
51
}
56
52
57
53
#define arch_flush_lazy_mmu_mode() do {} while (0)
+7
arch/powerpc/kernel/exceptions-64e.S
+7
arch/powerpc/kernel/exceptions-64e.S
···
813
813
EXCEPTION_COMMON(0x260)
814
814
CHECK_NAPPING()
815
815
addi r3,r1,STACK_FRAME_OVERHEAD
816
+
/*
817
+
* XXX: Returning from performance_monitor_exception taken as a
818
+
* soft-NMI (Linux irqs disabled) may be risky to use interrupt_return
819
+
* and could cause bugs in return or elsewhere. That case should just
820
+
* restore registers and return. There is a workaround for one known
821
+
* problem in interrupt_exit_kernel_prepare().
822
+
*/
816
823
bl performance_monitor_exception
817
824
b interrupt_return
818
825
+13
-1
arch/powerpc/kernel/exceptions-64s.S
+13
-1
arch/powerpc/kernel/exceptions-64s.S
···
2357
2357
EXC_COMMON_BEGIN(performance_monitor_common)
2358
2358
GEN_COMMON performance_monitor
2359
2359
addi r3,r1,STACK_FRAME_OVERHEAD
2360
-
bl performance_monitor_exception
2360
+
lbz r4,PACAIRQSOFTMASK(r13)
2361
+
cmpdi r4,IRQS_ENABLED
2362
+
bne 1f
2363
+
bl performance_monitor_exception_async
2361
2364
b interrupt_return_srr
2365
+
1:
2366
+
bl performance_monitor_exception_nmi
2367
+
/* Clear MSR_RI before setting SRR0 and SRR1. */
2368
+
li r9,0
2369
+
mtmsrd r9,1
2362
2370
2371
+
kuap_kernel_restore r9, r10
2372
+
2373
+
EXCEPTION_RESTORE_REGS hsrr=0
2374
+
RFI_TO_KERNEL
2363
2375
2364
2376
/**
2365
2377
* Interrupt 0xf20 - Vector Unavailable Interrupt.
+11
-3
arch/powerpc/kernel/interrupt.c
+11
-3
arch/powerpc/kernel/interrupt.c
···
374
374
if (regs_is_unrecoverable(regs))
375
375
unrecoverable_exception(regs);
376
376
/*
377
-
* CT_WARN_ON comes here via program_check_exception,
378
-
* so avoid recursion.
377
+
* CT_WARN_ON comes here via program_check_exception, so avoid
378
+
* recursion.
379
+
*
380
+
* Skip the assertion on PMIs on 64e to work around a problem caused
381
+
* by NMI PMIs incorrectly taking this interrupt return path, it's
382
+
* possible for this to hit after interrupt exit to user switches
383
+
* context to user. See also the comment in the performance monitor
384
+
* handler in exceptions-64e.S
379
385
*/
380
-
if (TRAP(regs) != INTERRUPT_PROGRAM)
386
+
if (!IS_ENABLED(CONFIG_PPC_BOOK3E_64) &&
387
+
TRAP(regs) != INTERRUPT_PROGRAM &&
388
+
TRAP(regs) != INTERRUPT_PERFMON)
381
389
CT_WARN_ON(ct_state() == CONTEXT_USER);
382
390
383
391
kuap = kuap_get_and_assert_locked();
+11
-2
arch/powerpc/kernel/interrupt_64.S
+11
-2
arch/powerpc/kernel/interrupt_64.S
···
532
532
* Returning to soft-disabled context.
533
533
* Check if a MUST_HARD_MASK interrupt has become pending, in which
534
534
* case we need to disable MSR[EE] in the return context.
535
+
*
536
+
* The MSR[EE] check catches among other things the short incoherency
537
+
* in hard_irq_disable() between clearing MSR[EE] and setting
538
+
* PACA_IRQ_HARD_DIS.
535
539
*/
536
540
ld r12,_MSR(r1)
537
541
andi. r10,r12,MSR_EE
538
542
beq .Lfast_kernel_interrupt_return_\srr\() // EE already disabled
539
543
lbz r11,PACAIRQHAPPENED(r13)
540
544
andi. r10,r11,PACA_IRQ_MUST_HARD_MASK
541
-
beq .Lfast_kernel_interrupt_return_\srr\() // No HARD_MASK pending
545
+
bne 1f // HARD_MASK is pending
546
+
// No HARD_MASK pending, clear possible HARD_DIS set by interrupt
547
+
andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l
548
+
stb r11,PACAIRQHAPPENED(r13)
549
+
b .Lfast_kernel_interrupt_return_\srr\()
542
550
543
-
/* Must clear MSR_EE from _MSR */
551
+
552
+
1: /* Must clear MSR_EE from _MSR */
544
553
#ifdef CONFIG_PPC_BOOK3S
545
554
li r10,0
546
555
/* Clear valid before changing _MSR */
+4
arch/powerpc/kvm/Kconfig
+4
arch/powerpc/kvm/Kconfig
···
51
51
config KVM_BOOK3S_32
52
52
tristate "KVM support for PowerPC book3s_32 processors"
53
53
depends on PPC_BOOK3S_32 && !SMP && !PTE_64BIT
54
+
depends on !CONTEXT_TRACKING_USER
54
55
select KVM
55
56
select KVM_BOOK3S_32_HANDLER
56
57
select KVM_BOOK3S_PR_POSSIBLE
···
106
105
config KVM_BOOK3S_64_PR
107
106
tristate "KVM support without using hypervisor mode in host"
108
107
depends on KVM_BOOK3S_64
108
+
depends on !CONTEXT_TRACKING_USER
109
109
select KVM_BOOK3S_PR_POSSIBLE
110
110
help
111
111
Support running guest kernels in virtual machines on processors
···
192
190
config KVM_E500V2
193
191
bool "KVM support for PowerPC E500v2 processors"
194
192
depends on PPC_E500 && !PPC_E500MC
193
+
depends on !CONTEXT_TRACKING_USER
195
194
select KVM
196
195
select KVM_MMIO
197
196
select MMU_NOTIFIER
···
208
205
config KVM_E500MC
209
206
bool "KVM support for PowerPC E500MC/E5500/E6500 processors"
210
207
depends on PPC_E500MC
208
+
depends on !CONTEXT_TRACKING_USER
211
209
select KVM
212
210
select KVM_MMIO
213
211
select KVM_BOOKE_HV
+11
-1
arch/powerpc/lib/vmx-helper.c
+11
-1
arch/powerpc/lib/vmx-helper.c
···
36
36
{
37
37
disable_kernel_altivec();
38
38
pagefault_enable();
39
-
preempt_enable();
39
+
preempt_enable_no_resched();
40
+
/*
41
+
* Must never explicitly call schedule (including preempt_enable())
42
+
* while in a kuap-unlocked user copy, because the AMR register will
43
+
* not be saved and restored across context switch. However preempt
44
+
* kernels need to be preempted as soon as possible if need_resched is
45
+
* set and we are preemptible. The hack here is to schedule a
46
+
* decrementer to fire here and reschedule for us if necessary.
47
+
*/
48
+
if (IS_ENABLED(CONFIG_PREEMPT) && need_resched())
49
+
set_dec(1);
40
50
return 0;
41
51
}
42
52
+59
-8
arch/powerpc/mm/book3s64/hash_native.c
+59
-8
arch/powerpc/mm/book3s64/hash_native.c
···
43
43
44
44
static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
45
45
46
+
#ifdef CONFIG_LOCKDEP
47
+
static struct lockdep_map hpte_lock_map =
48
+
STATIC_LOCKDEP_MAP_INIT("hpte_lock", &hpte_lock_map);
49
+
50
+
static void acquire_hpte_lock(void)
51
+
{
52
+
lock_map_acquire(&hpte_lock_map);
53
+
}
54
+
55
+
static void release_hpte_lock(void)
56
+
{
57
+
lock_map_release(&hpte_lock_map);
58
+
}
59
+
#else
60
+
static void acquire_hpte_lock(void)
61
+
{
62
+
}
63
+
64
+
static void release_hpte_lock(void)
65
+
{
66
+
}
67
+
#endif
68
+
46
69
static inline unsigned long ___tlbie(unsigned long vpn, int psize,
47
70
int apsize, int ssize)
48
71
{
···
243
220
{
244
221
unsigned long *word = (unsigned long *)&hptep->v;
245
222
223
+
acquire_hpte_lock();
246
224
while (1) {
247
225
if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
248
226
break;
···
258
234
{
259
235
unsigned long *word = (unsigned long *)&hptep->v;
260
236
237
+
release_hpte_lock();
261
238
clear_bit_unlock(HPTE_LOCK_BIT, word);
262
239
}
263
240
···
268
243
{
269
244
struct hash_pte *hptep = htab_address + hpte_group;
270
245
unsigned long hpte_v, hpte_r;
246
+
unsigned long flags;
271
247
int i;
248
+
249
+
local_irq_save(flags);
272
250
273
251
if (!(vflags & HPTE_V_BOLTED)) {
274
252
DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
···
291
263
hptep++;
292
264
}
293
265
294
-
if (i == HPTES_PER_GROUP)
266
+
if (i == HPTES_PER_GROUP) {
267
+
local_irq_restore(flags);
295
268
return -1;
269
+
}
296
270
297
271
hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
298
272
hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
···
316
286
* Now set the first dword including the valid bit
317
287
* NOTE: this also unlocks the hpte
318
288
*/
289
+
release_hpte_lock();
319
290
hptep->v = cpu_to_be64(hpte_v);
320
291
321
292
__asm__ __volatile__ ("ptesync" : : : "memory");
293
+
294
+
local_irq_restore(flags);
322
295
323
296
return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
324
297
}
···
360
327
return -1;
361
328
362
329
/* Invalidate the hpte. NOTE: this also unlocks it */
330
+
release_hpte_lock();
363
331
hptep->v = 0;
364
332
365
333
return i;
···
373
339
struct hash_pte *hptep = htab_address + slot;
374
340
unsigned long hpte_v, want_v;
375
341
int ret = 0, local = 0;
342
+
unsigned long irqflags;
343
+
344
+
local_irq_save(irqflags);
376
345
377
346
want_v = hpte_encode_avpn(vpn, bpsize, ssize);
378
347
···
418
381
*/
419
382
if (!(flags & HPTE_NOHPTE_UPDATE))
420
383
tlbie(vpn, bpsize, apsize, ssize, local);
384
+
385
+
local_irq_restore(irqflags);
421
386
422
387
return ret;
423
388
}
···
484
445
unsigned long vsid;
485
446
long slot;
486
447
struct hash_pte *hptep;
448
+
unsigned long flags;
449
+
450
+
local_irq_save(flags);
487
451
488
452
vsid = get_kernel_vsid(ea, ssize);
489
453
vpn = hpt_vpn(ea, vsid, ssize);
···
505
463
* actual page size will be same.
506
464
*/
507
465
tlbie(vpn, psize, psize, ssize, 0);
466
+
467
+
local_irq_restore(flags);
508
468
}
509
469
510
470
/*
···
520
476
unsigned long vsid;
521
477
long slot;
522
478
struct hash_pte *hptep;
479
+
unsigned long flags;
480
+
481
+
local_irq_save(flags);
523
482
524
483
vsid = get_kernel_vsid(ea, ssize);
525
484
vpn = hpt_vpn(ea, vsid, ssize);
···
540
493
541
494
/* Invalidate the TLB */
542
495
tlbie(vpn, psize, psize, ssize, 0);
496
+
497
+
local_irq_restore(flags);
498
+
543
499
return 0;
544
500
}
545
501
···
567
517
/* recheck with locks held */
568
518
hpte_v = hpte_get_old_v(hptep);
569
519
570
-
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
520
+
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
571
521
/* Invalidate the hpte. NOTE: this also unlocks it */
522
+
release_hpte_lock();
572
523
hptep->v = 0;
573
-
else
524
+
} else
574
525
native_unlock_hpte(hptep);
575
526
}
576
527
/*
···
631
580
hpte_v = hpte_get_old_v(hptep);
632
581
633
582
if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
634
-
/*
635
-
* Invalidate the hpte. NOTE: this also unlocks it
636
-
*/
637
-
583
+
/* Invalidate the hpte. NOTE: this also unlocks it */
584
+
release_hpte_lock();
638
585
hptep->v = 0;
639
586
} else
640
587
native_unlock_hpte(hptep);
···
814
765
815
766
if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
816
767
native_unlock_hpte(hptep);
817
-
else
768
+
else {
769
+
release_hpte_lock();
818
770
hptep->v = 0;
771
+
}
819
772
820
773
} pte_iterate_hashed_end();
821
774
}
+5
-3
arch/powerpc/mm/book3s64/hash_pgtable.c
+5
-3
arch/powerpc/mm/book3s64/hash_pgtable.c
···
404
404
405
405
struct change_memory_parms {
406
406
unsigned long start, end, newpp;
407
-
unsigned int step, nr_cpus, master_cpu;
407
+
unsigned int step, nr_cpus;
408
+
atomic_t master_cpu;
408
409
atomic_t cpu_counter;
409
410
};
410
411
···
479
478
{
480
479
struct change_memory_parms *parms = data;
481
480
482
-
if (parms->master_cpu != smp_processor_id())
481
+
// First CPU goes through, all others wait.
482
+
if (atomic_xchg(&parms->master_cpu, 1) == 1)
483
483
return chmem_secondary_loop(parms);
484
484
485
485
// Wait for all but one CPU (this one) to call-in
···
518
516
chmem_parms.end = end;
519
517
chmem_parms.step = step;
520
518
chmem_parms.newpp = newpp;
521
-
chmem_parms.master_cpu = smp_processor_id();
519
+
atomic_set(&chmem_parms.master_cpu, 0);
522
520
523
521
cpus_read_lock();
524
522
+6
-6
arch/powerpc/mm/book3s64/hash_utils.c
+6
-6
arch/powerpc/mm/book3s64/hash_utils.c
···
1981
1981
}
1982
1982
1983
1983
#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE)
1984
-
static DEFINE_SPINLOCK(linear_map_hash_lock);
1984
+
static DEFINE_RAW_SPINLOCK(linear_map_hash_lock);
1985
1985
1986
1986
static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1987
1987
{
···
2005
2005
mmu_linear_psize, mmu_kernel_ssize);
2006
2006
2007
2007
BUG_ON (ret < 0);
2008
-
spin_lock(&linear_map_hash_lock);
2008
+
raw_spin_lock(&linear_map_hash_lock);
2009
2009
BUG_ON(linear_map_hash_slots[lmi] & 0x80);
2010
2010
linear_map_hash_slots[lmi] = ret | 0x80;
2011
-
spin_unlock(&linear_map_hash_lock);
2011
+
raw_spin_unlock(&linear_map_hash_lock);
2012
2012
}
2013
2013
2014
2014
static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
···
2018
2018
unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
2019
2019
2020
2020
hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
2021
-
spin_lock(&linear_map_hash_lock);
2021
+
raw_spin_lock(&linear_map_hash_lock);
2022
2022
if (!(linear_map_hash_slots[lmi] & 0x80)) {
2023
-
spin_unlock(&linear_map_hash_lock);
2023
+
raw_spin_unlock(&linear_map_hash_lock);
2024
2024
return;
2025
2025
}
2026
2026
hidx = linear_map_hash_slots[lmi] & 0x7f;
2027
2027
linear_map_hash_slots[lmi] = 0;
2028
-
spin_unlock(&linear_map_hash_lock);
2028
+
raw_spin_unlock(&linear_map_hash_lock);
2029
2029
if (hidx & _PTEIDX_SECONDARY)
2030
2030
hash = ~hash;
2031
2031
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+11
arch/powerpc/platforms/pseries/lparcfg.c
+11
arch/powerpc/platforms/pseries/lparcfg.c
···
35
35
#include <asm/drmem.h>
36
36
37
37
#include "pseries.h"
38
+
#include "vas.h" /* pseries_vas_dlpar_cpu() */
38
39
39
40
/*
40
41
* This isn't a module but we expose that to userspace
···
749
748
return -EINVAL;
750
749
751
750
retval = update_ppp(new_entitled_ptr, NULL);
751
+
752
+
if (retval == H_SUCCESS || retval == H_CONSTRAINED) {
753
+
/*
754
+
* The hypervisor assigns VAS resources based
755
+
* on entitled capacity for shared mode.
756
+
* Reconfig VAS windows based on DLPAR CPU events.
757
+
*/
758
+
if (pseries_vas_dlpar_cpu() != 0)
759
+
retval = H_HARDWARE;
760
+
}
752
761
} else if (!strcmp(kbuf, "capacity_weight")) {
753
762
char *endp;
754
763
*new_weight_ptr = (u8) simple_strtoul(tmp, &endp, 10);
+62
-21
arch/powerpc/platforms/pseries/vas.c
+62
-21
arch/powerpc/platforms/pseries/vas.c
···
200
200
struct vas_user_win_ref *tsk_ref;
201
201
int rc;
202
202
203
-
rc = h_get_nx_fault(txwin->vas_win.winid, (u64)virt_to_phys(&crb));
204
-
if (!rc) {
205
-
tsk_ref = &txwin->vas_win.task_ref;
206
-
vas_dump_crb(&crb);
207
-
vas_update_csb(&crb, tsk_ref);
203
+
while (atomic_read(&txwin->pending_faults)) {
204
+
rc = h_get_nx_fault(txwin->vas_win.winid, (u64)virt_to_phys(&crb));
205
+
if (!rc) {
206
+
tsk_ref = &txwin->vas_win.task_ref;
207
+
vas_dump_crb(&crb);
208
+
vas_update_csb(&crb, tsk_ref);
209
+
}
210
+
atomic_dec(&txwin->pending_faults);
208
211
}
209
212
210
213
return IRQ_HANDLED;
214
+
}
215
+
216
+
/*
217
+
* irq_default_primary_handler() can be used only with IRQF_ONESHOT
218
+
* which disables IRQ before executing the thread handler and enables
219
+
* it after. But this disabling interrupt sets the VAS IRQ OFF
220
+
* state in the hypervisor. If the NX generates fault interrupt
221
+
* during this window, the hypervisor will not deliver this
222
+
* interrupt to the LPAR. So use VAS specific IRQ handler instead
223
+
* of calling the default primary handler.
224
+
*/
225
+
static irqreturn_t pseries_vas_irq_handler(int irq, void *data)
226
+
{
227
+
struct pseries_vas_window *txwin = data;
228
+
229
+
/*
230
+
* The thread hanlder will process this interrupt if it is
231
+
* already running.
232
+
*/
233
+
atomic_inc(&txwin->pending_faults);
234
+
235
+
return IRQ_WAKE_THREAD;
211
236
}
212
237
213
238
/*
···
265
240
goto out_irq;
266
241
}
267
242
268
-
rc = request_threaded_irq(txwin->fault_virq, NULL,
269
-
pseries_vas_fault_thread_fn, IRQF_ONESHOT,
243
+
rc = request_threaded_irq(txwin->fault_virq,
244
+
pseries_vas_irq_handler,
245
+
pseries_vas_fault_thread_fn, 0,
270
246
txwin->name, txwin);
271
247
if (rc) {
272
248
pr_err("VAS-Window[%d]: Request IRQ(%u) failed with %d\n",
···
852
826
mutex_unlock(&vas_pseries_mutex);
853
827
return rc;
854
828
}
829
+
830
+
int pseries_vas_dlpar_cpu(void)
831
+
{
832
+
int new_nr_creds, rc;
833
+
834
+
rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES,
835
+
vascaps[VAS_GZIP_DEF_FEAT_TYPE].feat,
836
+
(u64)virt_to_phys(&hv_cop_caps));
837
+
if (!rc) {
838
+
new_nr_creds = be16_to_cpu(hv_cop_caps.target_lpar_creds);
839
+
rc = vas_reconfig_capabilties(VAS_GZIP_DEF_FEAT_TYPE, new_nr_creds);
840
+
}
841
+
842
+
if (rc)
843
+
pr_err("Failed reconfig VAS capabilities with DLPAR\n");
844
+
845
+
return rc;
846
+
}
847
+
855
848
/*
856
849
* Total number of default credits available (target_credits)
857
850
* in LPAR depends on number of cores configured. It varies based on
···
885
840
struct of_reconfig_data *rd = data;
886
841
struct device_node *dn = rd->dn;
887
842
const __be32 *intserv = NULL;
888
-
int new_nr_creds, len, rc = 0;
843
+
int len;
844
+
845
+
/*
846
+
* For shared CPU partition, the hypervisor assigns total credits
847
+
* based on entitled core capacity. So updating VAS windows will
848
+
* be called from lparcfg_write().
849
+
*/
850
+
if (is_shared_processor())
851
+
return NOTIFY_OK;
889
852
890
853
if ((action == OF_RECONFIG_ATTACH_NODE) ||
891
854
(action == OF_RECONFIG_DETACH_NODE))
···
905
852
if (!intserv)
906
853
return NOTIFY_OK;
907
854
908
-
rc = h_query_vas_capabilities(H_QUERY_VAS_CAPABILITIES,
909
-
vascaps[VAS_GZIP_DEF_FEAT_TYPE].feat,
910
-
(u64)virt_to_phys(&hv_cop_caps));
911
-
if (!rc) {
912
-
new_nr_creds = be16_to_cpu(hv_cop_caps.target_lpar_creds);
913
-
rc = vas_reconfig_capabilties(VAS_GZIP_DEF_FEAT_TYPE,
914
-
new_nr_creds);
915
-
}
916
-
917
-
if (rc)
918
-
pr_err("Failed reconfig VAS capabilities with DLPAR\n");
919
-
920
-
return rc;
855
+
return pseries_vas_dlpar_cpu();
921
856
}
922
857
923
858
static struct notifier_block pseries_vas_nb = {
+6
arch/powerpc/platforms/pseries/vas.h
+6
arch/powerpc/platforms/pseries/vas.h
···
132
132
u64 flags;
133
133
char *name;
134
134
int fault_virq;
135
+
atomic_t pending_faults; /* Number of pending faults */
135
136
};
136
137
137
138
int sysfs_add_vas_caps(struct vas_cop_feat_caps *caps);
···
141
140
142
141
#ifdef CONFIG_PPC_VAS
143
142
int vas_migration_handler(int action);
143
+
int pseries_vas_dlpar_cpu(void);
144
144
#else
145
145
static inline int vas_migration_handler(int action)
146
+
{
147
+
return 0;
148
+
}
149
+
static inline int pseries_vas_dlpar_cpu(void)
146
150
{
147
151
return 0;
148
152
}