x86/decompressor: Use standard calling convention for trampoline

Update the trampoline code so its arguments are passed via RDI and RSI,
which matches the ordinary SysV calling convention for x86_64. This will
allow this code to be called directly from C.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: https://lore.kernel.org/r/20230807162720.545787-11-ardb@kernel.org

authored by

Ard Biesheuvel and committed by

Borislav Petkov (AMD) 2 years ago 918a7a04 e8972a76

+14 -15

2 changed files

expand all

arch

x86

boot

compressed

head_64.S

pgtable.h

+13 -14

arch/x86/boot/compressed/head_64.S

··· 444 444 movq %r15, %rdi 445 445 call paging_prepare 446 446 447 - /* Save the trampoline address in RCX */ 448 - movq %rax, %rcx 449 - 447 + /* Pass the trampoline address and boolean flag as args #1 and #2 */ 448 + movq %rax, %rdi 449 + movq %rdx, %rsi 450 450 leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax 451 451 call *%rax 452 452 ··· 531 531 SYM_FUNC_END(.Lrelocated) 532 532 533 533 /* 534 - * This is the 32-bit trampoline that will be copied over to low memory. 534 + * This is the 32-bit trampoline that will be copied over to low memory. It 535 + * will be called using the ordinary 64-bit calling convention from code 536 + * running in 64-bit mode. 535 537 * 536 538 * Return address is at the top of the stack (might be above 4G). 537 - * ECX contains the base address of the trampoline memory. 538 - * Non zero RDX means trampoline needs to enable 5-level paging. 539 + * The first argument (EDI) contains the 32-bit addressable base of the 540 + * trampoline memory. A non-zero second argument (ESI) means that the 541 + * trampoline needs to enable 5-level paging. 539 542 */ 540 543 SYM_CODE_START(trampoline_32bit_src) 541 544 /* ··· 585 582 movl %eax, %cr0 586 583 587 584 /* Check what paging mode we want to be in after the trampoline */ 588 - testl %edx, %edx 585 + testl %esi, %esi 589 586 jz 1f 590 587 591 588 /* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */ ··· 600 597 jz 3f 601 598 2: 602 599 /* Point CR3 to the trampoline's new top level page table */ 603 - leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax 600 + leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%edi), %eax 604 601 movl %eax, %cr3 605 602 3: 606 603 /* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */ 607 - pushl %ecx 608 - pushl %edx 609 604 movl $MSR_EFER, %ecx 610 605 rdmsr 611 606 btsl $_EFER_LME, %eax 612 607 /* Avoid writing EFER if no change was made (for TDX guest) */ 613 608 jc 1f 614 609 wrmsr 615 - 1: popl %edx 616 - popl %ecx 617 - 610 + 1: 618 611 #ifdef CONFIG_X86_MCE 619 612 /* 620 613 * Preserve CR4.MCE if the kernel will enable #MC support. ··· 627 628 628 629 /* Enable PAE and LA57 (if required) paging modes */ 629 630 orl $X86_CR4_PAE, %eax 630 - testl %edx, %edx 631 + testl %esi, %esi 631 632 jz 1f 632 633 orl $X86_CR4_LA57, %eax 633 634 1:

+1 -1

arch/x86/boot/compressed/pgtable.h

··· 14 14 15 15 extern unsigned long *trampoline_32bit; 16 16 17 - extern void trampoline_32bit_src(void *return_ptr); 17 + extern void trampoline_32bit_src(void *trampoline, bool enable_5lvl); 18 18 19 19 #endif /* __ASSEMBLER__ */ 20 20 #endif /* BOOT_COMPRESSED_PAGETABLE_H */

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