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interconnect: qcom: icc-rpm: Let nodes drive their own bus clock

If this hardware couldn't get messier, some nodes are supposed to drive
their own bus clock.. Presumably to connect to some intermediate
interface between the node itself and the bus it's (supposed to be)
connected to.

Expand the node struct with the necessary data and hook up the
allocations & calculations.

Note that the node-specific AB/IB coefficients contribute (by design)
to both the node-level and the bus-level aggregation.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-3-c04b60caa467@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>

authored by

Konrad Dybcio and committed by
Georgi Djakov
919791d8 db8fc100

+31
+27
drivers/interconnect/qcom/icc-rpm.c
··· 414 414 qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; 415 415 } 416 416 417 + /* Handle the node-specific clock */ 418 + if (!src_qn->bus_clk_desc) 419 + return 0; 420 + 421 + active_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_ACTIVE_STATE); 422 + sleep_rate = qcom_icc_calc_rate(qp, src_qn, QCOM_SMD_RPM_SLEEP_STATE); 423 + 424 + if (active_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE]) { 425 + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_ACTIVE_STATE, 426 + active_rate); 427 + if (ret) 428 + return ret; 429 + 430 + /* Cache the rate after we've successfully committed it to RPM */ 431 + src_qn->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate; 432 + } 433 + 434 + if (sleep_rate != src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE]) { 435 + ret = qcom_icc_rpm_set_bus_rate(src_qn->bus_clk_desc, QCOM_SMD_RPM_SLEEP_STATE, 436 + sleep_rate); 437 + if (ret) 438 + return ret; 439 + 440 + /* Cache the rate after we've successfully committed it to RPM */ 441 + src_qn->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate; 442 + } 443 + 417 444 return 0; 418 445 } 419 446
+4
drivers/interconnect/qcom/icc-rpm.h
··· 97 97 * @num_links: the total number of @links 98 98 * @channels: number of channels at this node (e.g. DDR channels) 99 99 * @buswidth: width of the interconnect between a node and the bus (bytes) 100 + * @bus_clk_desc: a pointer to a rpm_clk_resource description of bus clocks 100 101 * @sum_avg: current sum aggregate value of all avg bw requests 101 102 * @max_peak: current max aggregate value of all peak bw requests 102 103 * @mas_rpm_id: RPM id for devices that are bus masters 103 104 * @slv_rpm_id: RPM id for devices that are bus slaves 104 105 * @qos: NoC QoS setting parameters 106 + * @bus_clk_rate: a pointer to an array containing bus clock rates in Hz 105 107 */ 106 108 struct qcom_icc_node { 107 109 unsigned char *name; ··· 112 110 u16 num_links; 113 111 u16 channels; 114 112 u16 buswidth; 113 + const struct rpm_clk_resource *bus_clk_desc; 115 114 u64 sum_avg[QCOM_SMD_RPM_STATE_NUM]; 116 115 u64 max_peak[QCOM_SMD_RPM_STATE_NUM]; 117 116 int mas_rpm_id; 118 117 int slv_rpm_id; 119 118 struct qcom_icc_qos qos; 119 + u32 bus_clk_rate[QCOM_SMD_RPM_STATE_NUM]; 120 120 }; 121 121 122 122 struct qcom_icc_desc {