Merge tag 'dmaengine-fix-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

+1 -1

drivers/dma/apple-admac.c

··· 493 493 return NULL; 494 494 } 495 495 496 - return &ad->channels[index].chan; 496 + return dma_get_slave_channel(&ad->channels[index].chan); 497 497 } 498 498 499 499 static int admac_drain_reports(struct admac_data *ad, int channo)

+60 -93

drivers/dma/at_hdmac.c

··· 256 256 ATC_SPIP_BOUNDARY(first->boundary)); 257 257 channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) | 258 258 ATC_DPIP_BOUNDARY(first->boundary)); 259 + /* Don't allow CPU to reorder channel enable. */ 260 + wmb(); 259 261 dma_writel(atdma, CHER, atchan->mask); 260 262 261 263 vdbg_dump_regs(atchan); ··· 318 316 struct at_desc *desc_first = atc_first_active(atchan); 319 317 struct at_desc *desc; 320 318 int ret; 321 - u32 ctrla, dscr, trials; 319 + u32 ctrla, dscr; 320 + unsigned int i; 322 321 323 322 /* 324 323 * If the cookie doesn't match to the currently running transfer then ··· 389 386 dscr = channel_readl(atchan, DSCR); 390 387 rmb(); /* ensure DSCR is read before CTRLA */ 391 388 ctrla = channel_readl(atchan, CTRLA); 392 - for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) { 389 + for (i = 0; i < ATC_MAX_DSCR_TRIALS; ++i) { 393 390 u32 new_dscr; 394 391 395 392 rmb(); /* ensure DSCR is read after CTRLA */ ··· 415 412 rmb(); /* ensure DSCR is read before CTRLA */ 416 413 ctrla = channel_readl(atchan, CTRLA); 417 414 } 418 - if (unlikely(trials >= ATC_MAX_DSCR_TRIALS)) 415 + if (unlikely(i == ATC_MAX_DSCR_TRIALS)) 419 416 return -ETIMEDOUT; 420 417 421 418 /* for the first descriptor we can be more accurate */ ··· 465 462 if (!atc_chan_is_cyclic(atchan)) 466 463 dma_cookie_complete(txd); 467 464 468 - /* If the transfer was a memset, free our temporary buffer */ 469 - if (desc->memset_buffer) { 470 - dma_pool_free(atdma->memset_pool, desc->memset_vaddr, 471 - desc->memset_paddr); 472 - desc->memset_buffer = false; 473 - } 474 - 475 - /* move children to free_list */ 476 - list_splice_init(&desc->tx_list, &atchan->free_list); 477 - /* move myself to free_list */ 478 - list_move(&desc->desc_node, &atchan->free_list); 479 - 480 465 spin_unlock_irqrestore(&atchan->lock, flags); 481 466 482 467 dma_descriptor_unmap(txd); ··· 474 483 dmaengine_desc_get_callback_invoke(txd, NULL); 475 484 476 485 dma_run_dependencies(txd); 477 - } 478 - 479 - /** 480 - * atc_complete_all - finish work for all transactions 481 - * @atchan: channel to complete transactions for 482 - * 483 - * Eventually submit queued descriptors if any 484 - * 485 - * Assume channel is idle while calling this function 486 - * Called with atchan->lock held and bh disabled 487 - */ 488 - static void atc_complete_all(struct at_dma_chan *atchan) 489 - { 490 - struct at_desc *desc, *_desc; 491 - LIST_HEAD(list); 492 - unsigned long flags; 493 - 494 - dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 495 486 496 487 spin_lock_irqsave(&atchan->lock, flags); 497 - 498 - /* 499 - * Submit queued descriptors ASAP, i.e. before we go through 500 - * the completed ones. 501 - */ 502 - if (!list_empty(&atchan->queue)) 503 - atc_dostart(atchan, atc_first_queued(atchan)); 504 - /* empty active_list now it is completed */ 505 - list_splice_init(&atchan->active_list, &list); 506 - /* empty queue list by moving descriptors (if any) to active_list */ 507 - list_splice_init(&atchan->queue, &atchan->active_list); 508 - 488 + /* move children to free_list */ 489 + list_splice_init(&desc->tx_list, &atchan->free_list); 490 + /* add myself to free_list */ 491 + list_add(&desc->desc_node, &atchan->free_list); 509 492 spin_unlock_irqrestore(&atchan->lock, flags); 510 493 511 - list_for_each_entry_safe(desc, _desc, &list, desc_node) 512 - atc_chain_complete(atchan, desc); 494 + /* If the transfer was a memset, free our temporary buffer */ 495 + if (desc->memset_buffer) { 496 + dma_pool_free(atdma->memset_pool, desc->memset_vaddr, 497 + desc->memset_paddr); 498 + desc->memset_buffer = false; 499 + } 513 500 } 514 501 515 502 /** ··· 496 527 */ 497 528 static void atc_advance_work(struct at_dma_chan *atchan) 498 529 { 530 + struct at_desc *desc; 499 531 unsigned long flags; 500 - int ret; 501 532 502 533 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 503 534 504 535 spin_lock_irqsave(&atchan->lock, flags); 505 - ret = atc_chan_is_enabled(atchan); 536 + if (atc_chan_is_enabled(atchan) || list_empty(&atchan->active_list)) 537 + return spin_unlock_irqrestore(&atchan->lock, flags); 538 + 539 + desc = atc_first_active(atchan); 540 + /* Remove the transfer node from the active list. */ 541 + list_del_init(&desc->desc_node); 506 542 spin_unlock_irqrestore(&atchan->lock, flags); 507 - if (ret) 508 - return; 509 - 510 - if (list_empty(&atchan->active_list) || 511 - list_is_singular(&atchan->active_list)) 512 - return atc_complete_all(atchan); 513 - 514 - atc_chain_complete(atchan, atc_first_active(atchan)); 543 + atc_chain_complete(atchan, desc); 515 544 516 545 /* advance work */ 517 546 spin_lock_irqsave(&atchan->lock, flags); 518 - atc_dostart(atchan, atc_first_active(atchan)); 547 + if (!list_empty(&atchan->active_list)) { 548 + desc = atc_first_queued(atchan); 549 + list_move_tail(&desc->desc_node, &atchan->active_list); 550 + atc_dostart(atchan, desc); 551 + } 519 552 spin_unlock_irqrestore(&atchan->lock, flags); 520 553 } 521 554 ··· 529 558 static void atc_handle_error(struct at_dma_chan *atchan) 530 559 { 531 560 struct at_desc *bad_desc; 561 + struct at_desc *desc; 532 562 struct at_desc *child; 533 563 unsigned long flags; 534 564 ··· 542 570 bad_desc = atc_first_active(atchan); 543 571 list_del_init(&bad_desc->desc_node); 544 572 545 - /* As we are stopped, take advantage to push queued descriptors 546 - * in active_list */ 547 - list_splice_init(&atchan->queue, atchan->active_list.prev); 548 - 549 573 /* Try to restart the controller */ 550 - if (!list_empty(&atchan->active_list)) 551 - atc_dostart(atchan, atc_first_active(atchan)); 574 + if (!list_empty(&atchan->active_list)) { 575 + desc = atc_first_queued(atchan); 576 + list_move_tail(&desc->desc_node, &atchan->active_list); 577 + atc_dostart(atchan, desc); 578 + } 552 579 553 580 /* 554 581 * KERN_CRITICAL may seem harsh, but since this only happens ··· 662 691 spin_lock_irqsave(&atchan->lock, flags); 663 692 cookie = dma_cookie_assign(tx); 664 693 665 - if (list_empty(&atchan->active_list)) { 666 - dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 667 - desc->txd.cookie); 668 - atc_dostart(atchan, desc); 669 - list_add_tail(&desc->desc_node, &atchan->active_list); 670 - } else { 671 - dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 672 - desc->txd.cookie); 673 - list_add_tail(&desc->desc_node, &atchan->queue); 674 - } 675 - 694 + list_add_tail(&desc->desc_node, &atchan->queue); 676 695 spin_unlock_irqrestore(&atchan->lock, flags); 677 696 697 + dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 698 + desc->txd.cookie); 678 699 return cookie; 679 700 } 680 701 ··· 1408 1445 struct at_dma_chan *atchan = to_at_dma_chan(chan); 1409 1446 struct at_dma *atdma = to_at_dma(chan->device); 1410 1447 int chan_id = atchan->chan_common.chan_id; 1411 - struct at_desc *desc, *_desc; 1412 1448 unsigned long flags; 1413 - 1414 - LIST_HEAD(list); 1415 1449 1416 1450 dev_vdbg(chan2dev(chan), "%s\n", __func__); 1417 1451 ··· 1428 1468 cpu_relax(); 1429 1469 1430 1470 /* active_list entries will end up before queued entries */ 1431 - list_splice_init(&atchan->queue, &list); 1432 - list_splice_init(&atchan->active_list, &list); 1433 - 1434 - spin_unlock_irqrestore(&atchan->lock, flags); 1435 - 1436 - /* Flush all pending and queued descriptors */ 1437 - list_for_each_entry_safe(desc, _desc, &list, desc_node) 1438 - atc_chain_complete(atchan, desc); 1471 + list_splice_tail_init(&atchan->queue, &atchan->free_list); 1472 + list_splice_tail_init(&atchan->active_list, &atchan->free_list); 1439 1473 1440 1474 clear_bit(ATC_IS_PAUSED, &atchan->status); 1441 1475 /* if channel dedicated to cyclic operations, free it */ 1442 1476 clear_bit(ATC_IS_CYCLIC, &atchan->status); 1477 + 1478 + spin_unlock_irqrestore(&atchan->lock, flags); 1443 1479 1444 1480 return 0; 1445 1481 } ··· 1491 1535 } 1492 1536 1493 1537 /** 1494 - * atc_issue_pending - try to finish work 1538 + * atc_issue_pending - takes the first transaction descriptor in the pending 1539 + * queue and starts the transfer. 1495 1540 * @chan: target DMA channel 1496 1541 */ 1497 1542 static void atc_issue_pending(struct dma_chan *chan) 1498 1543 { 1499 - struct at_dma_chan *atchan = to_at_dma_chan(chan); 1544 + struct at_dma_chan *atchan = to_at_dma_chan(chan); 1545 + struct at_desc *desc; 1546 + unsigned long flags; 1500 1547 1501 1548 dev_vdbg(chan2dev(chan), "issue_pending\n"); 1502 1549 1503 - /* Not needed for cyclic transfers */ 1504 - if (atc_chan_is_cyclic(atchan)) 1505 - return; 1550 + spin_lock_irqsave(&atchan->lock, flags); 1551 + if (atc_chan_is_enabled(atchan) || list_empty(&atchan->queue)) 1552 + return spin_unlock_irqrestore(&atchan->lock, flags); 1506 1553 1507 - atc_advance_work(atchan); 1554 + desc = atc_first_queued(atchan); 1555 + list_move_tail(&desc->desc_node, &atchan->active_list); 1556 + atc_dostart(atchan, desc); 1557 + spin_unlock_irqrestore(&atchan->lock, flags); 1508 1558 } 1509 1559 1510 1560 /** ··· 1928 1966 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 1929 1967 plat_dat->nr_channels); 1930 1968 1931 - dma_async_device_register(&atdma->dma_common); 1969 + err = dma_async_device_register(&atdma->dma_common); 1970 + if (err) { 1971 + dev_err(&pdev->dev, "Unable to register: %d.\n", err); 1972 + goto err_dma_async_device_register; 1973 + } 1932 1974 1933 1975 /* 1934 1976 * Do not return an error if the dmac node is not present in order to ··· 1952 1986 1953 1987 err_of_dma_controller_register: 1954 1988 dma_async_device_unregister(&atdma->dma_common); 1989 + err_dma_async_device_register: 1955 1990 dma_pool_destroy(atdma->memset_pool); 1956 1991 err_memset_pool_create: 1957 1992 dma_pool_destroy(atdma->dma_desc_pool);

+5 -5

drivers/dma/at_hdmac_regs.h

··· 186 186 /* LLI == Linked List Item; aka DMA buffer descriptor */ 187 187 struct at_lli { 188 188 /* values that are not changed by hardware */ 189 - dma_addr_t saddr; 190 - dma_addr_t daddr; 189 + u32 saddr; 190 + u32 daddr; 191 191 /* value that may get written back: */ 192 - u32 ctrla; 192 + u32 ctrla; 193 193 /* more values that are not changed by hardware */ 194 - u32 ctrlb; 195 - dma_addr_t dscr; /* chain to next lli */ 194 + u32 ctrlb; 195 + u32 dscr; /* chain to next lli */ 196 196 }; 197 197 198 198 /**

+18

drivers/dma/idxd/cdev.c

··· 312 312 if (idxd->state != IDXD_DEV_ENABLED) 313 313 return -ENXIO; 314 314 315 + /* 316 + * User type WQ is enabled only when SVA is enabled for two reasons: 317 + * - If no IOMMU or IOMMU Passthrough without SVA, userspace 318 + * can directly access physical address through the WQ. 319 + * - The IDXD cdev driver does not provide any ways to pin 320 + * user pages and translate the address from user VA to IOVA or 321 + * PA without IOMMU SVA. Therefore the application has no way 322 + * to instruct the device to perform DMA function. This makes 323 + * the cdev not usable for normal application usage. 324 + */ 325 + if (!device_user_pasid_enabled(idxd)) { 326 + idxd->cmd_status = IDXD_SCMD_WQ_USER_NO_IOMMU; 327 + dev_dbg(&idxd->pdev->dev, 328 + "User type WQ cannot be enabled without SVA.\n"); 329 + 330 + return -EOPNOTSUPP; 331 + } 332 + 315 333 mutex_lock(&wq->wq_lock); 316 334 wq->type = IDXD_WQT_USER; 317 335 rc = drv_enable_wq(wq);

+17 -9

drivers/dma/idxd/device.c

··· 390 390 clear_bit(WQ_FLAG_ATS_DISABLE, &wq->flags); 391 391 memset(wq->name, 0, WQ_NAME_SIZE); 392 392 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 393 - wq->max_batch_size = WQ_DEFAULT_MAX_BATCH; 393 + idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 394 394 if (wq->opcap_bmap) 395 395 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 396 396 } ··· 730 730 731 731 void idxd_device_clear_state(struct idxd_device *idxd) 732 732 { 733 - if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 734 - return; 733 + /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */ 734 + if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 735 + /* 736 + * Clearing wq state is protected by wq lock. 737 + * So no need to be protected by device lock. 738 + */ 739 + idxd_device_wqs_clear_state(idxd); 735 740 736 - idxd_device_wqs_clear_state(idxd); 737 - spin_lock(&idxd->dev_lock); 738 - idxd_groups_clear_state(idxd); 739 - idxd_engines_clear_state(idxd); 741 + spin_lock(&idxd->dev_lock); 742 + idxd_groups_clear_state(idxd); 743 + idxd_engines_clear_state(idxd); 744 + } else { 745 + spin_lock(&idxd->dev_lock); 746 + } 747 + 740 748 idxd->state = IDXD_DEV_DISABLED; 741 749 spin_unlock(&idxd->dev_lock); 742 750 } ··· 877 869 878 870 /* bytes 12-15 */ 879 871 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 880 - wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 872 + idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size)); 881 873 882 874 /* bytes 32-63 */ 883 875 if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { ··· 1059 1051 wq->priority = wq->wqcfg->priority; 1060 1052 1061 1053 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1062 - wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift; 1054 + idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift); 1063 1055 1064 1056 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1065 1057 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);

+32

drivers/dma/idxd/idxd.h

··· 548 548 return wq->client_count; 549 549 }; 550 550 551 + /* 552 + * Intel IAA does not support batch processing. 553 + * The max batch size of device, max batch size of wq and 554 + * max batch shift of wqcfg should be always 0 on IAA. 555 + */ 556 + static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd, 557 + u32 max_batch_size) 558 + { 559 + if (idxd_type == IDXD_TYPE_IAX) 560 + idxd->max_batch_size = 0; 561 + else 562 + idxd->max_batch_size = max_batch_size; 563 + } 564 + 565 + static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq, 566 + u32 max_batch_size) 567 + { 568 + if (idxd_type == IDXD_TYPE_IAX) 569 + wq->max_batch_size = 0; 570 + else 571 + wq->max_batch_size = max_batch_size; 572 + } 573 + 574 + static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg, 575 + u32 max_batch_shift) 576 + { 577 + if (idxd_type == IDXD_TYPE_IAX) 578 + wqcfg->max_batch_shift = 0; 579 + else 580 + wqcfg->max_batch_shift = max_batch_shift; 581 + } 582 + 551 583 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv, 552 584 struct module *module, const char *mod_name); 553 585 #define idxd_driver_register(driver) \

+2 -2

drivers/dma/idxd/init.c

··· 183 183 init_completion(&wq->wq_dead); 184 184 init_completion(&wq->wq_resurrect); 185 185 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 186 - wq->max_batch_size = WQ_DEFAULT_MAX_BATCH; 186 + idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 187 187 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 188 188 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 189 189 if (!wq->wqcfg) { ··· 418 418 419 419 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 420 420 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 421 - idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift; 421 + idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift); 422 422 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 423 423 if (idxd->hw.gen_cap.config_en) 424 424 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);

+1 -1

drivers/dma/idxd/sysfs.c

··· 1046 1046 if (batch_size > idxd->max_batch_size) 1047 1047 return -EINVAL; 1048 1048 1049 - wq->max_batch_size = (u32)batch_size; 1049 + idxd_wq_set_max_batch_size(idxd->data->type, wq, (u32)batch_size); 1050 1050 1051 1051 return count; 1052 1052 }

+1

drivers/dma/mv_xor_v2.c

··· 893 893 tasklet_kill(&xor_dev->irq_tasklet); 894 894 895 895 clk_disable_unprepare(xor_dev->clk); 896 + clk_disable_unprepare(xor_dev->reg_clk); 896 897 897 898 return 0; 898 899 }

+2 -2

drivers/dma/pxa_dma.c

··· 1247 1247 return -ENOMEM; 1248 1248 1249 1249 for (i = 0; i < nb_phy_chans; i++) 1250 - if (platform_get_irq(op, i) > 0) 1250 + if (platform_get_irq_optional(op, i) > 0) 1251 1251 nr_irq++; 1252 1252 1253 1253 for (i = 0; i < nb_phy_chans; i++) { 1254 1254 phy = &pdev->phys[i]; 1255 1255 phy->base = pdev->base; 1256 1256 phy->idx = i; 1257 - irq = platform_get_irq(op, i); 1257 + irq = platform_get_irq_optional(op, i); 1258 1258 if ((nr_irq > 1) && (irq > 0)) 1259 1259 ret = devm_request_irq(&op->dev, irq, 1260 1260 pxad_chan_handler,

+6 -8

drivers/dma/stm32-dma.c

··· 675 675 676 676 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 677 677 678 + chan->status = DMA_PAUSED; 679 + 678 680 dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); 679 681 } 680 682 ··· 791 789 if (status & STM32_DMA_TCI) { 792 790 stm32_dma_irq_clear(chan, STM32_DMA_TCI); 793 791 if (scr & STM32_DMA_SCR_TCIE) { 794 - if (chan->status == DMA_PAUSED && !(scr & STM32_DMA_SCR_EN)) 795 - stm32_dma_handle_chan_paused(chan); 796 - else 792 + if (chan->status != DMA_PAUSED) 797 793 stm32_dma_handle_chan_done(chan, scr); 798 794 } 799 795 status &= ~STM32_DMA_TCI; ··· 838 838 return -EPERM; 839 839 840 840 spin_lock_irqsave(&chan->vchan.lock, flags); 841 + 841 842 ret = stm32_dma_disable_chan(chan); 842 - /* 843 - * A transfer complete flag is set to indicate the end of transfer due to the stream 844 - * interruption, so wait for interrupt 845 - */ 846 843 if (!ret) 847 - chan->status = DMA_PAUSED; 844 + stm32_dma_handle_chan_paused(chan); 845 + 848 846 spin_unlock_irqrestore(&chan->vchan.lock, flags); 849 847 850 848 return ret;

+1

drivers/dma/stm32-mdma.c

··· 1539 1539 return NULL; 1540 1540 } 1541 1541 1542 + memset(&config, 0, sizeof(config)); 1542 1543 config.request = dma_spec->args[0]; 1543 1544 config.priority_level = dma_spec->args[1]; 1544 1545 config.transfer_config = dma_spec->args[2];

+3

drivers/dma/ti/k3-udma-glue.c

··· 299 299 ret = device_register(&tx_chn->common.chan_dev); 300 300 if (ret) { 301 301 dev_err(dev, "Channel Device registration failed %d\n", ret); 302 + put_device(&tx_chn->common.chan_dev); 302 303 tx_chn->common.chan_dev.parent = NULL; 303 304 goto err; 304 305 } ··· 918 917 ret = device_register(&rx_chn->common.chan_dev); 919 918 if (ret) { 920 919 dev_err(dev, "Channel Device registration failed %d\n", ret); 920 + put_device(&rx_chn->common.chan_dev); 921 921 rx_chn->common.chan_dev.parent = NULL; 922 922 goto err; 923 923 } ··· 1050 1048 ret = device_register(&rx_chn->common.chan_dev); 1051 1049 if (ret) { 1052 1050 dev_err(dev, "Channel Device registration failed %d\n", ret); 1051 + put_device(&rx_chn->common.chan_dev); 1053 1052 rx_chn->common.chan_dev.parent = NULL; 1054 1053 goto err; 1055 1054 }

+1

include/uapi/linux/idxd.h

··· 29 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 + IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 32 33 }; 33 34 34 35 #define IDXD_SCMD_SOFTERR_MASK 0x80000000

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