Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tty-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty / serial driver updates from Greg KH:
"Here is the big set of TTY and Serial driver updates for 6.17-rc1.
Included in here is the following types of changes:
- another cleanup round from Jiri for the 8250 serial driver and some
other tty drivers, things are slowly getting better with our apis
thanks to this work. This touched many tty drivers all over the
tree.
- qcom_geni_serial driver update for new platforms and devices
- 8250 quirk handling fixups
- dt serial binding updates for different boards/platforms
- other minor cleanups and fixes
All of these have been in linux-next with no reported issues"
* tag 'tty-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (79 commits)
dt-bindings: serial: snps-dw-apb-uart: Allow use of a power-domain
serial: 8250: fix panic due to PSLVERR
dt-bindings: serial: samsung: add samsung,exynos2200-uart compatible
vt: defkeymap: Map keycodes above 127 to K_HOLE
vt: keyboard: Don't process Unicode characters in K_OFF mode
serial: qcom-geni: Enable Serial on SA8255p Qualcomm platforms
serial: qcom-geni: Enable PM runtime for serial driver
serial: qcom-geni: move clock-rate logic to separate function
serial: qcom-geni: move resource control logic to separate functions
serial: qcom-geni: move resource initialization to separate function
soc: qcom: geni-se: Enable QUPs on SA8255p Qualcomm platforms
dt-bindings: qcom: geni-se: describe SA8255p
dt-bindings: serial: describe SA8255p
serial: 8250_dw: Fix typo "notifer"
dt-bindings: serial: 8250: spacemit: set clocks property as required
dt-bindings: serial: renesas: Document RZ/V2N SCIF
serial: 8250_ce4100: Fix CONFIG_SERIAL_8250=n build
tty: omit need_resched() before cond_resched()
serial: 8250_ni: Reorder local variables
serial: 8250_ni: Fix build warning
...
+2331
-1153
+40
-5
Documentation/devicetree/bindings/serial/8250.yaml
+40
-5
Documentation/devicetree/bindings/serial/8250.yaml
···
49
49
- required: [ clock-frequency ]
50
50
- required: [ clocks ]
51
51
52
+
- if:
53
+
properties:
54
+
compatible:
55
+
contains:
56
+
const: nxp,lpc1850-uart
57
+
then:
58
+
properties:
59
+
clock-names:
60
+
items:
61
+
- const: uartclk
62
+
- const: reg
63
+
else:
64
+
properties:
65
+
clock-names:
66
+
items:
67
+
- const: core
68
+
- const: bus
69
+
52
70
properties:
53
71
compatible:
54
72
oneOf:
···
160
142
161
143
clock-names:
162
144
minItems: 1
163
-
items:
164
-
- const: core
165
-
- const: bus
145
+
maxItems: 2
146
+
oneOf:
147
+
- items:
148
+
- const: core
149
+
- const: bus
150
+
- items:
151
+
- const: uartclk
152
+
- const: reg
153
+
154
+
dmas:
155
+
minItems: 1
156
+
maxItems: 4
157
+
158
+
dma-names:
159
+
minItems: 1
160
+
maxItems: 4
166
161
167
162
resets:
168
163
maxItems: 1
···
268
237
properties:
269
238
compatible:
270
239
contains:
271
-
const: spacemit,k1-uart
240
+
enum:
241
+
- spacemit,k1-uart
242
+
- nxp,lpc1850-uart
272
243
then:
273
-
required: [clock-names]
244
+
required:
245
+
- clocks
246
+
- clock-names
274
247
properties:
275
248
clocks:
276
249
minItems: 2
+1
Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+1
Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+69
Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml
+69
Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/serial/qcom,sa8255p-geni-uart.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Geni based QUP UART interface
8
+
9
+
maintainers:
10
+
- Praveen Talari <quic_ptalari@quicinc.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/serial/serial.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- qcom,sa8255p-geni-uart
19
+
- qcom,sa8255p-geni-debug-uart
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
interrupts:
25
+
minItems: 1
26
+
items:
27
+
- description: UART core irq
28
+
- description: Wakeup irq (RX GPIO)
29
+
30
+
interrupt-names:
31
+
description:
32
+
The UART interrupt and optionally the RX in-band wakeup interrupt
33
+
as not all UART instances have a wakeup-capable interrupt routed
34
+
via the PDC.
35
+
minItems: 1
36
+
items:
37
+
- const: uart
38
+
- const: wakeup
39
+
40
+
power-domains:
41
+
minItems: 2
42
+
maxItems: 2
43
+
44
+
power-domain-names:
45
+
items:
46
+
- const: power
47
+
- const: perf
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- interrupts
53
+
- power-domains
54
+
- power-domain-names
55
+
56
+
unevaluatedProperties: false
57
+
58
+
examples:
59
+
- |
60
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
61
+
62
+
serial@990000 {
63
+
compatible = "qcom,sa8255p-geni-uart";
64
+
reg = <0x990000 0x4000>;
65
+
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
66
+
power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>;
67
+
power-domain-names = "power", "perf";
68
+
};
69
+
...
+7
Documentation/devicetree/bindings/serial/renesas,hscif.yaml
+7
Documentation/devicetree/bindings/serial/renesas,hscif.yaml
···
63
63
- const: renesas,rcar-gen4-hscif # R-Car Gen4
64
64
- const: renesas,hscif # generic HSCIF compatible UART
65
65
66
+
- items:
67
+
- enum:
68
+
- renesas,hscif-r8a78000 # R-Car X5H
69
+
- const: renesas,rcar-gen5-hscif # R-Car Gen5
70
+
- const: renesas,hscif # generic HSCIF compatible UART
71
+
66
72
reg:
67
73
maxItems: 1
68
74
···
126
120
- renesas,rcar-gen2-hscif
127
121
- renesas,rcar-gen3-hscif
128
122
- renesas,rcar-gen4-hscif
123
+
- renesas,rcar-gen5-hscif
129
124
then:
130
125
required:
131
126
- resets
+17
-10
Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+17
-10
Documentation/devicetree/bindings/serial/renesas,rsci.yaml
···
8
8
9
9
maintainers:
10
10
- Geert Uytterhoeven <geert+renesas@glider.be>
11
-
- Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
11
+
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12
12
13
13
allOf:
14
14
- $ref: serial.yaml#
15
15
16
16
properties:
17
17
compatible:
18
-
const: renesas,r9a09g077-rsci # RZ/T2H
18
+
oneOf:
19
+
- items:
20
+
- const: renesas,r9a09g087-rsci # RZ/N2H
21
+
- const: renesas,r9a09g077-rsci # RZ/T2H
22
+
23
+
- items:
24
+
- const: renesas,r9a09g077-rsci # RZ/T2H
19
25
20
26
reg:
21
27
maxItems: 1
···
41
35
- const: tei
42
36
43
37
clocks:
44
-
maxItems: 1
38
+
minItems: 2
39
+
maxItems: 3
45
40
46
41
clock-names:
47
-
const: fck # UART functional clock
42
+
minItems: 2
43
+
items:
44
+
- const: operation
45
+
- const: bus
46
+
- const: sck # optional external clock input
48
47
49
48
power-domains:
50
49
maxItems: 1
···
71
60
#include <dt-bindings/interrupt-controller/arm-gic.h>
72
61
#include <dt-bindings/clock/renesas-cpg-mssr.h>
73
62
74
-
aliases {
75
-
serial0 = &sci0;
76
-
};
77
-
78
63
sci0: serial@80005000 {
79
64
compatible = "renesas,r9a09g077-rsci";
80
65
reg = <0x80005000 0x400>;
···
79
72
<GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
80
73
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
81
74
interrupt-names = "eri", "rxi", "txi", "tei";
82
-
clocks = <&cpg CPG_MOD 108>;
83
-
clock-names = "fck";
75
+
clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE 13>;
76
+
clock-names = "operation", "bus";
84
77
power-domains = <&cpg>;
85
78
};
+8
Documentation/devicetree/bindings/serial/renesas,scif.yaml
+8
Documentation/devicetree/bindings/serial/renesas,scif.yaml
···
72
72
73
73
- items:
74
74
- enum:
75
+
- renesas,scif-r8a78000 # R-Car X5H
76
+
- const: renesas,rcar-gen5-scif # R-Car Gen5
77
+
- const: renesas,scif # generic SCIF compatible UART
78
+
79
+
- items:
80
+
- enum:
75
81
- renesas,scif-r9a07g044 # RZ/G2{L,LC}
76
82
77
83
- items:
···
92
86
- items:
93
87
- enum:
94
88
- renesas,scif-r9a09g047 # RZ/G3E
89
+
- renesas,scif-r9a09g056 # RZ/V2N
95
90
- const: renesas,scif-r9a09g057 # RZ/V2H fallback
96
91
97
92
reg:
···
181
174
- renesas,rcar-gen2-scif
182
175
- renesas,rcar-gen3-scif
183
176
- renesas,rcar-gen4-scif
177
+
- renesas,rcar-gen5-scif
184
178
- renesas,scif-r9a07g044
185
179
- renesas,scif-r9a09g057
186
180
then:
+4
Documentation/devicetree/bindings/serial/samsung_uart.yaml
+4
Documentation/devicetree/bindings/serial/samsung_uart.yaml
+3
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+3
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+107
Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml
+107
Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: GENI Serial Engine QUP Wrapper Controller
8
+
9
+
maintainers:
10
+
- Praveen Talari <quic_ptalari@quicinc.com>
11
+
12
+
description:
13
+
Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
14
+
is a programmable module for supporting a wide range of serial interfaces
15
+
like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial
16
+
Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
17
+
Wrapper controller is modeled as a node with zero or more child nodes each
18
+
representing a serial engine.
19
+
20
+
properties:
21
+
compatible:
22
+
const: qcom,sa8255p-geni-se-qup
23
+
24
+
reg:
25
+
description: QUP wrapper common register address and length.
26
+
maxItems: 1
27
+
28
+
"#address-cells":
29
+
const: 2
30
+
31
+
"#size-cells":
32
+
const: 2
33
+
34
+
ranges: true
35
+
36
+
iommus:
37
+
maxItems: 1
38
+
39
+
dma-coherent: true
40
+
41
+
patternProperties:
42
+
"spi@[0-9a-f]+$":
43
+
type: object
44
+
description: GENI serial engine based SPI controller. SPI in master mode
45
+
supports up to 50MHz, up to four chip selects, programmable
46
+
data path from 4 bits to 32 bits and numerous protocol
47
+
variants.
48
+
additionalProperties: true
49
+
50
+
properties:
51
+
compatible:
52
+
const: qcom,sa8255p-geni-spi
53
+
54
+
"i2c@[0-9a-f]+$":
55
+
type: object
56
+
description: GENI serial engine based I2C controller.
57
+
additionalProperties: true
58
+
59
+
properties:
60
+
compatible:
61
+
const: qcom,sa8255p-geni-i2c
62
+
63
+
"serial@[0-9a-f]+$":
64
+
type: object
65
+
description: GENI Serial Engine based UART Controller.
66
+
additionalProperties: true
67
+
68
+
properties:
69
+
compatible:
70
+
enum:
71
+
- qcom,sa8255p-geni-uart
72
+
- qcom,sa8255p-geni-debug-uart
73
+
74
+
required:
75
+
- compatible
76
+
- reg
77
+
- "#address-cells"
78
+
- "#size-cells"
79
+
- ranges
80
+
81
+
additionalProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
86
+
87
+
soc {
88
+
#address-cells = <2>;
89
+
#size-cells = <2>;
90
+
91
+
geniqup@9c0000 {
92
+
compatible = "qcom,sa8255p-geni-se-qup";
93
+
reg = <0 0x9c0000 0 0x6000>;
94
+
#address-cells = <2>;
95
+
#size-cells = <2>;
96
+
ranges;
97
+
98
+
serial@990000 {
99
+
compatible = "qcom,sa8255p-geni-uart";
100
+
reg = <0 0x990000 0 0x4000>;
101
+
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
102
+
power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>;
103
+
power-domain-names = "power", "perf";
104
+
};
105
+
};
106
+
};
107
+
...
+3
-4
Documentation/driver-api/serial/driver.rst
+3
-4
Documentation/driver-api/serial/driver.rst
···
24
24
Console Support
25
25
---------------
26
26
27
-
The serial core provides a few helper functions. This includes identifying
28
-
the correct port structure (via uart_get_console()) and decoding command line
29
-
arguments (uart_parse_options()).
27
+
The serial core provides a few helper functions. This includes
28
+
decoding command line arguments (uart_parse_options()).
30
29
31
30
There is also a helper function (uart_console_write()) which performs a
32
31
character by character write, translating newlines to CRLF sequences.
···
75
76
uart_add_one_port uart_remove_one_port uart_console_write
76
77
uart_parse_earlycon uart_parse_options uart_set_options
77
78
uart_get_lsr_info uart_handle_dcd_change uart_handle_cts_change
78
-
uart_try_toggle_sysrq uart_get_console
79
+
uart_try_toggle_sysrq
79
80
80
81
.. kernel-doc:: include/linux/serial_core.h
81
82
:identifiers: uart_port_tx_limited uart_port_tx
+3
-2
Documentation/driver-api/tty/tty_port.rst
+3
-2
Documentation/driver-api/tty/tty_port.rst
···
42
42
TTY Helpers
43
43
-----------
44
44
45
+
.. kernel-doc:: include/linux/tty_port.h
46
+
:identifiers: tty_port_tty_hangup tty_port_tty_vhangup
45
47
.. kernel-doc:: drivers/tty/tty_port.c
46
-
:identifiers: tty_port_tty_hangup tty_port_tty_wakeup
47
-
48
+
:identifiers: tty_port_tty_wakeup
48
49
49
50
Modem Signals
50
51
-------------
-2
arch/m68k/amiga/config.c
-2
arch/m68k/amiga/config.c
···
16
16
#include <linux/kernel.h>
17
17
#include <linux/mm.h>
18
18
#include <linux/seq_file.h>
19
-
#include <linux/tty.h>
20
19
#include <linux/clocksource.h>
21
20
#include <linux/console.h>
22
21
#include <linux/rtc.h>
23
22
#include <linux/init.h>
24
-
#include <linux/vt_kern.h>
25
23
#include <linux/delay.h>
26
24
#include <linux/interrupt.h>
27
25
#include <linux/zorro.h>
-2
arch/m68k/apollo/config.c
-2
arch/m68k/apollo/config.c
-1
arch/m68k/atari/config.c
-1
arch/m68k/atari/config.c
-2
arch/m68k/mac/config.c
-2
arch/m68k/mac/config.c
···
15
15
#include <linux/reboot.h>
16
16
#include <linux/types.h>
17
17
#include <linux/mm.h>
18
-
#include <linux/tty.h>
19
18
#include <linux/console.h>
20
19
#include <linux/interrupt.h>
21
20
/* keyb */
···
22
23
#include <linux/delay.h>
23
24
/* keyb */
24
25
#include <linux/init.h>
25
-
#include <linux/vt_kern.h>
26
26
#include <linux/platform_device.h>
27
27
#include <linux/ata_platform.h>
28
28
#include <linux/adb.h>
-2
arch/m68k/q40/config.c
-2
arch/m68k/q40/config.c
···
13
13
#include <linux/types.h>
14
14
#include <linux/kernel.h>
15
15
#include <linux/mm.h>
16
-
#include <linux/tty.h>
17
16
#include <linux/console.h>
18
17
#include <linux/linkage.h>
19
18
#include <linux/init.h>
20
19
#include <linux/major.h>
21
20
#include <linux/serial_reg.h>
22
21
#include <linux/rtc.h>
23
-
#include <linux/vt_kern.h>
24
22
#include <linux/bcd.h>
25
23
#include <linux/platform_device.h>
26
24
+30
-30
arch/powerpc/kernel/legacy_serial.c
+30
-30
arch/powerpc/kernel/legacy_serial.c
···
54
54
static const upf_t legacy_port_flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
55
55
UPF_SHARE_IRQ | UPF_FIXED_PORT;
56
56
57
-
static unsigned int tsi_serial_in(struct uart_port *p, int offset)
57
+
static u32 tsi_serial_in(struct uart_port *p, unsigned int offset)
58
58
{
59
-
unsigned int tmp;
59
+
u32 tmp;
60
+
60
61
offset = offset << p->regshift;
61
62
if (offset == UART_IIR) {
62
63
tmp = readl(p->membase + (UART_IIR & ~3));
···
66
65
return readb(p->membase + offset);
67
66
}
68
67
69
-
static void tsi_serial_out(struct uart_port *p, int offset, int value)
68
+
static void tsi_serial_out(struct uart_port *p, unsigned int offset, u32 value)
70
69
{
71
70
offset = offset << p->regshift;
72
71
if (!((offset == UART_IER) && (value & UART_IER_UUE)))
···
78
77
phys_addr_t taddr, unsigned long irq,
79
78
upf_t flags, int irq_check_parent)
80
79
{
80
+
struct plat_serial8250_port *legacy_port;
81
+
struct legacy_serial_info *legacy_info;
81
82
const __be32 *clk, *spd, *rs;
82
83
u32 clock = BASE_BAUD * 16;
83
84
u32 shift = 0;
···
113
110
if (index >= legacy_serial_count)
114
111
legacy_serial_count = index + 1;
115
112
113
+
legacy_port = &legacy_serial_ports[index];
114
+
legacy_info = &legacy_serial_infos[index];
115
+
116
116
/* Check if there is a port who already claimed our slot */
117
-
if (legacy_serial_infos[index].np != NULL) {
117
+
if (legacy_info->np != NULL) {
118
118
/* if we still have some room, move it, else override */
119
119
if (legacy_serial_count < MAX_LEGACY_SERIAL_PORTS) {
120
120
printk(KERN_DEBUG "Moved legacy port %d -> %d\n",
121
121
index, legacy_serial_count);
122
-
legacy_serial_ports[legacy_serial_count] =
123
-
legacy_serial_ports[index];
124
-
legacy_serial_infos[legacy_serial_count] =
125
-
legacy_serial_infos[index];
122
+
legacy_serial_ports[legacy_serial_count] = *legacy_port;
123
+
legacy_serial_infos[legacy_serial_count] = *legacy_info;
126
124
legacy_serial_count++;
127
125
} else {
128
126
printk(KERN_DEBUG "Replacing legacy port %d\n", index);
···
131
127
}
132
128
133
129
/* Now fill the entry */
134
-
memset(&legacy_serial_ports[index], 0,
135
-
sizeof(struct plat_serial8250_port));
130
+
memset(legacy_port, 0, sizeof(*legacy_port));
136
131
if (iotype == UPIO_PORT)
137
-
legacy_serial_ports[index].iobase = base;
132
+
legacy_port->iobase = base;
138
133
else
139
-
legacy_serial_ports[index].mapbase = base;
134
+
legacy_port->mapbase = base;
140
135
141
-
legacy_serial_ports[index].iotype = iotype;
142
-
legacy_serial_ports[index].uartclk = clock;
143
-
legacy_serial_ports[index].irq = irq;
144
-
legacy_serial_ports[index].flags = flags;
145
-
legacy_serial_ports[index].regshift = shift;
146
-
legacy_serial_infos[index].taddr = taddr;
147
-
legacy_serial_infos[index].np = of_node_get(np);
148
-
legacy_serial_infos[index].clock = clock;
149
-
legacy_serial_infos[index].speed = spd ? be32_to_cpup(spd) : 0;
150
-
legacy_serial_infos[index].irq_check_parent = irq_check_parent;
136
+
legacy_port->iotype = iotype;
137
+
legacy_port->uartclk = clock;
138
+
legacy_port->irq = irq;
139
+
legacy_port->flags = flags;
140
+
legacy_port->regshift = shift;
141
+
legacy_info->taddr = taddr;
142
+
legacy_info->np = of_node_get(np);
143
+
legacy_info->clock = clock;
144
+
legacy_info->speed = spd ? be32_to_cpup(spd) : 0;
145
+
legacy_info->irq_check_parent = irq_check_parent;
151
146
152
147
if (iotype == UPIO_TSI) {
153
-
legacy_serial_ports[index].serial_in = tsi_serial_in;
154
-
legacy_serial_ports[index].serial_out = tsi_serial_out;
148
+
legacy_port->serial_in = tsi_serial_in;
149
+
legacy_port->serial_out = tsi_serial_out;
155
150
}
156
151
157
-
printk(KERN_DEBUG "Found legacy serial port %d for %pOF\n",
158
-
index, np);
159
-
printk(KERN_DEBUG " %s=%llx, taddr=%llx, irq=%lx, clk=%d, speed=%d\n",
152
+
printk(KERN_DEBUG "Found legacy serial port %d for %pOF\n", index, np);
153
+
printk(KERN_DEBUG " %s=%pa, taddr=%pa, irq=%lx, clk=%d, speed=%d\n",
160
154
(iotype == UPIO_PORT) ? "port" : "mem",
161
-
(unsigned long long)base, (unsigned long long)taddr, irq,
162
-
legacy_serial_ports[index].uartclk,
163
-
legacy_serial_infos[index].speed);
155
+
&base, &taddr, irq, legacy_port->uartclk, legacy_info->speed);
164
156
165
157
return index;
166
158
}
-2
arch/powerpc/platforms/powermac/setup.c
-2
arch/powerpc/platforms/powermac/setup.c
···
28
28
#include <linux/ptrace.h>
29
29
#include <linux/export.h>
30
30
#include <linux/user.h>
31
-
#include <linux/tty.h>
32
31
#include <linux/string.h>
33
32
#include <linux/delay.h>
34
33
#include <linux/ioport.h>
35
34
#include <linux/major.h>
36
35
#include <linux/initrd.h>
37
-
#include <linux/vt_kern.h>
38
36
#include <linux/console.h>
39
37
#include <linux/pci.h>
40
38
#include <linux/adb.h>
+6
arch/x86/include/asm/ce4100.h
+6
arch/x86/include/asm/ce4100.h
-95
arch/x86/platform/ce4100/ce4100.c
-95
arch/x86/platform/ce4100/ce4100.c
···
5
5
* (C) Copyright 2010 Intel Corporation
6
6
*/
7
7
#include <linux/init.h>
8
-
#include <linux/kernel.h>
9
-
#include <linux/irq.h>
10
8
#include <linux/reboot.h>
11
-
#include <linux/serial_reg.h>
12
-
#include <linux/serial_8250.h>
13
9
14
10
#include <asm/ce4100.h>
15
11
#include <asm/prom.h>
16
12
#include <asm/setup.h>
17
-
#include <asm/i8259.h>
18
13
#include <asm/io.h>
19
-
#include <asm/io_apic.h>
20
-
#include <asm/emergency-restart.h>
21
14
22
15
/*
23
16
* The CE4100 platform has an internal 8051 Microcontroller which is
···
23
30
{
24
31
outb(0x4, 0xcf9);
25
32
}
26
-
27
-
#ifdef CONFIG_SERIAL_8250
28
-
29
-
static unsigned int mem_serial_in(struct uart_port *p, int offset)
30
-
{
31
-
offset = offset << p->regshift;
32
-
return readl(p->membase + offset);
33
-
}
34
-
35
-
/*
36
-
* The UART Tx interrupts are not set under some conditions and therefore serial
37
-
* transmission hangs. This is a silicon issue and has not been root caused. The
38
-
* workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
39
-
* bit of LSR register in interrupt handler to see whether at least one of these
40
-
* two bits is set, if so then process the transmit request. If this workaround
41
-
* is not applied, then the serial transmission may hang. This workaround is for
42
-
* errata number 9 in Errata - B step.
43
-
*/
44
-
45
-
static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
46
-
{
47
-
unsigned int ret, ier, lsr;
48
-
49
-
if (offset == UART_IIR) {
50
-
offset = offset << p->regshift;
51
-
ret = readl(p->membase + offset);
52
-
if (ret & UART_IIR_NO_INT) {
53
-
/* see if the TX interrupt should have really set */
54
-
ier = mem_serial_in(p, UART_IER);
55
-
/* see if the UART's XMIT interrupt is enabled */
56
-
if (ier & UART_IER_THRI) {
57
-
lsr = mem_serial_in(p, UART_LSR);
58
-
/* now check to see if the UART should be
59
-
generating an interrupt (but isn't) */
60
-
if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
61
-
ret &= ~UART_IIR_NO_INT;
62
-
}
63
-
}
64
-
} else
65
-
ret = mem_serial_in(p, offset);
66
-
return ret;
67
-
}
68
-
69
-
static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
70
-
{
71
-
offset = offset << p->regshift;
72
-
writel(value, p->membase + offset);
73
-
}
74
-
75
-
static void ce4100_serial_fixup(int port, struct uart_port *up,
76
-
u32 *capabilities)
77
-
{
78
-
#ifdef CONFIG_EARLY_PRINTK
79
-
/*
80
-
* Over ride the legacy port configuration that comes from
81
-
* asm/serial.h. Using the ioport driver then switching to the
82
-
* PCI memmaped driver hangs the IOAPIC
83
-
*/
84
-
if (up->iotype != UPIO_MEM32) {
85
-
up->uartclk = 14745600;
86
-
up->mapbase = 0xdffe0200;
87
-
set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
88
-
up->mapbase & PAGE_MASK);
89
-
up->membase =
90
-
(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
91
-
up->membase += up->mapbase & ~PAGE_MASK;
92
-
up->mapbase += port * 0x100;
93
-
up->membase += port * 0x100;
94
-
up->iotype = UPIO_MEM32;
95
-
up->regshift = 2;
96
-
up->irq = 4;
97
-
}
98
-
#endif
99
-
up->iobase = 0;
100
-
up->serial_in = ce4100_mem_serial_in;
101
-
up->serial_out = ce4100_mem_serial_out;
102
-
103
-
*capabilities |= (1 << 12);
104
-
}
105
-
106
-
static __init void sdv_serial_fixup(void)
107
-
{
108
-
serial8250_set_isa_configurator(ce4100_serial_fixup);
109
-
}
110
-
111
-
#else
112
-
static inline void sdv_serial_fixup(void) {};
113
-
#endif
114
33
115
34
static void __init sdv_arch_setup(void)
116
35
{
+1
-7
drivers/isdn/capi/capi.c
+1
-7
drivers/isdn/capi/capi.c
···
306
306
static void capincci_free_minor(struct capincci *np)
307
307
{
308
308
struct capiminor *mp = np->minorp;
309
-
struct tty_struct *tty;
310
309
311
310
if (mp) {
312
-
tty = tty_port_tty_get(&mp->port);
313
-
if (tty) {
314
-
tty_vhangup(tty);
315
-
tty_kref_put(tty);
316
-
}
317
-
311
+
tty_port_tty_vhangup(&mp->port);
318
312
capiminor_free(mp);
319
313
}
320
314
}
+7
-6
drivers/soc/qcom/qcom-geni-se.c
+7
-6
drivers/soc/qcom/qcom-geni-se.c
···
895
895
{
896
896
struct device *dev = &pdev->dev;
897
897
struct geni_wrapper *wrapper;
898
+
const struct geni_se_desc *desc;
898
899
int ret;
899
900
900
901
wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
···
907
906
if (IS_ERR(wrapper->base))
908
907
return PTR_ERR(wrapper->base);
909
908
910
-
if (!has_acpi_companion(&pdev->dev)) {
911
-
const struct geni_se_desc *desc;
912
-
int i;
909
+
desc = device_get_match_data(&pdev->dev);
913
910
914
-
desc = device_get_match_data(&pdev->dev);
915
-
if (!desc)
916
-
return -EINVAL;
911
+
if (!has_acpi_companion(&pdev->dev) && desc->num_clks) {
912
+
int i;
917
913
918
914
wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS);
919
915
···
951
953
.num_clks = ARRAY_SIZE(qup_clks),
952
954
};
953
955
956
+
static const struct geni_se_desc sa8255p_qup_desc = {};
957
+
954
958
static const char * const i2c_master_hub_clks[] = {
955
959
"s-ahb",
956
960
};
···
965
965
static const struct of_device_id geni_se_dt_match[] = {
966
966
{ .compatible = "qcom,geni-se-qup", .data = &qup_desc },
967
967
{ .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc },
968
+
{ .compatible = "qcom,sa8255p-geni-se-qup", .data = &sa8255p_qup_desc },
968
969
{}
969
970
};
970
971
MODULE_DEVICE_TABLE(of, geni_se_dt_match);
+1
-6
drivers/staging/greybus/uart.c
+1
-6
drivers/staging/greybus/uart.c
···
916
916
{
917
917
struct gb_tty *gb_tty = gb_gbphy_get_data(gbphy_dev);
918
918
struct gb_connection *connection = gb_tty->connection;
919
-
struct tty_struct *tty;
920
919
int ret;
921
920
922
921
ret = gbphy_runtime_get_sync(gbphy_dev);
···
928
929
wake_up_all(&gb_tty->wioctl);
929
930
mutex_unlock(&gb_tty->mutex);
930
931
931
-
tty = tty_port_tty_get(&gb_tty->port);
932
-
if (tty) {
933
-
tty_vhangup(tty);
934
-
tty_kref_put(tty);
935
-
}
932
+
tty_port_tty_vhangup(&gb_tty->port);
936
933
937
934
gb_connection_disable_rx(connection);
938
935
tty_unregister_device(gb_tty_driver, gb_tty->minor);
+8
drivers/tty/serial/8250/8250.h
+8
drivers/tty/serial/8250/8250.h
···
318
318
319
319
#ifdef CONFIG_SERIAL_8250_RSA
320
320
void univ8250_rsa_support(struct uart_ops *ops);
321
+
void rsa_enable(struct uart_8250_port *up);
322
+
void rsa_disable(struct uart_8250_port *up);
323
+
void rsa_autoconfig(struct uart_8250_port *up);
324
+
void rsa_reset(struct uart_8250_port *up);
321
325
#else
322
326
static inline void univ8250_rsa_support(struct uart_ops *ops) { }
327
+
static inline void rsa_enable(struct uart_8250_port *up) {}
328
+
static inline void rsa_disable(struct uart_8250_port *up) {}
329
+
static inline void rsa_autoconfig(struct uart_8250_port *up) {}
330
+
static inline void rsa_reset(struct uart_8250_port *up) {}
323
331
#endif
324
332
325
333
#ifdef CONFIG_SERIAL_8250_FINTEK
+93
drivers/tty/serial/8250/8250_ce4100.c
+93
drivers/tty/serial/8250/8250_ce4100.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Intel CE4100 platform specific setup code
4
+
*
5
+
* (C) Copyright 2010 Intel Corporation
6
+
*/
7
+
8
+
#include <linux/init.h>
9
+
#include <linux/io.h>
10
+
#include <linux/types.h>
11
+
12
+
#include <asm/ce4100.h>
13
+
#include <asm/fixmap.h>
14
+
#include <asm/page.h>
15
+
16
+
#include <linux/serial_reg.h>
17
+
#include <linux/serial_8250.h>
18
+
19
+
static unsigned int mem_serial_in(struct uart_port *p, int offset)
20
+
{
21
+
offset = offset << p->regshift;
22
+
return readl(p->membase + offset);
23
+
}
24
+
25
+
/*
26
+
* The UART Tx interrupts are not set under some conditions and therefore serial
27
+
* transmission hangs. This is a silicon issue and has not been root caused. The
28
+
* workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
29
+
* bit of LSR register in interrupt handler to see whether at least one of these
30
+
* two bits is set, if so then process the transmit request. If this workaround
31
+
* is not applied, then the serial transmission may hang. This workaround is for
32
+
* errata number 9 in Errata - B step.
33
+
*/
34
+
static u32 ce4100_mem_serial_in(struct uart_port *p, unsigned int offset)
35
+
{
36
+
u32 ret, ier, lsr;
37
+
38
+
ret = mem_serial_in(p, offset);
39
+
if (offset != UART_IIR || !(ret & UART_IIR_NO_INT))
40
+
return ret;
41
+
42
+
/* see if the TX interrupt should have really set */
43
+
ier = mem_serial_in(p, UART_IER);
44
+
/* see if the UART's XMIT interrupt is enabled */
45
+
if (!(ier & UART_IER_THRI))
46
+
return ret;
47
+
48
+
lsr = mem_serial_in(p, UART_LSR);
49
+
/* now check to see if the UART should be generating an interrupt (but isn't) */
50
+
if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
51
+
ret &= ~UART_IIR_NO_INT;
52
+
53
+
return ret;
54
+
}
55
+
56
+
static void ce4100_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
57
+
{
58
+
offset <<= p->regshift;
59
+
writel(value, p->membase + offset);
60
+
}
61
+
62
+
static void ce4100_serial_fixup(int port, struct uart_port *up, u32 *capabilities)
63
+
{
64
+
#ifdef CONFIG_EARLY_PRINTK
65
+
/*
66
+
* Override the legacy port configuration that comes from
67
+
* asm/serial.h. Using the ioport driver then switching to the
68
+
* PCI memmaped driver hangs the IOAPIC.
69
+
*/
70
+
if (up->iotype != UPIO_MEM32) {
71
+
up->uartclk = 14745600;
72
+
up->mapbase = 0xdffe0200;
73
+
set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, up->mapbase & PAGE_MASK);
74
+
up->membase = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
75
+
up->membase += up->mapbase & ~PAGE_MASK;
76
+
up->mapbase += port * 0x100;
77
+
up->membase += port * 0x100;
78
+
up->iotype = UPIO_MEM32;
79
+
up->regshift = 2;
80
+
up->irq = 4;
81
+
}
82
+
#endif
83
+
up->iobase = 0;
84
+
up->serial_in = ce4100_mem_serial_in;
85
+
up->serial_out = ce4100_mem_serial_out;
86
+
87
+
*capabilities |= (1 << 12);
88
+
}
89
+
90
+
void __init sdv_serial_fixup(void)
91
+
{
92
+
serial8250_set_isa_configurator(ce4100_serial_fixup);
93
+
}
+162
-156
drivers/tty/serial/8250/8250_core.c
+162
-156
drivers/tty/serial/8250/8250_core.c
···
13
13
*/
14
14
15
15
#include <linux/acpi.h>
16
+
#include <linux/hashtable.h>
16
17
#include <linux/module.h>
17
18
#include <linux/moduleparam.h>
18
19
#include <linux/ioport.h>
···
48
47
struct list_head *head;
49
48
};
50
49
51
-
#define NR_IRQ_HASH 32 /* Can be adjusted later */
52
-
static struct hlist_head irq_lists[NR_IRQ_HASH];
50
+
#define IRQ_HASH_BITS 5 /* Can be adjusted later */
51
+
static DEFINE_HASHTABLE(irq_lists, IRQ_HASH_BITS);
53
52
static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
54
53
55
54
/*
···
72
71
struct list_head *l, *end = NULL;
73
72
int pass_counter = 0, handled = 0;
74
73
75
-
pr_debug("%s(%d): start\n", __func__, irq);
76
-
77
74
spin_lock(&i->lock);
78
75
79
76
l = i->head;
80
77
do {
81
-
struct uart_8250_port *up;
82
-
struct uart_port *port;
83
-
84
-
up = list_entry(l, struct uart_8250_port, list);
85
-
port = &up->port;
78
+
struct uart_8250_port *up = list_entry(l, struct uart_8250_port, list);
79
+
struct uart_port *port = &up->port;
86
80
87
81
if (port->handle_irq(port)) {
88
82
handled = 1;
···
92
96
} while (l != end);
93
97
94
98
spin_unlock(&i->lock);
95
-
96
-
pr_debug("%s(%d): end\n", __func__, irq);
97
99
98
100
return IRQ_RETVAL(handled);
99
101
}
···
123
129
}
124
130
}
125
131
126
-
static int serial_link_irq_chain(struct uart_8250_port *up)
132
+
/*
133
+
* Either:
134
+
* - find the corresponding info in the hashtable and return it, or
135
+
* - allocate a new one, add it to the hashtable and return it.
136
+
*/
137
+
static struct irq_info *serial_get_or_create_irq_info(const struct uart_8250_port *up)
127
138
{
128
-
struct hlist_head *h;
129
139
struct irq_info *i;
130
-
int ret;
131
140
132
141
mutex_lock(&hash_mutex);
133
142
134
-
h = &irq_lists[up->port.irq % NR_IRQ_HASH];
135
-
136
-
hlist_for_each_entry(i, h, node)
143
+
hash_for_each_possible(irq_lists, i, node, up->port.irq)
137
144
if (i->irq == up->port.irq)
138
-
break;
145
+
goto unlock;
139
146
147
+
i = kzalloc(sizeof(*i), GFP_KERNEL);
140
148
if (i == NULL) {
141
-
i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
142
-
if (i == NULL) {
143
-
mutex_unlock(&hash_mutex);
144
-
return -ENOMEM;
145
-
}
146
-
spin_lock_init(&i->lock);
147
-
i->irq = up->port.irq;
148
-
hlist_add_head(&i->node, h);
149
+
i = ERR_PTR(-ENOMEM);
150
+
goto unlock;
149
151
}
152
+
spin_lock_init(&i->lock);
153
+
i->irq = up->port.irq;
154
+
hash_add(irq_lists, &i->node, i->irq);
155
+
unlock:
150
156
mutex_unlock(&hash_mutex);
157
+
158
+
return i;
159
+
}
160
+
161
+
static int serial_link_irq_chain(struct uart_8250_port *up)
162
+
{
163
+
struct irq_info *i;
164
+
int ret;
165
+
166
+
i = serial_get_or_create_irq_info(up);
167
+
if (IS_ERR(i))
168
+
return PTR_ERR(i);
151
169
152
170
spin_lock_irq(&i->lock);
153
171
···
184
178
static void serial_unlink_irq_chain(struct uart_8250_port *up)
185
179
{
186
180
struct irq_info *i;
187
-
struct hlist_head *h;
188
181
189
182
mutex_lock(&hash_mutex);
190
183
191
-
h = &irq_lists[up->port.irq % NR_IRQ_HASH];
192
-
193
-
hlist_for_each_entry(i, h, node)
184
+
hash_for_each_possible(irq_lists, i, node, up->port.irq)
194
185
if (i->irq == up->port.irq)
195
186
break;
196
187
···
717
714
nr_uarts++;
718
715
}
719
716
717
+
/* Check if it is CIR already. We check this below again, see there why. */
718
+
if (uart->port.type == PORT_8250_CIR) {
719
+
ret = -ENODEV;
720
+
goto unlock;
721
+
}
722
+
723
+
if (uart->port.dev)
724
+
uart_remove_one_port(&serial8250_reg, &uart->port);
725
+
726
+
uart->port.ctrl_id = up->port.ctrl_id;
727
+
uart->port.port_id = up->port.port_id;
728
+
uart->port.iobase = up->port.iobase;
729
+
uart->port.membase = up->port.membase;
730
+
uart->port.irq = up->port.irq;
731
+
uart->port.irqflags = up->port.irqflags;
732
+
uart->port.uartclk = up->port.uartclk;
733
+
uart->port.fifosize = up->port.fifosize;
734
+
uart->port.regshift = up->port.regshift;
735
+
uart->port.iotype = up->port.iotype;
736
+
uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
737
+
uart->bugs = up->bugs;
738
+
uart->port.mapbase = up->port.mapbase;
739
+
uart->port.mapsize = up->port.mapsize;
740
+
uart->port.private_data = up->port.private_data;
741
+
uart->tx_loadsz = up->tx_loadsz;
742
+
uart->capabilities = up->capabilities;
743
+
uart->port.throttle = up->port.throttle;
744
+
uart->port.unthrottle = up->port.unthrottle;
745
+
uart->port.rs485_config = up->port.rs485_config;
746
+
uart->port.rs485_supported = up->port.rs485_supported;
747
+
uart->port.rs485 = up->port.rs485;
748
+
uart->rs485_start_tx = up->rs485_start_tx;
749
+
uart->rs485_stop_tx = up->rs485_stop_tx;
750
+
uart->lsr_save_mask = up->lsr_save_mask;
751
+
uart->dma = up->dma;
752
+
753
+
/* Take tx_loadsz from fifosize if it wasn't set separately */
754
+
if (uart->port.fifosize && !uart->tx_loadsz)
755
+
uart->tx_loadsz = uart->port.fifosize;
756
+
757
+
if (up->port.dev) {
758
+
uart->port.dev = up->port.dev;
759
+
ret = uart_get_rs485_mode(&uart->port);
760
+
if (ret)
761
+
goto err;
762
+
}
763
+
764
+
if (up->port.flags & UPF_FIXED_TYPE)
765
+
uart->port.type = up->port.type;
766
+
767
+
/*
768
+
* Only call mctrl_gpio_init(), if the device has no ACPI
769
+
* companion device
770
+
*/
771
+
if (!has_acpi_companion(uart->port.dev)) {
772
+
struct mctrl_gpios *gpios = mctrl_gpio_init(&uart->port, 0);
773
+
if (IS_ERR(gpios)) {
774
+
ret = PTR_ERR(gpios);
775
+
goto err;
776
+
} else {
777
+
uart->gpios = gpios;
778
+
}
779
+
}
780
+
781
+
serial8250_set_defaults(uart);
782
+
783
+
/* Possibly override default I/O functions. */
784
+
if (up->port.serial_in)
785
+
uart->port.serial_in = up->port.serial_in;
786
+
if (up->port.serial_out)
787
+
uart->port.serial_out = up->port.serial_out;
788
+
if (up->port.handle_irq)
789
+
uart->port.handle_irq = up->port.handle_irq;
790
+
/* Possibly override set_termios call */
791
+
if (up->port.set_termios)
792
+
uart->port.set_termios = up->port.set_termios;
793
+
if (up->port.set_ldisc)
794
+
uart->port.set_ldisc = up->port.set_ldisc;
795
+
if (up->port.get_mctrl)
796
+
uart->port.get_mctrl = up->port.get_mctrl;
797
+
if (up->port.set_mctrl)
798
+
uart->port.set_mctrl = up->port.set_mctrl;
799
+
if (up->port.get_divisor)
800
+
uart->port.get_divisor = up->port.get_divisor;
801
+
if (up->port.set_divisor)
802
+
uart->port.set_divisor = up->port.set_divisor;
803
+
if (up->port.startup)
804
+
uart->port.startup = up->port.startup;
805
+
if (up->port.shutdown)
806
+
uart->port.shutdown = up->port.shutdown;
807
+
if (up->port.pm)
808
+
uart->port.pm = up->port.pm;
809
+
if (up->port.handle_break)
810
+
uart->port.handle_break = up->port.handle_break;
811
+
if (up->dl_read)
812
+
uart->dl_read = up->dl_read;
813
+
if (up->dl_write)
814
+
uart->dl_write = up->dl_write;
815
+
816
+
/* Check the type (again)! It might have changed by the port.type assignment above. */
720
817
if (uart->port.type != PORT_8250_CIR) {
721
-
struct mctrl_gpios *gpios;
818
+
if (uart_console_registered(&uart->port))
819
+
pm_runtime_get_sync(uart->port.dev);
722
820
723
-
if (uart->port.dev)
724
-
uart_remove_one_port(&serial8250_reg, &uart->port);
821
+
if (serial8250_isa_config != NULL)
822
+
serial8250_isa_config(0, &uart->port,
823
+
&uart->capabilities);
725
824
726
-
uart->port.ctrl_id = up->port.ctrl_id;
727
-
uart->port.port_id = up->port.port_id;
728
-
uart->port.iobase = up->port.iobase;
729
-
uart->port.membase = up->port.membase;
730
-
uart->port.irq = up->port.irq;
731
-
uart->port.irqflags = up->port.irqflags;
732
-
uart->port.uartclk = up->port.uartclk;
733
-
uart->port.fifosize = up->port.fifosize;
734
-
uart->port.regshift = up->port.regshift;
735
-
uart->port.iotype = up->port.iotype;
736
-
uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
737
-
uart->bugs = up->bugs;
738
-
uart->port.mapbase = up->port.mapbase;
739
-
uart->port.mapsize = up->port.mapsize;
740
-
uart->port.private_data = up->port.private_data;
741
-
uart->tx_loadsz = up->tx_loadsz;
742
-
uart->capabilities = up->capabilities;
743
-
uart->port.throttle = up->port.throttle;
744
-
uart->port.unthrottle = up->port.unthrottle;
745
-
uart->port.rs485_config = up->port.rs485_config;
746
-
uart->port.rs485_supported = up->port.rs485_supported;
747
-
uart->port.rs485 = up->port.rs485;
748
-
uart->rs485_start_tx = up->rs485_start_tx;
749
-
uart->rs485_stop_tx = up->rs485_stop_tx;
750
-
uart->lsr_save_mask = up->lsr_save_mask;
751
-
uart->dma = up->dma;
825
+
serial8250_apply_quirks(uart);
826
+
ret = uart_add_one_port(&serial8250_reg,
827
+
&uart->port);
828
+
if (ret)
829
+
goto err;
752
830
753
-
/* Take tx_loadsz from fifosize if it wasn't set separately */
754
-
if (uart->port.fifosize && !uart->tx_loadsz)
755
-
uart->tx_loadsz = uart->port.fifosize;
831
+
ret = uart->port.line;
832
+
} else {
833
+
dev_info(uart->port.dev,
834
+
"skipping CIR port at 0x%lx / 0x%llx, IRQ %d\n",
835
+
uart->port.iobase,
836
+
(unsigned long long)uart->port.mapbase,
837
+
uart->port.irq);
756
838
757
-
if (up->port.dev) {
758
-
uart->port.dev = up->port.dev;
759
-
ret = uart_get_rs485_mode(&uart->port);
760
-
if (ret)
761
-
goto err;
762
-
}
839
+
ret = 0;
840
+
}
763
841
764
-
if (up->port.flags & UPF_FIXED_TYPE)
765
-
uart->port.type = up->port.type;
842
+
if (!uart->lsr_save_mask)
843
+
uart->lsr_save_mask = LSR_SAVE_FLAGS; /* Use default LSR mask */
766
844
767
-
/*
768
-
* Only call mctrl_gpio_init(), if the device has no ACPI
769
-
* companion device
770
-
*/
771
-
if (!has_acpi_companion(uart->port.dev)) {
772
-
gpios = mctrl_gpio_init(&uart->port, 0);
773
-
if (IS_ERR(gpios)) {
774
-
ret = PTR_ERR(gpios);
775
-
goto err;
776
-
} else {
777
-
uart->gpios = gpios;
778
-
}
779
-
}
780
-
781
-
serial8250_set_defaults(uart);
782
-
783
-
/* Possibly override default I/O functions. */
784
-
if (up->port.serial_in)
785
-
uart->port.serial_in = up->port.serial_in;
786
-
if (up->port.serial_out)
787
-
uart->port.serial_out = up->port.serial_out;
788
-
if (up->port.handle_irq)
789
-
uart->port.handle_irq = up->port.handle_irq;
790
-
/* Possibly override set_termios call */
791
-
if (up->port.set_termios)
792
-
uart->port.set_termios = up->port.set_termios;
793
-
if (up->port.set_ldisc)
794
-
uart->port.set_ldisc = up->port.set_ldisc;
795
-
if (up->port.get_mctrl)
796
-
uart->port.get_mctrl = up->port.get_mctrl;
797
-
if (up->port.set_mctrl)
798
-
uart->port.set_mctrl = up->port.set_mctrl;
799
-
if (up->port.get_divisor)
800
-
uart->port.get_divisor = up->port.get_divisor;
801
-
if (up->port.set_divisor)
802
-
uart->port.set_divisor = up->port.set_divisor;
803
-
if (up->port.startup)
804
-
uart->port.startup = up->port.startup;
805
-
if (up->port.shutdown)
806
-
uart->port.shutdown = up->port.shutdown;
807
-
if (up->port.pm)
808
-
uart->port.pm = up->port.pm;
809
-
if (up->port.handle_break)
810
-
uart->port.handle_break = up->port.handle_break;
811
-
if (up->dl_read)
812
-
uart->dl_read = up->dl_read;
813
-
if (up->dl_write)
814
-
uart->dl_write = up->dl_write;
815
-
816
-
if (uart->port.type != PORT_8250_CIR) {
817
-
if (uart_console_registered(&uart->port))
818
-
pm_runtime_get_sync(uart->port.dev);
819
-
820
-
if (serial8250_isa_config != NULL)
821
-
serial8250_isa_config(0, &uart->port,
822
-
&uart->capabilities);
823
-
824
-
serial8250_apply_quirks(uart);
825
-
ret = uart_add_one_port(&serial8250_reg,
826
-
&uart->port);
827
-
if (ret)
828
-
goto err;
829
-
830
-
ret = uart->port.line;
831
-
} else {
832
-
dev_info(uart->port.dev,
833
-
"skipping CIR port at 0x%lx / 0x%llx, IRQ %d\n",
834
-
uart->port.iobase,
835
-
(unsigned long long)uart->port.mapbase,
836
-
uart->port.irq);
837
-
838
-
ret = 0;
839
-
}
840
-
841
-
if (!uart->lsr_save_mask)
842
-
uart->lsr_save_mask = LSR_SAVE_FLAGS; /* Use default LSR mask */
843
-
844
-
/* Initialise interrupt backoff work if required */
845
-
if (up->overrun_backoff_time_ms > 0) {
846
-
uart->overrun_backoff_time_ms =
847
-
up->overrun_backoff_time_ms;
848
-
INIT_DELAYED_WORK(&uart->overrun_backoff,
849
-
serial_8250_overrun_backoff_work);
850
-
} else {
851
-
uart->overrun_backoff_time_ms = 0;
852
-
}
845
+
/* Initialise interrupt backoff work if required */
846
+
if (up->overrun_backoff_time_ms > 0) {
847
+
uart->overrun_backoff_time_ms =
848
+
up->overrun_backoff_time_ms;
849
+
INIT_DELAYED_WORK(&uart->overrun_backoff,
850
+
serial_8250_overrun_backoff_work);
851
+
} else {
852
+
uart->overrun_backoff_time_ms = 0;
853
853
}
854
854
855
855
unlock:
+18
-18
drivers/tty/serial/8250/8250_dw.c
+18
-18
drivers/tty/serial/8250/8250_dw.c
···
67
67
struct dw8250_port_data data;
68
68
const struct dw8250_platform_data *pdata;
69
69
70
-
int msr_mask_on;
71
-
int msr_mask_off;
70
+
u32 msr_mask_on;
71
+
u32 msr_mask_off;
72
72
struct clk *clk;
73
73
struct clk *pclk;
74
74
struct notifier_block clk_notifier;
···
94
94
return container_of(work, struct dw8250_data, clk_work);
95
95
}
96
96
97
-
static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
97
+
static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value)
98
98
{
99
99
struct dw8250_data *d = to_dw8250_data(p->private_data);
100
100
···
145
145
* routine. Hence, it must not call serial_port_out() or serial_out()
146
146
* against the modified registers here, i.e. LCR.
147
147
*/
148
-
static void dw8250_check_lcr(struct uart_port *p, int offset, int value)
148
+
static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value)
149
149
{
150
150
struct dw8250_data *d = to_dw8250_data(p->private_data);
151
151
void __iomem *addr = p->membase + (offset << p->regshift);
···
156
156
157
157
/* Make sure LCR write wasn't ignored */
158
158
while (tries--) {
159
-
unsigned int lcr = serial_port_in(p, offset);
159
+
u32 lcr = serial_port_in(p, offset);
160
160
161
161
if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
162
162
return;
···
205
205
}
206
206
}
207
207
208
-
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
208
+
static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value)
209
209
{
210
210
writeb(value, p->membase + (offset << p->regshift));
211
211
dw8250_check_lcr(p, offset, value);
212
212
}
213
213
214
-
static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
214
+
static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value)
215
215
{
216
216
/* Allow the TX to drain before we reconfigure */
217
217
if (offset == UART_LCR)
···
220
220
dw8250_serial_out(p, offset, value);
221
221
}
222
222
223
-
static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
223
+
static u32 dw8250_serial_in(struct uart_port *p, unsigned int offset)
224
224
{
225
-
unsigned int value = readb(p->membase + (offset << p->regshift));
225
+
u32 value = readb(p->membase + (offset << p->regshift));
226
226
227
227
return dw8250_modify_msr(p, offset, value);
228
228
}
229
229
230
230
#ifdef CONFIG_64BIT
231
-
static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
231
+
static u32 dw8250_serial_inq(struct uart_port *p, unsigned int offset)
232
232
{
233
233
u8 value = __raw_readq(p->membase + (offset << p->regshift));
234
234
235
235
return dw8250_modify_msr(p, offset, value);
236
236
}
237
237
238
-
static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
238
+
static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value)
239
239
{
240
240
value &= 0xff;
241
241
__raw_writeq(value, p->membase + (offset << p->regshift));
···
246
246
}
247
247
#endif /* CONFIG_64BIT */
248
248
249
-
static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
249
+
static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value)
250
250
{
251
251
writel(value, p->membase + (offset << p->regshift));
252
252
dw8250_check_lcr(p, offset, value);
253
253
}
254
254
255
-
static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
255
+
static u32 dw8250_serial_in32(struct uart_port *p, unsigned int offset)
256
256
{
257
-
unsigned int value = readl(p->membase + (offset << p->regshift));
257
+
u32 value = readl(p->membase + (offset << p->regshift));
258
258
259
259
return dw8250_modify_msr(p, offset, value);
260
260
}
261
261
262
-
static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
262
+
static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value)
263
263
{
264
264
iowrite32be(value, p->membase + (offset << p->regshift));
265
265
dw8250_check_lcr(p, offset, value);
266
266
}
267
267
268
-
static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
268
+
static u32 dw8250_serial_in32be(struct uart_port *p, unsigned int offset)
269
269
{
270
-
unsigned int value = ioread32be(p->membase + (offset << p->regshift));
270
+
u32 value = ioread32be(p->membase + (offset << p->regshift));
271
271
272
272
return dw8250_modify_msr(p, offset, value);
273
273
}
···
392
392
rate = clk_round_rate(d->clk, newrate);
393
393
if (rate > 0) {
394
394
/*
395
-
* Note that any clock-notifer worker will block in
395
+
* Note that any clock-notifier worker will block in
396
396
* serial8250_update_uartclk() until we are done.
397
397
*/
398
398
ret = clk_set_rate(d->clk, newrate);
+2
-2
drivers/tty/serial/8250/8250_em.c
+2
-2
drivers/tty/serial/8250/8250_em.c
···
59
59
}
60
60
}
61
61
62
-
static unsigned int serial8250_em_serial_in(struct uart_port *p, int offset)
62
+
static u32 serial8250_em_serial_in(struct uart_port *p, unsigned int offset)
63
63
{
64
64
switch (offset) {
65
65
case UART_RX: /* RX @ 0x00 */
···
119
119
serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0);
120
120
}
121
121
122
-
static void serial8250_em_serial_out(struct uart_port *p, int offset, int value)
122
+
static void serial8250_em_serial_out(struct uart_port *p, unsigned int offset, u32 value)
123
123
{
124
124
switch (offset) {
125
125
case UART_TX:
+4
-4
drivers/tty/serial/8250/8250_ingenic.c
+4
-4
drivers/tty/serial/8250/8250_ingenic.c
···
168
168
OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
169
169
ingenic_early_console_setup);
170
170
171
-
static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
171
+
static void ingenic_uart_serial_out(struct uart_port *p, unsigned int offset, u32 value)
172
172
{
173
-
int ier;
173
+
u32 ier;
174
174
175
175
switch (offset) {
176
176
case UART_FCR:
···
206
206
writeb(value, p->membase + (offset << p->regshift));
207
207
}
208
208
209
-
static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
209
+
static u32 ingenic_uart_serial_in(struct uart_port *p, unsigned int offset)
210
210
{
211
-
unsigned int value;
211
+
u8 value;
212
212
213
213
value = readb(p->membase + (offset << p->regshift));
214
214
+2
-2
drivers/tty/serial/8250/8250_ioc3.c
+2
-2
drivers/tty/serial/8250/8250_ioc3.c
···
21
21
int line;
22
22
};
23
23
24
-
static unsigned int ioc3_serial_in(struct uart_port *p, int offset)
24
+
static u32 ioc3_serial_in(struct uart_port *p, unsigned int offset)
25
25
{
26
26
return readb(p->membase + (offset ^ 3));
27
27
}
28
28
29
-
static void ioc3_serial_out(struct uart_port *p, int offset, int value)
29
+
static void ioc3_serial_out(struct uart_port *p, unsigned int offset, u32 value)
30
30
{
31
31
writeb(value, p->membase + (offset ^ 3));
32
32
}
+1
-1
drivers/tty/serial/8250/8250_lpc18xx.c
+1
-1
drivers/tty/serial/8250/8250_lpc18xx.c
+30
-26
drivers/tty/serial/8250/8250_ni.c
+30
-26
drivers/tty/serial/8250/8250_ni.c
···
275
275
276
276
static int ni16550_probe(struct platform_device *pdev)
277
277
{
278
+
struct uart_8250_port *uart __free(kfree) = NULL;
278
279
const struct ni16550_device_info *info;
279
280
struct device *dev = &pdev->dev;
280
-
struct uart_8250_port uart = {};
281
281
unsigned int txfifosz, rxfifosz;
282
-
unsigned int prescaler;
283
282
struct ni16550_data *data;
283
+
unsigned int prescaler;
284
284
const char *portmode;
285
285
bool rs232_property;
286
286
int ret;
287
+
288
+
uart = kzalloc(sizeof(*uart), GFP_KERNEL);
289
+
if (!uart)
290
+
return -ENOMEM;
287
291
288
292
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
289
293
if (!data)
290
294
return -ENOMEM;
291
295
292
-
spin_lock_init(&uart.port.lock);
296
+
spin_lock_init(&uart->port.lock);
293
297
294
-
ret = ni16550_get_regs(pdev, &uart.port);
298
+
ret = ni16550_get_regs(pdev, &uart->port);
295
299
if (ret < 0)
296
300
return ret;
297
301
298
302
/* early setup so that serial_in()/serial_out() work */
299
-
serial8250_set_defaults(&uart);
303
+
serial8250_set_defaults(uart);
300
304
301
305
info = device_get_match_data(dev);
302
306
303
-
uart.port.dev = dev;
304
-
uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE;
305
-
uart.port.startup = ni16550_port_startup;
306
-
uart.port.shutdown = ni16550_port_shutdown;
307
+
uart->port.dev = dev;
308
+
uart->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE;
309
+
uart->port.startup = ni16550_port_startup;
310
+
uart->port.shutdown = ni16550_port_shutdown;
307
311
308
312
/*
309
313
* Hardware instantiation of FIFO sizes are held in registers.
310
314
*/
311
-
txfifosz = ni16550_read_fifo_size(&uart, NI16550_TFS_OFFSET);
312
-
rxfifosz = ni16550_read_fifo_size(&uart, NI16550_RFS_OFFSET);
315
+
txfifosz = ni16550_read_fifo_size(uart, NI16550_TFS_OFFSET);
316
+
rxfifosz = ni16550_read_fifo_size(uart, NI16550_RFS_OFFSET);
313
317
314
318
dev_dbg(dev, "NI 16550 has TX FIFO size %u, RX FIFO size %u\n",
315
319
txfifosz, rxfifosz);
316
320
317
-
uart.port.type = PORT_16550A;
318
-
uart.port.fifosize = txfifosz;
319
-
uart.tx_loadsz = txfifosz;
320
-
uart.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
321
-
uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR;
321
+
uart->port.type = PORT_16550A;
322
+
uart->port.fifosize = txfifosz;
323
+
uart->tx_loadsz = txfifosz;
324
+
uart->fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
325
+
uart->capabilities = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR;
322
326
323
327
/*
324
328
* Declaration of the base clock frequency can come from one of:
325
329
* - static declaration in this driver (for older ACPI IDs)
326
330
* - a "clock-frequency" ACPI
327
331
*/
328
-
uart.port.uartclk = info->uartclk;
332
+
uart->port.uartclk = info->uartclk;
329
333
330
-
ret = uart_read_port_properties(&uart.port);
334
+
ret = uart_read_port_properties(&uart->port);
331
335
if (ret)
332
336
return ret;
333
337
334
-
if (!uart.port.uartclk) {
338
+
if (!uart->port.uartclk) {
335
339
data->clk = devm_clk_get_enabled(dev, NULL);
336
340
if (!IS_ERR(data->clk))
337
-
uart.port.uartclk = clk_get_rate(data->clk);
341
+
uart->port.uartclk = clk_get_rate(data->clk);
338
342
}
339
343
340
-
if (!uart.port.uartclk)
344
+
if (!uart->port.uartclk)
341
345
return dev_err_probe(dev, -ENODEV, "unable to determine clock frequency!\n");
342
346
343
347
prescaler = info->prescaler;
344
348
device_property_read_u32(dev, "clock-prescaler", &prescaler);
345
349
if (prescaler) {
346
-
uart.port.set_mctrl = ni16550_set_mctrl;
347
-
ni16550_config_prescaler(&uart, (u8)prescaler);
350
+
uart->port.set_mctrl = ni16550_set_mctrl;
351
+
ni16550_config_prescaler(uart, (u8)prescaler);
348
352
}
349
353
350
354
/*
···
366
362
dev_dbg(dev, "port is in %s mode (via device property)\n",
367
363
rs232_property ? "RS-232" : "RS-485");
368
364
} else if (info->flags & NI_HAS_PMR) {
369
-
rs232_property = is_pmr_rs232_mode(&uart);
365
+
rs232_property = is_pmr_rs232_mode(uart);
370
366
371
367
dev_dbg(dev, "port is in %s mode (via PMR)\n",
372
368
rs232_property ? "RS-232" : "RS-485");
···
381
377
* Neither the 'transceiver' property nor the PMR indicate
382
378
* that this is an RS-232 port, so it must be an RS-485 one.
383
379
*/
384
-
ni16550_rs485_setup(&uart.port);
380
+
ni16550_rs485_setup(&uart->port);
385
381
}
386
382
387
-
ret = serial8250_register_8250_port(&uart);
383
+
ret = serial8250_register_8250_port(uart);
388
384
if (ret < 0)
389
385
return ret;
390
386
data->line = ret;
+27
-26
drivers/tty/serial/8250/8250_omap.c
+27
-26
drivers/tty/serial/8250/8250_omap.c
···
176
176
static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
177
177
{
178
178
struct uart_8250_port *up = up_to_u8250p(port);
179
-
struct omap8250_priv *priv = up->port.private_data;
179
+
struct omap8250_priv *priv = port->private_data;
180
180
u8 lcr;
181
181
182
182
serial8250_do_set_mctrl(port, mctrl);
···
303
303
304
304
static void omap8250_restore_regs(struct uart_8250_port *up)
305
305
{
306
-
struct omap8250_priv *priv = up->port.private_data;
306
+
struct uart_port *port = &up->port;
307
+
struct omap8250_priv *priv = port->private_data;
307
308
struct uart_8250_dma *dma = up->dma;
308
309
u8 mcr = serial8250_in_MCR(up);
309
310
310
311
/* Port locked to synchronize UART_IER access against the console. */
311
-
lockdep_assert_held_once(&up->port.lock);
312
+
lockdep_assert_held_once(&port->lock);
312
313
313
314
if (dma && dma->tx_running) {
314
315
/*
···
360
359
361
360
omap8250_update_mdr1(up, priv);
362
361
363
-
__omap8250_set_mctrl(&up->port, up->port.mctrl);
362
+
__omap8250_set_mctrl(port, port->mctrl);
364
363
365
364
serial_out(up, UART_OMAP_MDR3, priv->mdr3);
366
365
367
-
if (up->port.rs485.flags & SER_RS485_ENABLED &&
368
-
up->port.rs485_config == serial8250_em485_config)
366
+
if (port->rs485.flags & SER_RS485_ENABLED &&
367
+
port->rs485_config == serial8250_em485_config)
369
368
serial8250_em485_stop_tx(up, true);
370
369
}
371
370
···
378
377
const struct ktermios *old)
379
378
{
380
379
struct uart_8250_port *up = up_to_u8250p(port);
381
-
struct omap8250_priv *priv = up->port.private_data;
380
+
struct omap8250_priv *priv = port->private_data;
382
381
unsigned char cval = 0;
383
382
unsigned int baud;
384
383
···
419
418
* ignoring of characters only occurs if the bit is set
420
419
* in @ignore_status_mask as well.
421
420
*/
422
-
up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR;
421
+
port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
423
422
if (termios->c_iflag & INPCK)
424
-
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
423
+
port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
425
424
if (termios->c_iflag & (IGNBRK | PARMRK))
426
-
up->port.read_status_mask |= UART_LSR_BI;
425
+
port->read_status_mask |= UART_LSR_BI;
427
426
428
427
/*
429
428
* Characters to ignore
430
429
*/
431
-
up->port.ignore_status_mask = 0;
430
+
port->ignore_status_mask = 0;
432
431
if (termios->c_iflag & IGNPAR)
433
-
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
432
+
port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
434
433
if (termios->c_iflag & IGNBRK) {
435
-
up->port.ignore_status_mask |= UART_LSR_BI;
434
+
port->ignore_status_mask |= UART_LSR_BI;
436
435
/*
437
436
* If we're ignoring parity and break indicators,
438
437
* ignore overruns too (for real raw support).
439
438
*/
440
439
if (termios->c_iflag & IGNPAR)
441
-
up->port.ignore_status_mask |= UART_LSR_OE;
440
+
port->ignore_status_mask |= UART_LSR_OE;
442
441
}
443
442
444
443
/*
445
444
* ignore all characters if CREAD is not set
446
445
*/
447
446
if ((termios->c_cflag & CREAD) == 0)
448
-
up->port.ignore_status_mask |= UART_LSR_DR;
447
+
port->ignore_status_mask |= UART_LSR_DR;
449
448
450
449
/*
451
450
* Modem status interrupts
452
451
*/
453
452
up->ier &= ~UART_IER_MSI;
454
-
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
453
+
if (UART_ENABLE_MS(port, termios->c_cflag))
455
454
up->ier |= UART_IER_MSI;
456
455
457
456
up->lcr = cval;
···
489
488
priv->xoff = termios->c_cc[VSTOP];
490
489
491
490
priv->efr = 0;
492
-
up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
491
+
port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
493
492
494
-
if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
493
+
if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW &&
495
494
!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
496
495
!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
497
496
/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
498
-
up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
497
+
port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
499
498
priv->efr |= UART_EFR_CTS;
500
-
} else if (up->port.flags & UPF_SOFT_FLOW) {
499
+
} else if (port->flags & UPF_SOFT_FLOW) {
501
500
/*
502
501
* OMAP rx s/w flow control is borked; the transmitter remains
503
502
* stuck off even if rx flow control is subsequently disabled
···
509
508
* Transmit XON1, XOFF1
510
509
*/
511
510
if (termios->c_iflag & IXOFF) {
512
-
up->port.status |= UPSTAT_AUTOXOFF;
511
+
port->status |= UPSTAT_AUTOXOFF;
513
512
priv->efr |= OMAP_UART_SW_TX;
514
513
}
515
514
}
···
771
770
uart_port_unlock_irq(port);
772
771
}
773
772
774
-
enable_irq(up->port.irq);
773
+
enable_irq(port->irq);
775
774
776
775
pm_runtime_mark_last_busy(port->dev);
777
776
pm_runtime_put_autosuspend(port->dev);
···
798
797
up->ier = 0;
799
798
serial_out(up, UART_IER, 0);
800
799
uart_port_unlock_irq(port);
801
-
disable_irq_nosync(up->port.irq);
800
+
disable_irq_nosync(port->irq);
802
801
dev_pm_clear_wake_irq(port->dev);
803
802
804
803
serial8250_release_dma(up);
···
1311
1310
static int omap_8250_dma_handle_irq(struct uart_port *port)
1312
1311
{
1313
1312
struct uart_8250_port *up = up_to_u8250p(port);
1314
-
struct omap8250_priv *priv = up->port.private_data;
1313
+
struct omap8250_priv *priv = port->private_data;
1315
1314
u16 status;
1316
1315
u8 iir;
1317
1316
···
1333
1332
1334
1333
serial8250_modem_status(up);
1335
1334
if (status & UART_LSR_THRE && up->dma->tx_err) {
1336
-
if (uart_tx_stopped(&up->port) ||
1337
-
kfifo_is_empty(&up->port.state->port.xmit_fifo)) {
1335
+
if (uart_tx_stopped(port) ||
1336
+
kfifo_is_empty(&port->state->port.xmit_fifo)) {
1338
1337
up->dma->tx_err = 0;
1339
1338
serial8250_tx_chars(up);
1340
1339
} else {
+3
-3
drivers/tty/serial/8250/8250_pci.c
+3
-3
drivers/tty/serial/8250/8250_pci.c
···
1751
1751
return max_port;
1752
1752
}
1753
1753
1754
-
static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1754
+
static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1755
1755
{
1756
1756
struct f815xxa_data *data = p->private_data;
1757
1757
unsigned long flags;
···
1846
1846
serial8250_clear_and_reinit_fifos(up);
1847
1847
}
1848
1848
1849
-
static unsigned int kt_serial_in(struct uart_port *p, int offset)
1849
+
static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1850
1850
{
1851
1851
struct uart_8250_port *up = up_to_u8250p(p);
1852
-
unsigned int val;
1852
+
u32 val;
1853
1853
1854
1854
/*
1855
1855
* When the Intel ME (management engine) gets reset its serial
+386
-446
drivers/tty/serial/8250/8250_port.c
+386
-446
drivers/tty/serial/8250/8250_port.c
···
39
39
#include "8250.h"
40
40
41
41
/*
42
-
* Debugging.
43
-
*/
44
-
#if 0
45
-
#define DEBUG_AUTOCONF(fmt...) printk(fmt)
46
-
#else
47
-
#define DEBUG_AUTOCONF(fmt...) do { } while (0)
48
-
#endif
49
-
50
-
/*
51
42
* Here we define the default xmit fifo size used for each type of UART.
52
43
*/
53
44
static const struct serial8250_config uart_config[] = {
···
330
339
}
331
340
332
341
#ifdef CONFIG_HAS_IOPORT
333
-
static unsigned int hub6_serial_in(struct uart_port *p, int offset)
342
+
static u32 hub6_serial_in(struct uart_port *p, unsigned int offset)
334
343
{
335
344
offset = offset << p->regshift;
336
345
outb(p->hub6 - 1 + offset, p->iobase);
337
346
return inb(p->iobase + 1);
338
347
}
339
348
340
-
static void hub6_serial_out(struct uart_port *p, int offset, int value)
349
+
static void hub6_serial_out(struct uart_port *p, unsigned int offset, u32 value)
341
350
{
342
351
offset = offset << p->regshift;
343
352
outb(p->hub6 - 1 + offset, p->iobase);
···
345
354
}
346
355
#endif /* CONFIG_HAS_IOPORT */
347
356
348
-
static unsigned int mem_serial_in(struct uart_port *p, int offset)
357
+
static u32 mem_serial_in(struct uart_port *p, unsigned int offset)
349
358
{
350
359
offset = offset << p->regshift;
351
360
return readb(p->membase + offset);
352
361
}
353
362
354
-
static void mem_serial_out(struct uart_port *p, int offset, int value)
363
+
static void mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
355
364
{
356
365
offset = offset << p->regshift;
357
366
writeb(value, p->membase + offset);
358
367
}
359
368
360
-
static void mem16_serial_out(struct uart_port *p, int offset, int value)
369
+
static void mem16_serial_out(struct uart_port *p, unsigned int offset, u32 value)
361
370
{
362
371
offset = offset << p->regshift;
363
372
writew(value, p->membase + offset);
364
373
}
365
374
366
-
static unsigned int mem16_serial_in(struct uart_port *p, int offset)
375
+
static u32 mem16_serial_in(struct uart_port *p, unsigned int offset)
367
376
{
368
377
offset = offset << p->regshift;
369
378
return readw(p->membase + offset);
370
379
}
371
380
372
-
static void mem32_serial_out(struct uart_port *p, int offset, int value)
381
+
static void mem32_serial_out(struct uart_port *p, unsigned int offset, u32 value)
373
382
{
374
383
offset = offset << p->regshift;
375
384
writel(value, p->membase + offset);
376
385
}
377
386
378
-
static unsigned int mem32_serial_in(struct uart_port *p, int offset)
387
+
static u32 mem32_serial_in(struct uart_port *p, unsigned int offset)
379
388
{
380
389
offset = offset << p->regshift;
381
390
return readl(p->membase + offset);
382
391
}
383
392
384
-
static void mem32be_serial_out(struct uart_port *p, int offset, int value)
393
+
static void mem32be_serial_out(struct uart_port *p, unsigned int offset, u32 value)
385
394
{
386
395
offset = offset << p->regshift;
387
396
iowrite32be(value, p->membase + offset);
388
397
}
389
398
390
-
static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
399
+
static u32 mem32be_serial_in(struct uart_port *p, unsigned int offset)
391
400
{
392
401
offset = offset << p->regshift;
393
402
return ioread32be(p->membase + offset);
394
403
}
395
404
396
405
#ifdef CONFIG_HAS_IOPORT
397
-
static unsigned int io_serial_in(struct uart_port *p, int offset)
406
+
static u32 io_serial_in(struct uart_port *p, unsigned int offset)
398
407
{
399
408
offset = offset << p->regshift;
400
409
return inb(p->iobase + offset);
401
410
}
402
411
403
-
static void io_serial_out(struct uart_port *p, int offset, int value)
412
+
static void io_serial_out(struct uart_port *p, unsigned int offset, u32 value)
404
413
{
405
414
offset = offset << p->regshift;
406
415
outb(value, p->iobase + offset);
407
416
}
408
417
#endif
409
-
static unsigned int no_serial_in(struct uart_port *p, int offset)
418
+
static u32 no_serial_in(struct uart_port *p, unsigned int offset)
410
419
{
411
-
return (unsigned int)-1;
420
+
return ~0U;
412
421
}
413
422
414
-
static void no_serial_out(struct uart_port *p, int offset, int value)
423
+
static void no_serial_out(struct uart_port *p, unsigned int offset, u32 value)
415
424
{
416
425
}
417
426
···
696
705
serial8250_rpm_put(p);
697
706
}
698
707
708
+
/* Clear the interrupt registers. */
709
+
static void serial8250_clear_interrupts(struct uart_port *port)
710
+
{
711
+
serial_port_in(port, UART_LSR);
712
+
serial_port_in(port, UART_RX);
713
+
serial_port_in(port, UART_IIR);
714
+
serial_port_in(port, UART_MSR);
715
+
}
716
+
699
717
static void serial8250_clear_IER(struct uart_8250_port *up)
700
718
{
701
719
if (up->capabilities & UART_CAP_UUE)
···
712
712
else
713
713
serial_out(up, UART_IER, 0);
714
714
}
715
-
716
-
#ifdef CONFIG_SERIAL_8250_RSA
717
-
/*
718
-
* Attempts to turn on the RSA FIFO. Returns zero on failure.
719
-
* We set the port uart clock rate if we succeed.
720
-
*/
721
-
static int __enable_rsa(struct uart_8250_port *up)
722
-
{
723
-
unsigned char mode;
724
-
int result;
725
-
726
-
mode = serial_in(up, UART_RSA_MSR);
727
-
result = mode & UART_RSA_MSR_FIFO;
728
-
729
-
if (!result) {
730
-
serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
731
-
mode = serial_in(up, UART_RSA_MSR);
732
-
result = mode & UART_RSA_MSR_FIFO;
733
-
}
734
-
735
-
if (result)
736
-
up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
737
-
738
-
return result;
739
-
}
740
-
741
-
static void enable_rsa(struct uart_8250_port *up)
742
-
{
743
-
if (up->port.type == PORT_RSA) {
744
-
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
745
-
uart_port_lock_irq(&up->port);
746
-
__enable_rsa(up);
747
-
uart_port_unlock_irq(&up->port);
748
-
}
749
-
if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
750
-
serial_out(up, UART_RSA_FRR, 0);
751
-
}
752
-
}
753
-
754
-
/*
755
-
* Attempts to turn off the RSA FIFO. Returns zero on failure.
756
-
* It is unknown why interrupts were disabled in here. However,
757
-
* the caller is expected to preserve this behaviour by grabbing
758
-
* the spinlock before calling this function.
759
-
*/
760
-
static void disable_rsa(struct uart_8250_port *up)
761
-
{
762
-
unsigned char mode;
763
-
int result;
764
-
765
-
if (up->port.type == PORT_RSA &&
766
-
up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
767
-
uart_port_lock_irq(&up->port);
768
-
769
-
mode = serial_in(up, UART_RSA_MSR);
770
-
result = !(mode & UART_RSA_MSR_FIFO);
771
-
772
-
if (!result) {
773
-
serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
774
-
mode = serial_in(up, UART_RSA_MSR);
775
-
result = !(mode & UART_RSA_MSR_FIFO);
776
-
}
777
-
778
-
if (result)
779
-
up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
780
-
uart_port_unlock_irq(&up->port);
781
-
}
782
-
}
783
-
#endif /* CONFIG_SERIAL_8250_RSA */
784
715
785
716
/*
786
717
* This is a quickie test to see how big the FIFO is.
···
816
885
id3 = serial_icr_read(up, UART_ID3);
817
886
rev = serial_icr_read(up, UART_REV);
818
887
819
-
DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
820
-
821
888
if (id1 == 0x16 && id2 == 0xC9 &&
822
889
(id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
823
890
up->port.type = PORT_16C950;
···
839
910
* 0x14 - XR16C854.
840
911
*/
841
912
id1 = autoconfig_read_divisor_id(up);
842
-
DEBUG_AUTOCONF("850id=%04x ", id1);
843
913
844
914
id2 = id1 >> 8;
845
915
if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
···
925
997
if (serial_in(up, UART_EFR) == 0) {
926
998
serial_out(up, UART_EFR, 0xA8);
927
999
if (serial_in(up, UART_EFR) != 0) {
928
-
DEBUG_AUTOCONF("EFRv1 ");
929
1000
up->port.type = PORT_16650;
930
1001
up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
931
1002
} else {
···
937
1010
938
1011
if (status1 == UART_IIR_FIFO_ENABLED_16750)
939
1012
up->port.type = PORT_16550A_FSL64;
940
-
else
941
-
DEBUG_AUTOCONF("Motorola 8xxx DUART ");
942
1013
}
943
1014
serial_out(up, UART_EFR, 0);
944
1015
return;
···
948
1023
*/
949
1024
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
950
1025
if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
951
-
DEBUG_AUTOCONF("EFRv2 ");
952
1026
autoconfig_has_efr(up);
953
1027
return;
954
1028
}
···
1010
1086
1011
1087
serial_out(up, UART_LCR, 0);
1012
1088
1013
-
DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1014
-
1015
1089
if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1016
1090
status2 == UART_IIR_FIFO_ENABLED_16750) {
1017
1091
up->port.type = PORT_16750;
···
1038
1116
* It's an Xscale.
1039
1117
* We'll leave the UART_IER_UUE bit set to 1 (enabled).
1040
1118
*/
1041
-
DEBUG_AUTOCONF("Xscale ");
1042
1119
up->port.type = PORT_XSCALE;
1043
1120
up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1044
1121
return;
1045
1122
}
1046
-
} else {
1047
-
/*
1048
-
* If we got here we couldn't force the IER_UUE bit to 0.
1049
-
* Log it and continue.
1050
-
*/
1051
-
DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1052
1123
}
1053
1124
serial_out(up, UART_IER, iersave);
1054
1125
···
1072
1157
1073
1158
if (!port->iobase && !port->mapbase && !port->membase)
1074
1159
return;
1075
-
1076
-
DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1077
-
port->name, port->iobase, port->membase);
1078
1160
1079
1161
/*
1080
1162
* We really do need global IRQs disabled here - we're going to
···
1119
1207
* We failed; there's nothing here
1120
1208
*/
1121
1209
uart_port_unlock_irqrestore(port, flags);
1122
-
DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1123
-
scratch2, scratch3);
1124
-
goto out;
1210
+
return;
1125
1211
}
1126
1212
}
1127
1213
···
1141
1231
serial8250_out_MCR(up, save_mcr);
1142
1232
if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1143
1233
uart_port_unlock_irqrestore(port, flags);
1144
-
DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1145
-
status1);
1146
-
goto out;
1234
+
return;
1147
1235
}
1148
1236
}
1149
1237
···
1175
1267
break;
1176
1268
}
1177
1269
1178
-
#ifdef CONFIG_SERIAL_8250_RSA
1179
-
/*
1180
-
* Only probe for RSA ports if we got the region.
1181
-
*/
1182
-
if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1183
-
__enable_rsa(up))
1184
-
port->type = PORT_RSA;
1185
-
#endif
1270
+
rsa_autoconfig(up);
1186
1271
1187
1272
serial_out(up, UART_LCR, save_lcr);
1188
1273
···
1184
1283
up->capabilities = uart_config[port->type].flags;
1185
1284
up->tx_loadsz = uart_config[port->type].tx_loadsz;
1186
1285
1187
-
if (port->type == PORT_UNKNOWN)
1188
-
goto out_unlock;
1286
+
if (port->type != PORT_UNKNOWN) {
1287
+
/*
1288
+
* Reset the UART.
1289
+
*/
1290
+
rsa_reset(up);
1291
+
serial8250_out_MCR(up, save_mcr);
1292
+
serial8250_clear_fifos(up);
1293
+
serial_in(up, UART_RX);
1294
+
serial8250_clear_IER(up);
1295
+
}
1189
1296
1190
-
/*
1191
-
* Reset the UART.
1192
-
*/
1193
-
#ifdef CONFIG_SERIAL_8250_RSA
1194
-
if (port->type == PORT_RSA)
1195
-
serial_out(up, UART_RSA_FRR, 0);
1196
-
#endif
1197
-
serial8250_out_MCR(up, save_mcr);
1198
-
serial8250_clear_fifos(up);
1199
-
serial_in(up, UART_RX);
1200
-
serial8250_clear_IER(up);
1201
-
1202
-
out_unlock:
1203
1297
uart_port_unlock_irqrestore(port, flags);
1204
1298
1205
1299
/*
···
1207
1311
dev_warn(port->dev, "detected caps %08x should be %08x\n",
1208
1312
old_capabilities, up->capabilities);
1209
1313
}
1210
-
out:
1211
-
DEBUG_AUTOCONF("iir=%d ", scratch);
1212
-
DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1213
1314
}
1214
1315
1215
1316
static void autoconfig_irq(struct uart_8250_port *up)
···
1247
1354
uart_port_lock_irq(port);
1248
1355
serial_out(up, UART_IER, UART_IER_ALL_INTR);
1249
1356
uart_port_unlock_irq(port);
1250
-
serial_in(up, UART_LSR);
1251
-
serial_in(up, UART_RX);
1252
-
serial_in(up, UART_IIR);
1253
-
serial_in(up, UART_MSR);
1357
+
serial8250_clear_interrupts(port);
1254
1358
serial_out(up, UART_TX, 0xFF);
1255
1359
udelay(20);
1256
1360
irq = probe_irq_off(irqs);
···
2080
2190
2081
2191
#endif /* CONFIG_CONSOLE_POLL */
2082
2192
2083
-
int serial8250_do_startup(struct uart_port *port)
2193
+
static void serial8250_startup_special(struct uart_port *port)
2084
2194
{
2085
2195
struct uart_8250_port *up = up_to_u8250p(port);
2086
2196
unsigned long flags;
2087
-
unsigned char iir;
2088
-
int retval;
2089
-
u16 lsr;
2090
2197
2091
-
if (!port->fifosize)
2092
-
port->fifosize = uart_config[port->type].fifo_size;
2093
-
if (!up->tx_loadsz)
2094
-
up->tx_loadsz = uart_config[port->type].tx_loadsz;
2095
-
if (!up->capabilities)
2096
-
up->capabilities = uart_config[port->type].flags;
2097
-
up->mcr = 0;
2098
-
2099
-
if (port->iotype != up->cur_iotype)
2100
-
set_io_from_upio(port);
2101
-
2102
-
serial8250_rpm_get(up);
2103
-
if (port->type == PORT_16C950) {
2198
+
switch (port->type) {
2199
+
case PORT_16C950:
2104
2200
/*
2105
2201
* Wake up and initialize UART
2106
2202
*
···
2103
2227
serial_port_out(port, UART_EFR, UART_EFR_ECB);
2104
2228
serial_port_out(port, UART_LCR, 0);
2105
2229
uart_port_unlock_irqrestore(port, flags);
2106
-
}
2107
-
2108
-
if (port->type == PORT_DA830) {
2230
+
break;
2231
+
case PORT_DA830:
2109
2232
/*
2110
2233
* Reset the port
2111
2234
*
···
2121
2246
UART_DA830_PWREMU_MGMT_UTRST |
2122
2247
UART_DA830_PWREMU_MGMT_URRST |
2123
2248
UART_DA830_PWREMU_MGMT_FREE);
2249
+
break;
2250
+
case PORT_RSA:
2251
+
rsa_enable(up);
2252
+
break;
2253
+
}
2254
+
}
2255
+
2256
+
static void serial8250_set_TRG_levels(struct uart_port *port)
2257
+
{
2258
+
struct uart_8250_port *up = up_to_u8250p(port);
2259
+
2260
+
switch (port->type) {
2261
+
/* For a XR16C850, we need to set the trigger levels */
2262
+
case PORT_16850: {
2263
+
u8 fctr;
2264
+
2265
+
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2266
+
2267
+
fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2268
+
fctr |= UART_FCTR_TRGD;
2269
+
serial_port_out(port, UART_FCTR, fctr | UART_FCTR_RX);
2270
+
serial_port_out(port, UART_TRG, UART_TRG_96);
2271
+
serial_port_out(port, UART_FCTR, fctr | UART_FCTR_TX);
2272
+
serial_port_out(port, UART_TRG, UART_TRG_96);
2273
+
2274
+
serial_port_out(port, UART_LCR, 0);
2275
+
break;
2276
+
}
2277
+
/* For the Altera 16550 variants, set TX threshold trigger level. */
2278
+
case PORT_ALTR_16550_F32:
2279
+
case PORT_ALTR_16550_F64:
2280
+
case PORT_ALTR_16550_F128:
2281
+
if (port->fifosize <= 1)
2282
+
return;
2283
+
2284
+
/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2285
+
if (up->tx_loadsz < 2 || up->tx_loadsz > port->fifosize) {
2286
+
dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2287
+
return;
2288
+
}
2289
+
serial_port_out(port, UART_ALTR_AFR, UART_ALTR_EN_TXFIFO_LW);
2290
+
serial_port_out(port, UART_ALTR_TX_LOW, port->fifosize - up->tx_loadsz);
2291
+
port->handle_irq = serial8250_tx_threshold_handle_irq;
2292
+
break;
2293
+
}
2294
+
}
2295
+
2296
+
static void serial8250_THRE_test(struct uart_port *port)
2297
+
{
2298
+
struct uart_8250_port *up = up_to_u8250p(port);
2299
+
unsigned long flags;
2300
+
bool iir_noint1, iir_noint2;
2301
+
2302
+
if (!port->irq)
2303
+
return;
2304
+
2305
+
if (up->port.flags & UPF_NO_THRE_TEST)
2306
+
return;
2307
+
2308
+
if (port->irqflags & IRQF_SHARED)
2309
+
disable_irq_nosync(port->irq);
2310
+
2311
+
/*
2312
+
* Test for UARTs that do not reassert THRE when the transmitter is idle and the interrupt
2313
+
* has already been cleared. Real 16550s should always reassert this interrupt whenever the
2314
+
* transmitter is idle and the interrupt is enabled. Delays are necessary to allow register
2315
+
* changes to become visible.
2316
+
*
2317
+
* Synchronize UART_IER access against the console.
2318
+
*/
2319
+
uart_port_lock_irqsave(port, &flags);
2320
+
2321
+
wait_for_xmitr(up, UART_LSR_THRE);
2322
+
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2323
+
udelay(1); /* allow THRE to set */
2324
+
iir_noint1 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2325
+
serial_port_out(port, UART_IER, 0);
2326
+
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2327
+
udelay(1); /* allow a working UART time to re-assert THRE */
2328
+
iir_noint2 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2329
+
serial_port_out(port, UART_IER, 0);
2330
+
2331
+
uart_port_unlock_irqrestore(port, flags);
2332
+
2333
+
if (port->irqflags & IRQF_SHARED)
2334
+
enable_irq(port->irq);
2335
+
2336
+
/*
2337
+
* If the interrupt is not reasserted, or we otherwise don't trust the iir, setup a timer to
2338
+
* kick the UART on a regular basis.
2339
+
*/
2340
+
if ((!iir_noint1 && iir_noint2) || up->port.flags & UPF_BUG_THRE)
2341
+
up->bugs |= UART_BUG_THRE;
2342
+
}
2343
+
2344
+
static void serial8250_init_mctrl(struct uart_port *port)
2345
+
{
2346
+
if (port->flags & UPF_FOURPORT) {
2347
+
if (!port->irq)
2348
+
port->mctrl |= TIOCM_OUT1;
2349
+
} else {
2350
+
/* Most PC uarts need OUT2 raised to enable interrupts. */
2351
+
if (port->irq)
2352
+
port->mctrl |= TIOCM_OUT2;
2124
2353
}
2125
2354
2126
-
#ifdef CONFIG_SERIAL_8250_RSA
2355
+
serial8250_set_mctrl(port, port->mctrl);
2356
+
}
2357
+
2358
+
static void serial8250_iir_txen_test(struct uart_port *port)
2359
+
{
2360
+
struct uart_8250_port *up = up_to_u8250p(port);
2361
+
bool lsr_temt, iir_noint;
2362
+
2363
+
if (port->quirks & UPQ_NO_TXEN_TEST)
2364
+
return;
2365
+
2366
+
/* Do a quick test to see if we receive an interrupt when we enable the TX irq. */
2367
+
serial_port_out(port, UART_IER, UART_IER_THRI);
2368
+
lsr_temt = serial_port_in(port, UART_LSR) & UART_LSR_TEMT;
2369
+
iir_noint = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT;
2370
+
serial_port_out(port, UART_IER, 0);
2371
+
2127
2372
/*
2128
-
* If this is an RSA port, see if we can kick it up to the
2129
-
* higher speed clock.
2373
+
* Serial over Lan (SoL) hack:
2374
+
* Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be used for Serial Over
2375
+
* Lan. Those chips take a longer time than a normal serial device to signalize that a
2376
+
* transmission data was queued. Due to that, the above test generally fails. One solution
2377
+
* would be to delay the reading of iir. However, this is not reliable, since the timeout is
2378
+
* variable. So, in case of UPQ_NO_TXEN_TEST, let's just don't test if we receive TX irq.
2379
+
* This way, we'll never enable UART_BUG_TXEN.
2130
2380
*/
2131
-
enable_rsa(up);
2132
-
#endif
2381
+
if (lsr_temt && iir_noint) {
2382
+
if (!(up->bugs & UART_BUG_TXEN)) {
2383
+
up->bugs |= UART_BUG_TXEN;
2384
+
dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2385
+
}
2386
+
return;
2387
+
}
2388
+
2389
+
/* FIXME: why is this needed? */
2390
+
up->bugs &= ~UART_BUG_TXEN;
2391
+
}
2392
+
2393
+
static void serial8250_initialize(struct uart_port *port)
2394
+
{
2395
+
unsigned long flags;
2396
+
2397
+
uart_port_lock_irqsave(port, &flags);
2398
+
serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2399
+
2400
+
serial8250_init_mctrl(port);
2401
+
serial8250_iir_txen_test(port);
2402
+
uart_port_unlock_irqrestore(port, flags);
2403
+
}
2404
+
2405
+
int serial8250_do_startup(struct uart_port *port)
2406
+
{
2407
+
struct uart_8250_port *up = up_to_u8250p(port);
2408
+
int retval;
2409
+
2410
+
if (!port->fifosize)
2411
+
port->fifosize = uart_config[port->type].fifo_size;
2412
+
if (!up->tx_loadsz)
2413
+
up->tx_loadsz = uart_config[port->type].tx_loadsz;
2414
+
if (!up->capabilities)
2415
+
up->capabilities = uart_config[port->type].flags;
2416
+
up->mcr = 0;
2417
+
2418
+
if (port->iotype != up->cur_iotype)
2419
+
set_io_from_upio(port);
2420
+
2421
+
serial8250_rpm_get(up);
2422
+
2423
+
serial8250_startup_special(port);
2133
2424
2134
2425
/*
2135
2426
* Clear the FIFO buffers and disable them.
···
2303
2262
*/
2304
2263
serial8250_clear_fifos(up);
2305
2264
2306
-
/*
2307
-
* Clear the interrupt registers.
2308
-
*/
2309
-
serial_port_in(port, UART_LSR);
2310
-
serial_port_in(port, UART_RX);
2311
-
serial_port_in(port, UART_IIR);
2312
-
serial_port_in(port, UART_MSR);
2265
+
serial8250_clear_interrupts(port);
2313
2266
2314
2267
/*
2315
2268
* At this point, there's no way the LSR could still be 0xff;
···
2317
2282
goto out;
2318
2283
}
2319
2284
2320
-
/*
2321
-
* For a XR16C850, we need to set the trigger levels
2322
-
*/
2323
-
if (port->type == PORT_16850) {
2324
-
unsigned char fctr;
2325
-
2326
-
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2327
-
2328
-
fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2329
-
serial_port_out(port, UART_FCTR,
2330
-
fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2331
-
serial_port_out(port, UART_TRG, UART_TRG_96);
2332
-
serial_port_out(port, UART_FCTR,
2333
-
fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2334
-
serial_port_out(port, UART_TRG, UART_TRG_96);
2335
-
2336
-
serial_port_out(port, UART_LCR, 0);
2337
-
}
2338
-
2339
-
/*
2340
-
* For the Altera 16550 variants, set TX threshold trigger level.
2341
-
*/
2342
-
if (((port->type == PORT_ALTR_16550_F32) ||
2343
-
(port->type == PORT_ALTR_16550_F64) ||
2344
-
(port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2345
-
/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2346
-
if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2347
-
dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2348
-
} else {
2349
-
serial_port_out(port, UART_ALTR_AFR,
2350
-
UART_ALTR_EN_TXFIFO_LW);
2351
-
serial_port_out(port, UART_ALTR_TX_LOW,
2352
-
port->fifosize - up->tx_loadsz);
2353
-
port->handle_irq = serial8250_tx_threshold_handle_irq;
2354
-
}
2355
-
}
2285
+
serial8250_set_TRG_levels(port);
2356
2286
2357
2287
/* Check if we need to have shared IRQs */
2358
2288
if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
···
2327
2327
if (retval)
2328
2328
goto out;
2329
2329
2330
-
if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2331
-
unsigned char iir1;
2332
-
2333
-
if (port->irqflags & IRQF_SHARED)
2334
-
disable_irq_nosync(port->irq);
2335
-
2336
-
/*
2337
-
* Test for UARTs that do not reassert THRE when the
2338
-
* transmitter is idle and the interrupt has already
2339
-
* been cleared. Real 16550s should always reassert
2340
-
* this interrupt whenever the transmitter is idle and
2341
-
* the interrupt is enabled. Delays are necessary to
2342
-
* allow register changes to become visible.
2343
-
*
2344
-
* Synchronize UART_IER access against the console.
2345
-
*/
2346
-
uart_port_lock_irqsave(port, &flags);
2347
-
2348
-
wait_for_xmitr(up, UART_LSR_THRE);
2349
-
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2350
-
udelay(1); /* allow THRE to set */
2351
-
iir1 = serial_port_in(port, UART_IIR);
2352
-
serial_port_out(port, UART_IER, 0);
2353
-
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2354
-
udelay(1); /* allow a working UART time to re-assert THRE */
2355
-
iir = serial_port_in(port, UART_IIR);
2356
-
serial_port_out(port, UART_IER, 0);
2357
-
2358
-
uart_port_unlock_irqrestore(port, flags);
2359
-
2360
-
if (port->irqflags & IRQF_SHARED)
2361
-
enable_irq(port->irq);
2362
-
2363
-
/*
2364
-
* If the interrupt is not reasserted, or we otherwise
2365
-
* don't trust the iir, setup a timer to kick the UART
2366
-
* on a regular basis.
2367
-
*/
2368
-
if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2369
-
up->port.flags & UPF_BUG_THRE) {
2370
-
up->bugs |= UART_BUG_THRE;
2371
-
}
2372
-
}
2330
+
serial8250_THRE_test(port);
2373
2331
2374
2332
up->ops->setup_timer(up);
2375
2333
2376
-
/*
2377
-
* Now, initialize the UART
2378
-
*/
2379
-
serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2380
-
2381
-
uart_port_lock_irqsave(port, &flags);
2382
-
if (up->port.flags & UPF_FOURPORT) {
2383
-
if (!up->port.irq)
2384
-
up->port.mctrl |= TIOCM_OUT1;
2385
-
} else
2386
-
/*
2387
-
* Most PC uarts need OUT2 raised to enable interrupts.
2388
-
*/
2389
-
if (port->irq)
2390
-
up->port.mctrl |= TIOCM_OUT2;
2391
-
2392
-
serial8250_set_mctrl(port, port->mctrl);
2393
-
2394
-
/*
2395
-
* Serial over Lan (SoL) hack:
2396
-
* Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2397
-
* used for Serial Over Lan. Those chips take a longer time than a
2398
-
* normal serial device to signalize that a transmission data was
2399
-
* queued. Due to that, the above test generally fails. One solution
2400
-
* would be to delay the reading of iir. However, this is not
2401
-
* reliable, since the timeout is variable. So, let's just don't
2402
-
* test if we receive TX irq. This way, we'll never enable
2403
-
* UART_BUG_TXEN.
2404
-
*/
2405
-
if (!(up->port.quirks & UPQ_NO_TXEN_TEST)) {
2406
-
/*
2407
-
* Do a quick test to see if we receive an interrupt when we
2408
-
* enable the TX irq.
2409
-
*/
2410
-
serial_port_out(port, UART_IER, UART_IER_THRI);
2411
-
lsr = serial_port_in(port, UART_LSR);
2412
-
iir = serial_port_in(port, UART_IIR);
2413
-
serial_port_out(port, UART_IER, 0);
2414
-
2415
-
if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2416
-
if (!(up->bugs & UART_BUG_TXEN)) {
2417
-
up->bugs |= UART_BUG_TXEN;
2418
-
dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2419
-
}
2420
-
} else {
2421
-
up->bugs &= ~UART_BUG_TXEN;
2422
-
}
2423
-
}
2424
-
2425
-
uart_port_unlock_irqrestore(port, flags);
2334
+
serial8250_initialize(port);
2426
2335
2427
2336
/*
2428
2337
* Clear the interrupt registers again for luck, and clear the
2429
2338
* saved flags to avoid getting false values from polling
2430
2339
* routines or the previous session.
2431
2340
*/
2432
-
serial_port_in(port, UART_LSR);
2433
-
serial_port_in(port, UART_RX);
2434
-
serial_port_in(port, UART_IIR);
2435
-
serial_port_in(port, UART_MSR);
2341
+
serial8250_clear_interrupts(port);
2436
2342
up->lsr_saved_flags = 0;
2437
2343
up->msr_saved_flags = 0;
2438
2344
···
2427
2521
serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2428
2522
serial8250_clear_fifos(up);
2429
2523
2430
-
#ifdef CONFIG_SERIAL_8250_RSA
2431
-
/*
2432
-
* Reset the RSA board back to 115kbps compat mode.
2433
-
*/
2434
-
disable_rsa(up);
2435
-
#endif
2524
+
rsa_disable(up);
2436
2525
2437
2526
/*
2438
2527
* Read data port to reset things, and then unlink from
···
2456
2555
serial8250_tx_dma_flush(up);
2457
2556
}
2458
2557
2459
-
static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2460
-
unsigned int baud,
2461
-
unsigned int *frac)
2558
+
static unsigned int serial8250_do_get_divisor(struct uart_port *port, unsigned int baud)
2462
2559
{
2463
2560
upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2464
2561
struct uart_8250_port *up = up_to_u8250p(port);
···
2517
2618
if (port->get_divisor)
2518
2619
return port->get_divisor(port, baud, frac);
2519
2620
2520
-
return serial8250_do_get_divisor(port, baud, frac);
2621
+
return serial8250_do_get_divisor(port, baud);
2521
2622
}
2522
2623
2523
-
static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2524
-
tcflag_t c_cflag)
2624
+
static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, tcflag_t c_cflag)
2525
2625
{
2526
-
unsigned char cval;
2527
-
2528
-
cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2626
+
u8 lcr = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2529
2627
2530
2628
if (c_cflag & CSTOPB)
2531
-
cval |= UART_LCR_STOP;
2629
+
lcr |= UART_LCR_STOP;
2532
2630
if (c_cflag & PARENB)
2533
-
cval |= UART_LCR_PARITY;
2631
+
lcr |= UART_LCR_PARITY;
2534
2632
if (!(c_cflag & PARODD))
2535
-
cval |= UART_LCR_EPAR;
2633
+
lcr |= UART_LCR_EPAR;
2536
2634
if (c_cflag & CMSPAR)
2537
-
cval |= UART_LCR_SPAR;
2635
+
lcr |= UART_LCR_SPAR;
2538
2636
2539
-
return cval;
2637
+
return lcr;
2540
2638
}
2541
2639
2542
2640
void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
···
2640
2744
}
2641
2745
EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2642
2746
2747
+
static void serial8250_set_mini(struct uart_port *port, struct ktermios *termios)
2748
+
{
2749
+
struct uart_8250_port *up = up_to_u8250p(port);
2750
+
2751
+
if (!(up->capabilities & UART_CAP_MINI))
2752
+
return;
2753
+
2754
+
termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2755
+
2756
+
tcflag_t csize = termios->c_cflag & CSIZE;
2757
+
if (csize == CS5 || csize == CS6) {
2758
+
termios->c_cflag &= ~CSIZE;
2759
+
termios->c_cflag |= CS7;
2760
+
}
2761
+
}
2762
+
2763
+
static void serial8250_set_trigger_for_slow_speed(struct uart_port *port, struct ktermios *termios,
2764
+
unsigned int baud)
2765
+
{
2766
+
struct uart_8250_port *up = up_to_u8250p(port);
2767
+
2768
+
if (!(up->capabilities & UART_CAP_FIFO))
2769
+
return;
2770
+
if (port->fifosize <= 1)
2771
+
return;
2772
+
if (baud >= 2400)
2773
+
return;
2774
+
if (up->dma)
2775
+
return;
2776
+
2777
+
up->fcr &= ~UART_FCR_TRIGGER_MASK;
2778
+
up->fcr |= UART_FCR_TRIGGER_1;
2779
+
}
2780
+
2781
+
/*
2782
+
* MCR-based auto flow control. When AFE is enabled, RTS will be deasserted when the receive FIFO
2783
+
* contains more characters than the trigger, or the MCR RTS bit is cleared.
2784
+
*/
2785
+
static void serial8250_set_afe(struct uart_port *port, struct ktermios *termios)
2786
+
{
2787
+
struct uart_8250_port *up = up_to_u8250p(port);
2788
+
2789
+
if (!(up->capabilities & UART_CAP_AFE))
2790
+
return;
2791
+
2792
+
up->mcr &= ~UART_MCR_AFE;
2793
+
if (termios->c_cflag & CRTSCTS)
2794
+
up->mcr |= UART_MCR_AFE;
2795
+
}
2796
+
2797
+
static void serial8250_set_errors_and_ignores(struct uart_port *port, struct ktermios *termios)
2798
+
{
2799
+
/*
2800
+
* Specify which conditions may be considered for error handling and the ignoring of
2801
+
* characters. The actual ignoring of characters only occurs if the bit is set in
2802
+
* @ignore_status_mask as well.
2803
+
*/
2804
+
port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
2805
+
if (termios->c_iflag & INPCK)
2806
+
port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2807
+
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2808
+
port->read_status_mask |= UART_LSR_BI;
2809
+
2810
+
/* Characters to ignore */
2811
+
port->ignore_status_mask = 0;
2812
+
if (termios->c_iflag & IGNPAR)
2813
+
port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2814
+
if (termios->c_iflag & IGNBRK) {
2815
+
port->ignore_status_mask |= UART_LSR_BI;
2816
+
/*
2817
+
* If we're ignoring parity and break indicators, ignore overruns too (for real raw
2818
+
* support).
2819
+
*/
2820
+
if (termios->c_iflag & IGNPAR)
2821
+
port->ignore_status_mask |= UART_LSR_OE;
2822
+
}
2823
+
2824
+
/* ignore all characters if CREAD is not set */
2825
+
if ((termios->c_cflag & CREAD) == 0)
2826
+
port->ignore_status_mask |= UART_LSR_DR;
2827
+
}
2828
+
2829
+
static void serial8250_set_ier(struct uart_port *port, struct ktermios *termios)
2830
+
{
2831
+
struct uart_8250_port *up = up_to_u8250p(port);
2832
+
2833
+
/* CTS flow control flag and modem status interrupts */
2834
+
up->ier &= ~UART_IER_MSI;
2835
+
if (!(up->bugs & UART_BUG_NOMSR) && UART_ENABLE_MS(&up->port, termios->c_cflag))
2836
+
up->ier |= UART_IER_MSI;
2837
+
if (up->capabilities & UART_CAP_UUE)
2838
+
up->ier |= UART_IER_UUE;
2839
+
if (up->capabilities & UART_CAP_RTOIE)
2840
+
up->ier |= UART_IER_RTOIE;
2841
+
2842
+
serial_port_out(port, UART_IER, up->ier);
2843
+
}
2844
+
2845
+
static void serial8250_set_efr(struct uart_port *port, struct ktermios *termios)
2846
+
{
2847
+
struct uart_8250_port *up = up_to_u8250p(port);
2848
+
u8 efr_reg = UART_EFR;
2849
+
u8 efr = 0;
2850
+
2851
+
if (!(up->capabilities & UART_CAP_EFR))
2852
+
return;
2853
+
2854
+
/*
2855
+
* TI16C752/Startech hardware flow control. FIXME:
2856
+
* - TI16C752 requires control thresholds to be set.
2857
+
* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2858
+
*/
2859
+
if (termios->c_cflag & CRTSCTS)
2860
+
efr |= UART_EFR_CTS;
2861
+
2862
+
if (port->flags & UPF_EXAR_EFR)
2863
+
efr_reg = UART_XR_EFR;
2864
+
2865
+
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2866
+
serial_port_out(port, efr_reg, efr);
2867
+
}
2868
+
2869
+
static void serial8250_set_fcr(struct uart_port *port, struct ktermios *termios)
2870
+
{
2871
+
struct uart_8250_port *up = up_to_u8250p(port);
2872
+
bool is_16750 = port->type == PORT_16750;
2873
+
2874
+
if (is_16750)
2875
+
serial_port_out(port, UART_FCR, up->fcr);
2876
+
2877
+
/*
2878
+
* LCR DLAB must be reset to enable 64-byte FIFO mode. If the FCR is written without DLAB
2879
+
* set, this mode will be disabled.
2880
+
*/
2881
+
serial_port_out(port, UART_LCR, up->lcr);
2882
+
2883
+
if (is_16750)
2884
+
return;
2885
+
2886
+
/* emulated UARTs (Lucent Venus 167x) need two steps */
2887
+
if (up->fcr & UART_FCR_ENABLE_FIFO)
2888
+
serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2889
+
2890
+
serial_port_out(port, UART_FCR, up->fcr);
2891
+
}
2892
+
2643
2893
void
2644
2894
serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2645
2895
const struct ktermios *old)
2646
2896
{
2647
2897
struct uart_8250_port *up = up_to_u8250p(port);
2648
-
unsigned char cval;
2649
2898
unsigned long flags;
2650
2899
unsigned int baud, quot, frac = 0;
2900
+
u8 lcr;
2651
2901
2652
-
if (up->capabilities & UART_CAP_MINI) {
2653
-
termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2654
-
if ((termios->c_cflag & CSIZE) == CS5 ||
2655
-
(termios->c_cflag & CSIZE) == CS6)
2656
-
termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2657
-
}
2658
-
cval = serial8250_compute_lcr(up, termios->c_cflag);
2659
-
2902
+
serial8250_set_mini(port, termios);
2903
+
lcr = serial8250_compute_lcr(up, termios->c_cflag);
2660
2904
baud = serial8250_get_baud_rate(port, termios, old);
2661
2905
quot = serial8250_get_divisor(port, baud, &frac);
2662
2906
···
2809
2773
serial8250_rpm_get(up);
2810
2774
uart_port_lock_irqsave(port, &flags);
2811
2775
2812
-
up->lcr = cval; /* Save computed LCR */
2813
-
2814
-
if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2815
-
if (baud < 2400 && !up->dma) {
2816
-
up->fcr &= ~UART_FCR_TRIGGER_MASK;
2817
-
up->fcr |= UART_FCR_TRIGGER_1;
2818
-
}
2819
-
}
2820
-
2821
-
/*
2822
-
* MCR-based auto flow control. When AFE is enabled, RTS will be
2823
-
* deasserted when the receive FIFO contains more characters than
2824
-
* the trigger, or the MCR RTS bit is cleared.
2825
-
*/
2826
-
if (up->capabilities & UART_CAP_AFE) {
2827
-
up->mcr &= ~UART_MCR_AFE;
2828
-
if (termios->c_cflag & CRTSCTS)
2829
-
up->mcr |= UART_MCR_AFE;
2830
-
}
2831
-
2832
-
/*
2833
-
* Update the per-port timeout.
2834
-
*/
2776
+
up->lcr = lcr;
2777
+
serial8250_set_trigger_for_slow_speed(port, termios, baud);
2778
+
serial8250_set_afe(port, termios);
2835
2779
uart_update_timeout(port, termios->c_cflag, baud);
2836
-
2837
-
/*
2838
-
* Specify which conditions may be considered for error
2839
-
* handling and the ignoring of characters. The actual
2840
-
* ignoring of characters only occurs if the bit is set
2841
-
* in @ignore_status_mask as well.
2842
-
*/
2843
-
port->read_status_mask = UART_LSR_OE | UART_LSR_DR;
2844
-
if (termios->c_iflag & INPCK)
2845
-
port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2846
-
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2847
-
port->read_status_mask |= UART_LSR_BI;
2848
-
2849
-
/*
2850
-
* Characters to ignore
2851
-
*/
2852
-
port->ignore_status_mask = 0;
2853
-
if (termios->c_iflag & IGNPAR)
2854
-
port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2855
-
if (termios->c_iflag & IGNBRK) {
2856
-
port->ignore_status_mask |= UART_LSR_BI;
2857
-
/*
2858
-
* If we're ignoring parity and break indicators,
2859
-
* ignore overruns too (for real raw support).
2860
-
*/
2861
-
if (termios->c_iflag & IGNPAR)
2862
-
port->ignore_status_mask |= UART_LSR_OE;
2863
-
}
2864
-
2865
-
/*
2866
-
* ignore all characters if CREAD is not set
2867
-
*/
2868
-
if ((termios->c_cflag & CREAD) == 0)
2869
-
port->ignore_status_mask |= UART_LSR_DR;
2870
-
2871
-
/*
2872
-
* CTS flow control flag and modem status interrupts
2873
-
*/
2874
-
up->ier &= ~UART_IER_MSI;
2875
-
if (!(up->bugs & UART_BUG_NOMSR) &&
2876
-
UART_ENABLE_MS(&up->port, termios->c_cflag))
2877
-
up->ier |= UART_IER_MSI;
2878
-
if (up->capabilities & UART_CAP_UUE)
2879
-
up->ier |= UART_IER_UUE;
2880
-
if (up->capabilities & UART_CAP_RTOIE)
2881
-
up->ier |= UART_IER_RTOIE;
2882
-
2883
-
serial_port_out(port, UART_IER, up->ier);
2884
-
2885
-
if (up->capabilities & UART_CAP_EFR) {
2886
-
unsigned char efr = 0;
2887
-
/*
2888
-
* TI16C752/Startech hardware flow control. FIXME:
2889
-
* - TI16C752 requires control thresholds to be set.
2890
-
* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2891
-
*/
2892
-
if (termios->c_cflag & CRTSCTS)
2893
-
efr |= UART_EFR_CTS;
2894
-
2895
-
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2896
-
if (port->flags & UPF_EXAR_EFR)
2897
-
serial_port_out(port, UART_XR_EFR, efr);
2898
-
else
2899
-
serial_port_out(port, UART_EFR, efr);
2900
-
}
2901
-
2780
+
serial8250_set_errors_and_ignores(port, termios);
2781
+
serial8250_set_ier(port, termios);
2782
+
serial8250_set_efr(port, termios);
2902
2783
serial8250_set_divisor(port, baud, quot, frac);
2903
-
2904
-
/*
2905
-
* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2906
-
* is written without DLAB set, this mode will be disabled.
2907
-
*/
2908
-
if (port->type == PORT_16750)
2909
-
serial_port_out(port, UART_FCR, up->fcr);
2910
-
2911
-
serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2912
-
if (port->type != PORT_16750) {
2913
-
/* emulated UARTs (Lucent Venus 167x) need two steps */
2914
-
if (up->fcr & UART_FCR_ENABLE_FIFO)
2915
-
serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2916
-
serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2917
-
}
2784
+
serial8250_set_fcr(port, termios);
2918
2785
serial8250_set_mctrl(port, port->mctrl);
2786
+
2919
2787
uart_port_unlock_irqrestore(port, flags);
2920
2788
serial8250_rpm_put(up);
2921
2789
+96
drivers/tty/serial/8250/8250_rsa.c
+96
drivers/tty/serial/8250/8250_rsa.c
···
107
107
module_param_hw_array(probe_rsa, ulong, ioport, &probe_rsa_count, 0444);
108
108
MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
109
109
110
+
/*
111
+
* Attempts to turn on the RSA FIFO. Returns zero on failure.
112
+
* We set the port uart clock rate if we succeed.
113
+
*/
114
+
static int __rsa_enable(struct uart_8250_port *up)
115
+
{
116
+
unsigned char mode;
117
+
int result;
118
+
119
+
mode = serial_in(up, UART_RSA_MSR);
120
+
result = mode & UART_RSA_MSR_FIFO;
121
+
122
+
if (!result) {
123
+
serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
124
+
mode = serial_in(up, UART_RSA_MSR);
125
+
result = mode & UART_RSA_MSR_FIFO;
126
+
}
127
+
128
+
if (result)
129
+
up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
130
+
131
+
return result;
132
+
}
133
+
134
+
/*
135
+
* If this is an RSA port, see if we can kick it up to the higher speed clock.
136
+
*/
137
+
void rsa_enable(struct uart_8250_port *up)
138
+
{
139
+
if (up->port.type != PORT_RSA)
140
+
return;
141
+
142
+
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
143
+
uart_port_lock_irq(&up->port);
144
+
__rsa_enable(up);
145
+
uart_port_unlock_irq(&up->port);
146
+
}
147
+
if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
148
+
serial_out(up, UART_RSA_FRR, 0);
149
+
}
150
+
EXPORT_SYMBOL_GPL_FOR_MODULES(rsa_enable, "8250_base");
151
+
152
+
/*
153
+
* Attempts to turn off the RSA FIFO and resets the RSA board back to 115kbps compat mode. It is
154
+
* unknown why interrupts were disabled in here. However, the caller is expected to preserve this
155
+
* behaviour by grabbing the spinlock before calling this function.
156
+
*/
157
+
void rsa_disable(struct uart_8250_port *up)
158
+
{
159
+
unsigned char mode;
160
+
int result;
161
+
162
+
if (up->port.type != PORT_RSA)
163
+
return;
164
+
165
+
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16)
166
+
return;
167
+
168
+
uart_port_lock_irq(&up->port);
169
+
mode = serial_in(up, UART_RSA_MSR);
170
+
result = !(mode & UART_RSA_MSR_FIFO);
171
+
172
+
if (!result) {
173
+
serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
174
+
mode = serial_in(up, UART_RSA_MSR);
175
+
result = !(mode & UART_RSA_MSR_FIFO);
176
+
}
177
+
178
+
if (result)
179
+
up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
180
+
uart_port_unlock_irq(&up->port);
181
+
}
182
+
EXPORT_SYMBOL_GPL_FOR_MODULES(rsa_disable, "8250_base");
183
+
184
+
void rsa_autoconfig(struct uart_8250_port *up)
185
+
{
186
+
/* Only probe for RSA ports if we got the region. */
187
+
if (up->port.type != PORT_16550A)
188
+
return;
189
+
if (!(up->probe & UART_PROBE_RSA))
190
+
return;
191
+
192
+
if (__rsa_enable(up))
193
+
up->port.type = PORT_RSA;
194
+
}
195
+
EXPORT_SYMBOL_GPL_FOR_MODULES(rsa_autoconfig, "8250_base");
196
+
197
+
void rsa_reset(struct uart_8250_port *up)
198
+
{
199
+
if (up->port.type != PORT_RSA)
200
+
return;
201
+
202
+
serial_out(up, UART_RSA_FRR, 0);
203
+
}
204
+
EXPORT_SYMBOL_GPL_FOR_MODULES(rsa_reset, "8250_base");
205
+
110
206
#ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
111
207
#ifndef MODULE
112
208
/*
+2
-2
drivers/tty/serial/8250/8250_rt288x.c
+2
-2
drivers/tty/serial/8250/8250_rt288x.c
···
33
33
[UART_MCR] = 6,
34
34
};
35
35
36
-
static unsigned int au_serial_in(struct uart_port *p, int offset)
36
+
static u32 au_serial_in(struct uart_port *p, unsigned int offset)
37
37
{
38
38
if (offset >= ARRAY_SIZE(au_io_in_map))
39
39
return UINT_MAX;
···
42
42
return __raw_readl(p->membase + (offset << p->regshift));
43
43
}
44
44
45
-
static void au_serial_out(struct uart_port *p, int offset, int value)
45
+
static void au_serial_out(struct uart_port *p, unsigned int offset, u32 value)
46
46
{
47
47
if (offset >= ARRAY_SIZE(au_io_out_map))
48
48
return;
+2
-2
drivers/tty/serial/8250/8250_uniphier.c
+2
-2
drivers/tty/serial/8250/8250_uniphier.c
···
63
63
* The register map is slightly different from that of 8250.
64
64
* IO callbacks must be overridden for correct access to FCR, LCR, MCR and SCR.
65
65
*/
66
-
static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
66
+
static u32 uniphier_serial_in(struct uart_port *p, unsigned int offset)
67
67
{
68
68
unsigned int valshift = 0;
69
69
···
92
92
return (readl(p->membase + offset) >> valshift) & 0xff;
93
93
}
94
94
95
-
static void uniphier_serial_out(struct uart_port *p, int offset, int value)
95
+
static void uniphier_serial_out(struct uart_port *p, unsigned int offset, u32 value)
96
96
{
97
97
unsigned int valshift = 0;
98
98
bool normal = false;
+3
drivers/tty/serial/8250/Makefile
+3
drivers/tty/serial/8250/Makefile
···
24
24
obj-$(CONFIG_SERIAL_8250_BCM2835AUX) += 8250_bcm2835aux.o
25
25
obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o
26
26
obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
27
+
ifeq ($(CONFIG_SERIAL_8250),y)
28
+
obj-$(CONFIG_X86_INTEL_CE) += 8250_ce4100.o
29
+
endif
27
30
obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o
28
31
obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o
29
32
obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o
+7
drivers/tty/serial/Kconfig
+7
drivers/tty/serial/Kconfig
···
675
675
depends on SERIAL_SH_SCI && DMA_ENGINE
676
676
default ARCH_RENESAS
677
677
678
+
config SERIAL_RSCI
679
+
tristate "Support for Renesas RZ/T2H SCI variant"
680
+
depends on SERIAL_SH_SCI
681
+
help
682
+
Support for the RZ/T2H SCI variant with fifo.
683
+
Say Y if you want to be able to use the RZ/T2H SCI serial port.
684
+
678
685
config SERIAL_HS_LPC32XX
679
686
tristate "LPC32XX high speed serial port support"
680
687
depends on ARCH_LPC32XX || COMPILE_TEST
+1
drivers/tty/serial/Makefile
+1
drivers/tty/serial/Makefile
···
71
71
obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
72
72
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
73
73
obj-$(CONFIG_SERIAL_RP2) += rp2.o
74
+
obj-$(CONFIG_SERIAL_RSCI) += rsci.o
74
75
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
75
76
obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o
76
77
obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
+4
-4
drivers/tty/serial/fsl_lpuart.c
+4
-4
drivers/tty/serial/fsl_lpuart.c
···
318
318
.rx_watermark = 0,
319
319
};
320
320
321
-
static struct lpuart_soc_data imx7ulp_data = {
321
+
static const struct lpuart_soc_data imx7ulp_data = {
322
322
.devtype = IMX7ULP_LPUART,
323
323
.iotype = UPIO_MEM32,
324
324
.reg_off = IMX_REG_OFF,
325
325
.rx_watermark = 1,
326
326
};
327
327
328
-
static struct lpuart_soc_data imx8ulp_data = {
328
+
static const struct lpuart_soc_data imx8ulp_data = {
329
329
.devtype = IMX8ULP_LPUART,
330
330
.iotype = UPIO_MEM32,
331
331
.reg_off = IMX_REG_OFF,
332
332
.rx_watermark = 3,
333
333
};
334
334
335
-
static struct lpuart_soc_data imx8qxp_data = {
335
+
static const struct lpuart_soc_data imx8qxp_data = {
336
336
.devtype = IMX8QXP_LPUART,
337
337
.iotype = UPIO_MEM32,
338
338
.reg_off = IMX_REG_OFF,
339
339
.rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
340
340
};
341
-
static struct lpuart_soc_data imxrt1050_data = {
341
+
static const struct lpuart_soc_data imxrt1050_data = {
342
342
.devtype = IMXRT1050_LPUART,
343
343
.iotype = UPIO_MEM32,
344
344
.reg_off = IMX_REG_OFF,
+325
-70
drivers/tty/serial/qcom_geni_serial.c
+325
-70
drivers/tty/serial/qcom_geni_serial.c
···
11
11
#include <linux/irq.h>
12
12
#include <linux/module.h>
13
13
#include <linux/of.h>
14
+
#include <linux/pm_domain.h>
14
15
#include <linux/pm_opp.h>
15
16
#include <linux/platform_device.h>
16
17
#include <linux/pm_runtime.h>
···
100
99
#define DMA_RX_BUF_SIZE 2048
101
100
102
101
static DEFINE_IDA(port_ida);
102
+
#define DOMAIN_IDX_POWER 0
103
+
#define DOMAIN_IDX_PERF 1
103
104
104
105
struct qcom_geni_device_data {
105
106
bool console;
106
107
enum geni_se_xfer_mode mode;
108
+
struct dev_pm_domain_attach_data pd_data;
109
+
int (*resources_init)(struct uart_port *uport);
110
+
int (*set_rate)(struct uart_port *uport, unsigned int baud);
111
+
int (*power_state)(struct uart_port *uport, bool state);
107
112
};
108
113
109
114
struct qcom_geni_private_data {
···
147
140
148
141
struct qcom_geni_private_data private_data;
149
142
const struct qcom_geni_device_data *dev_data;
143
+
struct dev_pm_domain_list *pd_list;
150
144
};
151
145
152
146
static const struct uart_ops qcom_geni_console_pops;
···
199
191
.line = 0,
200
192
},
201
193
};
194
+
195
+
static const struct serial_rs485 qcom_geni_rs485_supported = {
196
+
.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RTS_ON_SEND,
197
+
};
198
+
199
+
/**
200
+
* qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode
201
+
* @uport: UART port
202
+
* @flag: RS485 flag to determine RTS polarity
203
+
*
204
+
* Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY
205
+
* based on the specified flag if RS485 mode is enabled.
206
+
*/
207
+
static void qcom_geni_set_rs485_mode(struct uart_port *uport, u32 flag)
208
+
{
209
+
if (!(uport->rs485.flags & SER_RS485_ENABLED))
210
+
return;
211
+
212
+
u32 rfr = UART_MANUAL_RFR_EN;
213
+
214
+
if (uport->rs485.flags & flag)
215
+
rfr |= UART_RFR_NOT_READY;
216
+
else
217
+
rfr |= UART_RFR_READY;
218
+
219
+
writel(rfr, uport->membase + SE_UART_MANUAL_RFR);
220
+
}
202
221
203
222
static int qcom_geni_serial_request_port(struct uart_port *uport)
204
223
{
···
699
664
xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
700
665
UART_XMIT_SIZE);
701
666
667
+
qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_ON_SEND);
668
+
702
669
qcom_geni_serial_setup_tx(uport, xmit_size);
703
670
704
671
ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size,
···
1108
1071
}
1109
1072
1110
1073
if (dma) {
1111
-
if (dma_tx_status & TX_DMA_DONE)
1074
+
if (dma_tx_status & TX_DMA_DONE) {
1112
1075
qcom_geni_serial_handle_tx_dma(uport);
1076
+
qcom_geni_set_rs485_mode(uport, SER_RS485_RTS_AFTER_SEND);
1077
+
}
1113
1078
1114
1079
if (dma_rx_status) {
1115
1080
if (dma_rx_status & RX_RESET_DONE)
···
1322
1283
return ser_clk;
1323
1284
}
1324
1285
1325
-
static void qcom_geni_serial_set_termios(struct uart_port *uport,
1326
-
struct ktermios *termios,
1327
-
const struct ktermios *old)
1286
+
static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud)
1328
1287
{
1329
-
unsigned int baud;
1330
-
u32 bits_per_char;
1331
-
u32 tx_trans_cfg;
1332
-
u32 tx_parity_cfg;
1333
-
u32 rx_trans_cfg;
1334
-
u32 rx_parity_cfg;
1335
-
u32 stop_bit_len;
1336
-
unsigned int clk_div;
1337
-
u32 ser_clk_cfg;
1338
1288
struct qcom_geni_serial_port *port = to_dev_port(uport);
1339
1289
unsigned long clk_rate;
1340
-
u32 ver, sampling_rate;
1341
1290
unsigned int avg_bw_core;
1342
-
unsigned long timeout;
1343
-
1344
-
/* baud rate */
1345
-
baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1291
+
unsigned int clk_div;
1292
+
u32 ver, sampling_rate;
1293
+
u32 ser_clk_cfg;
1346
1294
1347
1295
sampling_rate = UART_OVERSAMPLING;
1348
1296
/* Sampling rate is halved for IP versions >= 2.5 */
···
1343
1317
dev_err(port->se.dev,
1344
1318
"Couldn't find suitable clock rate for %u\n",
1345
1319
baud * sampling_rate);
1346
-
return;
1320
+
return -EINVAL;
1347
1321
}
1348
1322
1349
1323
dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
···
1364
1338
port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1365
1339
port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1366
1340
geni_icc_set_bw(&port->se);
1341
+
1342
+
writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1343
+
writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1344
+
return 0;
1345
+
}
1346
+
1347
+
static int geni_serial_set_level(struct uart_port *uport, unsigned int baud)
1348
+
{
1349
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1350
+
struct device *perf_dev = port->pd_list->pd_devs[DOMAIN_IDX_PERF];
1351
+
1352
+
/*
1353
+
* The performance protocol sets UART communication
1354
+
* speeds by selecting different performance levels
1355
+
* through the OPP framework.
1356
+
*
1357
+
* Supported perf levels for baudrates in firmware are below
1358
+
* +---------------------+--------------------+
1359
+
* | Perf level value | Baudrate values |
1360
+
* +---------------------+--------------------+
1361
+
* | 300 | 300 |
1362
+
* | 1200 | 1200 |
1363
+
* | 2400 | 2400 |
1364
+
* | 4800 | 4800 |
1365
+
* | 9600 | 9600 |
1366
+
* | 19200 | 19200 |
1367
+
* | 38400 | 38400 |
1368
+
* | 57600 | 57600 |
1369
+
* | 115200 | 115200 |
1370
+
* | 230400 | 230400 |
1371
+
* | 460800 | 460800 |
1372
+
* | 921600 | 921600 |
1373
+
* | 2000000 | 2000000 |
1374
+
* | 3000000 | 3000000 |
1375
+
* | 3200000 | 3200000 |
1376
+
* | 4000000 | 4000000 |
1377
+
* +---------------------+--------------------+
1378
+
*/
1379
+
1380
+
return dev_pm_opp_set_level(perf_dev, baud);
1381
+
}
1382
+
1383
+
static void qcom_geni_serial_set_termios(struct uart_port *uport,
1384
+
struct ktermios *termios,
1385
+
const struct ktermios *old)
1386
+
{
1387
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1388
+
unsigned int baud;
1389
+
unsigned long timeout;
1390
+
u32 bits_per_char;
1391
+
u32 tx_trans_cfg;
1392
+
u32 tx_parity_cfg;
1393
+
u32 rx_trans_cfg;
1394
+
u32 rx_parity_cfg;
1395
+
u32 stop_bit_len;
1396
+
int ret = 0;
1397
+
1398
+
/* baud rate */
1399
+
baud = uart_get_baud_rate(uport, termios, old, 300, 8000000);
1400
+
1401
+
ret = port->dev_data->set_rate(uport, baud);
1402
+
if (ret)
1403
+
return;
1367
1404
1368
1405
/* parity */
1369
1406
tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
···
1495
1406
writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1496
1407
writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1497
1408
writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1498
-
writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1499
-
writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1500
1409
}
1501
1410
1502
1411
#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
···
1675
1588
.nr = GENI_UART_PORTS,
1676
1589
};
1677
1590
1591
+
static int geni_serial_resources_on(struct uart_port *uport)
1592
+
{
1593
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1594
+
int ret;
1595
+
1596
+
ret = geni_icc_enable(&port->se);
1597
+
if (ret)
1598
+
return ret;
1599
+
1600
+
ret = geni_se_resources_on(&port->se);
1601
+
if (ret) {
1602
+
geni_icc_disable(&port->se);
1603
+
return ret;
1604
+
}
1605
+
1606
+
if (port->clk_rate)
1607
+
dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1608
+
1609
+
return 0;
1610
+
}
1611
+
1612
+
static int geni_serial_resources_off(struct uart_port *uport)
1613
+
{
1614
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1615
+
int ret;
1616
+
1617
+
dev_pm_opp_set_rate(uport->dev, 0);
1618
+
ret = geni_se_resources_off(&port->se);
1619
+
if (ret)
1620
+
return ret;
1621
+
1622
+
geni_icc_disable(&port->se);
1623
+
1624
+
return 0;
1625
+
}
1626
+
1627
+
static int geni_serial_resource_state(struct uart_port *uport, bool power_on)
1628
+
{
1629
+
return power_on ? geni_serial_resources_on(uport) : geni_serial_resources_off(uport);
1630
+
}
1631
+
1632
+
static int geni_serial_pwr_init(struct uart_port *uport)
1633
+
{
1634
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1635
+
int ret;
1636
+
1637
+
ret = dev_pm_domain_attach_list(port->se.dev,
1638
+
&port->dev_data->pd_data, &port->pd_list);
1639
+
if (ret <= 0)
1640
+
return -EINVAL;
1641
+
1642
+
return 0;
1643
+
}
1644
+
1645
+
static int geni_serial_resource_init(struct uart_port *uport)
1646
+
{
1647
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
1648
+
int ret;
1649
+
1650
+
port->se.clk = devm_clk_get(port->se.dev, "se");
1651
+
if (IS_ERR(port->se.clk)) {
1652
+
ret = PTR_ERR(port->se.clk);
1653
+
dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret);
1654
+
return ret;
1655
+
}
1656
+
1657
+
ret = geni_icc_get(&port->se, NULL);
1658
+
if (ret)
1659
+
return ret;
1660
+
1661
+
port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1662
+
port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1663
+
1664
+
/* Set BW for register access */
1665
+
ret = geni_icc_set_bw(&port->se);
1666
+
if (ret)
1667
+
return ret;
1668
+
1669
+
ret = devm_pm_opp_set_clkname(port->se.dev, "se");
1670
+
if (ret)
1671
+
return ret;
1672
+
1673
+
/* OPP table is optional */
1674
+
ret = devm_pm_opp_of_add_table(port->se.dev);
1675
+
if (ret && ret != -ENODEV) {
1676
+
dev_err(port->se.dev, "invalid OPP table in device tree\n");
1677
+
return ret;
1678
+
}
1679
+
1680
+
return 0;
1681
+
}
1682
+
1678
1683
static void qcom_geni_serial_pm(struct uart_port *uport,
1679
1684
unsigned int new_state, unsigned int old_state)
1680
1685
{
1681
-
struct qcom_geni_serial_port *port = to_dev_port(uport);
1682
1686
1683
1687
/* If we've never been called, treat it as off */
1684
1688
if (old_state == UART_PM_STATE_UNDEFINED)
1685
1689
old_state = UART_PM_STATE_OFF;
1686
1690
1687
-
if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1688
-
geni_icc_enable(&port->se);
1689
-
if (port->clk_rate)
1690
-
dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1691
-
geni_se_resources_on(&port->se);
1692
-
} else if (new_state == UART_PM_STATE_OFF &&
1693
-
old_state == UART_PM_STATE_ON) {
1694
-
geni_se_resources_off(&port->se);
1695
-
dev_pm_opp_set_rate(uport->dev, 0);
1696
-
geni_icc_disable(&port->se);
1697
-
}
1691
+
if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1692
+
pm_runtime_resume_and_get(uport->dev);
1693
+
else if (new_state == UART_PM_STATE_OFF &&
1694
+
old_state == UART_PM_STATE_ON)
1695
+
pm_runtime_put_sync(uport->dev);
1696
+
1697
+
}
1698
+
1699
+
/**
1700
+
* qcom_geni_rs485_config - Configure RS485 settings for the UART port
1701
+
* @uport: Pointer to the UART port structure
1702
+
* @termios: Pointer to the termios structure
1703
+
* @rs485: Pointer to the RS485 configuration structure
1704
+
* This function configures the RTS (Request to Send) pin behavior for RS485 mode.
1705
+
* When RS485 mode is enabled, the RTS pin is kept in default ACTIVE HIGH state.
1706
+
* Return: Always returns 0.
1707
+
*/
1708
+
1709
+
static int qcom_geni_rs485_config(struct uart_port *uport,
1710
+
struct ktermios *termios, struct serial_rs485 *rs485)
1711
+
{
1712
+
qcom_geni_set_rs485_mode(uport, SER_RS485_ENABLED);
1713
+
1714
+
return 0;
1698
1715
}
1699
1716
1700
1717
static const struct uart_ops qcom_geni_console_pops = {
···
1881
1690
port->dev_data = data;
1882
1691
port->se.dev = &pdev->dev;
1883
1692
port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1884
-
port->se.clk = devm_clk_get(&pdev->dev, "se");
1885
-
if (IS_ERR(port->se.clk)) {
1886
-
ret = PTR_ERR(port->se.clk);
1887
-
dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1693
+
1694
+
ret = port->dev_data->resources_init(uport);
1695
+
if (ret)
1888
1696
return ret;
1889
-
}
1890
1697
1891
1698
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1892
-
if (!res)
1893
-
return -EINVAL;
1699
+
if (!res) {
1700
+
ret = -EINVAL;
1701
+
goto error;
1702
+
}
1703
+
1894
1704
uport->mapbase = res->start;
1895
1705
1706
+
uport->rs485_config = qcom_geni_rs485_config;
1707
+
uport->rs485_supported = qcom_geni_rs485_supported;
1896
1708
port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1897
1709
port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1898
1710
port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
···
1903
1709
if (!data->console) {
1904
1710
port->rx_buf = devm_kzalloc(uport->dev,
1905
1711
DMA_RX_BUF_SIZE, GFP_KERNEL);
1906
-
if (!port->rx_buf)
1907
-
return -ENOMEM;
1712
+
if (!port->rx_buf) {
1713
+
ret = -ENOMEM;
1714
+
goto error;
1715
+
}
1908
1716
}
1909
-
1910
-
ret = geni_icc_get(&port->se, NULL);
1911
-
if (ret)
1912
-
return ret;
1913
-
port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1914
-
port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1915
-
1916
-
/* Set BW for register access */
1917
-
ret = geni_icc_set_bw(&port->se);
1918
-
if (ret)
1919
-
return ret;
1920
1717
1921
1718
port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1922
1719
"qcom_geni_serial_%s%d",
1923
1720
uart_console(uport) ? "console" : "uart", uport->line);
1924
-
if (!port->name)
1925
-
return -ENOMEM;
1721
+
if (!port->name) {
1722
+
ret = -ENOMEM;
1723
+
goto error;
1724
+
}
1926
1725
1927
1726
irq = platform_get_irq(pdev, 0);
1928
-
if (irq < 0)
1929
-
return irq;
1727
+
if (irq < 0) {
1728
+
ret = irq;
1729
+
goto error;
1730
+
}
1731
+
1930
1732
uport->irq = irq;
1931
1733
uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1932
1734
···
1935
1745
if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1936
1746
port->cts_rts_swap = true;
1937
1747
1938
-
ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1939
-
if (ret)
1940
-
return ret;
1941
-
/* OPP table is optional */
1942
-
ret = devm_pm_opp_of_add_table(&pdev->dev);
1943
-
if (ret && ret != -ENODEV) {
1944
-
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1945
-
return ret;
1946
-
}
1947
-
1948
1748
port->private_data.drv = drv;
1949
1749
uport->private_data = &port->private_data;
1950
1750
platform_set_drvdata(pdev, port);
···
1944
1764
IRQF_TRIGGER_HIGH, port->name, uport);
1945
1765
if (ret) {
1946
1766
dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1947
-
return ret;
1767
+
goto error;
1948
1768
}
1769
+
1770
+
ret = uart_get_rs485_mode(uport);
1771
+
if (ret)
1772
+
return ret;
1773
+
1774
+
devm_pm_runtime_enable(port->se.dev);
1949
1775
1950
1776
ret = uart_add_one_port(drv, uport);
1951
1777
if (ret)
1952
-
return ret;
1778
+
goto error;
1953
1779
1954
1780
if (port->wakeup_irq > 0) {
1955
1781
device_init_wakeup(&pdev->dev, true);
···
1965
1779
device_init_wakeup(&pdev->dev, false);
1966
1780
ida_free(&port_ida, uport->line);
1967
1781
uart_remove_one_port(drv, uport);
1968
-
return ret;
1782
+
goto error;
1969
1783
}
1970
1784
}
1971
1785
1972
1786
return 0;
1787
+
1788
+
error:
1789
+
dev_pm_domain_detach_list(port->pd_list);
1790
+
return ret;
1973
1791
}
1974
1792
1975
1793
static void qcom_geni_serial_remove(struct platform_device *pdev)
···
1986
1796
device_init_wakeup(&pdev->dev, false);
1987
1797
ida_free(&port_ida, uport->line);
1988
1798
uart_remove_one_port(drv, &port->uport);
1799
+
dev_pm_domain_detach_list(port->pd_list);
1800
+
}
1801
+
1802
+
static int __maybe_unused qcom_geni_serial_runtime_suspend(struct device *dev)
1803
+
{
1804
+
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1805
+
struct uart_port *uport = &port->uport;
1806
+
int ret = 0;
1807
+
1808
+
if (port->dev_data->power_state)
1809
+
ret = port->dev_data->power_state(uport, false);
1810
+
1811
+
return ret;
1812
+
}
1813
+
1814
+
static int __maybe_unused qcom_geni_serial_runtime_resume(struct device *dev)
1815
+
{
1816
+
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1817
+
struct uart_port *uport = &port->uport;
1818
+
int ret = 0;
1819
+
1820
+
if (port->dev_data->power_state)
1821
+
ret = port->dev_data->power_state(uport, true);
1822
+
1823
+
return ret;
1989
1824
}
1990
1825
1991
1826
static int qcom_geni_serial_suspend(struct device *dev)
···
2048
1833
static const struct qcom_geni_device_data qcom_geni_console_data = {
2049
1834
.console = true,
2050
1835
.mode = GENI_SE_FIFO,
1836
+
.resources_init = geni_serial_resource_init,
1837
+
.set_rate = geni_serial_set_rate,
1838
+
.power_state = geni_serial_resource_state,
2051
1839
};
2052
1840
2053
1841
static const struct qcom_geni_device_data qcom_geni_uart_data = {
2054
1842
.console = false,
2055
1843
.mode = GENI_SE_DMA,
1844
+
.resources_init = geni_serial_resource_init,
1845
+
.set_rate = geni_serial_set_rate,
1846
+
.power_state = geni_serial_resource_state,
1847
+
};
1848
+
1849
+
static const struct qcom_geni_device_data sa8255p_qcom_geni_console_data = {
1850
+
.console = true,
1851
+
.mode = GENI_SE_FIFO,
1852
+
.pd_data = {
1853
+
.pd_flags = PD_FLAG_DEV_LINK_ON,
1854
+
.pd_names = (const char*[]) { "power", "perf" },
1855
+
.num_pd_names = 2,
1856
+
},
1857
+
.resources_init = geni_serial_pwr_init,
1858
+
.set_rate = geni_serial_set_level,
1859
+
};
1860
+
1861
+
static const struct qcom_geni_device_data sa8255p_qcom_geni_uart_data = {
1862
+
.console = false,
1863
+
.mode = GENI_SE_DMA,
1864
+
.pd_data = {
1865
+
.pd_flags = PD_FLAG_DEV_LINK_ON,
1866
+
.pd_names = (const char*[]) { "power", "perf" },
1867
+
.num_pd_names = 2,
1868
+
},
1869
+
.resources_init = geni_serial_pwr_init,
1870
+
.set_rate = geni_serial_set_level,
2056
1871
};
2057
1872
2058
1873
static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1874
+
SET_RUNTIME_PM_OPS(qcom_geni_serial_runtime_suspend,
1875
+
qcom_geni_serial_runtime_resume, NULL)
2059
1876
SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_suspend, qcom_geni_serial_resume)
2060
1877
};
2061
1878
···
2097
1850
.data = &qcom_geni_console_data,
2098
1851
},
2099
1852
{
1853
+
.compatible = "qcom,sa8255p-geni-debug-uart",
1854
+
.data = &sa8255p_qcom_geni_console_data,
1855
+
},
1856
+
{
2100
1857
.compatible = "qcom,geni-uart",
2101
1858
.data = &qcom_geni_uart_data,
1859
+
},
1860
+
{
1861
+
.compatible = "qcom,sa8255p-geni-uart",
1862
+
.data = &sa8255p_qcom_geni_uart_data,
2102
1863
},
2103
1864
{}
2104
1865
};
+480
drivers/tty/serial/rsci.c
+480
drivers/tty/serial/rsci.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2025 Renesas Electronics Corp.
4
+
*/
5
+
6
+
#include <linux/bitfield.h>
7
+
#include <linux/bitops.h>
8
+
#include <linux/io.h>
9
+
#include <linux/iopoll.h>
10
+
#include <linux/module.h>
11
+
#include <linux/serial_core.h>
12
+
#include <linux/serial_sci.h>
13
+
#include <linux/tty_flip.h>
14
+
#include "rsci.h"
15
+
16
+
MODULE_IMPORT_NS("SH_SCI");
17
+
18
+
/* RSCI registers */
19
+
#define RDR 0x00
20
+
#define TDR 0x04
21
+
#define CCR0 0x08
22
+
#define CCR1 0x0C
23
+
#define CCR2 0x10
24
+
#define CCR3 0x14
25
+
#define CCR4 0x18
26
+
#define FCR 0x24
27
+
#define DCR 0x30
28
+
#define CSR 0x48
29
+
#define FRSR 0x50
30
+
#define FTSR 0x54
31
+
#define CFCLR 0x68
32
+
#define FFCLR 0x70
33
+
34
+
/* RDR (Receive Data Register) */
35
+
#define RDR_FFER BIT(12) /* FIFO Framing Error */
36
+
#define RDR_FPER BIT(11) /* FIFO Parity Error */
37
+
#define RDR_RDAT_MSK GENMASK(8, 0)
38
+
39
+
/* TDR (Transmit Data Register) */
40
+
#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */
41
+
#define TDR_TDAT_9BIT_LSHIFT 0
42
+
#define TDR_TDAT_9BIT_VAL 0x1FF
43
+
#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT)
44
+
45
+
/* CCR0 (Common Control Register 0) */
46
+
#define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */
47
+
#define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */
48
+
#define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */
49
+
#define CCR0_RIE BIT(16) /* Receive Interrupt Enable */
50
+
#define CCR0_IDSEL BIT(10) /* ID Frame Select */
51
+
#define CCR0_DCME BIT(9) /* Data Compare Match Enable */
52
+
#define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */
53
+
#define CCR0_TE BIT(4) /* Transmit Enable */
54
+
#define CCR0_RE BIT(0) /* Receive Enable */
55
+
56
+
/* CCR1 (Common Control Register 1) */
57
+
#define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */
58
+
#define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */
59
+
#define CCR1_SPLP BIT(16) /* Loopback Control */
60
+
#define CCR1_RINV BIT(13) /* RxD invert */
61
+
#define CCR1_TINV BIT(12) /* TxD invert */
62
+
#define CCR1_PM BIT(9) /* Parity Mode */
63
+
#define CCR1_PE BIT(8) /* Parity Enable */
64
+
#define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */
65
+
#define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */
66
+
#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */
67
+
#define CCR1_CTSE BIT(0) /* CTS Enable */
68
+
69
+
/* FCR (FIFO Control Register) */
70
+
#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */
71
+
#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */
72
+
#define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */
73
+
#define FCR_RTRG4_0 GENMASK(20, 16)
74
+
#define FCR_TTRG GENMASK(12, 8)
75
+
76
+
/* CSR (Common Status Register) */
77
+
#define CSR_RDRF BIT(31) /* Receive Data Full */
78
+
#define CSR_TEND BIT(30) /* Transmit End Flag */
79
+
#define CSR_TDRE BIT(29) /* Transmit Data Empty */
80
+
#define CSR_FER BIT(28) /* Framing Error */
81
+
#define CSR_PER BIT(27) /* Parity Error */
82
+
#define CSR_MFF BIT(26) /* Mode Fault Error */
83
+
#define CSR_ORER BIT(24) /* Overrun Error */
84
+
#define CSR_DFER BIT(18) /* Data Compare Match Framing Error */
85
+
#define CSR_DPER BIT(17) /* Data Compare Match Parity Error */
86
+
#define CSR_DCMF BIT(16) /* Data Compare Match */
87
+
#define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */
88
+
#define CSR_ERS BIT(4) /* Error Signal Status */
89
+
90
+
#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
91
+
#define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear)
92
+
93
+
#define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER)
94
+
95
+
#define RSCI_RDxF_CLEAR (CFCLR_RDRFC)
96
+
#define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC)
97
+
#define RSCI_TDxE_CLEAR (CFCLR_TDREC)
98
+
#define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC)
99
+
100
+
/* FRSR (FIFO Receive Status Register) */
101
+
#define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */
102
+
#define FRSR_DR BIT(0) /* Receive Data Ready */
103
+
104
+
/* CFCLR (Common Flag CLear Register) */
105
+
#define CFCLR_RDRFC BIT(31) /* RDRF Clear */
106
+
#define CFCLR_TDREC BIT(29) /* TDRE Clear */
107
+
#define CFCLR_FERC BIT(28) /* FER Clear */
108
+
#define CFCLR_PERC BIT(27) /* PER Clear */
109
+
#define CFCLR_MFFC BIT(26) /* MFF Clear */
110
+
#define CFCLR_ORERC BIT(24) /* ORER Clear */
111
+
#define CFCLR_DFERC BIT(18) /* DFER Clear */
112
+
#define CFCLR_DPERC BIT(17) /* DPER Clear */
113
+
#define CFCLR_DCMFC BIT(16) /* DCMF Clear */
114
+
#define CFCLR_ERSC BIT(4) /* ERS Clear */
115
+
#define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \
116
+
CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \
117
+
CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC)
118
+
119
+
/* FFCLR (FIFO Flag CLear Register) */
120
+
#define FFCLR_DRC BIT(0) /* DR Clear */
121
+
122
+
#define DCR_DEPOL BIT(0)
123
+
124
+
static u32 rsci_serial_in(struct uart_port *p, int offset)
125
+
{
126
+
return readl(p->membase + offset);
127
+
}
128
+
129
+
static void rsci_serial_out(struct uart_port *p, int offset, int value)
130
+
{
131
+
writel(value, p->membase + offset);
132
+
}
133
+
134
+
static void rsci_clear_DRxC(struct uart_port *port)
135
+
{
136
+
rsci_serial_out(port, CFCLR, CFCLR_RDRFC);
137
+
rsci_serial_out(port, FFCLR, FFCLR_DRC);
138
+
}
139
+
140
+
static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask)
141
+
{
142
+
rsci_serial_out(port, CFCLR, mask);
143
+
}
144
+
145
+
static void rsci_start_rx(struct uart_port *port)
146
+
{
147
+
unsigned int ctrl;
148
+
149
+
ctrl = rsci_serial_in(port, CCR0);
150
+
ctrl |= CCR0_RIE;
151
+
rsci_serial_out(port, CCR0, ctrl);
152
+
}
153
+
154
+
static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
155
+
const struct ktermios *old)
156
+
{
157
+
struct sci_port *s = to_sci_port(port);
158
+
unsigned long flags;
159
+
160
+
sci_port_enable(s);
161
+
uart_port_lock_irqsave(port, &flags);
162
+
163
+
/* For now, only RX enabling is supported */
164
+
if (termios->c_cflag & CREAD)
165
+
rsci_start_rx(port);
166
+
167
+
uart_port_unlock_irqrestore(port, flags);
168
+
sci_port_disable(s);
169
+
}
170
+
171
+
static int rsci_txfill(struct uart_port *port)
172
+
{
173
+
return rsci_serial_in(port, FTSR);
174
+
}
175
+
176
+
static int rsci_rxfill(struct uart_port *port)
177
+
{
178
+
u32 val = rsci_serial_in(port, FRSR);
179
+
180
+
return FIELD_GET(FRSR_R5_0, val);
181
+
}
182
+
183
+
static unsigned int rsci_tx_empty(struct uart_port *port)
184
+
{
185
+
unsigned int status = rsci_serial_in(port, CSR);
186
+
unsigned int in_tx_fifo = rsci_txfill(port);
187
+
188
+
return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0;
189
+
}
190
+
191
+
static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
192
+
{
193
+
/* Not supported yet */
194
+
}
195
+
196
+
static unsigned int rsci_get_mctrl(struct uart_port *port)
197
+
{
198
+
/* Not supported yet */
199
+
return 0;
200
+
}
201
+
202
+
static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
203
+
{
204
+
rsci_serial_out(port, CFCLR, mask);
205
+
}
206
+
207
+
static void rsci_start_tx(struct uart_port *port)
208
+
{
209
+
struct sci_port *sp = to_sci_port(port);
210
+
u32 ctrl;
211
+
212
+
if (sp->chan_tx)
213
+
return;
214
+
215
+
/*
216
+
* TE (Transmit Enable) must be set after setting TIE
217
+
* (Transmit Interrupt Enable) or in the same instruction
218
+
* to start the transmit process.
219
+
*/
220
+
ctrl = rsci_serial_in(port, CCR0);
221
+
ctrl |= CCR0_TIE | CCR0_TE;
222
+
rsci_serial_out(port, CCR0, ctrl);
223
+
}
224
+
225
+
static void rsci_stop_tx(struct uart_port *port)
226
+
{
227
+
u32 ctrl;
228
+
229
+
ctrl = rsci_serial_in(port, CCR0);
230
+
ctrl &= ~CCR0_TIE;
231
+
rsci_serial_out(port, CCR0, ctrl);
232
+
}
233
+
234
+
static void rsci_stop_rx(struct uart_port *port)
235
+
{
236
+
u32 ctrl;
237
+
238
+
ctrl = rsci_serial_in(port, CCR0);
239
+
ctrl &= ~CCR0_RIE;
240
+
rsci_serial_out(port, CCR0, ctrl);
241
+
}
242
+
243
+
static int rsci_txroom(struct uart_port *port)
244
+
{
245
+
return port->fifosize - rsci_txfill(port);
246
+
}
247
+
248
+
static void rsci_transmit_chars(struct uart_port *port)
249
+
{
250
+
unsigned int stopped = uart_tx_stopped(port);
251
+
struct tty_port *tport = &port->state->port;
252
+
u32 status, ctrl;
253
+
int count;
254
+
255
+
status = rsci_serial_in(port, CSR);
256
+
if (!(status & CSR_TDRE)) {
257
+
ctrl = rsci_serial_in(port, CCR0);
258
+
if (kfifo_is_empty(&tport->xmit_fifo))
259
+
ctrl &= ~CCR0_TIE;
260
+
else
261
+
ctrl |= CCR0_TIE;
262
+
rsci_serial_out(port, CCR0, ctrl);
263
+
return;
264
+
}
265
+
266
+
count = rsci_txroom(port);
267
+
268
+
do {
269
+
unsigned char c;
270
+
271
+
if (port->x_char) {
272
+
c = port->x_char;
273
+
port->x_char = 0;
274
+
} else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
275
+
break;
276
+
}
277
+
278
+
rsci_clear_CFC(port, CFCLR_TDREC);
279
+
rsci_serial_out(port, TDR, c);
280
+
281
+
port->icount.tx++;
282
+
} while (--count > 0);
283
+
284
+
if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
285
+
uart_write_wakeup(port);
286
+
287
+
if (kfifo_is_empty(&tport->xmit_fifo)) {
288
+
ctrl = rsci_serial_in(port, CCR0);
289
+
ctrl &= ~CCR0_TIE;
290
+
ctrl |= CCR0_TEIE;
291
+
rsci_serial_out(port, CCR0, ctrl);
292
+
}
293
+
}
294
+
295
+
static void rsci_receive_chars(struct uart_port *port)
296
+
{
297
+
struct tty_port *tport = &port->state->port;
298
+
u32 rdat, status, frsr_status = 0;
299
+
int i, count, copied = 0;
300
+
unsigned char flag;
301
+
302
+
status = rsci_serial_in(port, CSR);
303
+
frsr_status = rsci_serial_in(port, FRSR);
304
+
305
+
if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR))
306
+
return;
307
+
308
+
while (1) {
309
+
/* Don't copy more bytes than there is room for in the buffer */
310
+
count = tty_buffer_request_room(tport, rsci_rxfill(port));
311
+
312
+
/* If for any reason we can't copy more data, we're done! */
313
+
if (count == 0)
314
+
break;
315
+
316
+
for (i = 0; i < count; i++) {
317
+
char c;
318
+
319
+
rdat = rsci_serial_in(port, RDR);
320
+
/* 9-bits data is not supported yet */
321
+
c = rdat & RDR_RDAT_MSK;
322
+
323
+
if (uart_handle_sysrq_char(port, c)) {
324
+
count--;
325
+
i--;
326
+
continue;
327
+
}
328
+
329
+
/* Store data and status.
330
+
* Non FIFO mode is not supported
331
+
*/
332
+
if (rdat & RDR_FFER) {
333
+
flag = TTY_FRAME;
334
+
port->icount.frame++;
335
+
} else if (rdat & RDR_FPER) {
336
+
flag = TTY_PARITY;
337
+
port->icount.parity++;
338
+
} else {
339
+
flag = TTY_NORMAL;
340
+
}
341
+
342
+
tty_insert_flip_char(tport, c, flag);
343
+
}
344
+
345
+
rsci_serial_in(port, CSR); /* dummy read */
346
+
rsci_clear_DRxC(port);
347
+
348
+
copied += count;
349
+
port->icount.rx += count;
350
+
}
351
+
352
+
if (copied) {
353
+
/* Tell the rest of the system the news. New characters! */
354
+
tty_flip_buffer_push(tport);
355
+
} else {
356
+
/* TTY buffers full; read from RX reg to prevent lockup */
357
+
rsci_serial_in(port, RDR);
358
+
rsci_serial_in(port, CSR); /* dummy read */
359
+
rsci_clear_DRxC(port);
360
+
}
361
+
}
362
+
363
+
static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
364
+
{
365
+
u32 status;
366
+
int ret;
367
+
368
+
ret = readl_relaxed_poll_timeout_atomic(port->membase + CSR, status,
369
+
(status & CSR_TDRE), 100,
370
+
USEC_PER_SEC);
371
+
if (ret != 0) {
372
+
dev_err(port->dev,
373
+
"Error while sending data in UART TX : %d\n", ret);
374
+
goto done;
375
+
}
376
+
rsci_serial_out(port, TDR, c);
377
+
done:
378
+
rsci_clear_SCxSR(port, CFCLR_TDREC);
379
+
}
380
+
381
+
static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
382
+
{
383
+
struct sci_port *s = to_sci_port(port);
384
+
u32 ctrl_temp =
385
+
s->params->param_bits->rxtx_enable | CCR0_TIE |
386
+
s->hscif_tot;
387
+
rsci_serial_out(port, CCR0, ctrl_temp);
388
+
}
389
+
390
+
static const char *rsci_type(struct uart_port *port)
391
+
{
392
+
return "rsci";
393
+
}
394
+
395
+
static size_t rsci_suspend_regs_size(void)
396
+
{
397
+
return 0;
398
+
}
399
+
400
+
static void rsci_shutdown_complete(struct uart_port *port)
401
+
{
402
+
/*
403
+
* Stop RX and TX, disable related interrupts, keep clock source
404
+
*/
405
+
rsci_serial_out(port, CCR0, 0);
406
+
}
407
+
408
+
static const struct sci_common_regs rsci_common_regs = {
409
+
.status = CSR,
410
+
.control = CCR0,
411
+
};
412
+
413
+
static const struct sci_port_params_bits rsci_port_param_bits = {
414
+
.rxtx_enable = CCR0_RE | CCR0_TE,
415
+
.te_clear = CCR0_TE | CCR0_TEIE,
416
+
.poll_sent_bits = CSR_TDRE | CSR_TEND,
417
+
};
418
+
419
+
static const struct sci_port_params rsci_port_params = {
420
+
.fifosize = 16,
421
+
.overrun_reg = CSR,
422
+
.overrun_mask = CSR_ORER,
423
+
.sampling_rate_mask = SCI_SR(32),
424
+
.error_mask = RSCI_DEFAULT_ERROR_MASK,
425
+
.error_clear = RSCI_ERROR_CLEAR,
426
+
.param_bits = &rsci_port_param_bits,
427
+
.common_regs = &rsci_common_regs,
428
+
};
429
+
430
+
static const struct uart_ops rsci_uart_ops = {
431
+
.tx_empty = rsci_tx_empty,
432
+
.set_mctrl = rsci_set_mctrl,
433
+
.get_mctrl = rsci_get_mctrl,
434
+
.start_tx = rsci_start_tx,
435
+
.stop_tx = rsci_stop_tx,
436
+
.stop_rx = rsci_stop_rx,
437
+
.startup = sci_startup,
438
+
.shutdown = sci_shutdown,
439
+
.set_termios = rsci_set_termios,
440
+
.pm = sci_pm,
441
+
.type = rsci_type,
442
+
.release_port = sci_release_port,
443
+
.request_port = sci_request_port,
444
+
.config_port = sci_config_port,
445
+
.verify_port = sci_verify_port,
446
+
};
447
+
448
+
static const struct sci_port_ops rsci_port_ops = {
449
+
.read_reg = rsci_serial_in,
450
+
.write_reg = rsci_serial_out,
451
+
.clear_SCxSR = rsci_clear_SCxSR,
452
+
.transmit_chars = rsci_transmit_chars,
453
+
.receive_chars = rsci_receive_chars,
454
+
.poll_put_char = rsci_poll_put_char,
455
+
.prepare_console_write = rsci_prepare_console_write,
456
+
.suspend_regs_size = rsci_suspend_regs_size,
457
+
.shutdown_complete = rsci_shutdown_complete,
458
+
};
459
+
460
+
struct sci_of_data of_sci_rsci_data = {
461
+
.type = SCI_PORT_RSCI,
462
+
.ops = &rsci_port_ops,
463
+
.uart_ops = &rsci_uart_ops,
464
+
.params = &rsci_port_params,
465
+
};
466
+
467
+
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
468
+
469
+
static int __init rsci_early_console_setup(struct earlycon_device *device,
470
+
const char *opt)
471
+
{
472
+
return scix_early_console_setup(device, &of_sci_rsci_data);
473
+
}
474
+
475
+
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
476
+
477
+
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
478
+
479
+
MODULE_LICENSE("GPL");
480
+
MODULE_DESCRIPTION("RSCI serial driver");
+10
drivers/tty/serial/rsci.h
+10
drivers/tty/serial/rsci.h
+23
-55
drivers/tty/serial/serial_core.c
+23
-55
drivers/tty/serial/serial_core.c
···
1337
1337
if (!port->rs485_supported.delay_rts_before_send) {
1338
1338
if (rs485->delay_rts_before_send) {
1339
1339
dev_warn_ratelimited(port->dev,
1340
-
"%s (%d): RTS delay before sending not supported\n",
1340
+
"%s (%u): RTS delay before sending not supported\n",
1341
1341
port->name, port->line);
1342
1342
}
1343
1343
rs485->delay_rts_before_send = 0;
1344
1344
} else if (rs485->delay_rts_before_send > RS485_MAX_RTS_DELAY) {
1345
1345
rs485->delay_rts_before_send = RS485_MAX_RTS_DELAY;
1346
1346
dev_warn_ratelimited(port->dev,
1347
-
"%s (%d): RTS delay before sending clamped to %u ms\n",
1347
+
"%s (%u): RTS delay before sending clamped to %u ms\n",
1348
1348
port->name, port->line, rs485->delay_rts_before_send);
1349
1349
}
1350
1350
1351
1351
if (!port->rs485_supported.delay_rts_after_send) {
1352
1352
if (rs485->delay_rts_after_send) {
1353
1353
dev_warn_ratelimited(port->dev,
1354
-
"%s (%d): RTS delay after sending not supported\n",
1354
+
"%s (%u): RTS delay after sending not supported\n",
1355
1355
port->name, port->line);
1356
1356
}
1357
1357
rs485->delay_rts_after_send = 0;
1358
1358
} else if (rs485->delay_rts_after_send > RS485_MAX_RTS_DELAY) {
1359
1359
rs485->delay_rts_after_send = RS485_MAX_RTS_DELAY;
1360
1360
dev_warn_ratelimited(port->dev,
1361
-
"%s (%d): RTS delay after sending clamped to %u ms\n",
1361
+
"%s (%u): RTS delay after sending clamped to %u ms\n",
1362
1362
port->name, port->line, rs485->delay_rts_after_send);
1363
1363
}
1364
1364
}
···
1388
1388
rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1389
1389
1390
1390
dev_warn_ratelimited(port->dev,
1391
-
"%s (%d): invalid RTS setting, using RTS_ON_SEND instead\n",
1391
+
"%s (%u): invalid RTS setting, using RTS_ON_SEND instead\n",
1392
1392
port->name, port->line);
1393
1393
} else {
1394
1394
rs485->flags |= SER_RS485_RTS_AFTER_SEND;
1395
1395
rs485->flags &= ~SER_RS485_RTS_ON_SEND;
1396
1396
1397
1397
dev_warn_ratelimited(port->dev,
1398
-
"%s (%d): invalid RTS setting, using RTS_AFTER_SEND instead\n",
1398
+
"%s (%u): invalid RTS setting, using RTS_AFTER_SEND instead\n",
1399
1399
port->name, port->line);
1400
1400
}
1401
1401
}
···
1834
1834
1835
1835
expire = jiffies + timeout;
1836
1836
1837
-
pr_debug("uart_wait_until_sent(%d), jiffies=%lu, expire=%lu...\n",
1837
+
pr_debug("uart_wait_until_sent(%u), jiffies=%lu, expire=%lu...\n",
1838
1838
port->line, jiffies, expire);
1839
1839
1840
1840
/*
···
2028
2028
return;
2029
2029
2030
2030
mmio = uport->iotype >= UPIO_MEM;
2031
-
seq_printf(m, "%d: uart:%s %s%08llX irq:%d",
2031
+
seq_printf(m, "%u: uart:%s %s%08llX irq:%u",
2032
2032
uport->line, uart_type(uport),
2033
2033
mmio ? "mmio:0x" : "port:",
2034
2034
mmio ? (unsigned long long)uport->mapbase
···
2050
2050
if (pm_state != UART_PM_STATE_ON)
2051
2051
uart_change_pm(state, pm_state);
2052
2052
2053
-
seq_printf(m, " tx:%d rx:%d",
2053
+
seq_printf(m, " tx:%u rx:%u",
2054
2054
uport->icount.tx, uport->icount.rx);
2055
2055
if (uport->icount.frame)
2056
-
seq_printf(m, " fe:%d", uport->icount.frame);
2056
+
seq_printf(m, " fe:%u", uport->icount.frame);
2057
2057
if (uport->icount.parity)
2058
-
seq_printf(m, " pe:%d", uport->icount.parity);
2058
+
seq_printf(m, " pe:%u", uport->icount.parity);
2059
2059
if (uport->icount.brk)
2060
-
seq_printf(m, " brk:%d", uport->icount.brk);
2060
+
seq_printf(m, " brk:%u", uport->icount.brk);
2061
2061
if (uport->icount.overrun)
2062
-
seq_printf(m, " oe:%d", uport->icount.overrun);
2062
+
seq_printf(m, " oe:%u", uport->icount.overrun);
2063
2063
if (uport->icount.buf_overrun)
2064
-
seq_printf(m, " bo:%d", uport->icount.buf_overrun);
2064
+
seq_printf(m, " bo:%u", uport->icount.buf_overrun);
2065
2065
2066
2066
#define INFOBIT(bit, str) \
2067
2067
if (uport->mctrl & (bit)) \
···
2130
2130
}
2131
2131
}
2132
2132
EXPORT_SYMBOL_GPL(uart_console_write);
2133
-
2134
-
/**
2135
-
* uart_get_console - get uart port for console
2136
-
* @ports: ports to search in
2137
-
* @nr: number of @ports
2138
-
* @co: console to search for
2139
-
* Returns: uart_port for the console @co
2140
-
*
2141
-
* Check whether an invalid uart number has been specified (as @co->index), and
2142
-
* if so, search for the first available port that does have console support.
2143
-
*/
2144
-
struct uart_port * __init
2145
-
uart_get_console(struct uart_port *ports, int nr, struct console *co)
2146
-
{
2147
-
int idx = co->index;
2148
-
2149
-
if (idx < 0 || idx >= nr || (ports[idx].iobase == 0 &&
2150
-
ports[idx].membase == NULL))
2151
-
for (idx = 0; idx < nr; idx++)
2152
-
if (ports[idx].iobase != 0 ||
2153
-
ports[idx].membase != NULL)
2154
-
break;
2155
-
2156
-
co->index = idx;
2157
-
2158
-
return ports + idx;
2159
-
}
2160
2133
2161
2134
/**
2162
2135
* uart_parse_earlycon - Parse earlycon options
···
2526
2553
break;
2527
2554
}
2528
2555
2529
-
pr_info("%s%s%s at %s (irq = %d, base_baud = %d) is a %s\n",
2556
+
pr_info("%s%s%s at %s (irq = %u, base_baud = %u) is a %s\n",
2530
2557
port->dev ? dev_name(port->dev) : "",
2531
2558
port->dev ? ": " : "",
2532
2559
port->name,
···
2534
2561
2535
2562
/* The magic multiplier feature is a bit obscure, so report it too. */
2536
2563
if (port->flags & UPF_MAGIC_MULTIPLIER)
2537
-
pr_info("%s%s%s extra baud rates supported: %d, %d",
2564
+
pr_info("%s%s%s extra baud rates supported: %u, %u",
2538
2565
port->dev ? dev_name(port->dev) : "",
2539
2566
port->dev ? ": " : "",
2540
2567
port->name,
···
2933
2960
struct tty_port *port = dev_get_drvdata(dev);
2934
2961
2935
2962
uart_get_info(port, &tmp);
2936
-
return sprintf(buf, "%d\n", tmp.close_delay);
2963
+
return sprintf(buf, "%u\n", tmp.close_delay);
2937
2964
}
2938
2965
2939
2966
static ssize_t closing_wait_show(struct device *dev,
···
2943
2970
struct tty_port *port = dev_get_drvdata(dev);
2944
2971
2945
2972
uart_get_info(port, &tmp);
2946
-
return sprintf(buf, "%d\n", tmp.closing_wait);
2973
+
return sprintf(buf, "%u\n", tmp.closing_wait);
2947
2974
}
2948
2975
2949
2976
static ssize_t custom_divisor_show(struct device *dev,
···
2963
2990
struct tty_port *port = dev_get_drvdata(dev);
2964
2991
2965
2992
uart_get_info(port, &tmp);
2966
-
return sprintf(buf, "%d\n", tmp.io_type);
2993
+
return sprintf(buf, "%u\n", tmp.io_type);
2967
2994
}
2968
2995
2969
2996
static ssize_t iomem_base_show(struct device *dev,
···
2983
3010
struct tty_port *port = dev_get_drvdata(dev);
2984
3011
2985
3012
uart_get_info(port, &tmp);
2986
-
return sprintf(buf, "%d\n", tmp.iomem_reg_shift);
3013
+
return sprintf(buf, "%u\n", tmp.iomem_reg_shift);
2987
3014
}
2988
3015
2989
3016
static ssize_t console_show(struct device *dev,
···
3119
3146
state->pm_state = UART_PM_STATE_UNDEFINED;
3120
3147
uart_port_set_cons(uport, drv->cons);
3121
3148
uport->minor = drv->tty_driver->minor_start + uport->line;
3122
-
uport->name = kasprintf(GFP_KERNEL, "%s%d", drv->dev_name,
3149
+
uport->name = kasprintf(GFP_KERNEL, "%s%u", drv->dev_name,
3123
3150
drv->tty_driver->name_base + uport->line);
3124
3151
if (!uport->name)
3125
3152
return -ENOMEM;
···
3158
3185
device_set_wakeup_capable(tty_dev, 1);
3159
3186
} else {
3160
3187
uport->flags |= UPF_DEAD;
3161
-
dev_err(uport->dev, "Cannot register tty device on line %d\n",
3188
+
dev_err(uport->dev, "Cannot register tty device on line %u\n",
3162
3189
uport->line);
3163
3190
}
3164
3191
···
3182
3209
struct uart_state *state = drv->state + uport->line;
3183
3210
struct tty_port *port = &state->port;
3184
3211
struct uart_port *uart_port;
3185
-
struct tty_struct *tty;
3186
3212
3187
3213
mutex_lock(&port->mutex);
3188
3214
uart_port = uart_port_check(state);
···
3200
3228
*/
3201
3229
tty_port_unregister_device(port, drv->tty_driver, uport->line);
3202
3230
3203
-
tty = tty_port_tty_get(port);
3204
-
if (tty) {
3205
-
tty_vhangup(port->tty);
3206
-
tty_kref_put(tty);
3207
-
}
3231
+
tty_port_tty_vhangup(port);
3208
3232
3209
3233
/*
3210
3234
* If the port is used as a console, unregister it
+8
drivers/tty/serial/sh-sci-common.h
+8
drivers/tty/serial/sh-sci-common.h
···
5
5
6
6
#include <linux/serial_core.h>
7
7
8
+
/* Private port IDs */
9
+
enum SCI_PORT_TYPE {
10
+
SCI_PORT_RSCI = BIT(7) | 0,
11
+
};
12
+
8
13
enum SCI_CLKS {
9
14
SCI_FCK, /* Functional Clock */
10
15
SCI_SCK, /* Optional External Clock */
···
146
141
struct timer_list rx_fifo_timer;
147
142
int rx_fifo_timeout;
148
143
u16 hscif_tot;
144
+
145
+
u8 type;
146
+
u8 regtype;
149
147
150
148
const struct sci_port_ops *ops;
151
149
+139
-84
drivers/tty/serial/sh-sci.c
+139
-84
drivers/tty/serial/sh-sci.c
···
54
54
#include <asm/platform_early.h>
55
55
#endif
56
56
57
+
#include "rsci.h"
57
58
#include "serial_mctrl_gpio.h"
58
59
#include "sh-sci.h"
59
60
#include "sh-sci-common.h"
···
75
74
if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
76
75
77
76
#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
77
+
78
+
#define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))
78
79
79
80
static struct sci_port sci_ports[SCI_NPORTS];
80
81
static unsigned long sci_ports_in_use;
···
551
548
}
552
549
sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
553
550
}
551
+
EXPORT_SYMBOL_NS_GPL(sci_port_enable, "SH_SCI");
554
552
555
553
void sci_port_disable(struct sci_port *sci_port)
556
554
{
···
565
561
566
562
pm_runtime_put_sync(sci_port->port.dev);
567
563
}
564
+
EXPORT_SYMBOL_NS_GPL(sci_port_disable, "SH_SCI");
568
565
569
566
static inline unsigned long port_rx_irq_mask(struct uart_port *port)
570
567
{
···
585
580
unsigned short ctrl;
586
581
587
582
#ifdef CONFIG_SERIAL_SH_SCI_DMA
588
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
583
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
589
584
u16 new, scr = sci_serial_in(port, SCSCR);
590
585
if (s->chan_tx)
591
586
new = scr | SCSCR_TDRQE;
···
597
592
598
593
if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
599
594
dma_submit_error(s->cookie_tx)) {
600
-
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
595
+
if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
601
596
/* Switch irq from SCIF to DMA */
602
597
disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
603
598
···
606
601
}
607
602
#endif
608
603
609
-
if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
610
-
port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
604
+
if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
605
+
s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
611
606
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
612
607
ctrl = sci_serial_in(port, SCSCR);
613
608
···
616
611
* (transmit interrupt enable) or in the same instruction to start
617
612
* the transmit process.
618
613
*/
619
-
if (port->type == PORT_SCI)
614
+
if (s->type == PORT_SCI)
620
615
ctrl |= SCSCR_TE;
621
616
622
617
sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
···
625
620
626
621
static void sci_stop_tx(struct uart_port *port)
627
622
{
623
+
struct sci_port *s = to_sci_port(port);
628
624
unsigned short ctrl;
629
625
630
626
/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
631
627
ctrl = sci_serial_in(port, SCSCR);
632
628
633
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
629
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
634
630
ctrl &= ~SCSCR_TDRQE;
635
631
636
632
ctrl &= ~SCSCR_TIE;
···
639
633
sci_serial_out(port, SCSCR, ctrl);
640
634
641
635
#ifdef CONFIG_SERIAL_SH_SCI_DMA
642
-
if (to_sci_port(port)->chan_tx &&
643
-
!dma_submit_error(to_sci_port(port)->cookie_tx)) {
644
-
dmaengine_terminate_async(to_sci_port(port)->chan_tx);
645
-
to_sci_port(port)->cookie_tx = -EINVAL;
636
+
if (s->chan_tx &&
637
+
!dma_submit_error(s->cookie_tx)) {
638
+
dmaengine_terminate_async(s->chan_tx);
639
+
s->cookie_tx = -EINVAL;
646
640
}
647
641
#endif
648
642
}
649
643
650
644
static void sci_start_rx(struct uart_port *port)
651
645
{
646
+
struct sci_port *s = to_sci_port(port);
652
647
unsigned short ctrl;
653
648
654
649
ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
655
650
656
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
651
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
657
652
ctrl &= ~SCSCR_RDRQE;
658
653
659
654
sci_serial_out(port, SCSCR, ctrl);
···
662
655
663
656
static void sci_stop_rx(struct uart_port *port)
664
657
{
658
+
struct sci_port *s = to_sci_port(port);
665
659
unsigned short ctrl;
666
660
667
661
ctrl = sci_serial_in(port, SCSCR);
668
662
669
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
663
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
670
664
ctrl &= ~SCSCR_RDRQE;
671
665
672
666
ctrl &= ~port_rx_irq_mask(port);
···
677
669
678
670
static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
679
671
{
680
-
if (port->type == PORT_SCI) {
672
+
struct sci_port *s = to_sci_port(port);
673
+
674
+
if (s->type == PORT_SCI) {
681
675
/* Just store the mask */
682
676
sci_serial_out(port, SCxSR, mask);
683
-
} else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
677
+
} else if (s->params->overrun_mask == SCIFA_ORER) {
684
678
/* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
685
679
/* Only clear the status bits we want to clear */
686
680
sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
···
752
742
return;
753
743
}
754
744
755
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
745
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
756
746
u16 data = sci_serial_in(port, SCPDR);
757
747
u16 ctrl = sci_serial_in(port, SCPCR);
758
748
759
749
/* Enable RXD and TXD pin functions */
760
750
ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
761
-
if (to_sci_port(port)->has_rtscts) {
751
+
if (s->has_rtscts) {
762
752
/* RTS# is output, active low, unless autorts */
763
753
if (!(port->mctrl & TIOCM_RTS)) {
764
754
ctrl |= SCPCR_RTSC;
···
775
765
}
776
766
sci_serial_out(port, SCPDR, data);
777
767
sci_serial_out(port, SCPCR, ctrl);
778
-
} else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
768
+
} else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
779
769
u16 status = sci_serial_in(port, SCSPTR);
780
770
781
771
/* RTS# is always output; and active low, unless autorts */
···
862
852
c = port->x_char;
863
853
port->x_char = 0;
864
854
} else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
865
-
if (port->type == PORT_SCI &&
866
-
kfifo_is_empty(&tport->xmit_fifo)) {
855
+
if (s->type == PORT_SCI &&
856
+
kfifo_is_empty(&tport->xmit_fifo)) {
867
857
ctrl = sci_serial_in(port, SCSCR);
868
858
ctrl &= ~SCSCR_TE;
869
859
sci_serial_out(port, SCSCR, ctrl);
···
883
873
if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
884
874
uart_write_wakeup(port);
885
875
if (kfifo_is_empty(&tport->xmit_fifo)) {
886
-
if (port->type == PORT_SCI) {
876
+
if (s->type == PORT_SCI) {
887
877
ctrl = sci_serial_in(port, SCSCR);
888
878
ctrl &= ~SCSCR_TIE;
889
879
ctrl |= SCSCR_TEIE;
···
914
904
if (count == 0)
915
905
break;
916
906
917
-
if (port->type == PORT_SCI) {
907
+
if (s->type == PORT_SCI) {
918
908
char c = sci_serial_in(port, SCxRDR);
919
909
if (uart_handle_sysrq_char(port, c))
920
910
count = 0;
···
924
914
for (i = 0; i < count; i++) {
925
915
char c;
926
916
927
-
if (port->type == PORT_SCIF ||
928
-
port->type == PORT_HSCIF) {
917
+
if (s->type == PORT_SCIF ||
918
+
s->type == PORT_HSCIF) {
929
919
status = sci_serial_in(port, SCxSR);
930
920
c = sci_serial_in(port, SCxRDR);
931
921
} else {
···
1062
1052
1063
1053
static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1064
1054
{
1055
+
struct sci_port *s = to_sci_port(port);
1065
1056
unsigned int bits;
1066
1057
1067
1058
if (rx_trig >= port->fifosize)
···
1076
1065
return rx_trig;
1077
1066
}
1078
1067
1079
-
switch (port->type) {
1068
+
switch (s->type) {
1080
1069
case PORT_SCIF:
1081
1070
if (rx_trig < 4) {
1082
1071
bits = 0;
···
1161
1150
return ret;
1162
1151
1163
1152
sci->rx_trigger = sci->ops->set_rtrg(port, r);
1164
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1153
+
if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)
1165
1154
sci->ops->set_rtrg(port, 1);
1166
1155
1167
1156
return count;
···
1177
1166
struct sci_port *sci = to_sci_port(port);
1178
1167
int v;
1179
1168
1180
-
if (port->type == PORT_HSCIF)
1169
+
if (sci->type == PORT_HSCIF)
1181
1170
v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1182
1171
else
1183
1172
v = sci->rx_fifo_timeout;
···
1199
1188
if (ret)
1200
1189
return ret;
1201
1190
1202
-
if (port->type == PORT_HSCIF) {
1191
+
if (sci->type == PORT_HSCIF) {
1203
1192
if (r < 0 || r > 3)
1204
1193
return -EINVAL;
1205
1194
sci->hscif_tot = r << HSSCR_TOT_SHIFT;
···
1240
1229
schedule_work(&s->work_tx);
1241
1230
} else {
1242
1231
s->cookie_tx = -EINVAL;
1243
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1244
-
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1232
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1233
+
s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1245
1234
u16 ctrl = sci_serial_in(port, SCSCR);
1246
1235
sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1247
-
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1236
+
if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1248
1237
/* Switch irq from DMA to SCIF */
1249
1238
dmaengine_pause(s->chan_tx_saved);
1250
1239
enable_irq(s->irqs[SCIx_TXI_IRQ]);
···
1326
1315
1327
1316
/* Direct new serial port interrupts back to CPU */
1328
1317
scr = sci_serial_in(port, SCSCR);
1329
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1330
-
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1318
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1319
+
s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1331
1320
enable_irq(s->irqs[SCIx_RXI_IRQ]);
1332
-
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1321
+
if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1333
1322
s->ops->set_rtrg(port, s->rx_trigger);
1334
1323
else
1335
1324
scr &= ~SCSCR_RDRQE;
···
1569
1558
tty_flip_buffer_push(&port->state->port);
1570
1559
}
1571
1560
1572
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1573
-
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1561
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1562
+
s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1574
1563
sci_dma_rx_submit(s, true);
1575
1564
1576
1565
sci_dma_rx_reenable_irq(s);
···
1693
1682
1694
1683
s->chan_rx_saved = s->chan_rx = chan;
1695
1684
1696
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1697
-
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1685
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1686
+
s->regtype == SCIx_RZ_SCIFA_REGTYPE)
1698
1687
sci_dma_rx_submit(s, false);
1699
1688
}
1700
1689
}
···
1764
1753
u16 ssr = sci_serial_in(port, SCxSR);
1765
1754
1766
1755
/* Disable future Rx interrupts */
1767
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1768
-
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1756
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
1757
+
s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1769
1758
disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1770
-
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1759
+
if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1771
1760
s->ops->set_rtrg(port, 1);
1772
1761
scr |= SCSCR_RIE;
1773
1762
} else {
···
1831
1820
unsigned long flags;
1832
1821
u32 ctrl;
1833
1822
1834
-
if (port->type != PORT_SCI)
1823
+
if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)
1835
1824
return sci_tx_interrupt(irq, ptr);
1836
1825
1837
1826
uart_port_lock_irqsave(port, &flags);
···
1878
1867
}
1879
1868
1880
1869
/* Handle errors */
1881
-
if (port->type == PORT_SCI) {
1870
+
if (s->type == PORT_SCI) {
1882
1871
if (sci_handle_errors(port)) {
1883
1872
/* discard character in rx buffer */
1884
1873
sci_serial_in(port, SCxSR);
···
2102
2091
2103
2092
static void sci_set_rts(struct uart_port *port, bool state)
2104
2093
{
2105
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2094
+
struct sci_port *s = to_sci_port(port);
2095
+
2096
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2106
2097
u16 data = sci_serial_in(port, SCPDR);
2107
2098
2108
2099
/* Active low */
···
2131
2118
2132
2119
static bool sci_get_cts(struct uart_port *port)
2133
2120
{
2134
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2121
+
struct sci_port *s = to_sci_port(port);
2122
+
2123
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2135
2124
/* Active low */
2136
2125
return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2137
2126
} else if (sci_getreg(port, SCSPTR)->size) {
···
2179
2164
2180
2165
if (!(mctrl & TIOCM_RTS)) {
2181
2166
/* Disable Auto RTS */
2182
-
if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2167
+
if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2183
2168
sci_serial_out(port, SCFCR,
2184
2169
sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2185
2170
2186
2171
/* Clear RTS */
2187
2172
sci_set_rts(port, 0);
2188
2173
} else if (s->autorts) {
2189
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2174
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
2190
2175
/* Enable RTS# pin function */
2191
2176
sci_serial_out(port, SCPCR,
2192
2177
sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2193
2178
}
2194
2179
2195
2180
/* Enable Auto RTS */
2196
-
if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2181
+
if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2197
2182
sci_serial_out(port, SCFCR,
2198
2183
sci_serial_in(port, SCFCR) | SCFCR_MCE);
2199
2184
} else {
···
2292
2277
2293
2278
return 0;
2294
2279
}
2280
+
EXPORT_SYMBOL_NS_GPL(sci_startup, "SH_SCI");
2295
2281
2296
2282
void sci_shutdown(struct uart_port *port)
2297
2283
{
···
2305
2289
mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2306
2290
2307
2291
uart_port_lock_irqsave(port, &flags);
2308
-
sci_stop_rx(port);
2309
-
sci_stop_tx(port);
2292
+
s->port.ops->stop_rx(port);
2293
+
s->port.ops->stop_tx(port);
2310
2294
s->ops->shutdown_complete(port);
2311
2295
uart_port_unlock_irqrestore(port, flags);
2312
2296
···
2323
2307
sci_free_irq(s);
2324
2308
sci_free_dma(port);
2325
2309
}
2310
+
EXPORT_SYMBOL_NS_GPL(sci_shutdown, "SH_SCI");
2326
2311
2327
2312
static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2328
2313
unsigned int *srr)
···
2332
2315
int err, min_err = INT_MAX;
2333
2316
unsigned int sr;
2334
2317
2335
-
if (s->port.type != PORT_HSCIF)
2318
+
if (s->type != PORT_HSCIF)
2336
2319
freq *= 2;
2337
2320
2338
2321
for_each_sr(sr, s) {
···
2359
2342
int err, min_err = INT_MAX;
2360
2343
unsigned int sr, dl;
2361
2344
2362
-
if (s->port.type != PORT_HSCIF)
2345
+
if (s->type != PORT_HSCIF)
2363
2346
freq *= 2;
2364
2347
2365
2348
for_each_sr(sr, s) {
···
2392
2375
unsigned int sr, br, prediv, scrate, c;
2393
2376
int err, min_err = INT_MAX;
2394
2377
2395
-
if (s->port.type != PORT_HSCIF)
2378
+
if (s->type != PORT_HSCIF)
2396
2379
freq *= 2;
2397
2380
2398
2381
/*
···
2477
2460
s->ops->set_rtrg(port, 1);
2478
2461
timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2479
2462
} else {
2480
-
if (port->type == PORT_SCIFA ||
2481
-
port->type == PORT_SCIFB)
2463
+
if (s->type == PORT_SCIFA ||
2464
+
s->type == PORT_SCIFB)
2482
2465
s->ops->set_rtrg(port, 1);
2483
2466
else
2484
2467
s->ops->set_rtrg(port, s->rx_trigger);
···
2538
2521
*/
2539
2522
2540
2523
/* Optional Undivided External Clock */
2541
-
if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2542
-
port->type != PORT_SCIFB) {
2524
+
if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&
2525
+
s->type != PORT_SCIFB) {
2543
2526
err = sci_sck_calc(s, baud, &srr1);
2544
2527
if (abs(err) < abs(min_err)) {
2545
2528
best_clk = SCI_SCK;
···
2624
2607
sci_serial_out(port, SEMR, 0);
2625
2608
2626
2609
if (best_clk >= 0) {
2627
-
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2610
+
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)
2628
2611
switch (srr + 1) {
2629
2612
case 5: smr_val |= SCSMR_SRC_5; break;
2630
2613
case 7: smr_val |= SCSMR_SRC_7; break;
···
2709
2692
* (transmit interrupt enable) or in the same instruction to
2710
2693
* start the transmitting process. So skip setting TE here for SCI.
2711
2694
*/
2712
-
if (port->type != PORT_SCI)
2695
+
if (s->type != PORT_SCI)
2713
2696
scr_val |= SCSCR_TE;
2714
2697
scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2715
2698
sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2716
2699
if ((srr + 1 == 5) &&
2717
-
(port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2700
+
(s->type == PORT_SCIFA || s->type == PORT_SCIFB)) {
2718
2701
/*
2719
2702
* In asynchronous mode, when the sampling rate is 1/5, first
2720
2703
* received data may become invalid on some SCIFA and SCIFB.
···
2755
2738
break;
2756
2739
}
2757
2740
}
2741
+
EXPORT_SYMBOL_NS_GPL(sci_pm, "SH_SCI");
2758
2742
2759
2743
static const char *sci_type(struct uart_port *port)
2760
2744
{
2761
-
switch (port->type) {
2745
+
struct sci_port *s = to_sci_port(port);
2746
+
2747
+
switch (s->type) {
2762
2748
case PORT_IRDA:
2763
2749
return "irda";
2764
2750
case PORT_SCI:
···
2818
2798
2819
2799
release_mem_region(port->mapbase, sport->reg_size);
2820
2800
}
2801
+
EXPORT_SYMBOL_NS_GPL(sci_release_port, "SH_SCI");
2821
2802
2822
2803
int sci_request_port(struct uart_port *port)
2823
2804
{
···
2841
2820
2842
2821
return 0;
2843
2822
}
2823
+
EXPORT_SYMBOL_NS_GPL(sci_request_port, "SH_SCI");
2844
2824
2845
2825
void sci_config_port(struct uart_port *port, int flags)
2846
2826
{
2847
2827
if (flags & UART_CONFIG_TYPE) {
2848
2828
struct sci_port *sport = to_sci_port(port);
2849
-
2850
-
port->type = sport->cfg->type;
2829
+
port->type = SCI_PUBLIC_PORT_ID(sport->type);
2851
2830
sci_request_port(port);
2852
2831
}
2853
2832
}
2833
+
EXPORT_SYMBOL_NS_GPL(sci_config_port, "SH_SCI");
2854
2834
2855
2835
int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2856
2836
{
···
2861
2839
2862
2840
return 0;
2863
2841
}
2842
+
EXPORT_SYMBOL_NS_GPL(sci_verify_port, "SH_SCI");
2864
2843
2865
2844
static void sci_prepare_console_write(struct uart_port *port, u32 ctrl)
2866
2845
{
···
2987
2964
struct clk *clk;
2988
2965
unsigned int i;
2989
2966
2990
-
if (sci_port->cfg->type == PORT_HSCIF)
2967
+
if (sci_port->type == PORT_HSCIF) {
2991
2968
clk_names[SCI_SCK] = "hsck";
2969
+
} else if (sci_port->type == SCI_PORT_RSCI) {
2970
+
clk_names[SCI_FCK] = "operation";
2971
+
clk_names[SCI_BRG_INT] = "bus";
2972
+
}
2992
2973
2993
2974
for (i = 0; i < SCI_NUM_CLKS; i++) {
2994
-
clk = devm_clk_get_optional(dev, clk_names[i]);
2975
+
const char *name = clk_names[i];
2976
+
2977
+
clk = devm_clk_get_optional(dev, name);
2995
2978
if (IS_ERR(clk))
2996
2979
return PTR_ERR(clk);
2980
+
2981
+
if (!clk && sci_port->type == SCI_PORT_RSCI &&
2982
+
(i == SCI_FCK || i == SCI_BRG_INT)) {
2983
+
return dev_err_probe(dev, -ENODEV,
2984
+
"failed to get %s\n",
2985
+
name);
2986
+
}
2997
2987
2998
2988
if (!clk && i == SCI_FCK) {
2999
2989
/*
···
3018
2982
if (IS_ERR(clk))
3019
2983
return dev_err_probe(dev, PTR_ERR(clk),
3020
2984
"failed to get %s\n",
3021
-
clk_names[i]);
2985
+
name);
3022
2986
}
3023
2987
3024
2988
if (!clk)
3025
-
dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2989
+
dev_dbg(dev, "failed to get %s\n", name);
3026
2990
else
3027
-
dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2991
+
dev_dbg(dev, "clk %s is %pC rate %lu\n", name,
3028
2992
clk, clk_get_rate(clk));
3029
2993
sci_port->clks[i] = clk;
3030
2994
}
···
3086
3050
3087
3051
sci_port->cfg = p;
3088
3052
3053
+
sci_port->type = p->type;
3054
+
sci_port->regtype = p->regtype;
3055
+
3089
3056
port->iotype = UPIO_MEM;
3090
3057
port->line = index;
3091
3058
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
···
3108
3069
}
3109
3070
3110
3071
/*
3111
-
* The fourth interrupt on SCI port is transmit end interrupt, so
3072
+
* The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
3112
3073
* shuffle the interrupts.
3113
3074
*/
3114
-
if (p->type == PORT_SCI)
3075
+
if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
3115
3076
swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3116
3077
3117
3078
/* The SCI generates several interrupts. They can be muxed together or
···
3145
3106
else
3146
3107
sci_port->rx_trigger = 8;
3147
3108
break;
3109
+
case SCI_PORT_RSCI:
3110
+
sci_port->rx_trigger = 15;
3111
+
break;
3148
3112
default:
3149
3113
sci_port->rx_trigger = 1;
3150
3114
break;
···
3170
3128
return ret;
3171
3129
}
3172
3130
3173
-
port->type = p->type;
3131
+
port->type = SCI_PUBLIC_PORT_ID(p->type);
3174
3132
port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3175
3133
port->fifosize = sci_port->params->fifosize;
3176
3134
3177
-
if (port->type == PORT_SCI && !dev->dev.of_node) {
3135
+
if (p->type == PORT_SCI && !dev->dev.of_node) {
3178
3136
if (sci_port->reg_size >= 0x20)
3179
3137
port->regshift = 2;
3180
3138
else
···
3364
3322
3365
3323
static void sci_remove(struct platform_device *dev)
3366
3324
{
3367
-
struct sci_port *port = platform_get_drvdata(dev);
3368
-
unsigned int type = port->port.type; /* uart_remove_... clears it */
3325
+
struct sci_port *s = platform_get_drvdata(dev);
3326
+
unsigned int type = s->type; /* uart_remove_... clears it */
3369
3327
3370
-
sci_ports_in_use &= ~BIT(port->port.line);
3371
-
uart_remove_one_port(&sci_uart_driver, &port->port);
3328
+
sci_ports_in_use &= ~BIT(s->port.line);
3329
+
uart_remove_one_port(&sci_uart_driver, &s->port);
3372
3330
3373
-
if (port->port.fifosize > 1)
3331
+
if (s->port.fifosize > 1)
3374
3332
device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3375
-
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3333
+
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
3334
+
type == SCI_PORT_RSCI)
3376
3335
device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3377
3336
}
3378
3337
···
3467
3424
.compatible = "renesas,scif-r9a09g057",
3468
3425
.data = &of_sci_scif_rzv2h,
3469
3426
},
3427
+
#ifdef CONFIG_SERIAL_RSCI
3428
+
{
3429
+
.compatible = "renesas,r9a09g077-rsci",
3430
+
.data = &of_sci_rsci_data,
3431
+
},
3432
+
#endif /* CONFIG_SERIAL_RSCI */
3470
3433
/* Family-specific types */
3471
3434
{
3472
3435
.compatible = "renesas,rcar-gen1-scif",
···
3485
3436
.data = &of_sci_rcar_scif
3486
3437
}, {
3487
3438
.compatible = "renesas,rcar-gen4-scif",
3439
+
.data = &of_sci_rcar_scif
3440
+
}, {
3441
+
.compatible = "renesas,rcar-gen5-scif",
3488
3442
.data = &of_sci_rcar_scif
3489
3443
},
3490
3444
/* Generic types */
···
3734
3682
if (ret)
3735
3683
return ret;
3736
3684
}
3737
-
if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3738
-
sp->port.type == PORT_HSCIF) {
3685
+
if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
3686
+
sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
3739
3687
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3740
3688
if (ret) {
3741
3689
if (sp->port.fifosize > 1) {
···
3754
3702
return 0;
3755
3703
}
3756
3704
3757
-
static __maybe_unused int sci_suspend(struct device *dev)
3705
+
static int sci_suspend(struct device *dev)
3758
3706
{
3759
3707
struct sci_port *sport = dev_get_drvdata(dev);
3760
3708
···
3772
3720
return 0;
3773
3721
}
3774
3722
3775
-
static __maybe_unused int sci_resume(struct device *dev)
3723
+
static int sci_resume(struct device *dev)
3776
3724
{
3777
3725
struct sci_port *sport = dev_get_drvdata(dev);
3778
3726
···
3793
3741
return 0;
3794
3742
}
3795
3743
3796
-
static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3744
+
static DEFINE_SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3797
3745
3798
3746
static struct platform_driver sci_driver = {
3799
3747
.probe = sci_probe,
3800
3748
.remove = sci_remove,
3801
3749
.driver = {
3802
3750
.name = "sh-sci",
3803
-
.pm = &sci_dev_pm_ops,
3751
+
.pm = pm_sleep_ptr(&sci_dev_pm_ops),
3804
3752
.of_match_table = of_match_ptr(of_sci_match),
3805
3753
},
3806
3754
};
···
3851
3799
if (!device->port.membase)
3852
3800
return -ENODEV;
3853
3801
3854
-
device->port.type = data->type;
3802
+
device->port.type = SCI_PUBLIC_PORT_ID(data->type);
3803
+
3855
3804
sci_ports[0].port = device->port;
3805
+
sci_ports[0].type = data->type;
3806
+
sci_ports[0].regtype = data->regtype;
3856
3807
3857
3808
port_cfg.type = data->type;
3858
3809
port_cfg.regtype = data->regtype;
+1
-2
drivers/tty/tty_buffer.c
+1
-2
drivers/tty/tty_buffer.c
+8
-9
drivers/tty/tty_port.c
+8
-9
drivers/tty/tty_port.c
···
391
391
}
392
392
EXPORT_SYMBOL(tty_port_hangup);
393
393
394
-
/**
395
-
* tty_port_tty_hangup - helper to hang up a tty
396
-
* @port: tty port
397
-
* @check_clocal: hang only ttys with %CLOCAL unset?
398
-
*/
399
-
void tty_port_tty_hangup(struct tty_port *port, bool check_clocal)
394
+
void __tty_port_tty_hangup(struct tty_port *port, bool check_clocal, bool async)
400
395
{
401
396
struct tty_struct *tty = tty_port_tty_get(port);
402
397
403
-
if (tty && (!check_clocal || !C_CLOCAL(tty)))
404
-
tty_hangup(tty);
398
+
if (tty && (!check_clocal || !C_CLOCAL(tty))) {
399
+
if (async)
400
+
tty_hangup(tty);
401
+
else
402
+
tty_vhangup(tty);
403
+
}
405
404
tty_kref_put(tty);
406
405
}
407
-
EXPORT_SYMBOL_GPL(tty_port_tty_hangup);
406
+
EXPORT_SYMBOL_GPL(__tty_port_tty_hangup);
408
407
409
408
/**
410
409
* tty_port_tty_wakeup - helper to wake up a tty
+112
drivers/tty/vt/defkeymap.c_shipped
+112
drivers/tty/vt/defkeymap.c_shipped
···
23
23
0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
24
24
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
25
25
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
26
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
27
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
28
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
29
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
30
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
31
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
32
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
33
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
34
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
35
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
36
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
37
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
38
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
39
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
40
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
41
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
26
42
};
27
43
28
44
static unsigned short shift_map[NR_KEYS] = {
···
57
41
0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,
58
42
0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116,
59
43
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
44
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
45
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
46
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
47
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
48
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
49
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
50
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
51
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
52
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
53
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
54
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
55
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
56
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
57
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
58
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
59
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
60
60
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
61
61
};
62
62
···
93
61
0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
94
62
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
95
63
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
64
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
65
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
66
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
67
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
68
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
69
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
70
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
71
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
72
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
73
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
74
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
75
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
76
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
77
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
78
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
79
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
96
80
};
97
81
98
82
static unsigned short ctrl_map[NR_KEYS] = {
···
127
79
0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
128
80
0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
129
81
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
82
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
83
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
84
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
85
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
86
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
87
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
88
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
89
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
90
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
91
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
92
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
93
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
94
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
95
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
96
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
97
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
130
98
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
131
99
};
132
100
···
163
99
0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
164
100
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
165
101
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
102
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
103
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
104
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
105
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
106
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
107
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
108
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
109
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
110
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
111
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
112
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
113
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
114
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
115
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
116
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
117
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
166
118
};
167
119
168
120
static unsigned short alt_map[NR_KEYS] = {
···
198
118
0xf118, 0xf210, 0xf211, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
199
119
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
200
120
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
121
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
122
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
123
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
124
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
125
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
126
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
127
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
128
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
129
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
130
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
131
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
132
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
133
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
134
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
135
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
136
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
201
137
};
202
138
203
139
static unsigned short ctrl_alt_map[NR_KEYS] = {
···
232
136
0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,
233
137
0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c,
234
138
0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
139
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
140
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
141
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
142
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
143
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
144
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
145
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
146
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
147
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
148
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
149
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
150
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
151
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
152
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
153
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
154
+
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
235
155
0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
236
156
};
237
157
+1
-1
drivers/tty/vt/keyboard.c
+1
-1
drivers/tty/vt/keyboard.c
+1
-6
drivers/usb/class/cdc-acm.c
+1
-6
drivers/usb/class/cdc-acm.c
···
1571
1571
static void acm_disconnect(struct usb_interface *intf)
1572
1572
{
1573
1573
struct acm *acm = usb_get_intfdata(intf);
1574
-
struct tty_struct *tty;
1575
1574
int i;
1576
1575
1577
1576
/* sibling interface is already cleaning up */
···
1597
1598
usb_set_intfdata(acm->data, NULL);
1598
1599
mutex_unlock(&acm->mutex);
1599
1600
1600
-
tty = tty_port_tty_get(&acm->port);
1601
-
if (tty) {
1602
-
tty_vhangup(tty);
1603
-
tty_kref_put(tty);
1604
-
}
1601
+
tty_port_tty_vhangup(&acm->port);
1605
1602
1606
1603
cancel_delayed_work_sync(&acm->dwork);
1607
1604
+1
-6
drivers/usb/serial/usb-serial.c
+1
-6
drivers/usb/serial/usb-serial.c
···
1176
1176
struct usb_serial *serial = usb_get_intfdata(interface);
1177
1177
struct device *dev = &interface->dev;
1178
1178
struct usb_serial_port *port;
1179
-
struct tty_struct *tty;
1180
1179
1181
1180
/* sibling interface is cleaning up */
1182
1181
if (!serial)
···
1190
1191
1191
1192
for (i = 0; i < serial->num_ports; ++i) {
1192
1193
port = serial->port[i];
1193
-
tty = tty_port_tty_get(&port->port);
1194
-
if (tty) {
1195
-
tty_vhangup(tty);
1196
-
tty_kref_put(tty);
1197
-
}
1194
+
tty_port_tty_vhangup(&port->port);
1198
1195
usb_serial_port_poison_urbs(port);
1199
1196
wake_up_interruptible(&port->port.delta_msr_wait);
1200
1197
cancel_work_sync(&port->work);
+2
-2
include/linux/serial_8250.h
+2
-2
include/linux/serial_8250.h
···
46
46
unsigned int type; /* If UPF_FIXED_TYPE */
47
47
upf_t flags; /* UPF_* flags */
48
48
u16 bugs; /* port bugs */
49
-
unsigned int (*serial_in)(struct uart_port *, int);
50
-
void (*serial_out)(struct uart_port *, int, int);
49
+
u32 (*serial_in)(struct uart_port *, unsigned int offset);
50
+
void (*serial_out)(struct uart_port *, unsigned int offset, u32 val);
51
51
u32 (*dl_read)(struct uart_8250_port *up);
52
52
void (*dl_write)(struct uart_8250_port *up, u32 value);
53
53
void (*set_termios)(struct uart_port *,
+2
-4
include/linux/serial_core.h
+2
-4
include/linux/serial_core.h
···
443
443
spinlock_t lock; /* port lock */
444
444
unsigned long iobase; /* in/out[bwl] */
445
445
unsigned char __iomem *membase; /* read/write[bwl] */
446
-
unsigned int (*serial_in)(struct uart_port *, int);
447
-
void (*serial_out)(struct uart_port *, int, int);
446
+
u32 (*serial_in)(struct uart_port *, unsigned int offset);
447
+
void (*serial_out)(struct uart_port *, unsigned int offset, u32 val);
448
448
void (*set_termios)(struct uart_port *,
449
449
struct ktermios *new,
450
450
const struct ktermios *old);
···
1101
1101
return uart_console(port) && console_is_registered(port->cons);
1102
1102
}
1103
1103
1104
-
struct uart_port *uart_get_console(struct uart_port *ports, int nr,
1105
-
struct console *c);
1106
1104
int uart_parse_earlycon(char *p, enum uart_iotype *iotype,
1107
1105
resource_size_t *addr, char **options);
1108
1106
void uart_parse_options(const char *options, int *baud, int *parity, int *bits,
+20
-1
include/linux/tty_port.h
+20
-1
include/linux/tty_port.h
···
232
232
void tty_port_raise_dtr_rts(struct tty_port *port);
233
233
void tty_port_lower_dtr_rts(struct tty_port *port);
234
234
void tty_port_hangup(struct tty_port *port);
235
-
void tty_port_tty_hangup(struct tty_port *port, bool check_clocal);
235
+
void __tty_port_tty_hangup(struct tty_port *port, bool check_clocal, bool async);
236
236
void tty_port_tty_wakeup(struct tty_port *port);
237
237
int tty_port_block_til_ready(struct tty_port *port, struct tty_struct *tty,
238
238
struct file *filp);
···
249
249
static inline int tty_port_users(struct tty_port *port)
250
250
{
251
251
return port->count + port->blocked_open;
252
+
}
253
+
254
+
/**
255
+
* tty_port_tty_hangup - helper to hang up a tty asynchronously
256
+
* @port: tty port
257
+
* @check_clocal: hang only ttys with %CLOCAL unset?
258
+
*/
259
+
static inline void tty_port_tty_hangup(struct tty_port *port, bool check_clocal)
260
+
{
261
+
__tty_port_tty_hangup(port, check_clocal, true);
262
+
}
263
+
264
+
/**
265
+
* tty_port_tty_vhangup - helper to hang up a tty synchronously
266
+
* @port: tty port
267
+
*/
268
+
static inline void tty_port_tty_vhangup(struct tty_port *port)
269
+
{
270
+
__tty_port_tty_hangup(port, false, false);
252
271
}
253
272
254
273
#endif
+39
-39
include/uapi/linux/vt.h
+39
-39
include/uapi/linux/vt.h
···
14
14
/* Note: the ioctl VT_GETSTATE does not work for
15
15
consoles 16 and higher (since it returns a short) */
16
16
17
-
/* 0x56 is 'V', to avoid collision with termios and kd */
17
+
/* 'V' to avoid collision with termios and kd */
18
18
19
-
#define VT_OPENQRY 0x5600 /* find available vt */
19
+
#define VT_OPENQRY _IO('V', 0x00) /* find available vt */
20
20
21
21
struct vt_mode {
22
-
char mode; /* vt mode */
23
-
char waitv; /* if set, hang on writes if not active */
24
-
short relsig; /* signal to raise on release req */
25
-
short acqsig; /* signal to raise on acquisition */
26
-
short frsig; /* unused (set to 0) */
22
+
__u8 mode; /* vt mode */
23
+
__u8 waitv; /* if set, hang on writes if not active */
24
+
__s16 relsig; /* signal to raise on release req */
25
+
__s16 acqsig; /* signal to raise on acquisition */
26
+
__s16 frsig; /* unused (set to 0) */
27
27
};
28
-
#define VT_GETMODE 0x5601 /* get mode of active vt */
29
-
#define VT_SETMODE 0x5602 /* set mode of active vt */
28
+
#define VT_GETMODE _IO('V', 0x01) /* get mode of active vt */
29
+
#define VT_SETMODE _IO('V', 0x02) /* set mode of active vt */
30
30
#define VT_AUTO 0x00 /* auto vt switching */
31
31
#define VT_PROCESS 0x01 /* process controls switching */
32
32
#define VT_ACKACQ 0x02 /* acknowledge switch */
33
33
34
34
struct vt_stat {
35
-
unsigned short v_active; /* active vt */
36
-
unsigned short v_signal; /* signal to send */
37
-
unsigned short v_state; /* vt bitmask */
35
+
__u16 v_active; /* active vt */
36
+
__u16 v_signal; /* signal to send */
37
+
__u16 v_state; /* vt bitmask */
38
38
};
39
-
#define VT_GETSTATE 0x5603 /* get global vt state info */
40
-
#define VT_SENDSIG 0x5604 /* signal to send to bitmask of vts */
39
+
#define VT_GETSTATE _IO('V', 0x03) /* get global vt state info */
40
+
#define VT_SENDSIG _IO('V', 0x04) /* signal to send to bitmask of vts */
41
41
42
-
#define VT_RELDISP 0x5605 /* release display */
42
+
#define VT_RELDISP _IO('V', 0x05) /* release display */
43
43
44
-
#define VT_ACTIVATE 0x5606 /* make vt active */
45
-
#define VT_WAITACTIVE 0x5607 /* wait for vt active */
46
-
#define VT_DISALLOCATE 0x5608 /* free memory associated to vt */
44
+
#define VT_ACTIVATE _IO('V', 0x06) /* make vt active */
45
+
#define VT_WAITACTIVE _IO('V', 0x07) /* wait for vt active */
46
+
#define VT_DISALLOCATE _IO('V', 0x08) /* free memory associated to vt */
47
47
48
48
struct vt_sizes {
49
-
unsigned short v_rows; /* number of rows */
50
-
unsigned short v_cols; /* number of columns */
51
-
unsigned short v_scrollsize; /* number of lines of scrollback */
49
+
__u16 v_rows; /* number of rows */
50
+
__u16 v_cols; /* number of columns */
51
+
__u16 v_scrollsize; /* number of lines of scrollback */
52
52
};
53
-
#define VT_RESIZE 0x5609 /* set kernel's idea of screensize */
53
+
#define VT_RESIZE _IO('V', 0x09) /* set kernel's idea of screensize */
54
54
55
55
struct vt_consize {
56
-
unsigned short v_rows; /* number of rows */
57
-
unsigned short v_cols; /* number of columns */
58
-
unsigned short v_vlin; /* number of pixel rows on screen */
59
-
unsigned short v_clin; /* number of pixel rows per character */
60
-
unsigned short v_vcol; /* number of pixel columns on screen */
61
-
unsigned short v_ccol; /* number of pixel columns per character */
56
+
__u16 v_rows; /* number of rows */
57
+
__u16 v_cols; /* number of columns */
58
+
__u16 v_vlin; /* number of pixel rows on screen */
59
+
__u16 v_clin; /* number of pixel rows per character */
60
+
__u16 v_vcol; /* number of pixel columns on screen */
61
+
__u16 v_ccol; /* number of pixel columns per character */
62
62
};
63
-
#define VT_RESIZEX 0x560A /* set kernel's idea of screensize + more */
64
-
#define VT_LOCKSWITCH 0x560B /* disallow vt switching */
65
-
#define VT_UNLOCKSWITCH 0x560C /* allow vt switching */
66
-
#define VT_GETHIFONTMASK 0x560D /* return hi font mask */
63
+
#define VT_RESIZEX _IO('V', 0x0A) /* set kernel's idea of screensize + more */
64
+
#define VT_LOCKSWITCH _IO('V', 0x0B) /* disallow vt switching */
65
+
#define VT_UNLOCKSWITCH _IO('V', 0x0C) /* allow vt switching */
66
+
#define VT_GETHIFONTMASK _IO('V', 0x0D) /* return hi font mask */
67
67
68
68
struct vt_event {
69
-
unsigned int event;
69
+
__u32 event;
70
70
#define VT_EVENT_SWITCH 0x0001 /* Console switch */
71
71
#define VT_EVENT_BLANK 0x0002 /* Screen blank */
72
72
#define VT_EVENT_UNBLANK 0x0004 /* Screen unblank */
73
73
#define VT_EVENT_RESIZE 0x0008 /* Resize display */
74
74
#define VT_MAX_EVENT 0x000F
75
-
unsigned int oldev; /* Old console */
76
-
unsigned int newev; /* New console (if changing) */
77
-
unsigned int pad[4]; /* Padding for expansion */
75
+
__u32 oldev; /* Old console */
76
+
__u32 newev; /* New console (if changing) */
77
+
__u32 pad[4]; /* Padding for expansion */
78
78
};
79
79
80
-
#define VT_WAITEVENT 0x560E /* Wait for an event */
80
+
#define VT_WAITEVENT _IO('V', 0x0E) /* Wait for an event */
81
81
82
82
struct vt_setactivate {
83
-
unsigned int console;
83
+
__u32 console;
84
84
struct vt_mode mode;
85
85
};
86
86
87
-
#define VT_SETACTIVATE 0x560F /* Activate and set the mode of a console */
87
+
#define VT_SETACTIVATE _IO('V', 0x0F) /* Activate and set the mode of a console */
88
88
89
89
/* get console size and cursor position */
90
90
struct vt_consizecsrpos {
+1
-6
net/bluetooth/rfcomm/tty.c
+1
-6
net/bluetooth/rfcomm/tty.c
···
438
438
{
439
439
struct rfcomm_dev_req req;
440
440
struct rfcomm_dev *dev;
441
-
struct tty_struct *tty;
442
441
443
442
if (copy_from_user(&req, arg, sizeof(req)))
444
443
return -EFAULT;
···
463
464
rfcomm_dlc_close(dev->dlc, 0);
464
465
465
466
/* Shut down TTY synchronously before freeing rfcomm_dev */
466
-
tty = tty_port_tty_get(&dev->port);
467
-
if (tty) {
468
-
tty_vhangup(tty);
469
-
tty_kref_put(tty);
470
-
}
467
+
tty_port_tty_vhangup(&dev->port);
471
468
472
469
if (!test_bit(RFCOMM_TTY_OWNED, &dev->status))
473
470
tty_port_put(&dev->port);