tjh.dev / kernel
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ASoC: rt722: fix pop noise at the beginning of headphone playback

This patch added the function_status check to avoid the calibration again.
The codec driver reinitializes when the 'FUNCTION_NEEDS_INITIALIZATION' flag raises.

Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://patch.msgid.link/20250416092528.737845-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shuming Fan and committed by
Mark Brown 91f4ca73 d1965f00

+176 -122
+8
sound/soc/codecs/rt722-sdca-sdw.c
··· 24 24 case 0x2f50: 25 25 case 0x2f54: 26 26 case 0x2f58 ... 0x2f5d: 27 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 27 28 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_SELECTED_MODE, 28 29 0): 29 30 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE, ··· 57 56 RT722_SDCA_CTL_VENDOR_DEF, 0): 58 57 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 59 58 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 59 + case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 60 60 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 61 61 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 62 62 case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, ··· 72 70 RT722_SDCA_CTL_VENDOR_DEF, CH_08): 73 71 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 74 72 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 73 + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 75 74 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 76 75 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 77 76 case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2: ··· 153 150 switch (reg) { 154 151 case 0x2f01: 155 152 case 0x2f54: 153 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 156 154 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE, 157 155 0): 156 + case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 158 157 case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 159 158 0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 160 159 RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0): 160 + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 161 161 case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2: 162 162 case 0x2000000: 163 163 case 0x200000d: ··· 172 166 case 0x2000084: 173 167 case 0x2000086: 174 168 case 0x3110000: 169 + case 0x5800003: 170 + case 0x5810000: 175 171 return true; 176 172 default: 177 173 return false;
+163 -122
sound/soc/codecs/rt722-sdca.c
··· 1302 1302 1303 1303 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722) 1304 1304 { 1305 - /* Set AD07 power entity floating control */ 1306 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1307 - RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1308 - /* Set AD10 power entity floating control */ 1309 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1310 - RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1311 - /* Set DMIC1/DMIC2 power entity floating control */ 1312 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1313 - RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1314 - /* Set DMIC2 IT entity floating control */ 1315 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1316 - RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1317 - /* Set AD10 FU entity floating control */ 1318 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1319 - RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1320 - /* Set DMIC2 FU entity floating control */ 1321 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1322 - RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1323 - /* Set AD10 FU channel floating control */ 1324 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1325 - RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1326 - /* Set DMIC2 FU channel floating control */ 1327 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1328 - RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1329 - /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1330 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1331 - RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1332 - /* Enable vf707_r12_05/vf707_r13_05 */ 1333 - regmap_write(rt722->regmap, 1334 - SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1335 - RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1336 - /* Fine tune PDE2A latency */ 1337 - regmap_write(rt722->regmap, 0x2f5c, 0x25); 1305 + unsigned int mic_func_status; 1306 + struct device *dev = &rt722->slave->dev; 1307 + 1308 + regmap_read(rt722->regmap, 1309 + SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &mic_func_status); 1310 + dev_dbg(dev, "%s mic func_status=0x%x\n", __func__, mic_func_status); 1311 + 1312 + if ((mic_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1313 + /* Set AD07 power entity floating control */ 1314 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1315 + RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29); 1316 + /* Set AD10 power entity floating control */ 1317 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1318 + RT722_ADC10_PDE_FLOAT_CTL, 0x2a00); 1319 + /* Set DMIC1/DMIC2 power entity floating control */ 1320 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1321 + RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a); 1322 + /* Set DMIC2 IT entity floating control */ 1323 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1324 + RT722_DMIC_ENT_FLOAT_CTL, 0x2626); 1325 + /* Set AD10 FU entity floating control */ 1326 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1327 + RT722_ADC_ENT_FLOAT_CTL, 0x1e00); 1328 + /* Set DMIC2 FU entity floating control */ 1329 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1330 + RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515); 1331 + /* Set AD10 FU channel floating control */ 1332 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1333 + RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304); 1334 + /* Set DMIC2 FU channel floating control */ 1335 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1336 + RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304); 1337 + /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */ 1338 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, 1339 + RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000); 1340 + /* Enable vf707_r12_05/vf707_r13_05 */ 1341 + regmap_write(rt722->regmap, 1342 + SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, 1343 + RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1344 + /* Fine tune PDE2A latency */ 1345 + regmap_write(rt722->regmap, 0x2f5c, 0x25); 1346 + 1347 + /* clear flag */ 1348 + regmap_write(rt722->regmap, 1349 + SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1350 + FUNCTION_NEEDS_INITIALIZATION); 1351 + } 1338 1352 } 1339 1353 1340 1354 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722) 1341 1355 { 1342 - /* Set DVQ=01 */ 1343 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1344 - 0xc215); 1345 - /* Reset dc_cal_top */ 1346 - rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1347 - 0x702c); 1348 - /* W1C Trigger Calibration */ 1349 - rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1350 - 0xf02d); 1351 - /* Set DAC02/ClassD power entity floating control */ 1352 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1353 - 0x2323); 1354 - /* Set EAPD high */ 1355 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1356 - 0x0002); 1357 - /* Enable vf707_r14 */ 1358 - regmap_write(rt722->regmap, 1359 - SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1360 - RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1356 + unsigned int amp_func_status; 1357 + struct device *dev = &rt722->slave->dev; 1358 + 1359 + regmap_read(rt722->regmap, 1360 + SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &amp_func_status); 1361 + dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); 1362 + 1363 + if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1364 + /* Set DVQ=01 */ 1365 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1366 + 0xc215); 1367 + /* Reset dc_cal_top */ 1368 + rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1369 + 0x702c); 1370 + /* W1C Trigger Calibration */ 1371 + rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL, 1372 + 0xf02d); 1373 + /* Set DAC02/ClassD power entity floating control */ 1374 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL, 1375 + 0x2323); 1376 + /* Set EAPD high */ 1377 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL, 1378 + 0x0002); 1379 + /* Enable vf707_r14 */ 1380 + regmap_write(rt722->regmap, 1381 + SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, 1382 + RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04); 1383 + 1384 + /* clear flag */ 1385 + regmap_write(rt722->regmap, 1386 + SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1387 + FUNCTION_NEEDS_INITIALIZATION); 1388 + } 1361 1389 } 1362 1390 1363 1391 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722) 1364 1392 { 1365 1393 int loop_check, chk_cnt = 100, ret; 1366 1394 unsigned int calib_status = 0; 1395 + unsigned int jack_func_status; 1396 + struct device *dev = &rt722->slave->dev; 1367 1397 1368 - /* Config analog bias */ 1369 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1370 - 0xa081); 1371 - /* GE related settings */ 1372 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1373 - 0xa009); 1374 - /* Button A, B, C, D bypass mode */ 1375 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1376 - 0xcf00); 1377 - /* HID1 slot enable */ 1378 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1379 - 0x000f); 1380 - /* Report ID for HID1 */ 1381 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1382 - 0x1100); 1383 - /* OSC/OOC for slot 2, 3 */ 1384 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1385 - 0x0c12); 1386 - /* Set JD de-bounce clock control */ 1387 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1388 - 0x7002); 1389 - /* Set DVQ=01 */ 1390 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1391 - 0xc215); 1392 - /* FSM switch to calibration manual mode */ 1393 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1394 - 0x4100); 1395 - /* W1C Trigger DC calibration (HP) */ 1396 - rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1397 - 0x008d); 1398 - /* check HP calibration FSM status */ 1399 - for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1400 - usleep_range(10000, 11000); 1401 - ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1402 - RT722_DAC_DC_CALI_CTL3, &calib_status); 1403 - if (ret < 0) 1404 - dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1405 - if ((calib_status & 0x0040) == 0x0) 1406 - break; 1398 + regmap_read(rt722->regmap, 1399 + SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &jack_func_status); 1400 + dev_dbg(dev, "%s jack func_status=0x%x\n", __func__, jack_func_status); 1401 + 1402 + if ((jack_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) { 1403 + /* Config analog bias */ 1404 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3, 1405 + 0xa081); 1406 + /* GE related settings */ 1407 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2, 1408 + 0xa009); 1409 + /* Button A, B, C, D bypass mode */ 1410 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4, 1411 + 0xcf00); 1412 + /* HID1 slot enable */ 1413 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5, 1414 + 0x000f); 1415 + /* Report ID for HID1 */ 1416 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0, 1417 + 0x1100); 1418 + /* OSC/OOC for slot 2, 3 */ 1419 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7, 1420 + 0x0c12); 1421 + /* Set JD de-bounce clock control */ 1422 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1, 1423 + 0x7002); 1424 + /* Set DVQ=01 */ 1425 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6, 1426 + 0xc215); 1427 + /* FSM switch to calibration manual mode */ 1428 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL, 1429 + 0x4100); 1430 + /* W1C Trigger DC calibration (HP) */ 1431 + rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3, 1432 + 0x008d); 1433 + /* check HP calibration FSM status */ 1434 + for (loop_check = 0; loop_check < chk_cnt; loop_check++) { 1435 + usleep_range(10000, 11000); 1436 + ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI, 1437 + RT722_DAC_DC_CALI_CTL3, &calib_status); 1438 + if (ret < 0) 1439 + dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret); 1440 + if ((calib_status & 0x0040) == 0x0) 1441 + break; 1442 + } 1443 + 1444 + if (loop_check == chk_cnt) 1445 + dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__); 1446 + 1447 + /* Set ADC09 power entity floating control */ 1448 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1449 + 0x2a12); 1450 + /* Set MIC2 and LINE1 power entity floating control */ 1451 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1452 + 0x3429); 1453 + /* Set ET41h and LINE2 power entity floating control */ 1454 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1455 + 0x4112); 1456 + /* Set DAC03 and HP power entity floating control */ 1457 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1458 + 0x4040); 1459 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1460 + 0x4141); 1461 + rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1462 + 0x0101); 1463 + /* Fine tune PDE40 latency */ 1464 + regmap_write(rt722->regmap, 0x2f58, 0x07); 1465 + regmap_write(rt722->regmap, 0x2f03, 0x06); 1466 + /* MIC VRefo */ 1467 + rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1468 + RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1469 + rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1470 + RT722_VREFO_GAT, 0x4000, 0x4000); 1471 + /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1472 + rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1473 + 0x0010); 1474 + 1475 + /* clear flag */ 1476 + regmap_write(rt722->regmap, 1477 + SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), 1478 + FUNCTION_NEEDS_INITIALIZATION); 1407 1479 } 1408 - 1409 - if (loop_check == chk_cnt) 1410 - dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__); 1411 - 1412 - /* Set ADC09 power entity floating control */ 1413 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL, 1414 - 0x2a12); 1415 - /* Set MIC2 and LINE1 power entity floating control */ 1416 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL, 1417 - 0x3429); 1418 - /* Set ET41h and LINE2 power entity floating control */ 1419 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL, 1420 - 0x4112); 1421 - /* Set DAC03 and HP power entity floating control */ 1422 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL, 1423 - 0x4040); 1424 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1, 1425 - 0x4141); 1426 - rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1, 1427 - 0x0101); 1428 - /* Fine tune PDE40 latency */ 1429 - regmap_write(rt722->regmap, 0x2f58, 0x07); 1430 - regmap_write(rt722->regmap, 0x2f03, 0x06); 1431 - /* MIC VRefo */ 1432 - rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1433 - RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200); 1434 - rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG, 1435 - RT722_VREFO_GAT, 0x4000, 0x4000); 1436 - /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */ 1437 - rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4, 1438 - 0x0010); 1439 1480 } 1440 1481 1441 1482 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
+5
sound/soc/codecs/rt722-sdca.h
··· 183 183 #define RT722_SDCA_ENT_PLATFORM_FU44 0x44 184 184 #define RT722_SDCA_ENT_XU03 0x03 185 185 #define RT722_SDCA_ENT_XU0D 0x0d 186 + #define RT722_SDCA_ENT0 0x00 186 187 187 188 /* RT722 SDCA control */ 188 189 #define RT722_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10 ··· 198 197 #define RT722_SDCA_CTL_REQ_POWER_STATE 0x01 199 198 #define RT722_SDCA_CTL_VENDOR_DEF 0x30 200 199 #define RT722_SDCA_CTL_FU_CH_GAIN 0x0b 200 + #define RT722_SDCA_CTL_FUNC_STATUS 0x10 201 201 202 202 /* RT722 SDCA channel */ 203 203 #define CH_L 0x01 ··· 216 214 #define RT722_SDCA_RATE_48000HZ 0x09 217 215 #define RT722_SDCA_RATE_96000HZ 0x0b 218 216 #define RT722_SDCA_RATE_192000HZ 0x0d 217 + 218 + /* Function_Status */ 219 + #define FUNCTION_NEEDS_INITIALIZATION BIT(5) 219 220 220 221 enum { 221 222 RT722_AIF1, /* For headset mic and headphone */