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riscv: Update MIPS vendor id to 0x127

[1] defines MIPS vendor id as 0x127. All previous MIPS RISC-V patches
were tested on QEMU, also modified to use 0x722 as MIPS_VENDOR_ID. This
new value should reflect real hardware.

[1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Fixes: a8fed1bc03ac ("riscv: Add xmipsexectl as a vendor extension")
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Link: https://patch.msgid.link/20251113-mips-vendorid-v2-1-3279489b7f84@htecgroup.com
Cc: <stable@vger.kernel.org>
Signed-off-by: Paul WAlmsley <pjw@kernel.org>

authored by

Chao-ying Fu and committed by
Paul Walmsley 91f815b7 4427259c

+1 -1
+1 -1
arch/riscv/include/asm/vendorid_list.h
··· 7 7 8 8 #define ANDES_VENDOR_ID 0x31e 9 9 #define MICROCHIP_VENDOR_ID 0x029 10 + #define MIPS_VENDOR_ID 0x127 10 11 #define SIFIVE_VENDOR_ID 0x489 11 12 #define THEAD_VENDOR_ID 0x5b7 12 - #define MIPS_VENDOR_ID 0x722 13 13 14 14 #endif