Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang:
"I2C has quite some patches for you this time. I hope it is the move to
per-driver-maintainers which is now showing results. We will see.
The big news is two new drivers (Nuvoton NPCM and Qualcomm CCI),
larger refactoring of the Designware, Tegra, and PXA drivers, the
Cadence driver supports being a slave now, and there is support to
instanciate SPD eeproms for well-known cases (which will be
user-visible because the i801 driver supports it), and some
devm_platform_ioremap_resource() conversions which blow up the
diffstat.
Note that I applied the Nuvoton driver quite late, so some minor fixup
patches arrived during the merge window. I chose to apply them right
away because they were trivial"
* 'i2c/for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (109 commits)
i2c: Drop stray comma in MODULE_AUTHOR statements
i2c: npcm7xx: npcm_i2caddr[] can be static
MAINTAINERS: npcm7xx: Add maintainer for Nuvoton NPCM BMC
i2c: npcm7xx: Fix a couple of error codes in probe
i2c: icy: Fix build with CONFIG_AMIGA_PCMCIA=n
i2c: npcm7xx: Remove unnecessary parentheses
i2c: npcm7xx: Add support for slave mode for Nuvoton
i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver
dt-bindings: i2c: npcm7xx: add NPCM I2C controller
i2c: pxa: don't error out if there's no pinctrl
i2c: add 'single-master' property to generic bindings
i2c: designware: Add Baikal-T1 System I2C support
i2c: designware: Move reg-space remapping into a dedicated function
i2c: designware: Retrieve quirk flags as early as possible
i2c: designware: Convert driver to using regmap API
i2c: designware: Discard Cherry Trail model flag
i2c: designware: Add Baytrail sem config DW I2C platform dependency
i2c: designware: slave: Set DW I2C core module dependency
i2c: designware: Use `-y` to build multi-object modules
dt-bindings: i2c: dw: Add Baikal-T1 SoC I2C controller
...
+5869
-1393
-73
Documentation/devicetree/bindings/i2c/i2c-designware.txt
-73
Documentation/devicetree/bindings/i2c/i2c-designware.txt
···
1
-
* Synopsys DesignWare I2C
2
-
3
-
Required properties :
4
-
5
-
- compatible : should be "snps,designware-i2c"
6
-
or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
7
-
- reg : Offset and length of the register set for the device
8
-
- interrupts : <IRQ> where IRQ is the interrupt number.
9
-
- clocks : phandles for the clocks, see the description of clock-names below.
10
-
The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
11
-
clock is optional. If a single clock is specified but no clock-name, it is
12
-
the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
13
-
14
-
Recommended properties :
15
-
16
-
- clock-frequency : desired I2C bus clock frequency in Hz.
17
-
18
-
Optional properties :
19
-
20
-
- clock-names : Contains the names of the clocks:
21
-
"ic_clk", for the core clock used to generate the external I2C clock.
22
-
"pclk", the interface clock, required for register access.
23
-
24
-
- reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
25
-
time, named ICPU_CFG:TWI_DELAY in the datasheet.
26
-
27
-
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
28
-
This option is only supported in hardware blocks version 1.11a or newer and
29
-
on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
30
-
31
-
- i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
32
-
This value which is by default 300ns is used to compute the tLOW period.
33
-
34
-
- i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
35
-
This value which is by default 300ns is used to compute the tHIGH period.
36
-
37
-
Examples :
38
-
39
-
i2c@f0000 {
40
-
#address-cells = <1>;
41
-
#size-cells = <0>;
42
-
compatible = "snps,designware-i2c";
43
-
reg = <0xf0000 0x1000>;
44
-
interrupts = <11>;
45
-
clock-frequency = <400000>;
46
-
};
47
-
48
-
i2c@1120000 {
49
-
#address-cells = <1>;
50
-
#size-cells = <0>;
51
-
compatible = "snps,designware-i2c";
52
-
reg = <0x1120000 0x1000>;
53
-
interrupt-parent = <&ictl>;
54
-
interrupts = <12 1>;
55
-
clock-frequency = <400000>;
56
-
i2c-sda-hold-time-ns = <300>;
57
-
i2c-sda-falling-time-ns = <300>;
58
-
i2c-scl-falling-time-ns = <300>;
59
-
};
60
-
61
-
i2c@1120000 {
62
-
#address-cells = <1>;
63
-
#size-cells = <0>;
64
-
reg = <0x2000 0x100>;
65
-
clock-frequency = <400000>;
66
-
clocks = <&i2cclk>;
67
-
interrupts = <0>;
68
-
69
-
eeprom@64 {
70
-
compatible = "linux,slave-24c02";
71
-
reg = <0x40000064>;
72
-
};
73
-
};
+92
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
+92
Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt
···
1
+
Qualcomm Camera Control Interface (CCI) I2C controller
2
+
3
+
PROPERTIES:
4
+
5
+
- compatible:
6
+
Usage: required
7
+
Value type: <string>
8
+
Definition: must be one of:
9
+
"qcom,msm8916-cci"
10
+
"qcom,msm8996-cci"
11
+
"qcom,sdm845-cci"
12
+
13
+
- reg
14
+
Usage: required
15
+
Value type: <prop-encoded-array>
16
+
Definition: base address CCI I2C controller and length of memory
17
+
mapped region.
18
+
19
+
- interrupts:
20
+
Usage: required
21
+
Value type: <prop-encoded-array>
22
+
Definition: specifies the CCI I2C interrupt. The format of the
23
+
specifier is defined by the binding document describing
24
+
the node's interrupt parent.
25
+
26
+
- clocks:
27
+
Usage: required
28
+
Value type: <prop-encoded-array>
29
+
Definition: a list of phandle, should contain an entry for each
30
+
entries in clock-names.
31
+
32
+
- clock-names
33
+
Usage: required
34
+
Value type: <string>
35
+
Definition: a list of clock names, must include "cci" clock.
36
+
37
+
- power-domains
38
+
Usage: required for "qcom,msm8996-cci"
39
+
Value type: <prop-encoded-array>
40
+
Definition:
41
+
42
+
SUBNODES:
43
+
44
+
The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and
45
+
sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
46
+
47
+
PROPERTIES:
48
+
49
+
- reg:
50
+
Usage: required
51
+
Value type: <u32>
52
+
Definition: Index of the CCI bus/master
53
+
54
+
- clock-frequency:
55
+
Usage: optional
56
+
Value type: <u32>
57
+
Definition: Desired I2C bus clock frequency in Hz, defaults to 100
58
+
kHz if omitted.
59
+
60
+
Example:
61
+
62
+
cci@a0c000 {
63
+
compatible = "qcom,msm8996-cci";
64
+
#address-cells = <1>;
65
+
#size-cells = <0>;
66
+
reg = <0xa0c000 0x1000>;
67
+
interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
68
+
clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
69
+
<&mmcc CAMSS_TOP_AHB_CLK>,
70
+
<&mmcc CAMSS_CCI_AHB_CLK>,
71
+
<&mmcc CAMSS_CCI_CLK>,
72
+
<&mmcc CAMSS_AHB_CLK>;
73
+
clock-names = "mmss_mmagic_ahb",
74
+
"camss_top_ahb",
75
+
"cci_ahb",
76
+
"cci",
77
+
"camss_ahb";
78
+
79
+
i2c-bus@0 {
80
+
reg = <0>;
81
+
clock-frequency = <400000>;
82
+
#address-cells = <1>;
83
+
#size-cells = <0>;
84
+
};
85
+
86
+
i2c-bus@1 {
87
+
reg = <1>;
88
+
clock-frequency = <400000>;
89
+
#address-cells = <1>;
90
+
#size-cells = <0>;
91
+
};
92
+
};
+45
-28
Documentation/devicetree/bindings/i2c/i2c.txt
+45
-28
Documentation/devicetree/bindings/i2c/i2c.txt
···
2
2
===========================================
3
3
4
4
This document describes generic bindings which can be used to describe I2C
5
-
busses in a device tree.
5
+
busses and their child devices in a device tree.
6
6
7
-
Required properties
8
-
-------------------
7
+
Required properties (per bus)
8
+
-----------------------------
9
9
10
10
- #address-cells - should be <1>. Read more about addresses below.
11
11
- #size-cells - should be <0>.
12
-
- compatible - name of I2C bus controller following generic names
13
-
recommended practice.
12
+
- compatible - name of I2C bus controller
14
13
15
14
For other required properties e.g. to describe register sets,
16
15
clocks, etc. check the binding documentation of the specific driver.
17
16
18
17
The cells properties above define that an address of children of an I2C bus
19
-
are described by a single value. This is usually a 7 bit address. However,
20
-
flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10
21
-
bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address
22
-
of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.
23
-
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to
24
-
be devices ourselves.
18
+
are described by a single value.
25
19
26
-
Optional properties
27
-
-------------------
20
+
Optional properties (per bus)
21
+
-----------------------------
28
22
29
23
These properties may not be supported by all drivers. However, if a driver
30
-
wants to support one of the below features, it should adapt the bindings below.
24
+
wants to support one of the below features, it should adapt these bindings.
31
25
32
26
- clock-frequency
33
27
frequency of bus clock in Hz.
···
67
73
i2c bus clock frequency (clock-frequency).
68
74
Specified in Hz.
69
75
76
+
- multi-master
77
+
states that there is another master active on this bus. The OS can use
78
+
this information to adapt power management to keep the arbitration awake
79
+
all the time, for example. Can not be combined with 'single-master'.
80
+
81
+
- single-master
82
+
states that there is no other master active on this bus. The OS can use
83
+
this information to detect a stalled bus more reliably, for example.
84
+
Can not be combined with 'multi-master'.
85
+
86
+
Required properties (per child device)
87
+
--------------------------------------
88
+
89
+
- compatible
90
+
name of I2C slave device
91
+
92
+
- reg
93
+
One or many I2C slave addresses. These are usually a 7 bit addresses.
94
+
However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
95
+
used to mark a 10 bit address. It is needed to avoid the ambiguity
96
+
between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
97
+
which, in theory, can be on the same bus.
98
+
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
99
+
listen to be devices ourselves.
100
+
101
+
Optional properties (per child device)
102
+
--------------------------------------
103
+
104
+
These properties may not be supported by all drivers. However, if a driver
105
+
wants to support one of the below features, it should adapt these bindings.
106
+
107
+
- host-notify
108
+
device uses SMBus host notify protocol instead of interrupt line.
109
+
70
110
- interrupts
71
111
interrupts used by the device.
72
112
···
108
80
"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
109
81
other names are left to individual drivers.
110
82
111
-
- host-notify
112
-
device uses SMBus host notify protocol instead of interrupt line.
113
-
114
-
- multi-master
115
-
states that there is another master active on this bus. The OS can use
116
-
this information to adapt power management to keep the arbitration awake
117
-
all the time, for example.
118
-
119
-
- wakeup-source
120
-
device can be used as a wakeup source.
121
-
122
-
- reg
123
-
I2C slave addresses
124
-
125
83
- reg-names
126
84
Names of map programmable addresses.
127
85
It can contain any map needing another address than default one.
86
+
87
+
- wakeup-source
88
+
device can be used as a wakeup source.
128
89
129
90
Binding may contain optional "interrupts" property, describing interrupts
130
91
used by the device. I2C core will assign "irq" interrupt (or the very first
+62
Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
+62
Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
8
+
9
+
description: |
10
+
The NPCM750x includes sixteen I2C bus controllers. All Controllers support
11
+
both master and slave mode. Each controller can switch between master and slave
12
+
at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
13
+
RX.
14
+
15
+
maintainers:
16
+
- Tali Perry <tali.perry1@gmail.com>
17
+
18
+
properties:
19
+
compatible:
20
+
const: nuvoton,npcm7xx-i2c
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
maxItems: 1
30
+
description: Reference clock for the I2C bus
31
+
32
+
clock-frequency:
33
+
description: Desired I2C bus clock frequency in Hz. If not specified,
34
+
the default 100 kHz frequency will be used.
35
+
possible values are 100000, 400000 and 1000000.
36
+
default: 100000
37
+
enum: [100000, 400000, 1000000]
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- interrupts
43
+
- clocks
44
+
45
+
allOf:
46
+
- $ref: /schemas/i2c/i2c-controller.yaml#
47
+
48
+
unevaluatedProperties: false
49
+
50
+
examples:
51
+
- |
52
+
#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
53
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
54
+
i2c0: i2c@80000 {
55
+
reg = <0x80000 0x1000>;
56
+
clocks = <&clk NPCM7XX_CLK_APB2>;
57
+
clock-frequency = <100000>;
58
+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
59
+
compatible = "nuvoton,npcm750-i2c";
60
+
};
61
+
62
+
...
+156
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+156
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Synopsys DesignWare APB I2C Controller
8
+
9
+
maintainers:
10
+
- Jarkko Nikula <jarkko.nikula@linux.intel.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/i2c/i2c-controller.yaml#
14
+
- if:
15
+
properties:
16
+
compatible:
17
+
not:
18
+
contains:
19
+
const: mscc,ocelot-i2c
20
+
then:
21
+
properties:
22
+
reg:
23
+
maxItems: 1
24
+
25
+
properties:
26
+
compatible:
27
+
oneOf:
28
+
- description: Generic Synopsys DesignWare I2C controller
29
+
const: snps,designware-i2c
30
+
- description: Microsemi Ocelot SoCs I2C controller
31
+
items:
32
+
- const: mscc,ocelot-i2c
33
+
- const: snps,designware-i2c
34
+
- description: Baikal-T1 SoC System I2C controller
35
+
const: baikal,bt1-sys-i2c
36
+
37
+
reg:
38
+
minItems: 1
39
+
items:
40
+
- description: DW APB I2C controller memory mapped registers
41
+
- description: |
42
+
ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
43
+
This registers are specific to the Ocelot I2C-controller.
44
+
45
+
interrupts:
46
+
maxItems: 1
47
+
48
+
clocks:
49
+
minItems: 1
50
+
items:
51
+
- description: I2C controller reference clock source
52
+
- description: APB interface clock source
53
+
54
+
clock-names:
55
+
minItems: 1
56
+
items:
57
+
- const: ref
58
+
- const: pclk
59
+
60
+
resets:
61
+
maxItems: 1
62
+
63
+
clock-frequency:
64
+
description: Desired I2C bus clock frequency in Hz
65
+
enum: [100000, 400000, 1000000, 3400000]
66
+
default: 400000
67
+
68
+
i2c-sda-hold-time-ns:
69
+
maxItems: 1
70
+
description: |
71
+
The property should contain the SDA hold time in nanoseconds. This option
72
+
is only supported in hardware blocks version 1.11a or newer or on
73
+
Microsemi SoCs.
74
+
75
+
i2c-scl-falling-time-ns:
76
+
maxItems: 1
77
+
description: |
78
+
The property should contain the SCL falling time in nanoseconds.
79
+
This value is used to compute the tLOW period.
80
+
default: 300
81
+
82
+
i2c-sda-falling-time-ns:
83
+
maxItems: 1
84
+
description: |
85
+
The property should contain the SDA falling time in nanoseconds.
86
+
This value is used to compute the tHIGH period.
87
+
default: 300
88
+
89
+
dmas:
90
+
items:
91
+
- description: TX DMA Channel
92
+
- description: RX DMA Channel
93
+
94
+
dma-names:
95
+
items:
96
+
- const: tx
97
+
- const: rx
98
+
99
+
unevaluatedProperties: false
100
+
101
+
required:
102
+
- compatible
103
+
- reg
104
+
- "#address-cells"
105
+
- "#size-cells"
106
+
- interrupts
107
+
108
+
examples:
109
+
- |
110
+
i2c@f0000 {
111
+
compatible = "snps,designware-i2c";
112
+
reg = <0xf0000 0x1000>;
113
+
#address-cells = <1>;
114
+
#size-cells = <0>;
115
+
interrupts = <11>;
116
+
clock-frequency = <400000>;
117
+
};
118
+
- |
119
+
i2c@1120000 {
120
+
compatible = "snps,designware-i2c";
121
+
reg = <0x1120000 0x1000>;
122
+
#address-cells = <1>;
123
+
#size-cells = <0>;
124
+
interrupts = <12 1>;
125
+
clock-frequency = <400000>;
126
+
i2c-sda-hold-time-ns = <300>;
127
+
i2c-sda-falling-time-ns = <300>;
128
+
i2c-scl-falling-time-ns = <300>;
129
+
};
130
+
- |
131
+
i2c@2000 {
132
+
compatible = "snps,designware-i2c";
133
+
reg = <0x2000 0x100>;
134
+
#address-cells = <1>;
135
+
#size-cells = <0>;
136
+
clock-frequency = <400000>;
137
+
clocks = <&i2cclk>;
138
+
interrupts = <0>;
139
+
140
+
eeprom@64 {
141
+
compatible = "atmel,24c02";
142
+
reg = <0x64>;
143
+
};
144
+
};
145
+
- |
146
+
i2c@100400 {
147
+
compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
148
+
reg = <0x100400 0x100>, <0x198 0x8>;
149
+
pinctrl-0 = <&i2c_pins>;
150
+
pinctrl-names = "default";
151
+
#address-cells = <1>;
152
+
#size-cells = <0>;
153
+
interrupts = <8>;
154
+
clocks = <&ahb_clk>;
155
+
};
156
+
...
+4
-4
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+4
-4
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
···
81
81
clock-frequency:
82
82
description: Desired I2C bus clock frequency in Hz. If not specified,
83
83
the default 100 kHz frequency will be used.
84
-
For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode,
85
-
Fast-mode and Fast-mode Plus are supported, possible
86
-
values are 100000, 400000 and 1000000.
84
+
For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters
85
+
match, the bus clock frequency can be from 1Hz to 1MHz.
87
86
default: 100000
88
-
enum: [100000, 400000, 1000000]
87
+
minimum: 1
88
+
maximum: 1000000
89
89
90
90
required:
91
91
- compatible
+1
MAINTAINERS
+1
MAINTAINERS
+45
-23
drivers/i2c/busses/Kconfig
+45
-23
drivers/i2c/busses/Kconfig
···
475
475
476
476
config I2C_BRCMSTB
477
477
tristate "BRCM Settop/DSL I2C controller"
478
-
depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_63XX || \
479
-
COMPILE_TEST
478
+
depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
479
+
ARCH_BCM_63XX || COMPILE_TEST
480
480
default y
481
481
help
482
482
If you say yes to this option, support will be included for the
···
526
526
527
527
config I2C_DESIGNWARE_CORE
528
528
tristate
529
+
select REGMAP
530
+
531
+
config I2C_DESIGNWARE_SLAVE
532
+
bool "Synopsys DesignWare Slave"
533
+
depends on I2C_DESIGNWARE_CORE
534
+
select I2C_SLAVE
535
+
help
536
+
If you say yes to this option, support will be included for the
537
+
Synopsys DesignWare I2C slave adapter.
538
+
539
+
This is not a standalone module, this module compiles together with
540
+
i2c-designware-core.
529
541
530
542
config I2C_DESIGNWARE_PLATFORM
531
543
tristate "Synopsys DesignWare Platform"
532
-
select I2C_DESIGNWARE_CORE
533
544
depends on (ACPI && COMMON_CLK) || !ACPI
545
+
select I2C_DESIGNWARE_CORE
546
+
select MFD_SYSCON if MIPS_BAIKAL_T1
534
547
help
535
548
If you say yes to this option, support will be included for the
536
549
Synopsys DesignWare I2C adapter.
···
551
538
This driver can also be built as a module. If so, the module
552
539
will be called i2c-designware-platform.
553
540
554
-
config I2C_DESIGNWARE_SLAVE
555
-
bool "Synopsys DesignWare Slave"
556
-
select I2C_SLAVE
541
+
config I2C_DESIGNWARE_BAYTRAIL
542
+
bool "Intel Baytrail I2C semaphore support"
543
+
depends on ACPI
557
544
depends on I2C_DESIGNWARE_PLATFORM
545
+
depends on (I2C_DESIGNWARE_PLATFORM=m && IOSF_MBI) || \
546
+
(I2C_DESIGNWARE_PLATFORM=y && IOSF_MBI=y)
558
547
help
559
-
If you say yes to this option, support will be included for the
560
-
Synopsys DesignWare I2C slave adapter.
561
-
562
-
This is not a standalone module, this module compiles together with
563
-
i2c-designware-core.
548
+
This driver enables managed host access to the PMIC I2C bus on select
549
+
Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows
550
+
the host to request uninterrupted access to the PMIC's I2C bus from
551
+
the platform firmware controlling it. You should say Y if running on
552
+
a BayTrail system using the AXP288.
564
553
565
554
config I2C_DESIGNWARE_PCI
566
555
tristate "Synopsys DesignWare PCI"
···
574
559
575
560
This driver can also be built as a module. If so, the module
576
561
will be called i2c-designware-pci.
577
-
578
-
config I2C_DESIGNWARE_BAYTRAIL
579
-
bool "Intel Baytrail I2C semaphore support"
580
-
depends on ACPI
581
-
depends on (I2C_DESIGNWARE_PLATFORM=m && IOSF_MBI) || \
582
-
(I2C_DESIGNWARE_PLATFORM=y && IOSF_MBI=y)
583
-
help
584
-
This driver enables managed host access to the PMIC I2C bus on select
585
-
Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows
586
-
the host to request uninterrupted access to the PMIC's I2C bus from
587
-
the platform firmware controlling it. You should say Y if running on
588
-
a BayTrail system using the AXP288.
589
562
590
563
config I2C_DIGICOLOR
591
564
tristate "Conexant Digicolor I2C driver"
···
794
791
I2C interface from ST-Ericsson's Nomadik and Ux500 architectures,
795
792
as well as the STA2X11 PCIe I/O HUB.
796
793
794
+
config I2C_NPCM7XX
795
+
tristate "Nuvoton I2C Controller"
796
+
depends on ARCH_NPCM7XX || COMPILE_TEST
797
+
help
798
+
If you say yes to this option, support will be included for the
799
+
Nuvoton I2C controller, which is available on the NPCM7xx BMC
800
+
controller.
801
+
Driver can also support slave mode (select I2C_SLAVE).
802
+
797
803
config I2C_OCORES
798
804
tristate "OpenCores I2C Controller"
799
805
help
···
896
884
Support I2C slave mode communications on the PXA I2C bus. This
897
885
is necessary for systems where the PXA may be a target on the
898
886
I2C bus.
887
+
888
+
config I2C_QCOM_CCI
889
+
tristate "Qualcomm Camera Control Interface"
890
+
depends on ARCH_QCOM || COMPILE_TEST
891
+
help
892
+
If you say yes to this option, support will be included for the
893
+
built-in camera control interface on the Qualcomm SoCs.
894
+
895
+
This driver can also be built as a module. If so, the module
896
+
will be called i2c-qcom-cci.
899
897
900
898
config I2C_QCOM_GENI
901
899
tristate "Qualcomm Technologies Inc.'s GENI based I2C controller"
+10
-9
drivers/i2c/busses/Makefile
+10
-9
drivers/i2c/busses/Makefile
···
48
48
obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
49
49
obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
50
50
obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
51
-
obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
52
-
i2c-designware-core-objs := i2c-designware-common.o i2c-designware-master.o
53
-
ifeq ($(CONFIG_I2C_DESIGNWARE_SLAVE),y)
54
-
i2c-designware-core-objs += i2c-designware-slave.o
55
-
endif
56
-
obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
57
-
i2c-designware-platform-objs := i2c-designware-platdrv.o
51
+
obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
52
+
i2c-designware-core-y := i2c-designware-common.o
53
+
i2c-designware-core-y += i2c-designware-master.o
54
+
i2c-designware-core-$(CONFIG_I2C_DESIGNWARE_SLAVE) += i2c-designware-slave.o
55
+
obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
56
+
i2c-designware-platform-y := i2c-designware-platdrv.o
58
57
i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o
59
-
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
60
-
i2c-designware-pci-objs := i2c-designware-pcidrv.o
58
+
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
59
+
i2c-designware-pci-y := i2c-designware-pcidrv.o
61
60
obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
62
61
obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
63
62
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
···
80
81
obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
81
82
obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
82
83
obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
84
+
obj-$(CONFIG_I2C_NPCM7XX) += i2c-npcm7xx.o
83
85
obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
84
86
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
85
87
obj-$(CONFIG_I2C_OWL) += i2c-owl.o
···
91
91
obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
92
92
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
93
93
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
94
+
obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o
94
95
obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
95
96
obj-$(CONFIG_I2C_QUP) += i2c-qup.o
96
97
obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
+6
-14
drivers/i2c/busses/i2c-altera.c
+6
-14
drivers/i2c/busses/i2c-altera.c
···
69
69
* @fifo_size: size of the FIFO passed in.
70
70
* @isr_mask: cached copy of local ISR enables.
71
71
* @isr_status: cached copy of local ISR status.
72
-
* @lock: spinlock for IRQ synchronization.
73
72
* @isr_mutex: mutex for IRQ thread.
74
73
*/
75
74
struct altr_i2c_dev {
···
85
86
u32 fifo_size;
86
87
u32 isr_mask;
87
88
u32 isr_status;
88
-
spinlock_t lock; /* IRQ synchronization */
89
89
struct mutex isr_mutex;
90
90
};
91
91
92
92
static void
93
93
altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
94
94
{
95
-
unsigned long flags;
96
95
u32 int_en;
97
-
98
-
spin_lock_irqsave(&idev->lock, flags);
99
96
100
97
int_en = readl(idev->base + ALTR_I2C_ISER);
101
98
if (enable)
···
100
105
idev->isr_mask = int_en & ~mask;
101
106
102
107
writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
103
-
104
-
spin_unlock_irqrestore(&idev->lock, flags);
105
108
}
106
109
107
110
static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
···
339
346
340
347
time_left = wait_for_completion_timeout(&idev->msg_complete,
341
348
ALTR_I2C_XFER_TIMEOUT);
349
+
mutex_lock(&idev->isr_mutex);
342
350
altr_i2c_int_enable(idev, imask, false);
343
351
344
352
value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE;
···
352
358
}
353
359
354
360
altr_i2c_core_disable(idev);
361
+
mutex_unlock(&idev->isr_mutex);
355
362
356
363
return idev->msg_err;
357
364
}
···
384
389
static int altr_i2c_probe(struct platform_device *pdev)
385
390
{
386
391
struct altr_i2c_dev *idev = NULL;
387
-
struct resource *res;
388
392
int irq, ret;
389
393
390
394
idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
391
395
if (!idev)
392
396
return -ENOMEM;
393
397
394
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
395
-
idev->base = devm_ioremap_resource(&pdev->dev, res);
398
+
idev->base = devm_platform_ioremap_resource(pdev, 0);
396
399
if (IS_ERR(idev->base))
397
400
return PTR_ERR(idev->base);
398
401
399
402
irq = platform_get_irq(pdev, 0);
400
-
if (irq < 0) {
401
-
dev_err(&pdev->dev, "missing interrupt resource\n");
403
+
if (irq < 0)
402
404
return irq;
403
-
}
404
405
405
406
idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
406
407
if (IS_ERR(idev->i2c_clk)) {
···
406
415
407
416
idev->dev = &pdev->dev;
408
417
init_completion(&idev->msg_complete);
409
-
spin_lock_init(&idev->lock);
410
418
mutex_init(&idev->isr_mutex);
411
419
412
420
ret = device_property_read_u32(idev->dev, "fifo-size",
···
443
453
return ret;
444
454
}
445
455
456
+
mutex_lock(&idev->isr_mutex);
446
457
altr_i2c_init(idev);
458
+
mutex_unlock(&idev->isr_mutex);
447
459
448
460
i2c_set_adapdata(&idev->adapter, idev);
449
461
strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
+2
drivers/i2c/busses/i2c-at91-core.c
+2
drivers/i2c/busses/i2c-at91-core.c
···
131
131
.has_dig_filtr = true,
132
132
.has_adv_dig_filtr = true,
133
133
.has_ana_filtr = true,
134
+
.has_clear_cmd = false, /* due to errata, CLEAR cmd is not working */
134
135
};
135
136
136
137
static struct at91_twi_pdata sam9x60_config = {
···
143
142
.has_dig_filtr = true,
144
143
.has_adv_dig_filtr = true,
145
144
.has_ana_filtr = true,
145
+
.has_clear_cmd = true,
146
146
};
147
147
148
148
static const struct of_device_id atmel_twi_dt_ids[] = {
+42
-7
drivers/i2c/busses/i2c-at91-master.c
+42
-7
drivers/i2c/busses/i2c-at91-master.c
···
480
480
unsigned long time_left;
481
481
bool has_unre_flag = dev->pdata->has_unre_flag;
482
482
bool has_alt_cmd = dev->pdata->has_alt_cmd;
483
-
struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
484
483
485
484
/*
486
485
* WARNING: the TXCOMP bit in the Status Register is NOT a clear on
···
640
641
AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
641
642
}
642
643
643
-
if (rinfo->get_sda && !(rinfo->get_sda(&dev->adapter))) {
644
-
dev_dbg(dev->dev,
645
-
"SDA is down; clear bus using gpio\n");
646
-
i2c_recover_bus(&dev->adapter);
647
-
}
644
+
/*
645
+
* some faulty I2C slave devices might hold SDA down;
646
+
* we can send a bus clear command, hoping that the pins will be
647
+
* released
648
+
*/
649
+
i2c_recover_bus(&dev->adapter);
648
650
649
651
return ret;
650
652
}
···
830
830
pinctrl_select_state(dev->pinctrl, dev->pinctrl_pins_default);
831
831
}
832
832
833
-
static int at91_init_twi_recovery_info(struct platform_device *pdev,
833
+
static int at91_init_twi_recovery_gpio(struct platform_device *pdev,
834
834
struct at91_twi_dev *dev)
835
835
{
836
836
struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
···
889
889
rinfo->prepare_recovery = at91_prepare_twi_recovery;
890
890
rinfo->unprepare_recovery = at91_unprepare_twi_recovery;
891
891
rinfo->recover_bus = i2c_generic_scl_recovery;
892
+
dev->adapter.bus_recovery_info = rinfo;
893
+
894
+
return 0;
895
+
}
896
+
897
+
static int at91_twi_recover_bus_cmd(struct i2c_adapter *adap)
898
+
{
899
+
struct at91_twi_dev *dev = i2c_get_adapdata(adap);
900
+
901
+
dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
902
+
if (!(dev->transfer_status & AT91_TWI_SDA)) {
903
+
dev_dbg(dev->dev, "SDA is down; sending bus clear command\n");
904
+
if (dev->use_alt_cmd) {
905
+
unsigned int acr;
906
+
907
+
acr = at91_twi_read(dev, AT91_TWI_ACR);
908
+
acr &= ~AT91_TWI_ACR_DATAL_MASK;
909
+
at91_twi_write(dev, AT91_TWI_ACR, acr);
910
+
}
911
+
at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_CLEAR);
912
+
}
913
+
914
+
return 0;
915
+
}
916
+
917
+
static int at91_init_twi_recovery_info(struct platform_device *pdev,
918
+
struct at91_twi_dev *dev)
919
+
{
920
+
struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
921
+
bool has_clear_cmd = dev->pdata->has_clear_cmd;
922
+
923
+
if (!has_clear_cmd)
924
+
return at91_init_twi_recovery_gpio(pdev, dev);
925
+
926
+
rinfo->recover_bus = at91_twi_recover_bus_cmd;
892
927
dev->adapter.bus_recovery_info = rinfo;
893
928
894
929
return 0;
+6
-1
drivers/i2c/busses/i2c-at91.h
+6
-1
drivers/i2c/busses/i2c-at91.h
···
36
36
#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
37
37
#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
38
38
#define AT91_TWI_SWRST BIT(7) /* Software Reset */
39
+
#define AT91_TWI_CLEAR BIT(15) /* Bus clear command */
39
40
#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
40
41
#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
41
42
#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
···
70
69
#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
71
70
#define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */
72
71
#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
72
+
#define AT91_TWI_SCL BIT(24) /* TWI SCL status */
73
+
#define AT91_TWI_SDA BIT(25) /* TWI SDA status */
73
74
74
75
#define AT91_TWI_INT_MASK \
75
76
(AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \
···
84
81
#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
85
82
86
83
#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
87
-
#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
84
+
#define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0)
85
+
#define AT91_TWI_ACR_DATAL(len) ((len) & AT91_TWI_ACR_DATAL_MASK)
88
86
#define AT91_TWI_ACR_DIR BIT(8)
89
87
90
88
#define AT91_TWI_FILTR 0x0044
···
122
118
bool has_dig_filtr;
123
119
bool has_adv_dig_filtr;
124
120
bool has_ana_filtr;
121
+
bool has_clear_cmd;
125
122
struct at_dma_slave dma_slave;
126
123
};
127
124
+2
-6
drivers/i2c/busses/i2c-axxia.c
+2
-6
drivers/i2c/busses/i2c-axxia.c
···
734
734
{
735
735
struct device_node *np = pdev->dev.of_node;
736
736
struct axxia_i2c_dev *idev = NULL;
737
-
struct resource *res;
738
737
void __iomem *base;
739
738
int ret = 0;
740
739
···
741
742
if (!idev)
742
743
return -ENOMEM;
743
744
744
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
745
-
base = devm_ioremap_resource(&pdev->dev, res);
745
+
base = devm_platform_ioremap_resource(pdev, 0);
746
746
if (IS_ERR(base))
747
747
return PTR_ERR(base);
748
748
749
749
idev->irq = platform_get_irq(pdev, 0);
750
-
if (idev->irq < 0) {
751
-
dev_err(&pdev->dev, "missing interrupt resource\n");
750
+
if (idev->irq < 0)
752
751
return idev->irq;
753
-
}
754
752
755
753
idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
756
754
if (IS_ERR(idev->i2c_clk)) {
+7
-3
drivers/i2c/busses/i2c-bcm-iproc.c
+7
-3
drivers/i2c/busses/i2c-bcm-iproc.c
···
79
79
#define M_CMD_STATUS_RX_FIFO_FULL 0x6
80
80
#define M_CMD_PROTOCOL_SHIFT 9
81
81
#define M_CMD_PROTOCOL_MASK 0xf
82
+
#define M_CMD_PROTOCOL_QUICK 0x0
82
83
#define M_CMD_PROTOCOL_BLK_WR 0x7
83
84
#define M_CMD_PROTOCOL_BLK_RD 0x8
84
85
#define M_CMD_PROTOCOL_PROCESS 0xa
···
769
768
* number of bytes to read
770
769
*/
771
770
val = BIT(M_CMD_START_BUSY_SHIFT);
772
-
if (msg->flags & I2C_M_RD) {
771
+
772
+
if (msg->len == 0) {
773
+
/* SMBUS QUICK Command (Read/Write) */
774
+
val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
775
+
} else if (msg->flags & I2C_M_RD) {
773
776
u32 protocol;
774
777
775
778
iproc_i2c->rx_bytes = 0;
···
835
830
{
836
831
u32 val;
837
832
838
-
/* We do not support the SMBUS Quick command */
839
-
val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
833
+
val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
840
834
841
835
if (adap->algo->reg_slave)
842
836
val |= I2C_FUNC_SLAVE;
+2
-5
drivers/i2c/busses/i2c-bcm-kona.c
+2
-5
drivers/i2c/busses/i2c-bcm-kona.c
···
750
750
int rc = 0;
751
751
struct bcm_kona_i2c_dev *dev;
752
752
struct i2c_adapter *adap;
753
-
struct resource *iomem;
754
753
755
754
/* Allocate memory for private data structure */
756
755
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
···
761
762
init_completion(&dev->done);
762
763
763
764
/* Map hardware registers */
764
-
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
765
-
dev->base = devm_ioremap_resource(dev->device, iomem);
765
+
dev->base = devm_platform_ioremap_resource(pdev, 0);
766
766
if (IS_ERR(dev->base))
767
767
return -ENOMEM;
768
768
···
821
823
/* Get the interrupt number */
822
824
dev->irq = platform_get_irq(pdev, 0);
823
825
if (dev->irq < 0) {
824
-
dev_err(dev->device, "no irq resource\n");
825
-
rc = -ENODEV;
826
+
rc = dev->irq;
826
827
goto probe_disable_clk;
827
828
}
828
829
+10
-8
drivers/i2c/busses/i2c-brcmstb.c
+10
-8
drivers/i2c/busses/i2c-brcmstb.c
···
647
647
int_name = NULL;
648
648
649
649
/* Get the interrupt number */
650
-
dev->irq = platform_get_irq(pdev, 0);
650
+
dev->irq = platform_get_irq_optional(pdev, 0);
651
651
652
652
/* disable the bsc interrupt line */
653
653
brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
654
654
655
655
/* register the ISR handler */
656
-
rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
657
-
IRQF_SHARED,
658
-
int_name ? int_name : pdev->name,
659
-
dev);
656
+
if (dev->irq >= 0) {
657
+
rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
658
+
IRQF_SHARED,
659
+
int_name ? int_name : pdev->name,
660
+
dev);
660
661
661
-
if (rc) {
662
-
dev_dbg(dev->device, "falling back to polling mode");
663
-
dev->irq = -1;
662
+
if (rc) {
663
+
dev_dbg(dev->device, "falling back to polling mode");
664
+
dev->irq = -1;
665
+
}
664
666
}
665
667
666
668
if (of_property_read_u32(dev->device->of_node,
+311
-14
drivers/i2c/busses/i2c-cadence.c
+311
-14
drivers/i2c/busses/i2c-cadence.c
···
23
23
#define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
24
24
#define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
25
25
#define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
26
+
#define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
26
27
#define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
27
28
#define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
28
29
···
41
40
#define CDNS_I2C_CR_DIVB_SHIFT 8
42
41
#define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
43
42
43
+
#define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
44
+
CDNS_I2C_CR_ACK_EN | \
45
+
CDNS_I2C_CR_MS)
46
+
47
+
#define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
48
+
44
49
/* Status Register Bit mask definitions */
45
50
#define CDNS_I2C_SR_BA BIT(8)
51
+
#define CDNS_I2C_SR_TXDV BIT(6)
46
52
#define CDNS_I2C_SR_RXDV BIT(5)
53
+
#define CDNS_I2C_SR_RXRW BIT(3)
47
54
48
55
/*
49
56
* I2C Address Register Bit mask definitions
···
100
91
CDNS_I2C_IXR_DATA | \
101
92
CDNS_I2C_IXR_COMP)
102
93
94
+
#define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
95
+
CDNS_I2C_IXR_TX_OVF | \
96
+
CDNS_I2C_IXR_RX_OVF | \
97
+
CDNS_I2C_IXR_TO | \
98
+
CDNS_I2C_IXR_NACK | \
99
+
CDNS_I2C_IXR_DATA | \
100
+
CDNS_I2C_IXR_COMP)
101
+
103
102
#define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
104
103
/* timeout for pm runtime autosuspend */
105
104
#define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
···
131
114
#define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
132
115
#define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
133
116
117
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
118
+
/**
119
+
* enum cdns_i2c_mode - I2C Controller current operating mode
120
+
*
121
+
* @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
122
+
* @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
123
+
*/
124
+
enum cdns_i2c_mode {
125
+
CDNS_I2C_MODE_SLAVE,
126
+
CDNS_I2C_MODE_MASTER,
127
+
};
128
+
129
+
/**
130
+
* enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode
131
+
*
132
+
* @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
133
+
* @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
134
+
* @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
135
+
*/
136
+
enum cdns_i2c_slave_state {
137
+
CDNS_I2C_SLAVE_STATE_IDLE,
138
+
CDNS_I2C_SLAVE_STATE_SEND,
139
+
CDNS_I2C_SLAVE_STATE_RECV,
140
+
};
141
+
#endif
142
+
134
143
/**
135
144
* struct cdns_i2c - I2C device private data structure
136
145
*
···
178
135
* @clk: Pointer to struct clk
179
136
* @clk_rate_change_nb: Notifier block for clock rate changes
180
137
* @quirks: flag for broken hold bit usage in r1p10
138
+
* @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
139
+
* @slave: Registered slave instance.
140
+
* @dev_mode: I2C operating role(master/slave).
141
+
* @slave_state: I2C Slave state(idle/read/write).
181
142
*/
182
143
struct cdns_i2c {
183
144
struct device *dev;
···
202
155
struct clk *clk;
203
156
struct notifier_block clk_rate_change_nb;
204
157
u32 quirks;
158
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
159
+
u16 ctrl_reg_diva_divb;
160
+
struct i2c_client *slave;
161
+
enum cdns_i2c_mode dev_mode;
162
+
enum cdns_i2c_slave_state slave_state;
163
+
#endif
205
164
};
206
165
207
166
struct cdns_platform_data {
···
236
183
(id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
237
184
}
238
185
186
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
187
+
static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
188
+
{
189
+
/* Disable all interrupts */
190
+
cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
191
+
192
+
/* Clear FIFO and transfer size */
193
+
cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
194
+
195
+
/* Update device mode and state */
196
+
id->dev_mode = mode;
197
+
id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
198
+
199
+
switch (mode) {
200
+
case CDNS_I2C_MODE_MASTER:
201
+
/* Enable i2c master */
202
+
cdns_i2c_writereg(id->ctrl_reg_diva_divb |
203
+
CDNS_I2C_CR_MASTER_EN_MASK,
204
+
CDNS_I2C_CR_OFFSET);
205
+
/*
206
+
* This delay is needed to give the IP some time to switch to
207
+
* the master mode. With lower values(like 110 us) i2cdetect
208
+
* will not detect any slave and without this delay, the IP will
209
+
* trigger a timeout interrupt.
210
+
*/
211
+
usleep_range(115, 125);
212
+
break;
213
+
case CDNS_I2C_MODE_SLAVE:
214
+
/* Enable i2c slave */
215
+
cdns_i2c_writereg(id->ctrl_reg_diva_divb &
216
+
CDNS_I2C_CR_SLAVE_EN_MASK,
217
+
CDNS_I2C_CR_OFFSET);
218
+
219
+
/* Setting slave address */
220
+
cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
221
+
CDNS_I2C_ADDR_OFFSET);
222
+
223
+
/* Enable slave send/receive interrupts */
224
+
cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
225
+
CDNS_I2C_IER_OFFSET);
226
+
break;
227
+
}
228
+
}
229
+
230
+
static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
231
+
{
232
+
u8 bytes;
233
+
unsigned char data;
234
+
235
+
/* Prepare backend for data reception */
236
+
if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
237
+
id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
238
+
i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
239
+
}
240
+
241
+
/* Fetch number of bytes to receive */
242
+
bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
243
+
244
+
/* Read data and send to backend */
245
+
while (bytes--) {
246
+
data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
247
+
i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
248
+
}
249
+
}
250
+
251
+
static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
252
+
{
253
+
u8 data;
254
+
255
+
/* Prepare backend for data transmission */
256
+
if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
257
+
id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
258
+
i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
259
+
} else {
260
+
i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
261
+
}
262
+
263
+
/* Send data over bus */
264
+
cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
265
+
}
266
+
239
267
/**
240
-
* cdns_i2c_isr - Interrupt handler for the I2C device
241
-
* @irq: irq number for the I2C device
242
-
* @ptr: void pointer to cdns_i2c structure
268
+
* cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
269
+
* @ptr: Pointer to I2C device private data
243
270
*
244
-
* This function handles the data interrupt, transfer complete interrupt and
245
-
* the error interrupts of the I2C device.
271
+
* This function handles the data interrupt and transfer complete interrupt of
272
+
* the I2C device in slave role.
246
273
*
247
274
* Return: IRQ_HANDLED always
248
275
*/
249
-
static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
276
+
static irqreturn_t cdns_i2c_slave_isr(void *ptr)
277
+
{
278
+
struct cdns_i2c *id = ptr;
279
+
unsigned int isr_status, i2c_status;
280
+
281
+
/* Fetch the interrupt status */
282
+
isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
283
+
cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
284
+
285
+
/* Ignore masked interrupts */
286
+
isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
287
+
288
+
/* Fetch transfer mode (send/receive) */
289
+
i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
290
+
291
+
/* Handle data send/receive */
292
+
if (i2c_status & CDNS_I2C_SR_RXRW) {
293
+
/* Send data to master */
294
+
if (isr_status & CDNS_I2C_IXR_DATA)
295
+
cdns_i2c_slave_send_data(id);
296
+
297
+
if (isr_status & CDNS_I2C_IXR_COMP) {
298
+
id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
299
+
i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
300
+
}
301
+
} else {
302
+
/* Receive data from master */
303
+
if (isr_status & CDNS_I2C_IXR_DATA)
304
+
cdns_i2c_slave_rcv_data(id);
305
+
306
+
if (isr_status & CDNS_I2C_IXR_COMP) {
307
+
cdns_i2c_slave_rcv_data(id);
308
+
id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
309
+
i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
310
+
}
311
+
}
312
+
313
+
/* Master indicated xfer stop or fifo underflow/overflow */
314
+
if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
315
+
CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
316
+
id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
317
+
i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
318
+
cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
319
+
}
320
+
321
+
return IRQ_HANDLED;
322
+
}
323
+
#endif
324
+
325
+
/**
326
+
* cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
327
+
* @ptr: Pointer to I2C device private data
328
+
*
329
+
* This function handles the data interrupt, transfer complete interrupt and
330
+
* the error interrupts of the I2C device in master role.
331
+
*
332
+
* Return: IRQ_HANDLED always
333
+
*/
334
+
static irqreturn_t cdns_i2c_master_isr(void *ptr)
250
335
{
251
336
unsigned int isr_status, avail_bytes, updatetx;
252
337
unsigned int bytes_to_send;
···
546
355
complete(&id->xfer_done);
547
356
548
357
return status;
358
+
}
359
+
360
+
/**
361
+
* cdns_i2c_isr - Interrupt handler for the I2C device
362
+
* @irq: irq number for the I2C device
363
+
* @ptr: void pointer to cdns_i2c structure
364
+
*
365
+
* This function passes the control to slave/master based on current role of
366
+
* i2c controller.
367
+
*
368
+
* Return: IRQ_HANDLED always
369
+
*/
370
+
static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
371
+
{
372
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
373
+
struct cdns_i2c *id = ptr;
374
+
375
+
if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
376
+
return cdns_i2c_slave_isr(ptr);
377
+
#endif
378
+
return cdns_i2c_master_isr(ptr);
549
379
}
550
380
551
381
/**
···
789
577
u32 reg;
790
578
struct cdns_i2c *id = adap->algo_data;
791
579
bool hold_quirk;
580
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
581
+
bool change_role = false;
582
+
#endif
792
583
793
584
ret = pm_runtime_get_sync(id->dev);
794
585
if (ret < 0)
795
586
return ret;
587
+
588
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
589
+
/* Check i2c operating mode and switch if possible */
590
+
if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
591
+
if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE)
592
+
return -EAGAIN;
593
+
594
+
/* Set mode to master */
595
+
cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
596
+
597
+
/* Mark flag to change role once xfer is completed */
598
+
change_role = true;
599
+
}
600
+
#endif
601
+
796
602
/* Check if the bus is free */
797
603
if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) {
798
604
ret = -EAGAIN;
···
869
639
}
870
640
871
641
ret = num;
642
+
872
643
out:
644
+
645
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
646
+
/* Switch i2c mode to slave */
647
+
if (change_role)
648
+
cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
649
+
#endif
650
+
873
651
pm_runtime_mark_last_busy(id->dev);
874
652
pm_runtime_put_autosuspend(id->dev);
875
653
return ret;
···
891
653
*/
892
654
static u32 cdns_i2c_func(struct i2c_adapter *adap)
893
655
{
894
-
return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
895
-
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
896
-
I2C_FUNC_SMBUS_BLOCK_DATA;
656
+
u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
657
+
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
658
+
I2C_FUNC_SMBUS_BLOCK_DATA;
659
+
660
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
661
+
func |= I2C_FUNC_SLAVE;
662
+
#endif
663
+
664
+
return func;
897
665
}
666
+
667
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
668
+
static int cdns_reg_slave(struct i2c_client *slave)
669
+
{
670
+
int ret;
671
+
struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
672
+
adap);
673
+
674
+
if (id->slave)
675
+
return -EBUSY;
676
+
677
+
if (slave->flags & I2C_CLIENT_TEN)
678
+
return -EAFNOSUPPORT;
679
+
680
+
ret = pm_runtime_get_sync(id->dev);
681
+
if (ret < 0)
682
+
return ret;
683
+
684
+
/* Store slave information */
685
+
id->slave = slave;
686
+
687
+
/* Enable I2C slave */
688
+
cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
689
+
690
+
return 0;
691
+
}
692
+
693
+
static int cdns_unreg_slave(struct i2c_client *slave)
694
+
{
695
+
struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
696
+
adap);
697
+
698
+
pm_runtime_put(id->dev);
699
+
700
+
/* Remove slave information */
701
+
id->slave = NULL;
702
+
703
+
/* Enable I2C master */
704
+
cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
705
+
706
+
return 0;
707
+
}
708
+
#endif
898
709
899
710
static const struct i2c_algorithm cdns_i2c_algo = {
900
711
.master_xfer = cdns_i2c_master_xfer,
901
712
.functionality = cdns_i2c_func,
713
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
714
+
.reg_slave = cdns_reg_slave,
715
+
.unreg_slave = cdns_unreg_slave,
716
+
#endif
902
717
};
903
718
904
719
/**
···
1046
755
ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1047
756
(div_b << CDNS_I2C_CR_DIVB_SHIFT));
1048
757
cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1049
-
758
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
759
+
id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
760
+
CDNS_I2C_CR_DIVB_MASK);
761
+
#endif
1050
762
return 0;
1051
763
}
1052
764
···
1200
906
id->quirks = data->quirks;
1201
907
}
1202
908
1203
-
r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204
-
id->membase = devm_ioremap_resource(&pdev->dev, r_mem);
909
+
id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1205
910
if (IS_ERR(id->membase))
1206
911
return PTR_ERR(id->membase);
1207
912
···
1242
949
if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1243
950
id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1244
951
1245
-
cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS,
1246
-
CDNS_I2C_CR_OFFSET);
952
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
953
+
/* Set initial mode to master */
954
+
id->dev_mode = CDNS_I2C_MODE_MASTER;
955
+
id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
956
+
#endif
957
+
cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET);
1247
958
1248
959
ret = cdns_i2c_setclk(id->input_clk, id);
1249
960
if (ret) {
+2
-4
drivers/i2c/busses/i2c-cht-wc.c
+2
-4
drivers/i2c/busses/i2c-cht-wc.c
···
314
314
int ret, reg, irq;
315
315
316
316
irq = platform_get_irq(pdev, 0);
317
-
if (irq < 0) {
318
-
dev_err(&pdev->dev, "Error missing irq resource\n");
319
-
return -EINVAL;
320
-
}
317
+
if (irq < 0)
318
+
return irq;
321
319
322
320
adap = devm_kzalloc(&pdev->dev, sizeof(*adap), GFP_KERNEL);
323
321
if (!adap)
+1
-3
drivers/i2c/busses/i2c-davinci.c
+1
-3
drivers/i2c/busses/i2c-davinci.c
···
761
761
{
762
762
struct davinci_i2c_dev *dev;
763
763
struct i2c_adapter *adap;
764
-
struct resource *mem;
765
764
struct i2c_bus_recovery_info *rinfo;
766
765
int r, irq;
767
766
···
813
814
if (IS_ERR(dev->clk))
814
815
return PTR_ERR(dev->clk);
815
816
816
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817
-
dev->base = devm_ioremap_resource(&pdev->dev, mem);
817
+
dev->base = devm_platform_ioremap_resource(pdev, 0);
818
818
if (IS_ERR(dev->base)) {
819
819
return PTR_ERR(dev->base);
820
820
}
+273
-52
drivers/i2c/busses/i2c-designware-common.c
+273
-52
drivers/i2c/busses/i2c-designware-common.c
···
8
8
* Copyright (C) 2007 MontaVista Software Inc.
9
9
* Copyright (C) 2009 Provigent Ltd.
10
10
*/
11
+
#include <linux/acpi.h>
11
12
#include <linux/clk.h>
12
13
#include <linux/delay.h>
13
-
#include <linux/export.h>
14
-
#include <linux/errno.h>
14
+
#include <linux/device.h>
15
15
#include <linux/err.h>
16
+
#include <linux/errno.h>
17
+
#include <linux/export.h>
16
18
#include <linux/i2c.h>
17
19
#include <linux/interrupt.h>
18
20
#include <linux/io.h>
21
+
#include <linux/kernel.h>
19
22
#include <linux/module.h>
20
23
#include <linux/pm_runtime.h>
24
+
#include <linux/regmap.h>
21
25
#include <linux/swab.h>
26
+
#include <linux/types.h>
22
27
23
28
#include "i2c-designware-core.h"
24
29
···
58
53
"incorrect slave-transmitter mode configuration",
59
54
};
60
55
61
-
u32 dw_readl(struct dw_i2c_dev *dev, int offset)
56
+
static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
62
57
{
63
-
u32 value;
58
+
struct dw_i2c_dev *dev = context;
64
59
65
-
if (dev->flags & ACCESS_16BIT)
66
-
value = readw_relaxed(dev->base + offset) |
67
-
(readw_relaxed(dev->base + offset + 2) << 16);
68
-
else
69
-
value = readl_relaxed(dev->base + offset);
60
+
*val = readl_relaxed(dev->base + reg);
70
61
71
-
if (dev->flags & ACCESS_SWAP)
72
-
return swab32(value);
73
-
else
74
-
return value;
62
+
return 0;
75
63
}
76
64
77
-
void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
65
+
static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
78
66
{
79
-
if (dev->flags & ACCESS_SWAP)
80
-
b = swab32(b);
67
+
struct dw_i2c_dev *dev = context;
81
68
82
-
if (dev->flags & ACCESS_16BIT) {
83
-
writew_relaxed((u16)b, dev->base + offset);
84
-
writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
85
-
} else {
86
-
writel_relaxed(b, dev->base + offset);
87
-
}
69
+
writel_relaxed(val, dev->base + reg);
70
+
71
+
return 0;
72
+
}
73
+
74
+
static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
75
+
{
76
+
struct dw_i2c_dev *dev = context;
77
+
78
+
*val = swab32(readl_relaxed(dev->base + reg));
79
+
80
+
return 0;
81
+
}
82
+
83
+
static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
84
+
{
85
+
struct dw_i2c_dev *dev = context;
86
+
87
+
writel_relaxed(swab32(val), dev->base + reg);
88
+
89
+
return 0;
90
+
}
91
+
92
+
static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
93
+
{
94
+
struct dw_i2c_dev *dev = context;
95
+
96
+
*val = readw_relaxed(dev->base + reg) |
97
+
(readw_relaxed(dev->base + reg + 2) << 16);
98
+
99
+
return 0;
100
+
}
101
+
102
+
static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
103
+
{
104
+
struct dw_i2c_dev *dev = context;
105
+
106
+
writew_relaxed(val, dev->base + reg);
107
+
writew_relaxed(val >> 16, dev->base + reg + 2);
108
+
109
+
return 0;
88
110
}
89
111
90
112
/**
91
-
* i2c_dw_set_reg_access() - Set register access flags
113
+
* i2c_dw_init_regmap() - Initialize registers map
92
114
* @dev: device private data
93
115
*
94
-
* Autodetects needed register access mode and sets access flags accordingly.
95
-
* This must be called before doing any other register access.
116
+
* Autodetects needed register access mode and creates the regmap with
117
+
* corresponding read/write callbacks. This must be called before doing any
118
+
* other register access.
96
119
*/
97
-
int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
120
+
int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
98
121
{
122
+
struct regmap_config map_cfg = {
123
+
.reg_bits = 32,
124
+
.val_bits = 32,
125
+
.reg_stride = 4,
126
+
.disable_locking = true,
127
+
.reg_read = dw_reg_read,
128
+
.reg_write = dw_reg_write,
129
+
.max_register = DW_IC_COMP_TYPE,
130
+
};
99
131
u32 reg;
100
132
int ret;
133
+
134
+
/*
135
+
* Skip detecting the registers map configuration if the regmap has
136
+
* already been provided by a higher code.
137
+
*/
138
+
if (dev->map)
139
+
return 0;
101
140
102
141
ret = i2c_dw_acquire_lock(dev);
103
142
if (ret)
104
143
return ret;
105
144
106
-
reg = dw_readl(dev, DW_IC_COMP_TYPE);
145
+
reg = readl(dev->base + DW_IC_COMP_TYPE);
107
146
i2c_dw_release_lock(dev);
108
147
109
148
if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
110
-
/* Configure register endianness access */
111
-
dev->flags |= ACCESS_SWAP;
149
+
map_cfg.reg_read = dw_reg_read_swab;
150
+
map_cfg.reg_write = dw_reg_write_swab;
112
151
} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
113
-
/* Configure register access mode 16bit */
114
-
dev->flags |= ACCESS_16BIT;
152
+
map_cfg.reg_read = dw_reg_read_word;
153
+
map_cfg.reg_write = dw_reg_write_word;
115
154
} else if (reg != DW_IC_COMP_TYPE_VALUE) {
116
155
dev_err(dev->dev,
117
156
"Unknown Synopsys component type: 0x%08x\n", reg);
118
157
return -ENODEV;
119
158
}
120
159
160
+
/*
161
+
* Note we'll check the return value of the regmap IO accessors only
162
+
* at the probe stage. The rest of the code won't do this because
163
+
* basically we have MMIO-based regmap so non of the read/write methods
164
+
* can fail.
165
+
*/
166
+
dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
167
+
if (IS_ERR(dev->map)) {
168
+
dev_err(dev->dev, "Failed to init the registers map\n");
169
+
return PTR_ERR(dev->map);
170
+
}
171
+
121
172
return 0;
122
173
}
174
+
175
+
static const u32 supported_speeds[] = {
176
+
I2C_MAX_HIGH_SPEED_MODE_FREQ,
177
+
I2C_MAX_FAST_MODE_PLUS_FREQ,
178
+
I2C_MAX_FAST_MODE_FREQ,
179
+
I2C_MAX_STANDARD_MODE_FREQ,
180
+
};
181
+
182
+
int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
183
+
{
184
+
struct i2c_timings *t = &dev->timings;
185
+
unsigned int i;
186
+
187
+
/*
188
+
* Only standard mode at 100kHz, fast mode at 400kHz,
189
+
* fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
190
+
*/
191
+
for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
192
+
if (t->bus_freq_hz == supported_speeds[i])
193
+
return 0;
194
+
}
195
+
196
+
dev_err(dev->dev,
197
+
"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
198
+
t->bus_freq_hz);
199
+
200
+
return -EINVAL;
201
+
}
202
+
EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
203
+
204
+
#ifdef CONFIG_ACPI
205
+
206
+
#include <linux/dmi.h>
207
+
208
+
/*
209
+
* The HCNT/LCNT information coming from ACPI should be the most accurate
210
+
* for given platform. However, some systems get it wrong. On such systems
211
+
* we get better results by calculating those based on the input clock.
212
+
*/
213
+
static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
214
+
{
215
+
.ident = "Dell Inspiron 7348",
216
+
.matches = {
217
+
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
218
+
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
219
+
},
220
+
},
221
+
{}
222
+
};
223
+
224
+
static void i2c_dw_acpi_params(struct device *device, char method[],
225
+
u16 *hcnt, u16 *lcnt, u32 *sda_hold)
226
+
{
227
+
struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
228
+
acpi_handle handle = ACPI_HANDLE(device);
229
+
union acpi_object *obj;
230
+
231
+
if (dmi_check_system(i2c_dw_no_acpi_params))
232
+
return;
233
+
234
+
if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
235
+
return;
236
+
237
+
obj = (union acpi_object *)buf.pointer;
238
+
if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
239
+
const union acpi_object *objs = obj->package.elements;
240
+
241
+
*hcnt = (u16)objs[0].integer.value;
242
+
*lcnt = (u16)objs[1].integer.value;
243
+
*sda_hold = (u32)objs[2].integer.value;
244
+
}
245
+
246
+
kfree(buf.pointer);
247
+
}
248
+
249
+
int i2c_dw_acpi_configure(struct device *device)
250
+
{
251
+
struct dw_i2c_dev *dev = dev_get_drvdata(device);
252
+
struct i2c_timings *t = &dev->timings;
253
+
u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
254
+
255
+
/*
256
+
* Try to get SDA hold time and *CNT values from an ACPI method for
257
+
* selected speed modes.
258
+
*/
259
+
i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
260
+
i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
261
+
i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
262
+
i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
263
+
264
+
switch (t->bus_freq_hz) {
265
+
case I2C_MAX_STANDARD_MODE_FREQ:
266
+
dev->sda_hold_time = ss_ht;
267
+
break;
268
+
case I2C_MAX_FAST_MODE_PLUS_FREQ:
269
+
dev->sda_hold_time = fp_ht;
270
+
break;
271
+
case I2C_MAX_HIGH_SPEED_MODE_FREQ:
272
+
dev->sda_hold_time = hs_ht;
273
+
break;
274
+
case I2C_MAX_FAST_MODE_FREQ:
275
+
default:
276
+
dev->sda_hold_time = fs_ht;
277
+
break;
278
+
}
279
+
280
+
return 0;
281
+
}
282
+
EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
283
+
284
+
void i2c_dw_acpi_adjust_bus_speed(struct device *device)
285
+
{
286
+
struct dw_i2c_dev *dev = dev_get_drvdata(device);
287
+
struct i2c_timings *t = &dev->timings;
288
+
u32 acpi_speed;
289
+
int i;
290
+
291
+
acpi_speed = i2c_acpi_find_bus_speed(device);
292
+
/*
293
+
* Some DSTDs use a non standard speed, round down to the lowest
294
+
* standard speed.
295
+
*/
296
+
for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
297
+
if (acpi_speed >= supported_speeds[i])
298
+
break;
299
+
}
300
+
acpi_speed = i < ARRAY_SIZE(supported_speeds) ? supported_speeds[i] : 0;
301
+
302
+
/*
303
+
* Find bus speed from the "clock-frequency" device property, ACPI
304
+
* or by using fast mode if neither is set.
305
+
*/
306
+
if (acpi_speed && t->bus_freq_hz)
307
+
t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
308
+
else if (acpi_speed || t->bus_freq_hz)
309
+
t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
310
+
else
311
+
t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
312
+
}
313
+
EXPORT_SYMBOL_GPL(i2c_dw_acpi_adjust_bus_speed);
314
+
315
+
#endif /* CONFIG_ACPI */
123
316
124
317
u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
125
318
{
···
384
181
return ret;
385
182
386
183
/* Configure SDA Hold Time if required */
387
-
reg = dw_readl(dev, DW_IC_COMP_VERSION);
184
+
ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
185
+
if (ret)
186
+
goto err_release_lock;
187
+
388
188
if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
389
189
if (!dev->sda_hold_time) {
390
190
/* Keep previous hold time setting if no one set it */
391
-
dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
191
+
ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
192
+
&dev->sda_hold_time);
193
+
if (ret)
194
+
goto err_release_lock;
392
195
}
393
196
394
197
/*
···
418
209
dev->sda_hold_time = 0;
419
210
}
420
211
212
+
err_release_lock:
421
213
i2c_dw_release_lock(dev);
422
214
423
-
return 0;
215
+
return ret;
424
216
}
425
217
426
218
void __i2c_dw_disable(struct dw_i2c_dev *dev)
427
219
{
428
220
int timeout = 100;
221
+
u32 status;
429
222
430
223
do {
431
224
__i2c_dw_disable_nowait(dev);
···
435
224
* The enable status register may be unimplemented, but
436
225
* in that case this test reads zero and exits the loop.
437
226
*/
438
-
if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
227
+
regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
228
+
if ((status & 1) == 0)
439
229
return;
440
230
441
231
/*
···
515
303
*/
516
304
int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
517
305
{
518
-
int timeout = TIMEOUT;
306
+
u32 status;
307
+
int ret;
519
308
520
-
while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
521
-
if (timeout <= 0) {
522
-
dev_warn(dev->dev, "timeout waiting for bus ready\n");
523
-
i2c_recover_bus(&dev->adapter);
309
+
ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
310
+
!(status & DW_IC_STATUS_ACTIVITY),
311
+
1100, 20000);
312
+
if (ret) {
313
+
dev_warn(dev->dev, "timeout waiting for bus ready\n");
524
314
525
-
if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
526
-
return -ETIMEDOUT;
527
-
return 0;
528
-
}
529
-
timeout--;
530
-
usleep_range(1000, 1100);
315
+
i2c_recover_bus(&dev->adapter);
316
+
317
+
regmap_read(dev->map, DW_IC_STATUS, &status);
318
+
if (!(status & DW_IC_STATUS_ACTIVITY))
319
+
ret = 0;
531
320
}
532
321
533
-
return 0;
322
+
return ret;
534
323
}
535
324
536
325
int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
···
557
344
return -EIO;
558
345
}
559
346
560
-
void i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
347
+
int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
561
348
{
562
349
u32 param, tx_fifo_depth, rx_fifo_depth;
350
+
int ret;
563
351
564
352
/*
565
353
* Try to detect the FIFO depth if not set by interface driver,
566
354
* the depth could be from 2 to 256 from HW spec.
567
355
*/
568
-
param = dw_readl(dev, DW_IC_COMP_PARAM_1);
356
+
ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
357
+
if (ret)
358
+
return ret;
359
+
569
360
tx_fifo_depth = ((param >> 16) & 0xff) + 1;
570
361
rx_fifo_depth = ((param >> 8) & 0xff) + 1;
571
362
if (!dev->tx_fifo_depth) {
···
581
364
dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
582
365
rx_fifo_depth);
583
366
}
367
+
368
+
return 0;
584
369
}
585
370
586
371
u32 i2c_dw_func(struct i2c_adapter *adap)
···
594
375
595
376
void i2c_dw_disable(struct dw_i2c_dev *dev)
596
377
{
378
+
u32 dummy;
379
+
597
380
/* Disable controller */
598
381
__i2c_dw_disable(dev);
599
382
600
383
/* Disable all interrupts */
601
-
dw_writel(dev, 0, DW_IC_INTR_MASK);
602
-
dw_readl(dev, DW_IC_CLR_INTR);
384
+
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
385
+
regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
603
386
}
604
387
605
388
void i2c_dw_disable_int(struct dw_i2c_dev *dev)
606
389
{
607
-
dw_writel(dev, 0, DW_IC_INTR_MASK);
390
+
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
608
391
}
609
392
610
393
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
+59
-16
drivers/i2c/busses/i2c-designware-core.h
+59
-16
drivers/i2c/busses/i2c-designware-core.h
···
9
9
* Copyright (C) 2009 Provigent Ltd.
10
10
*/
11
11
12
+
#include <linux/bits.h>
13
+
#include <linux/compiler_types.h>
14
+
#include <linux/completion.h>
15
+
#include <linux/dev_printk.h>
16
+
#include <linux/errno.h>
12
17
#include <linux/i2c.h>
18
+
#include <linux/regmap.h>
19
+
#include <linux/types.h>
13
20
14
21
#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
15
22
I2C_FUNC_SMBUS_BYTE | \
···
127
120
#define STATUS_WRITE_IN_PROGRESS 0x1
128
121
#define STATUS_READ_IN_PROGRESS 0x2
129
122
130
-
#define TIMEOUT 20 /* ms */
131
-
132
123
/*
133
124
* operation modes
134
125
*/
···
175
170
DW_IC_TX_ABRT_TXDATA_NOACK | \
176
171
DW_IC_TX_ABRT_GCALL_NOACK)
177
172
173
+
struct clk;
174
+
struct device;
175
+
struct reset_control;
178
176
179
177
/**
180
178
* struct dw_i2c_dev - private i2c-designware data
181
179
* @dev: driver model device node
180
+
* @map: IO registers map
181
+
* @sysmap: System controller registers map
182
182
* @base: IO registers pointer
183
+
* @ext: Extended IO registers pointer
183
184
* @cmd_complete: tx completion indicator
184
185
* @clk: input reference clock
185
186
* @pclk: clock required to access the registers
···
235
224
*/
236
225
struct dw_i2c_dev {
237
226
struct device *dev;
227
+
struct regmap *map;
228
+
struct regmap *sysmap;
238
229
void __iomem *base;
239
230
void __iomem *ext;
240
231
struct completion cmd_complete;
···
245
232
struct reset_control *rst;
246
233
struct i2c_client *slave;
247
234
u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
248
-
struct dw_pci_controller *controller;
249
235
int cmd_err;
250
236
struct i2c_msg *msgs;
251
237
int msgs_num;
···
288
276
bool suspended;
289
277
};
290
278
291
-
#define ACCESS_SWAP 0x00000001
292
-
#define ACCESS_16BIT 0x00000002
293
-
#define ACCESS_INTR_MASK 0x00000004
294
-
#define ACCESS_NO_IRQ_SUSPEND 0x00000008
279
+
#define ACCESS_INTR_MASK 0x00000001
280
+
#define ACCESS_NO_IRQ_SUSPEND 0x00000002
295
281
296
-
#define MODEL_CHERRYTRAIL 0x00000100
297
-
#define MODEL_MSCC_OCELOT 0x00000200
282
+
#define MODEL_MSCC_OCELOT 0x00000100
283
+
#define MODEL_BAIKAL_BT1 0x00000200
298
284
#define MODEL_MASK 0x00000f00
299
285
300
-
u32 dw_readl(struct dw_i2c_dev *dev, int offset);
301
-
void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset);
302
-
int i2c_dw_set_reg_access(struct dw_i2c_dev *dev);
286
+
int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
303
287
u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
304
288
u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
305
289
int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
···
305
297
void i2c_dw_release_lock(struct dw_i2c_dev *dev);
306
298
int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
307
299
int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
308
-
void i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
300
+
int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
309
301
u32 i2c_dw_func(struct i2c_adapter *adap);
310
302
void i2c_dw_disable(struct dw_i2c_dev *dev);
311
303
void i2c_dw_disable_int(struct dw_i2c_dev *dev);
312
304
313
305
static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
314
306
{
315
-
dw_writel(dev, 1, DW_IC_ENABLE);
307
+
regmap_write(dev->map, DW_IC_ENABLE, 1);
316
308
}
317
309
318
310
static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
319
311
{
320
-
dw_writel(dev, 0, DW_IC_ENABLE);
312
+
regmap_write(dev->map, DW_IC_ENABLE, 0);
321
313
}
322
314
323
315
void __i2c_dw_disable(struct dw_i2c_dev *dev);
324
316
325
-
extern int i2c_dw_probe(struct dw_i2c_dev *dev);
317
+
extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
318
+
extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
319
+
326
320
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
321
+
extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
327
322
extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
328
323
#else
324
+
static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
329
325
static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
330
326
#endif
327
+
328
+
static inline int i2c_dw_probe(struct dw_i2c_dev *dev)
329
+
{
330
+
switch (dev->mode) {
331
+
case DW_IC_SLAVE:
332
+
return i2c_dw_probe_slave(dev);
333
+
case DW_IC_MASTER:
334
+
return i2c_dw_probe_master(dev);
335
+
default:
336
+
dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
337
+
return -EINVAL;
338
+
}
339
+
}
340
+
341
+
static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
342
+
{
343
+
if (i2c_detect_slave_mode(dev->dev))
344
+
i2c_dw_configure_slave(dev);
345
+
else
346
+
i2c_dw_configure_master(dev);
347
+
}
331
348
332
349
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
333
350
extern int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev);
334
351
#else
335
352
static inline int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { return 0; }
353
+
#endif
354
+
355
+
int i2c_dw_validate_speed(struct dw_i2c_dev *dev);
356
+
357
+
#if IS_ENABLED(CONFIG_ACPI)
358
+
int i2c_dw_acpi_configure(struct device *device);
359
+
void i2c_dw_acpi_adjust_bus_speed(struct device *device);
360
+
#else
361
+
static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; }
362
+
static inline void i2c_dw_acpi_adjust_bus_speed(struct device *device) {}
336
363
#endif
+127
-65
drivers/i2c/busses/i2c-designware-master.c
+127
-65
drivers/i2c/busses/i2c-designware-master.c
···
18
18
#include <linux/io.h>
19
19
#include <linux/module.h>
20
20
#include <linux/pm_runtime.h>
21
+
#include <linux/regmap.h>
21
22
#include <linux/reset.h>
22
23
23
24
#include "i2c-designware-core.h"
···
26
25
static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
27
26
{
28
27
/* Configure Tx/Rx FIFO threshold levels */
29
-
dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
30
-
dw_writel(dev, 0, DW_IC_RX_TL);
28
+
regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
29
+
regmap_write(dev->map, DW_IC_RX_TL, 0);
31
30
32
31
/* Configure the I2C master */
33
-
dw_writel(dev, dev->master_cfg, DW_IC_CON);
32
+
regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
34
33
}
35
34
36
35
static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
···
45
44
ret = i2c_dw_acquire_lock(dev);
46
45
if (ret)
47
46
return ret;
48
-
comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
47
+
48
+
ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
49
49
i2c_dw_release_lock(dev);
50
+
if (ret)
51
+
return ret;
50
52
51
53
/* Set standard and fast speed dividers for high/low periods */
52
54
sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
···
80
76
*/
81
77
if (t->bus_freq_hz == 1000000) {
82
78
/*
83
-
* Check are fast mode plus parameters available and use
84
-
* fast mode if not.
79
+
* Check are Fast Mode Plus parameters available. Calculate
80
+
* SCL timing parameters for Fast Mode Plus if not set.
85
81
*/
86
82
if (dev->fp_hcnt && dev->fp_lcnt) {
87
83
dev->fs_hcnt = dev->fp_hcnt;
88
84
dev->fs_lcnt = dev->fp_lcnt;
89
-
fp_str = " Plus";
85
+
} else {
86
+
ic_clk = i2c_dw_clk_rate(dev);
87
+
dev->fs_hcnt =
88
+
i2c_dw_scl_hcnt(ic_clk,
89
+
260, /* tHIGH = 260 ns */
90
+
sda_falling_time,
91
+
0, /* DW default */
92
+
0); /* No offset */
93
+
dev->fs_lcnt =
94
+
i2c_dw_scl_lcnt(ic_clk,
95
+
500, /* tLOW = 500 ns */
96
+
scl_falling_time,
97
+
0); /* No offset */
90
98
}
99
+
fp_str = " Plus";
91
100
}
92
101
/*
93
102
* Calculate SCL timing parameters for fast mode if not set. They are
···
133
116
dev->master_cfg |= DW_IC_CON_SPEED_FAST;
134
117
dev->hs_hcnt = 0;
135
118
dev->hs_lcnt = 0;
136
-
} else if (dev->hs_hcnt && dev->hs_lcnt) {
137
-
dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
138
-
dev->hs_hcnt, dev->hs_lcnt);
119
+
} else if (!dev->hs_hcnt || !dev->hs_lcnt) {
120
+
ic_clk = i2c_dw_clk_rate(dev);
121
+
dev->hs_hcnt =
122
+
i2c_dw_scl_hcnt(ic_clk,
123
+
160, /* tHIGH = 160 ns */
124
+
sda_falling_time,
125
+
0, /* DW default */
126
+
0); /* No offset */
127
+
dev->hs_lcnt =
128
+
i2c_dw_scl_lcnt(ic_clk,
129
+
320, /* tLOW = 320 ns */
130
+
scl_falling_time,
131
+
0); /* No offset */
139
132
}
133
+
dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
134
+
dev->hs_hcnt, dev->hs_lcnt);
140
135
}
141
136
142
137
ret = i2c_dw_set_sda_hold(dev);
···
191
162
__i2c_dw_disable(dev);
192
163
193
164
/* Write standard speed timing parameters */
194
-
dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
195
-
dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
165
+
regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
166
+
regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
196
167
197
168
/* Write fast mode/fast mode plus timing parameters */
198
-
dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
199
-
dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
169
+
regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
170
+
regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
200
171
201
172
/* Write high speed timing parameters if supported */
202
173
if (dev->hs_hcnt && dev->hs_lcnt) {
203
-
dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
204
-
dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
174
+
regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
175
+
regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
205
176
}
206
177
207
178
/* Write SDA hold time if supported */
208
179
if (dev->sda_hold_time)
209
-
dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
180
+
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
210
181
211
182
i2c_dw_configure_fifo_master(dev);
212
183
i2c_dw_release_lock(dev);
···
217
188
static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
218
189
{
219
190
struct i2c_msg *msgs = dev->msgs;
220
-
u32 ic_con, ic_tar = 0;
191
+
u32 ic_con = 0, ic_tar = 0;
192
+
u32 dummy;
221
193
222
194
/* Disable the adapter */
223
195
__i2c_dw_disable(dev);
224
196
225
197
/* If the slave address is ten bit address, enable 10BITADDR */
226
-
ic_con = dw_readl(dev, DW_IC_CON);
227
198
if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
228
-
ic_con |= DW_IC_CON_10BITADDR_MASTER;
199
+
ic_con = DW_IC_CON_10BITADDR_MASTER;
229
200
/*
230
201
* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
231
202
* mode has to be enabled via bit 12 of IC_TAR register.
···
233
204
* detected from registers.
234
205
*/
235
206
ic_tar = DW_IC_TAR_10BITADDR_MASTER;
236
-
} else {
237
-
ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
238
207
}
239
208
240
-
dw_writel(dev, ic_con, DW_IC_CON);
209
+
regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
210
+
ic_con);
241
211
242
212
/*
243
213
* Set the slave (target) address and enable 10-bit addressing mode
244
214
* if applicable.
245
215
*/
246
-
dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
216
+
regmap_write(dev->map, DW_IC_TAR,
217
+
msgs[dev->msg_write_idx].addr | ic_tar);
247
218
248
219
/* Enforce disabled interrupts (due to HW issues) */
249
220
i2c_dw_disable_int(dev);
···
252
223
__i2c_dw_enable(dev);
253
224
254
225
/* Dummy read to avoid the register getting stuck on Bay Trail */
255
-
dw_readl(dev, DW_IC_ENABLE_STATUS);
226
+
regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
256
227
257
228
/* Clear and enable interrupts */
258
-
dw_readl(dev, DW_IC_CLR_INTR);
259
-
dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
229
+
regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
230
+
regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
260
231
}
261
232
262
233
/*
···
275
246
u32 buf_len = dev->tx_buf_len;
276
247
u8 *buf = dev->tx_buf;
277
248
bool need_restart = false;
249
+
unsigned int flr;
278
250
279
251
intr_mask = DW_IC_INTR_MASTER_MASK;
280
252
···
308
278
need_restart = true;
309
279
}
310
280
311
-
tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
312
-
rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
281
+
regmap_read(dev->map, DW_IC_TXFLR, &flr);
282
+
tx_limit = dev->tx_fifo_depth - flr;
283
+
284
+
regmap_read(dev->map, DW_IC_RXFLR, &flr);
285
+
rx_limit = dev->rx_fifo_depth - flr;
313
286
314
287
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
315
288
u32 cmd = 0;
···
345
312
if (dev->rx_outstanding >= dev->rx_fifo_depth)
346
313
break;
347
314
348
-
dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
315
+
regmap_write(dev->map, DW_IC_DATA_CMD,
316
+
cmd | 0x100);
349
317
rx_limit--;
350
318
dev->rx_outstanding++;
351
-
} else
352
-
dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
319
+
} else {
320
+
regmap_write(dev->map, DW_IC_DATA_CMD,
321
+
cmd | *buf++);
322
+
}
353
323
tx_limit--; buf_len--;
354
324
}
355
325
···
382
346
if (dev->msg_err)
383
347
intr_mask = 0;
384
348
385
-
dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
349
+
regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
386
350
}
387
351
388
352
static u8
···
407
371
i2c_dw_read(struct dw_i2c_dev *dev)
408
372
{
409
373
struct i2c_msg *msgs = dev->msgs;
410
-
int rx_valid;
374
+
unsigned int rx_valid;
411
375
412
376
for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
413
-
u32 len;
377
+
u32 len, tmp;
414
378
u8 *buf;
415
379
416
380
if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
···
424
388
buf = dev->rx_buf;
425
389
}
426
390
427
-
rx_valid = dw_readl(dev, DW_IC_RXFLR);
391
+
regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
428
392
429
393
for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
430
394
u32 flags = msgs[dev->msg_read_idx].flags;
431
395
432
-
*buf = dw_readl(dev, DW_IC_DATA_CMD);
396
+
regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
433
397
/* Ensure length byte is a valid value */
434
398
if (flags & I2C_M_RECV_LEN &&
435
-
*buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
436
-
len = i2c_dw_recv_len(dev, *buf);
399
+
tmp <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
400
+
len = i2c_dw_recv_len(dev, tmp);
437
401
}
438
-
buf++;
402
+
*buf++ = tmp;
439
403
dev->rx_outstanding--;
440
404
}
441
405
···
553
517
554
518
static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
555
519
{
556
-
u32 stat;
520
+
u32 stat, dummy;
557
521
558
522
/*
559
523
* The IC_INTR_STAT register just indicates "enabled" interrupts.
···
561
525
* in the IC_RAW_INTR_STAT register.
562
526
*
563
527
* That is,
564
-
* stat = dw_readl(IC_INTR_STAT);
528
+
* stat = readl(IC_INTR_STAT);
565
529
* equals to,
566
-
* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
530
+
* stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
567
531
*
568
532
* The raw version might be useful for debugging purposes.
569
533
*/
570
-
stat = dw_readl(dev, DW_IC_INTR_STAT);
534
+
regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
571
535
572
536
/*
573
537
* Do not use the IC_CLR_INTR register to clear interrupts, or
574
538
* you'll miss some interrupts, triggered during the period from
575
-
* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
539
+
* readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
576
540
*
577
541
* Instead, use the separately-prepared IC_CLR_* registers.
578
542
*/
579
543
if (stat & DW_IC_INTR_RX_UNDER)
580
-
dw_readl(dev, DW_IC_CLR_RX_UNDER);
544
+
regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
581
545
if (stat & DW_IC_INTR_RX_OVER)
582
-
dw_readl(dev, DW_IC_CLR_RX_OVER);
546
+
regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
583
547
if (stat & DW_IC_INTR_TX_OVER)
584
-
dw_readl(dev, DW_IC_CLR_TX_OVER);
548
+
regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
585
549
if (stat & DW_IC_INTR_RD_REQ)
586
-
dw_readl(dev, DW_IC_CLR_RD_REQ);
550
+
regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
587
551
if (stat & DW_IC_INTR_TX_ABRT) {
588
552
/*
589
553
* The IC_TX_ABRT_SOURCE register is cleared whenever
590
554
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
591
555
*/
592
-
dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
593
-
dw_readl(dev, DW_IC_CLR_TX_ABRT);
556
+
regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
557
+
regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
594
558
}
595
559
if (stat & DW_IC_INTR_RX_DONE)
596
-
dw_readl(dev, DW_IC_CLR_RX_DONE);
560
+
regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
597
561
if (stat & DW_IC_INTR_ACTIVITY)
598
-
dw_readl(dev, DW_IC_CLR_ACTIVITY);
562
+
regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
599
563
if (stat & DW_IC_INTR_STOP_DET)
600
-
dw_readl(dev, DW_IC_CLR_STOP_DET);
564
+
regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
601
565
if (stat & DW_IC_INTR_START_DET)
602
-
dw_readl(dev, DW_IC_CLR_START_DET);
566
+
regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
603
567
if (stat & DW_IC_INTR_GEN_CALL)
604
-
dw_readl(dev, DW_IC_CLR_GEN_CALL);
568
+
regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
605
569
606
570
return stat;
607
571
}
···
623
587
* Anytime TX_ABRT is set, the contents of the tx/rx
624
588
* buffers are flushed. Make sure to skip them.
625
589
*/
626
-
dw_writel(dev, 0, DW_IC_INTR_MASK);
590
+
regmap_write(dev->map, DW_IC_INTR_MASK, 0);
627
591
goto tx_aborted;
628
592
}
629
593
···
644
608
complete(&dev->cmd_complete);
645
609
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
646
610
/* Workaround to trigger pending interrupt */
647
-
stat = dw_readl(dev, DW_IC_INTR_MASK);
611
+
regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
648
612
i2c_dw_disable_int(dev);
649
-
dw_writel(dev, stat, DW_IC_INTR_MASK);
613
+
regmap_write(dev->map, DW_IC_INTR_MASK, stat);
650
614
}
651
615
652
616
return 0;
···
657
621
struct dw_i2c_dev *dev = dev_id;
658
622
u32 stat, enabled;
659
623
660
-
enabled = dw_readl(dev, DW_IC_ENABLE);
661
-
stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
624
+
regmap_read(dev->map, DW_IC_ENABLE, &enabled);
625
+
regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
662
626
dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
663
627
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
664
628
return IRQ_NONE;
···
667
631
668
632
return IRQ_HANDLED;
669
633
}
634
+
635
+
void i2c_dw_configure_master(struct dw_i2c_dev *dev)
636
+
{
637
+
struct i2c_timings *t = &dev->timings;
638
+
639
+
dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
640
+
641
+
dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
642
+
DW_IC_CON_RESTART_EN;
643
+
644
+
dev->mode = DW_IC_MASTER;
645
+
646
+
switch (t->bus_freq_hz) {
647
+
case I2C_MAX_STANDARD_MODE_FREQ:
648
+
dev->master_cfg |= DW_IC_CON_SPEED_STD;
649
+
break;
650
+
case I2C_MAX_HIGH_SPEED_MODE_FREQ:
651
+
dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
652
+
break;
653
+
default:
654
+
dev->master_cfg |= DW_IC_CON_SPEED_FAST;
655
+
}
656
+
}
657
+
EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
670
658
671
659
static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
672
660
{
···
738
678
return 0;
739
679
}
740
680
741
-
int i2c_dw_probe(struct dw_i2c_dev *dev)
681
+
int i2c_dw_probe_master(struct dw_i2c_dev *dev)
742
682
{
743
683
struct i2c_adapter *adap = &dev->adapter;
744
684
unsigned long irq_flags;
···
750
690
dev->disable = i2c_dw_disable;
751
691
dev->disable_int = i2c_dw_disable_int;
752
692
753
-
ret = i2c_dw_set_reg_access(dev);
693
+
ret = i2c_dw_init_regmap(dev);
754
694
if (ret)
755
695
return ret;
756
696
···
758
698
if (ret)
759
699
return ret;
760
700
761
-
i2c_dw_set_fifo_size(dev);
701
+
ret = i2c_dw_set_fifo_size(dev);
702
+
if (ret)
703
+
return ret;
762
704
763
705
ret = dev->init(dev);
764
706
if (ret)
···
807
745
808
746
return ret;
809
747
}
810
-
EXPORT_SYMBOL_GPL(i2c_dw_probe);
748
+
EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
811
749
812
750
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
813
751
MODULE_LICENSE("GPL");
+32
-54
drivers/i2c/busses/i2c-designware-pcidrv.c
+32
-54
drivers/i2c/busses/i2c-designware-pcidrv.c
···
46
46
47
47
struct dw_pci_controller {
48
48
u32 bus_num;
49
-
u32 bus_cfg;
50
-
u32 tx_fifo_depth;
51
-
u32 rx_fifo_depth;
52
-
u32 clk_khz;
53
-
u32 functionality;
54
49
u32 flags;
55
50
struct dw_scl_sda_cfg *scl_sda_cfg;
56
51
int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
52
+
u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
57
53
};
58
-
59
-
#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
60
-
DW_IC_CON_SLAVE_DISABLE | \
61
-
DW_IC_CON_RESTART_EN)
62
54
63
55
/* Merrifield HCNT/LCNT/SDA hold time */
64
56
static struct dw_scl_sda_cfg mrfld_config = {
···
78
86
.sda_hold = 0x9,
79
87
};
80
88
89
+
static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
90
+
{
91
+
return 25000;
92
+
}
93
+
81
94
static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
82
95
{
96
+
struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
97
+
83
98
switch (pdev->device) {
84
99
case 0x0817:
85
-
c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
86
-
c->bus_cfg |= DW_IC_CON_SPEED_STD;
100
+
dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
87
101
/* fall through */
88
102
case 0x0818:
89
103
case 0x0819:
···
123
125
return -ENODEV;
124
126
}
125
127
128
+
static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
129
+
{
130
+
return 100000;
131
+
}
132
+
126
133
static struct dw_pci_controller dw_pci_controllers[] = {
127
134
[medfield] = {
128
135
.bus_num = -1,
129
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
130
-
.tx_fifo_depth = 32,
131
-
.rx_fifo_depth = 32,
132
-
.functionality = I2C_FUNC_10BIT_ADDR,
133
-
.clk_khz = 25000,
134
136
.setup = mfld_setup,
137
+
.get_clk_rate_khz = mfld_get_clk_rate_khz,
135
138
},
136
139
[merrifield] = {
137
140
.bus_num = -1,
138
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
139
-
.tx_fifo_depth = 64,
140
-
.rx_fifo_depth = 64,
141
-
.functionality = I2C_FUNC_10BIT_ADDR,
142
141
.scl_sda_cfg = &mrfld_config,
143
142
.setup = mrfld_setup,
144
143
},
145
144
[baytrail] = {
146
145
.bus_num = -1,
147
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
148
-
.tx_fifo_depth = 32,
149
-
.rx_fifo_depth = 32,
150
-
.functionality = I2C_FUNC_10BIT_ADDR,
151
146
.scl_sda_cfg = &byt_config,
152
147
},
153
148
[haswell] = {
154
149
.bus_num = -1,
155
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
156
-
.tx_fifo_depth = 32,
157
-
.rx_fifo_depth = 32,
158
-
.functionality = I2C_FUNC_10BIT_ADDR,
159
150
.scl_sda_cfg = &hsw_config,
160
151
},
161
152
[cherrytrail] = {
162
153
.bus_num = -1,
163
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
164
-
.tx_fifo_depth = 32,
165
-
.rx_fifo_depth = 32,
166
-
.functionality = I2C_FUNC_10BIT_ADDR,
167
-
.flags = MODEL_CHERRYTRAIL,
168
154
.scl_sda_cfg = &byt_config,
169
155
},
170
156
[elkhartlake] = {
171
157
.bus_num = -1,
172
-
.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
173
-
.tx_fifo_depth = 32,
174
-
.rx_fifo_depth = 32,
175
-
.functionality = I2C_FUNC_10BIT_ADDR,
176
-
.clk_khz = 100000,
158
+
.get_clk_rate_khz = ehl_get_clk_rate_khz,
177
159
},
178
160
};
179
161
···
182
204
183
205
static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
184
206
i2c_dw_pci_resume, NULL);
185
-
186
-
static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
187
-
{
188
-
return dev->controller->clk_khz;
189
-
}
190
207
191
208
static int i2c_dw_pci_probe(struct pci_dev *pdev,
192
209
const struct pci_device_id *id)
···
223
250
if (r < 0)
224
251
return r;
225
252
226
-
dev->clk = NULL;
227
-
dev->controller = controller;
228
-
dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
253
+
dev->get_clk_rate_khz = controller->get_clk_rate_khz;
254
+
dev->timings.bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
229
255
dev->base = pcim_iomap_table(pdev)[0];
230
256
dev->dev = &pdev->dev;
231
257
dev->irq = pci_irq_vector(pdev, 0);
232
258
dev->flags |= controller->flags;
259
+
260
+
pci_set_drvdata(pdev, dev);
233
261
234
262
if (controller->setup) {
235
263
r = controller->setup(pdev, controller);
···
240
266
}
241
267
}
242
268
243
-
dev->functionality = controller->functionality |
244
-
DW_IC_DEFAULT_FUNCTIONALITY;
269
+
i2c_dw_acpi_adjust_bus_speed(&pdev->dev);
245
270
246
-
dev->master_cfg = controller->bus_cfg;
271
+
if (has_acpi_companion(&pdev->dev))
272
+
i2c_dw_acpi_configure(&pdev->dev);
273
+
274
+
r = i2c_dw_validate_speed(dev);
275
+
if (r) {
276
+
pci_free_irq_vectors(pdev);
277
+
return r;
278
+
}
279
+
280
+
i2c_dw_configure(dev);
281
+
247
282
if (controller->scl_sda_cfg) {
248
283
cfg = controller->scl_sda_cfg;
249
284
dev->ss_hcnt = cfg->ss_hcnt;
···
261
278
dev->fs_lcnt = cfg->fs_lcnt;
262
279
dev->sda_hold_time = cfg->sda_hold;
263
280
}
264
-
265
-
pci_set_drvdata(pdev, dev);
266
-
267
-
dev->tx_fifo_depth = controller->tx_fifo_depth;
268
-
dev->rx_fifo_depth = controller->rx_fifo_depth;
269
281
270
282
adap = &dev->adapter;
271
283
adap->owner = THIS_MODULE;
+96
-182
drivers/i2c/busses/i2c-designware-platdrv.c
+96
-182
drivers/i2c/busses/i2c-designware-platdrv.c
···
12
12
#include <linux/clk-provider.h>
13
13
#include <linux/clk.h>
14
14
#include <linux/delay.h>
15
-
#include <linux/dmi.h>
16
15
#include <linux/err.h>
17
16
#include <linux/errno.h>
18
17
#include <linux/i2c.h>
19
18
#include <linux/interrupt.h>
20
19
#include <linux/io.h>
21
20
#include <linux/kernel.h>
21
+
#include <linux/mfd/syscon.h>
22
22
#include <linux/module.h>
23
23
#include <linux/of.h>
24
24
#include <linux/platform_data/i2c-designware.h>
···
26
26
#include <linux/pm.h>
27
27
#include <linux/pm_runtime.h>
28
28
#include <linux/property.h>
29
+
#include <linux/regmap.h>
29
30
#include <linux/reset.h>
30
31
#include <linux/sched.h>
31
32
#include <linux/slab.h>
···
40
39
}
41
40
42
41
#ifdef CONFIG_ACPI
43
-
/*
44
-
* The HCNT/LCNT information coming from ACPI should be the most accurate
45
-
* for given platform. However, some systems get it wrong. On such systems
46
-
* we get better results by calculating those based on the input clock.
47
-
*/
48
-
static const struct dmi_system_id dw_i2c_no_acpi_params[] = {
49
-
{
50
-
.ident = "Dell Inspiron 7348",
51
-
.matches = {
52
-
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
53
-
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
54
-
},
55
-
},
56
-
{ }
57
-
};
58
-
59
-
static void dw_i2c_acpi_params(struct platform_device *pdev, char method[],
60
-
u16 *hcnt, u16 *lcnt, u32 *sda_hold)
61
-
{
62
-
struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
63
-
acpi_handle handle = ACPI_HANDLE(&pdev->dev);
64
-
union acpi_object *obj;
65
-
66
-
if (dmi_check_system(dw_i2c_no_acpi_params))
67
-
return;
68
-
69
-
if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
70
-
return;
71
-
72
-
obj = (union acpi_object *)buf.pointer;
73
-
if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
74
-
const union acpi_object *objs = obj->package.elements;
75
-
76
-
*hcnt = (u16)objs[0].integer.value;
77
-
*lcnt = (u16)objs[1].integer.value;
78
-
*sda_hold = (u32)objs[2].integer.value;
79
-
}
80
-
81
-
kfree(buf.pointer);
82
-
}
83
-
84
-
static int dw_i2c_acpi_configure(struct platform_device *pdev)
85
-
{
86
-
struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
87
-
struct i2c_timings *t = &dev->timings;
88
-
u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
89
-
90
-
dev->tx_fifo_depth = 32;
91
-
dev->rx_fifo_depth = 32;
92
-
93
-
/*
94
-
* Try to get SDA hold time and *CNT values from an ACPI method for
95
-
* selected speed modes.
96
-
*/
97
-
dw_i2c_acpi_params(pdev, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
98
-
dw_i2c_acpi_params(pdev, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
99
-
dw_i2c_acpi_params(pdev, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
100
-
dw_i2c_acpi_params(pdev, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
101
-
102
-
switch (t->bus_freq_hz) {
103
-
case I2C_MAX_STANDARD_MODE_FREQ:
104
-
dev->sda_hold_time = ss_ht;
105
-
break;
106
-
case I2C_MAX_FAST_MODE_PLUS_FREQ:
107
-
dev->sda_hold_time = fp_ht;
108
-
break;
109
-
case I2C_MAX_HIGH_SPEED_MODE_FREQ:
110
-
dev->sda_hold_time = hs_ht;
111
-
break;
112
-
case I2C_MAX_FAST_MODE_FREQ:
113
-
default:
114
-
dev->sda_hold_time = fs_ht;
115
-
break;
116
-
}
117
-
118
-
return 0;
119
-
}
120
-
121
42
static const struct acpi_device_id dw_i2c_acpi_match[] = {
122
43
{ "INT33C2", 0 },
123
44
{ "INT33C3", 0 },
124
45
{ "INT3432", 0 },
125
46
{ "INT3433", 0 },
126
47
{ "80860F41", ACCESS_NO_IRQ_SUSPEND },
127
-
{ "808622C1", ACCESS_NO_IRQ_SUSPEND | MODEL_CHERRYTRAIL },
48
+
{ "808622C1", ACCESS_NO_IRQ_SUSPEND },
128
49
{ "AMD0010", ACCESS_INTR_MASK },
129
50
{ "AMDI0010", ACCESS_INTR_MASK },
130
51
{ "AMDI0510", 0 },
···
57
134
{ }
58
135
};
59
136
MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);
60
-
#else
61
-
static inline int dw_i2c_acpi_configure(struct platform_device *pdev)
62
-
{
63
-
return -ENODEV;
64
-
}
65
137
#endif
66
138
67
139
#ifdef CONFIG_OF
140
+
#define BT1_I2C_CTL 0x100
141
+
#define BT1_I2C_CTL_ADDR_MASK GENMASK(7, 0)
142
+
#define BT1_I2C_CTL_WR BIT(8)
143
+
#define BT1_I2C_CTL_GO BIT(31)
144
+
#define BT1_I2C_DI 0x104
145
+
#define BT1_I2C_DO 0x108
146
+
147
+
static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val)
148
+
{
149
+
struct dw_i2c_dev *dev = context;
150
+
int ret;
151
+
152
+
/*
153
+
* Note these methods shouldn't ever fail because the system controller
154
+
* registers are memory mapped. We check the return value just in case.
155
+
*/
156
+
ret = regmap_write(dev->sysmap, BT1_I2C_CTL,
157
+
BT1_I2C_CTL_GO | (reg & BT1_I2C_CTL_ADDR_MASK));
158
+
if (ret)
159
+
return ret;
160
+
161
+
return regmap_read(dev->sysmap, BT1_I2C_DO, val);
162
+
}
163
+
164
+
static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val)
165
+
{
166
+
struct dw_i2c_dev *dev = context;
167
+
int ret;
168
+
169
+
ret = regmap_write(dev->sysmap, BT1_I2C_DI, val);
170
+
if (ret)
171
+
return ret;
172
+
173
+
return regmap_write(dev->sysmap, BT1_I2C_CTL,
174
+
BT1_I2C_CTL_GO | BT1_I2C_CTL_WR | (reg & BT1_I2C_CTL_ADDR_MASK));
175
+
}
176
+
177
+
static struct regmap_config bt1_i2c_cfg = {
178
+
.reg_bits = 32,
179
+
.val_bits = 32,
180
+
.reg_stride = 4,
181
+
.fast_io = true,
182
+
.reg_read = bt1_i2c_read,
183
+
.reg_write = bt1_i2c_write,
184
+
.max_register = DW_IC_COMP_TYPE,
185
+
};
186
+
187
+
static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
188
+
{
189
+
dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent);
190
+
if (IS_ERR(dev->sysmap))
191
+
return PTR_ERR(dev->sysmap);
192
+
193
+
dev->map = devm_regmap_init(dev->dev, NULL, dev, &bt1_i2c_cfg);
194
+
return PTR_ERR_OR_ZERO(dev->map);
195
+
}
196
+
68
197
#define MSCC_ICPU_CFG_TWI_DELAY 0x0
69
198
#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0)
70
199
#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4
···
132
157
static int dw_i2c_of_configure(struct platform_device *pdev)
133
158
{
134
159
struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
135
-
struct resource *mem;
136
160
137
161
switch (dev->flags & MODEL_MASK) {
138
162
case MODEL_MSCC_OCELOT:
139
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
140
-
dev->ext = devm_ioremap_resource(&pdev->dev, mem);
163
+
dev->ext = devm_platform_ioremap_resource(pdev, 1);
141
164
if (!IS_ERR(dev->ext))
142
165
dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;
143
166
break;
···
149
176
static const struct of_device_id dw_i2c_of_match[] = {
150
177
{ .compatible = "snps,designware-i2c", },
151
178
{ .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT },
179
+
{ .compatible = "baikal,bt1-sys-i2c", .data = (void *)MODEL_BAIKAL_BT1 },
152
180
{},
153
181
};
154
182
MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
155
183
#else
184
+
static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
185
+
{
186
+
return -ENODEV;
187
+
}
188
+
156
189
static inline int dw_i2c_of_configure(struct platform_device *pdev)
157
190
{
158
191
return -ENODEV;
159
192
}
160
193
#endif
161
-
162
-
static void i2c_dw_configure_master(struct dw_i2c_dev *dev)
163
-
{
164
-
struct i2c_timings *t = &dev->timings;
165
-
166
-
dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
167
-
168
-
dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
169
-
DW_IC_CON_RESTART_EN;
170
-
171
-
dev->mode = DW_IC_MASTER;
172
-
173
-
switch (t->bus_freq_hz) {
174
-
case I2C_MAX_STANDARD_MODE_FREQ:
175
-
dev->master_cfg |= DW_IC_CON_SPEED_STD;
176
-
break;
177
-
case I2C_MAX_HIGH_SPEED_MODE_FREQ:
178
-
dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
179
-
break;
180
-
default:
181
-
dev->master_cfg |= DW_IC_CON_SPEED_FAST;
182
-
}
183
-
}
184
-
185
-
static void i2c_dw_configure_slave(struct dw_i2c_dev *dev)
186
-
{
187
-
dev->functionality = I2C_FUNC_SLAVE | DW_IC_DEFAULT_FUNCTIONALITY;
188
-
189
-
dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL |
190
-
DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED;
191
-
192
-
dev->mode = DW_IC_SLAVE;
193
-
}
194
194
195
195
static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
196
196
{
···
173
227
pm_runtime_put_noidle(dev->dev);
174
228
}
175
229
176
-
static const u32 supported_speeds[] = {
177
-
I2C_MAX_HIGH_SPEED_MODE_FREQ,
178
-
I2C_MAX_FAST_MODE_PLUS_FREQ,
179
-
I2C_MAX_FAST_MODE_FREQ,
180
-
I2C_MAX_STANDARD_MODE_FREQ,
181
-
};
230
+
static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
231
+
{
232
+
struct platform_device *pdev = to_platform_device(dev->dev);
233
+
int ret;
234
+
235
+
switch (dev->flags & MODEL_MASK) {
236
+
case MODEL_BAIKAL_BT1:
237
+
ret = bt1_i2c_request_regs(dev);
238
+
break;
239
+
default:
240
+
dev->base = devm_platform_ioremap_resource(pdev, 0);
241
+
ret = PTR_ERR_OR_ZERO(dev->base);
242
+
break;
243
+
}
244
+
245
+
return ret;
246
+
}
182
247
183
248
static int dw_i2c_plat_probe(struct platform_device *pdev)
184
249
{
···
197
240
struct i2c_adapter *adap;
198
241
struct dw_i2c_dev *dev;
199
242
struct i2c_timings *t;
200
-
u32 acpi_speed;
201
-
struct resource *mem;
202
-
int i, irq, ret;
243
+
int irq, ret;
203
244
204
245
irq = platform_get_irq(pdev, 0);
205
246
if (irq < 0)
···
207
252
if (!dev)
208
253
return -ENOMEM;
209
254
210
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
211
-
dev->base = devm_ioremap_resource(&pdev->dev, mem);
212
-
if (IS_ERR(dev->base))
213
-
return PTR_ERR(dev->base);
214
-
255
+
dev->flags = (uintptr_t)device_get_match_data(&pdev->dev);
215
256
dev->dev = &pdev->dev;
216
257
dev->irq = irq;
217
258
platform_set_drvdata(pdev, dev);
259
+
260
+
ret = dw_i2c_plat_request_regs(dev);
261
+
if (ret)
262
+
return ret;
218
263
219
264
dev->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
220
265
if (IS_ERR(dev->rst))
···
228
273
else
229
274
i2c_parse_fw_timings(&pdev->dev, t, false);
230
275
231
-
acpi_speed = i2c_acpi_find_bus_speed(&pdev->dev);
232
-
/*
233
-
* Some DSTDs use a non standard speed, round down to the lowest
234
-
* standard speed.
235
-
*/
236
-
for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
237
-
if (acpi_speed >= supported_speeds[i])
238
-
break;
239
-
}
240
-
acpi_speed = i < ARRAY_SIZE(supported_speeds) ? supported_speeds[i] : 0;
241
-
242
-
/*
243
-
* Find bus speed from the "clock-frequency" device property, ACPI
244
-
* or by using fast mode if neither is set.
245
-
*/
246
-
if (acpi_speed && t->bus_freq_hz)
247
-
t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
248
-
else if (acpi_speed || t->bus_freq_hz)
249
-
t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
250
-
else
251
-
t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
252
-
253
-
dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev);
276
+
i2c_dw_acpi_adjust_bus_speed(&pdev->dev);
254
277
255
278
if (pdev->dev.of_node)
256
279
dw_i2c_of_configure(pdev);
257
280
258
281
if (has_acpi_companion(&pdev->dev))
259
-
dw_i2c_acpi_configure(pdev);
282
+
i2c_dw_acpi_configure(&pdev->dev);
260
283
261
-
/*
262
-
* Only standard mode at 100kHz, fast mode at 400kHz,
263
-
* fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
264
-
*/
265
-
for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
266
-
if (t->bus_freq_hz == supported_speeds[i])
267
-
break;
268
-
}
269
-
if (i == ARRAY_SIZE(supported_speeds)) {
270
-
dev_err(&pdev->dev,
271
-
"%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
272
-
t->bus_freq_hz);
273
-
ret = -EINVAL;
284
+
ret = i2c_dw_validate_speed(dev);
285
+
if (ret)
274
286
goto exit_reset;
275
-
}
276
287
277
288
ret = i2c_dw_probe_lock_support(dev);
278
289
if (ret)
279
290
goto exit_reset;
280
291
281
-
if (i2c_detect_slave_mode(&pdev->dev))
282
-
i2c_dw_configure_slave(dev);
283
-
else
284
-
i2c_dw_configure_master(dev);
292
+
i2c_dw_configure(dev);
285
293
286
294
/* Optional interface clock */
287
295
dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
···
295
377
296
378
pm_runtime_enable(&pdev->dev);
297
379
298
-
if (dev->mode == DW_IC_SLAVE)
299
-
ret = i2c_dw_probe_slave(dev);
300
-
else
301
-
ret = i2c_dw_probe(dev);
302
-
380
+
ret = i2c_dw_probe(dev);
303
381
if (ret)
304
382
goto exit_probe;
305
383
+52
-36
drivers/i2c/busses/i2c-designware-slave.c
+52
-36
drivers/i2c/busses/i2c-designware-slave.c
···
14
14
#include <linux/io.h>
15
15
#include <linux/module.h>
16
16
#include <linux/pm_runtime.h>
17
+
#include <linux/regmap.h>
17
18
18
19
#include "i2c-designware-core.h"
19
20
20
21
static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
21
22
{
22
23
/* Configure Tx/Rx FIFO threshold levels. */
23
-
dw_writel(dev, 0, DW_IC_TX_TL);
24
-
dw_writel(dev, 0, DW_IC_RX_TL);
24
+
regmap_write(dev->map, DW_IC_TX_TL, 0);
25
+
regmap_write(dev->map, DW_IC_RX_TL, 0);
25
26
26
27
/* Configure the I2C slave. */
27
-
dw_writel(dev, dev->slave_cfg, DW_IC_CON);
28
-
dw_writel(dev, DW_IC_INTR_SLAVE_MASK, DW_IC_INTR_MASK);
28
+
regmap_write(dev->map, DW_IC_CON, dev->slave_cfg);
29
+
regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);
29
30
}
30
31
31
32
/**
···
50
49
51
50
/* Write SDA hold time if supported */
52
51
if (dev->sda_hold_time)
53
-
dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
52
+
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
54
53
55
54
i2c_dw_configure_fifo_slave(dev);
56
55
i2c_dw_release_lock(dev);
···
73
72
* the address to which the DW_apb_i2c responds.
74
73
*/
75
74
__i2c_dw_disable_nowait(dev);
76
-
dw_writel(dev, slave->addr, DW_IC_SAR);
75
+
regmap_write(dev->map, DW_IC_SAR, slave->addr);
77
76
dev->slave = slave;
78
77
79
78
__i2c_dw_enable(dev);
···
104
103
105
104
static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
106
105
{
107
-
u32 stat;
106
+
u32 stat, dummy;
108
107
109
108
/*
110
109
* The IC_INTR_STAT register just indicates "enabled" interrupts.
···
112
111
* in the IC_RAW_INTR_STAT register.
113
112
*
114
113
* That is,
115
-
* stat = dw_readl(IC_INTR_STAT);
114
+
* stat = readl(IC_INTR_STAT);
116
115
* equals to,
117
-
* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
116
+
* stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
118
117
*
119
118
* The raw version might be useful for debugging purposes.
120
119
*/
121
-
stat = dw_readl(dev, DW_IC_INTR_STAT);
120
+
regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
122
121
123
122
/*
124
123
* Do not use the IC_CLR_INTR register to clear interrupts, or
125
124
* you'll miss some interrupts, triggered during the period from
126
-
* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
125
+
* readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
127
126
*
128
127
* Instead, use the separately-prepared IC_CLR_* registers.
129
128
*/
130
129
if (stat & DW_IC_INTR_TX_ABRT)
131
-
dw_readl(dev, DW_IC_CLR_TX_ABRT);
130
+
regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
132
131
if (stat & DW_IC_INTR_RX_UNDER)
133
-
dw_readl(dev, DW_IC_CLR_RX_UNDER);
132
+
regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
134
133
if (stat & DW_IC_INTR_RX_OVER)
135
-
dw_readl(dev, DW_IC_CLR_RX_OVER);
134
+
regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
136
135
if (stat & DW_IC_INTR_TX_OVER)
137
-
dw_readl(dev, DW_IC_CLR_TX_OVER);
136
+
regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
138
137
if (stat & DW_IC_INTR_RX_DONE)
139
-
dw_readl(dev, DW_IC_CLR_RX_DONE);
138
+
regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
140
139
if (stat & DW_IC_INTR_ACTIVITY)
141
-
dw_readl(dev, DW_IC_CLR_ACTIVITY);
140
+
regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
142
141
if (stat & DW_IC_INTR_STOP_DET)
143
-
dw_readl(dev, DW_IC_CLR_STOP_DET);
142
+
regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
144
143
if (stat & DW_IC_INTR_START_DET)
145
-
dw_readl(dev, DW_IC_CLR_START_DET);
144
+
regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
146
145
if (stat & DW_IC_INTR_GEN_CALL)
147
-
dw_readl(dev, DW_IC_CLR_GEN_CALL);
146
+
regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
148
147
149
148
return stat;
150
149
}
···
156
155
157
156
static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
158
157
{
159
-
u32 raw_stat, stat, enabled;
160
-
u8 val, slave_activity;
158
+
u32 raw_stat, stat, enabled, tmp;
159
+
u8 val = 0, slave_activity;
161
160
162
-
stat = dw_readl(dev, DW_IC_INTR_STAT);
163
-
enabled = dw_readl(dev, DW_IC_ENABLE);
164
-
raw_stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
165
-
slave_activity = ((dw_readl(dev, DW_IC_STATUS) &
166
-
DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
161
+
regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
162
+
regmap_read(dev->map, DW_IC_ENABLE, &enabled);
163
+
regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_stat);
164
+
regmap_read(dev->map, DW_IC_STATUS, &tmp);
165
+
slave_activity = ((tmp & DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
167
166
168
167
if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
169
168
return 0;
···
178
177
if (stat & DW_IC_INTR_RD_REQ) {
179
178
if (slave_activity) {
180
179
if (stat & DW_IC_INTR_RX_FULL) {
181
-
val = dw_readl(dev, DW_IC_DATA_CMD);
180
+
regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
181
+
val = tmp;
182
182
183
183
if (!i2c_slave_event(dev->slave,
184
184
I2C_SLAVE_WRITE_RECEIVED,
···
187
185
dev_vdbg(dev->dev, "Byte %X acked!",
188
186
val);
189
187
}
190
-
dw_readl(dev, DW_IC_CLR_RD_REQ);
188
+
regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
191
189
stat = i2c_dw_read_clear_intrbits_slave(dev);
192
190
} else {
193
-
dw_readl(dev, DW_IC_CLR_RD_REQ);
194
-
dw_readl(dev, DW_IC_CLR_RX_UNDER);
191
+
regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
192
+
regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &tmp);
195
193
stat = i2c_dw_read_clear_intrbits_slave(dev);
196
194
}
197
195
if (!i2c_slave_event(dev->slave,
198
196
I2C_SLAVE_READ_REQUESTED,
199
197
&val))
200
-
dw_writel(dev, val, DW_IC_DATA_CMD);
198
+
regmap_write(dev->map, DW_IC_DATA_CMD, val);
201
199
}
202
200
}
203
201
204
202
if (stat & DW_IC_INTR_RX_DONE) {
205
203
if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
206
204
&val))
207
-
dw_readl(dev, DW_IC_CLR_RX_DONE);
205
+
regmap_read(dev->map, DW_IC_CLR_RX_DONE, &tmp);
208
206
209
207
i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
210
208
stat = i2c_dw_read_clear_intrbits_slave(dev);
···
212
210
}
213
211
214
212
if (stat & DW_IC_INTR_RX_FULL) {
215
-
val = dw_readl(dev, DW_IC_DATA_CMD);
213
+
regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
214
+
val = tmp;
216
215
if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
217
216
&val))
218
217
dev_vdbg(dev->dev, "Byte %X acked!", val);
···
244
241
.unreg_slave = i2c_dw_unreg_slave,
245
242
};
246
243
244
+
void i2c_dw_configure_slave(struct dw_i2c_dev *dev)
245
+
{
246
+
dev->functionality = I2C_FUNC_SLAVE | DW_IC_DEFAULT_FUNCTIONALITY;
247
+
248
+
dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL |
249
+
DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED;
250
+
251
+
dev->mode = DW_IC_SLAVE;
252
+
}
253
+
EXPORT_SYMBOL_GPL(i2c_dw_configure_slave);
254
+
247
255
int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
248
256
{
249
257
struct i2c_adapter *adap = &dev->adapter;
···
266
252
dev->disable = i2c_dw_disable;
267
253
dev->disable_int = i2c_dw_disable_int;
268
254
269
-
ret = i2c_dw_set_reg_access(dev);
255
+
ret = i2c_dw_init_regmap(dev);
270
256
if (ret)
271
257
return ret;
272
258
···
274
260
if (ret)
275
261
return ret;
276
262
277
-
i2c_dw_set_fifo_size(dev);
263
+
ret = i2c_dw_set_fifo_size(dev);
264
+
if (ret)
265
+
return ret;
278
266
279
267
ret = dev->init(dev);
280
268
if (ret)
+1
-3
drivers/i2c/busses/i2c-digicolor.c
+1
-3
drivers/i2c/busses/i2c-digicolor.c
···
290
290
{
291
291
struct device_node *np = pdev->dev.of_node;
292
292
struct dc_i2c *i2c;
293
-
struct resource *r;
294
293
int ret = 0, irq;
295
294
296
295
i2c = devm_kzalloc(&pdev->dev, sizeof(struct dc_i2c), GFP_KERNEL);
···
310
311
if (IS_ERR(i2c->clk))
311
312
return PTR_ERR(i2c->clk);
312
313
313
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
314
-
i2c->regs = devm_ioremap_resource(&pdev->dev, r);
314
+
i2c->regs = devm_platform_ioremap_resource(pdev, 0);
315
315
if (IS_ERR(i2c->regs))
316
316
return PTR_ERR(i2c->regs);
317
317
-4
drivers/i2c/busses/i2c-efm32.c
-4
drivers/i2c/busses/i2c-efm32.c
···
312
312
int ret;
313
313
u32 clkdiv;
314
314
315
-
if (!np)
316
-
return -EINVAL;
317
-
318
315
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
319
316
if (!ddata)
320
317
return -ENOMEM;
···
349
352
350
353
ret = platform_get_irq(pdev, 0);
351
354
if (ret <= 0) {
352
-
dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
353
355
if (!ret)
354
356
ret = -EINVAL;
355
357
return ret;
+1
-3
drivers/i2c/busses/i2c-emev2.c
+1
-3
drivers/i2c/busses/i2c-emev2.c
···
361
361
static int em_i2c_probe(struct platform_device *pdev)
362
362
{
363
363
struct em_i2c_device *priv;
364
-
struct resource *r;
365
364
int ret;
366
365
367
366
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
368
367
if (!priv)
369
368
return -ENOMEM;
370
369
371
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
372
-
priv->base = devm_ioremap_resource(&pdev->dev, r);
370
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
373
371
if (IS_ERR(priv->base))
374
372
return PTR_ERR(priv->base);
375
373
+3
-5
drivers/i2c/busses/i2c-exynos5.c
+3
-5
drivers/i2c/busses/i2c-exynos5.c
···
736
736
{
737
737
struct device_node *np = pdev->dev.of_node;
738
738
struct exynos5_i2c *i2c;
739
-
struct resource *mem;
740
739
int ret;
741
740
742
741
i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
···
761
762
if (ret)
762
763
return ret;
763
764
764
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
765
-
i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
765
+
i2c->regs = devm_platform_ioremap_resource(pdev, 0);
766
766
if (IS_ERR(i2c->regs)) {
767
767
ret = PTR_ERR(i2c->regs);
768
768
goto err_clk;
···
877
879
module_platform_driver(exynos5_i2c_driver);
878
880
879
881
MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
880
-
MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
881
-
MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
882
+
MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
883
+
MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
882
884
MODULE_LICENSE("GPL v2");
+1
-3
drivers/i2c/busses/i2c-hix5hd2.c
+1
-3
drivers/i2c/busses/i2c-hix5hd2.c
···
388
388
{
389
389
struct device_node *np = pdev->dev.of_node;
390
390
struct hix5hd2_i2c_priv *priv;
391
-
struct resource *mem;
392
391
unsigned int freq;
393
392
int irq, ret;
394
393
···
408
409
}
409
410
}
410
411
411
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412
-
priv->regs = devm_ioremap_resource(&pdev->dev, mem);
412
+
priv->regs = devm_platform_ioremap_resource(pdev, 0);
413
413
if (IS_ERR(priv->regs))
414
414
return PTR_ERR(priv->regs);
415
415
+6
drivers/i2c/busses/i2c-i801.c
+6
drivers/i2c/busses/i2c-i801.c
···
1318
1318
1319
1319
if (is_dell_system_with_lis3lv02d())
1320
1320
register_dell_lis3lv02d_i2c_device(priv);
1321
+
1322
+
/* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1323
+
#if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1324
+
if (!priv->mux_drvdata)
1325
+
#endif
1326
+
i2c_register_spd(&priv->adapter);
1321
1327
}
1322
1328
#else
1323
1329
static void __init input_apanel_init(void) {}
+1
drivers/i2c/busses/i2c-icy.c
+1
drivers/i2c/busses/i2c-icy.c
+2
-6
drivers/i2c/busses/i2c-img-scb.c
+2
-6
drivers/i2c/busses/i2c-img-scb.c
···
1330
1330
{
1331
1331
struct device_node *node = pdev->dev.of_node;
1332
1332
struct img_i2c *i2c;
1333
-
struct resource *res;
1334
1333
int irq, ret;
1335
1334
u32 val;
1336
1335
···
1337
1338
if (!i2c)
1338
1339
return -ENOMEM;
1339
1340
1340
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1341
-
i2c->base = devm_ioremap_resource(&pdev->dev, res);
1341
+
i2c->base = devm_platform_ioremap_resource(pdev, 0);
1342
1342
if (IS_ERR(i2c->base))
1343
1343
return PTR_ERR(i2c->base);
1344
1344
1345
1345
irq = platform_get_irq(pdev, 0);
1346
-
if (irq < 0) {
1347
-
dev_err(&pdev->dev, "can't get irq number\n");
1346
+
if (irq < 0)
1348
1347
return irq;
1349
-
}
1350
1348
1351
1349
i2c->sys_clk = devm_clk_get(&pdev->dev, "sys");
1352
1350
if (IS_ERR(i2c->sys_clk)) {
+1
-3
drivers/i2c/busses/i2c-imx-lpi2c.c
+1
-3
drivers/i2c/busses/i2c-imx-lpi2c.c
···
551
551
return PTR_ERR(lpi2c_imx->base);
552
552
553
553
irq = platform_get_irq(pdev, 0);
554
-
if (irq < 0) {
555
-
dev_err(&pdev->dev, "can't get irq number\n");
554
+
if (irq < 0)
556
555
return irq;
557
-
}
558
556
559
557
lpi2c_imx->adapter.owner = THIS_MODULE;
560
558
lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
+1
-3
drivers/i2c/busses/i2c-jz4780.c
+1
-3
drivers/i2c/busses/i2c-jz4780.c
···
763
763
int ret = 0;
764
764
unsigned int clk_freq = 0;
765
765
unsigned short tmp;
766
-
struct resource *r;
767
766
struct jz4780_i2c *i2c;
768
767
769
768
i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
···
786
787
init_completion(&i2c->trans_waitq);
787
788
spin_lock_init(&i2c->lock);
788
789
789
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
790
-
i2c->iomem = devm_ioremap_resource(&pdev->dev, r);
790
+
i2c->iomem = devm_platform_ioremap_resource(pdev, 0);
791
791
if (IS_ERR(i2c->iomem))
792
792
return PTR_ERR(i2c->iomem);
793
793
+2
-6
drivers/i2c/busses/i2c-lpc2k.c
+2
-6
drivers/i2c/busses/i2c-lpc2k.c
···
346
346
static int i2c_lpc2k_probe(struct platform_device *pdev)
347
347
{
348
348
struct lpc2k_i2c *i2c;
349
-
struct resource *res;
350
349
u32 bus_clk_rate;
351
350
u32 scl_high;
352
351
u32 clkrate;
···
355
356
if (!i2c)
356
357
return -ENOMEM;
357
358
358
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359
-
i2c->base = devm_ioremap_resource(&pdev->dev, res);
359
+
i2c->base = devm_platform_ioremap_resource(pdev, 0);
360
360
if (IS_ERR(i2c->base))
361
361
return PTR_ERR(i2c->base);
362
362
363
363
i2c->irq = platform_get_irq(pdev, 0);
364
-
if (i2c->irq < 0) {
365
-
dev_err(&pdev->dev, "can't get interrupt resource\n");
364
+
if (i2c->irq < 0)
366
365
return i2c->irq;
367
-
}
368
366
369
367
init_waitqueue_head(&i2c->wait);
370
368
+2
-6
drivers/i2c/busses/i2c-meson.c
+2
-6
drivers/i2c/busses/i2c-meson.c
···
397
397
{
398
398
struct device_node *np = pdev->dev.of_node;
399
399
struct meson_i2c *i2c;
400
-
struct resource *mem;
401
400
struct i2c_timings timings;
402
401
int irq, ret = 0;
403
402
···
421
422
return PTR_ERR(i2c->clk);
422
423
}
423
424
424
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
425
-
i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
425
+
i2c->regs = devm_platform_ioremap_resource(pdev, 0);
426
426
if (IS_ERR(i2c->regs))
427
427
return PTR_ERR(i2c->regs);
428
428
429
429
irq = platform_get_irq(pdev, 0);
430
-
if (irq < 0) {
431
-
dev_err(&pdev->dev, "can't find IRQ\n");
430
+
if (irq < 0)
432
431
return irq;
433
-
}
434
432
435
433
ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
436
434
if (ret < 0) {
+275
-48
drivers/i2c/busses/i2c-mt65xx.c
+275
-48
drivers/i2c/busses/i2c-mt65xx.c
···
40
40
#define I2C_SOFT_RST 0x0001
41
41
#define I2C_FIFO_ADDR_CLR 0x0001
42
42
#define I2C_DELAY_LEN 0x0002
43
-
#define I2C_ST_START_CON 0x8001
44
-
#define I2C_FS_START_CON 0x1800
45
43
#define I2C_TIME_CLR_VALUE 0x0000
46
44
#define I2C_TIME_DEFAULT_VALUE 0x0003
47
45
#define I2C_WRRD_TRANAC_VALUE 0x0002
48
46
#define I2C_RD_TRANAC_VALUE 0x0001
47
+
#define I2C_SCL_MIS_COMP_VALUE 0x0000
49
48
50
49
#define I2C_DMA_CON_TX 0x0000
51
50
#define I2C_DMA_CON_RX 0x0001
···
54
55
#define I2C_DMA_HARD_RST 0x0002
55
56
#define I2C_DMA_4G_MODE 0x0001
56
57
57
-
#define I2C_DEFAULT_CLK_DIV 5
58
58
#define MAX_SAMPLE_CNT_DIV 8
59
59
#define MAX_STEP_CNT_DIV 64
60
+
#define MAX_CLOCK_DIV 256
60
61
#define MAX_HS_STEP_CNT_DIV 8
62
+
#define I2C_STANDARD_MODE_BUFFER (1000 / 2)
63
+
#define I2C_FAST_MODE_BUFFER (300 / 2)
64
+
#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
61
65
62
66
#define I2C_CONTROL_RS (0x1 << 1)
63
67
#define I2C_CONTROL_DMA_EN (0x1 << 2)
···
125
123
OFFSET_TRANSFER_LEN_AUX,
126
124
OFFSET_CLOCK_DIV,
127
125
OFFSET_LTIMING,
126
+
OFFSET_SCL_HIGH_LOW_RATIO,
127
+
OFFSET_HS_SCL_HIGH_LOW_RATIO,
128
+
OFFSET_SCL_MIS_COMP_POINT,
129
+
OFFSET_STA_STO_AC_TIMING,
130
+
OFFSET_HS_STA_STO_AC_TIMING,
131
+
OFFSET_SDA_TIMING,
128
132
};
129
133
130
134
static const u16 mt_i2c_regs_v1[] = {
···
158
150
[OFFSET_DEBUGCTRL] = 0x68,
159
151
[OFFSET_TRANSFER_LEN_AUX] = 0x6c,
160
152
[OFFSET_CLOCK_DIV] = 0x70,
153
+
[OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
154
+
[OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
155
+
[OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
156
+
[OFFSET_STA_STO_AC_TIMING] = 0x80,
157
+
[OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
158
+
[OFFSET_SDA_TIMING] = 0x88,
161
159
};
162
160
163
161
static const u16 mt_i2c_regs_v2[] = {
···
182
168
[OFFSET_HS] = 0x30,
183
169
[OFFSET_IO_CONFIG] = 0x34,
184
170
[OFFSET_FIFO_ADDR_CLR] = 0x38,
171
+
[OFFSET_SDA_TIMING] = 0x3c,
185
172
[OFFSET_TRANSFER_LEN_AUX] = 0x44,
186
173
[OFFSET_CLOCK_DIV] = 0x48,
187
174
[OFFSET_SOFTRESET] = 0x50,
175
+
[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
188
176
[OFFSET_DEBUGSTAT] = 0xe0,
189
177
[OFFSET_DEBUGCTRL] = 0xe8,
190
178
[OFFSET_FIFO_STAT] = 0xf4,
···
205
189
unsigned char timing_adjust: 1;
206
190
unsigned char dma_sync: 1;
207
191
unsigned char ltiming_adjust: 1;
192
+
};
193
+
194
+
struct mtk_i2c_ac_timing {
195
+
u16 htiming;
196
+
u16 ltiming;
197
+
u16 hs;
198
+
u16 ext;
199
+
u16 inter_clk_div;
200
+
u16 scl_hl_ratio;
201
+
u16 hs_scl_hl_ratio;
202
+
u16 sta_stop;
203
+
u16 hs_sta_stop;
204
+
u16 sda_timing;
208
205
};
209
206
210
207
struct mtk_i2c {
···
244
215
u16 ltiming_reg;
245
216
unsigned char auto_restart;
246
217
bool ignore_restart_irq;
218
+
struct mtk_i2c_ac_timing ac_timing;
247
219
const struct mtk_i2c_compatible *dev_comp;
220
+
};
221
+
222
+
/**
223
+
* struct i2c_spec_values:
224
+
* min_low_ns: min LOW period of the SCL clock
225
+
* min_su_sta_ns: min set-up time for a repeated START condition
226
+
* max_hd_dat_ns: max data hold time
227
+
* min_su_dat_ns: min data set-up time
228
+
*/
229
+
struct i2c_spec_values {
230
+
unsigned int min_low_ns;
231
+
unsigned int min_high_ns;
232
+
unsigned int min_su_sta_ns;
233
+
unsigned int max_hd_dat_ns;
234
+
unsigned int min_su_dat_ns;
235
+
};
236
+
237
+
static const struct i2c_spec_values standard_mode_spec = {
238
+
.min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
239
+
.min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
240
+
.max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
241
+
.min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
242
+
};
243
+
244
+
static const struct i2c_spec_values fast_mode_spec = {
245
+
.min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
246
+
.min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
247
+
.max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
248
+
.min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
249
+
};
250
+
251
+
static const struct i2c_spec_values fast_mode_plus_spec = {
252
+
.min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
253
+
.min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
254
+
.max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
255
+
.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
248
256
};
249
257
250
258
static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
···
463
397
if (i2c->dev_comp->dcm)
464
398
mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
465
399
466
-
if (i2c->dev_comp->timing_adjust)
467
-
mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
468
-
469
400
mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
470
401
mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
471
402
if (i2c->dev_comp->ltiming_adjust)
472
403
mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
404
+
405
+
if (i2c->dev_comp->timing_adjust) {
406
+
mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF);
407
+
mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
408
+
OFFSET_CLOCK_DIV);
409
+
mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
410
+
OFFSET_SCL_MIS_COMP_POINT);
411
+
mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
412
+
OFFSET_SDA_TIMING);
413
+
414
+
if (i2c->dev_comp->ltiming_adjust) {
415
+
mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
416
+
OFFSET_TIMING);
417
+
mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
418
+
mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
419
+
OFFSET_LTIMING);
420
+
} else {
421
+
mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
422
+
OFFSET_SCL_HIGH_LOW_RATIO);
423
+
mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
424
+
OFFSET_HS_SCL_HIGH_LOW_RATIO);
425
+
mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
426
+
OFFSET_STA_STO_AC_TIMING);
427
+
mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
428
+
OFFSET_HS_STA_STO_AC_TIMING);
429
+
}
430
+
}
473
431
474
432
/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
475
433
if (i2c->have_pmic)
···
510
420
writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
511
421
udelay(50);
512
422
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
423
+
}
424
+
425
+
static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
426
+
{
427
+
if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
428
+
return &standard_mode_spec;
429
+
else if (speed <= I2C_MAX_FAST_MODE_FREQ)
430
+
return &fast_mode_spec;
431
+
else
432
+
return &fast_mode_plus_spec;
433
+
}
434
+
435
+
static int mtk_i2c_max_step_cnt(unsigned int target_speed)
436
+
{
437
+
if (target_speed > I2C_MAX_FAST_MODE_FREQ)
438
+
return MAX_HS_STEP_CNT_DIV;
439
+
else
440
+
return MAX_STEP_CNT_DIV;
441
+
}
442
+
443
+
/*
444
+
* Check and Calculate i2c ac-timing
445
+
*
446
+
* Hardware design:
447
+
* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
448
+
* xxx_cnt_div = spec->min_xxx_ns / sample_ns
449
+
*
450
+
* Sample_ns is rounded down for xxx_cnt_div would be greater
451
+
* than the smallest spec.
452
+
* The sda_timing is chosen as the middle value between
453
+
* the largest and smallest.
454
+
*/
455
+
static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
456
+
unsigned int clk_src,
457
+
unsigned int check_speed,
458
+
unsigned int step_cnt,
459
+
unsigned int sample_cnt)
460
+
{
461
+
const struct i2c_spec_values *spec;
462
+
unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
463
+
unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
464
+
unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
465
+
clk_src);
466
+
467
+
if (!i2c->dev_comp->timing_adjust)
468
+
return 0;
469
+
470
+
if (i2c->dev_comp->ltiming_adjust)
471
+
max_sta_cnt = 0x100;
472
+
473
+
spec = mtk_i2c_get_spec(check_speed);
474
+
475
+
if (i2c->dev_comp->ltiming_adjust)
476
+
clk_ns = 1000000000 / clk_src;
477
+
else
478
+
clk_ns = sample_ns / 2;
479
+
480
+
su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
481
+
if (su_sta_cnt > max_sta_cnt)
482
+
return -1;
483
+
484
+
low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
485
+
max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
486
+
if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
487
+
if (low_cnt > step_cnt) {
488
+
high_cnt = 2 * step_cnt - low_cnt;
489
+
} else {
490
+
high_cnt = step_cnt;
491
+
low_cnt = step_cnt;
492
+
}
493
+
} else {
494
+
return -2;
495
+
}
496
+
497
+
sda_max = spec->max_hd_dat_ns / sample_ns;
498
+
if (sda_max > low_cnt)
499
+
sda_max = 0;
500
+
501
+
sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
502
+
if (sda_min < low_cnt)
503
+
sda_min = 0;
504
+
505
+
if (sda_min > sda_max)
506
+
return -3;
507
+
508
+
if (check_speed > I2C_MAX_FAST_MODE_FREQ) {
509
+
if (i2c->dev_comp->ltiming_adjust) {
510
+
i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
511
+
(sample_cnt << 12) | (high_cnt << 8);
512
+
i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
513
+
i2c->ac_timing.ltiming |= (sample_cnt << 12) |
514
+
(low_cnt << 9);
515
+
i2c->ac_timing.ext &= ~GENMASK(7, 1);
516
+
i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
517
+
} else {
518
+
i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
519
+
(high_cnt << 6) | low_cnt;
520
+
i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
521
+
su_sta_cnt;
522
+
}
523
+
i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
524
+
i2c->ac_timing.sda_timing |= (1 << 12) |
525
+
((sda_max + sda_min) / 2) << 6;
526
+
} else {
527
+
if (i2c->dev_comp->ltiming_adjust) {
528
+
i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
529
+
i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
530
+
i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
531
+
} else {
532
+
i2c->ac_timing.scl_hl_ratio = (1 << 12) |
533
+
(high_cnt << 6) | low_cnt;
534
+
i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
535
+
su_sta_cnt;
536
+
}
537
+
538
+
i2c->ac_timing.sda_timing = (1 << 12) |
539
+
(sda_max + sda_min) / 2;
540
+
}
541
+
542
+
return 0;
513
543
}
514
544
515
545
/*
···
656
446
unsigned int opt_div;
657
447
unsigned int best_mul;
658
448
unsigned int cnt_mul;
449
+
int ret = -EINVAL;
659
450
660
451
if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
661
452
target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ;
662
453
663
-
if (target_speed > I2C_MAX_FAST_MODE_FREQ)
664
-
max_step_cnt = MAX_HS_STEP_CNT_DIV;
665
-
else
666
-
max_step_cnt = MAX_STEP_CNT_DIV;
667
-
454
+
max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
668
455
base_step_cnt = max_step_cnt;
669
456
/* Find the best combination */
670
457
opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
···
680
473
continue;
681
474
682
475
if (cnt_mul < best_mul) {
476
+
ret = mtk_i2c_check_ac_timing(i2c, clk_src,
477
+
target_speed, step_cnt - 1, sample_cnt - 1);
478
+
if (ret)
479
+
continue;
480
+
683
481
best_mul = cnt_mul;
684
482
base_sample_cnt = sample_cnt;
685
483
base_step_cnt = step_cnt;
···
692
480
break;
693
481
}
694
482
}
483
+
484
+
if (ret)
485
+
return -EINVAL;
695
486
696
487
sample_cnt = base_sample_cnt;
697
488
step_cnt = base_step_cnt;
···
721
506
unsigned int l_step_cnt;
722
507
unsigned int l_sample_cnt;
723
508
unsigned int target_speed;
509
+
unsigned int clk_div;
510
+
unsigned int max_clk_div;
724
511
int ret;
725
512
726
-
clk_src = parent_clk / i2c->clk_src_div;
727
513
target_speed = i2c->speed_hz;
514
+
parent_clk /= i2c->clk_src_div;
728
515
729
-
if (target_speed > I2C_MAX_FAST_MODE_FREQ) {
730
-
/* Set master code speed register */
731
-
ret = mtk_i2c_calculate_speed(i2c, clk_src, I2C_MAX_FAST_MODE_FREQ,
732
-
&l_step_cnt, &l_sample_cnt);
733
-
if (ret < 0)
734
-
return ret;
516
+
if (i2c->dev_comp->timing_adjust)
517
+
max_clk_div = MAX_CLOCK_DIV;
518
+
else
519
+
max_clk_div = 1;
735
520
736
-
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
521
+
for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
522
+
clk_src = parent_clk / clk_div;
737
523
738
-
/* Set the high speed mode register */
739
-
ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
740
-
&step_cnt, &sample_cnt);
741
-
if (ret < 0)
742
-
return ret;
524
+
if (target_speed > I2C_MAX_FAST_MODE_FREQ) {
525
+
/* Set master code speed register */
526
+
ret = mtk_i2c_calculate_speed(i2c, clk_src,
527
+
I2C_MAX_FAST_MODE_FREQ,
528
+
&l_step_cnt,
529
+
&l_sample_cnt);
530
+
if (ret < 0)
531
+
continue;
743
532
744
-
i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
745
-
(sample_cnt << 12) | (step_cnt << 8);
533
+
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
746
534
747
-
if (i2c->dev_comp->ltiming_adjust)
748
-
i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
749
-
(sample_cnt << 12) | (step_cnt << 9);
750
-
} else {
751
-
ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
752
-
&step_cnt, &sample_cnt);
753
-
if (ret < 0)
754
-
return ret;
535
+
/* Set the high speed mode register */
536
+
ret = mtk_i2c_calculate_speed(i2c, clk_src,
537
+
target_speed, &step_cnt,
538
+
&sample_cnt);
539
+
if (ret < 0)
540
+
continue;
755
541
756
-
i2c->timing_reg = (sample_cnt << 8) | step_cnt;
542
+
i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
543
+
(sample_cnt << 12) | (step_cnt << 8);
757
544
758
-
/* Disable the high speed transaction */
759
-
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
545
+
if (i2c->dev_comp->ltiming_adjust)
546
+
i2c->ltiming_reg =
547
+
(l_sample_cnt << 6) | l_step_cnt |
548
+
(sample_cnt << 12) | (step_cnt << 9);
549
+
} else {
550
+
ret = mtk_i2c_calculate_speed(i2c, clk_src,
551
+
target_speed, &l_step_cnt,
552
+
&l_sample_cnt);
553
+
if (ret < 0)
554
+
continue;
760
555
761
-
if (i2c->dev_comp->ltiming_adjust)
762
-
i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
556
+
i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
557
+
558
+
/* Disable the high speed transaction */
559
+
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
560
+
561
+
if (i2c->dev_comp->ltiming_adjust)
562
+
i2c->ltiming_reg =
563
+
(l_sample_cnt << 6) | l_step_cnt;
564
+
}
565
+
566
+
break;
763
567
}
568
+
569
+
i2c->ac_timing.inter_clk_div = clk_div - 1;
764
570
765
571
return 0;
766
572
}
···
821
585
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
822
586
823
587
mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
824
-
825
-
/* set start condition */
826
-
if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
827
-
mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
828
-
else
829
-
mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
830
588
831
589
addr_reg = i2c_8bit_addr_from_msg(msgs);
832
590
mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
···
1177
947
ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1178
948
if (ret)
1179
949
return -EINVAL;
1180
-
1181
-
if (i2c->dev_comp->timing_adjust)
1182
-
i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
1183
950
1184
951
if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1185
952
return -EINVAL;
+1
-3
drivers/i2c/busses/i2c-mv64xxx.c
+1
-3
drivers/i2c/busses/i2c-mv64xxx.c
···
877
877
{
878
878
struct mv64xxx_i2c_data *drv_data;
879
879
struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
880
-
struct resource *r;
881
880
int rc;
882
881
883
882
if ((!pdata && !pd->dev.of_node))
···
887
888
if (!drv_data)
888
889
return -ENOMEM;
889
890
890
-
r = platform_get_resource(pd, IORESOURCE_MEM, 0);
891
-
drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
891
+
drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
892
892
if (IS_ERR(drv_data->reg_base))
893
893
return PTR_ERR(drv_data->reg_base);
894
894
+2342
drivers/i2c/busses/i2c-npcm7xx.c
+2342
drivers/i2c/busses/i2c-npcm7xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Nuvoton NPCM7xx I2C Controller driver
4
+
*
5
+
* Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
6
+
*/
7
+
#include <linux/bitfield.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/debugfs.h>
10
+
#include <linux/errno.h>
11
+
#include <linux/i2c.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/iopoll.h>
14
+
#include <linux/irq.h>
15
+
#include <linux/jiffies.h>
16
+
#include <linux/kernel.h>
17
+
#include <linux/mfd/syscon.h>
18
+
#include <linux/module.h>
19
+
#include <linux/of.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/regmap.h>
22
+
23
+
enum i2c_mode {
24
+
I2C_MASTER,
25
+
I2C_SLAVE,
26
+
};
27
+
28
+
/*
29
+
* External I2C Interface driver xfer indication values, which indicate status
30
+
* of the bus.
31
+
*/
32
+
enum i2c_state_ind {
33
+
I2C_NO_STATUS_IND = 0,
34
+
I2C_SLAVE_RCV_IND,
35
+
I2C_SLAVE_XMIT_IND,
36
+
I2C_SLAVE_XMIT_MISSING_DATA_IND,
37
+
I2C_SLAVE_RESTART_IND,
38
+
I2C_SLAVE_DONE_IND,
39
+
I2C_MASTER_DONE_IND,
40
+
I2C_NACK_IND,
41
+
I2C_BUS_ERR_IND,
42
+
I2C_WAKE_UP_IND,
43
+
I2C_BLOCK_BYTES_ERR_IND,
44
+
I2C_SLAVE_RCV_MISSING_DATA_IND,
45
+
};
46
+
47
+
/*
48
+
* Operation type values (used to define the operation currently running)
49
+
* module is interrupt driven, on each interrupt the current operation is
50
+
* checked to see if the module is currently reading or writing.
51
+
*/
52
+
enum i2c_oper {
53
+
I2C_NO_OPER = 0,
54
+
I2C_WRITE_OPER,
55
+
I2C_READ_OPER,
56
+
};
57
+
58
+
/* I2C Bank (module had 2 banks of registers) */
59
+
enum i2c_bank {
60
+
I2C_BANK_0 = 0,
61
+
I2C_BANK_1,
62
+
};
63
+
64
+
/* Internal I2C states values (for the I2C module state machine). */
65
+
enum i2c_state {
66
+
I2C_DISABLE = 0,
67
+
I2C_IDLE,
68
+
I2C_MASTER_START,
69
+
I2C_SLAVE_MATCH,
70
+
I2C_OPER_STARTED,
71
+
I2C_STOP_PENDING,
72
+
};
73
+
74
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
75
+
/* Module supports setting multiple own slave addresses */
76
+
enum i2c_addr {
77
+
I2C_SLAVE_ADDR1 = 0,
78
+
I2C_SLAVE_ADDR2,
79
+
I2C_SLAVE_ADDR3,
80
+
I2C_SLAVE_ADDR4,
81
+
I2C_SLAVE_ADDR5,
82
+
I2C_SLAVE_ADDR6,
83
+
I2C_SLAVE_ADDR7,
84
+
I2C_SLAVE_ADDR8,
85
+
I2C_SLAVE_ADDR9,
86
+
I2C_SLAVE_ADDR10,
87
+
I2C_GC_ADDR,
88
+
I2C_ARP_ADDR,
89
+
};
90
+
#endif
91
+
92
+
/* init register and default value required to enable module */
93
+
#define NPCM_I2CSEGCTL 0xE4
94
+
#define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000
95
+
96
+
/* Common regs */
97
+
#define NPCM_I2CSDA 0x00
98
+
#define NPCM_I2CST 0x02
99
+
#define NPCM_I2CCST 0x04
100
+
#define NPCM_I2CCTL1 0x06
101
+
#define NPCM_I2CADDR1 0x08
102
+
#define NPCM_I2CCTL2 0x0A
103
+
#define NPCM_I2CADDR2 0x0C
104
+
#define NPCM_I2CCTL3 0x0E
105
+
#define NPCM_I2CCST2 0x18
106
+
#define NPCM_I2CCST3 0x19
107
+
#define I2C_VER 0x1F
108
+
109
+
/*BANK0 regs*/
110
+
#define NPCM_I2CADDR3 0x10
111
+
#define NPCM_I2CADDR7 0x11
112
+
#define NPCM_I2CADDR4 0x12
113
+
#define NPCM_I2CADDR8 0x13
114
+
#define NPCM_I2CADDR5 0x14
115
+
#define NPCM_I2CADDR9 0x15
116
+
#define NPCM_I2CADDR6 0x16
117
+
#define NPCM_I2CADDR10 0x17
118
+
119
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
120
+
/*
121
+
* npcm_i2caddr array:
122
+
* The module supports having multiple own slave addresses.
123
+
* Since the addr regs are sprinkled all over the address space,
124
+
* use this array to get the address or each register.
125
+
*/
126
+
#define I2C_NUM_OWN_ADDR 10
127
+
static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
128
+
NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4,
129
+
NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
130
+
NPCM_I2CADDR9, NPCM_I2CADDR10,
131
+
};
132
+
#endif
133
+
134
+
#define NPCM_I2CCTL4 0x1A
135
+
#define NPCM_I2CCTL5 0x1B
136
+
#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
137
+
#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
138
+
#define NPCM_I2CSCLHT 0x1E /* SCL High Time */
139
+
140
+
/* BANK 1 regs */
141
+
#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
142
+
#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
143
+
#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
144
+
#define NPCM_I2CPEC 0x16 /* PEC Data */
145
+
#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
146
+
#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
147
+
#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
148
+
149
+
/* NPCM_I2CST reg fields */
150
+
#define NPCM_I2CST_XMIT BIT(0)
151
+
#define NPCM_I2CST_MASTER BIT(1)
152
+
#define NPCM_I2CST_NMATCH BIT(2)
153
+
#define NPCM_I2CST_STASTR BIT(3)
154
+
#define NPCM_I2CST_NEGACK BIT(4)
155
+
#define NPCM_I2CST_BER BIT(5)
156
+
#define NPCM_I2CST_SDAST BIT(6)
157
+
#define NPCM_I2CST_SLVSTP BIT(7)
158
+
159
+
/* NPCM_I2CCST reg fields */
160
+
#define NPCM_I2CCST_BUSY BIT(0)
161
+
#define NPCM_I2CCST_BB BIT(1)
162
+
#define NPCM_I2CCST_MATCH BIT(2)
163
+
#define NPCM_I2CCST_GCMATCH BIT(3)
164
+
#define NPCM_I2CCST_TSDA BIT(4)
165
+
#define NPCM_I2CCST_TGSCL BIT(5)
166
+
#define NPCM_I2CCST_MATCHAF BIT(6)
167
+
#define NPCM_I2CCST_ARPMATCH BIT(7)
168
+
169
+
/* NPCM_I2CCTL1 reg fields */
170
+
#define NPCM_I2CCTL1_START BIT(0)
171
+
#define NPCM_I2CCTL1_STOP BIT(1)
172
+
#define NPCM_I2CCTL1_INTEN BIT(2)
173
+
#define NPCM_I2CCTL1_EOBINTE BIT(3)
174
+
#define NPCM_I2CCTL1_ACK BIT(4)
175
+
#define NPCM_I2CCTL1_GCMEN BIT(5)
176
+
#define NPCM_I2CCTL1_NMINTE BIT(6)
177
+
#define NPCM_I2CCTL1_STASTRE BIT(7)
178
+
179
+
/* RW1S fields (inside a RW reg): */
180
+
#define NPCM_I2CCTL1_RWS \
181
+
(NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
182
+
183
+
/* npcm_i2caddr reg fields */
184
+
#define NPCM_I2CADDR_A GENMASK(6, 0)
185
+
#define NPCM_I2CADDR_SAEN BIT(7)
186
+
187
+
/* NPCM_I2CCTL2 reg fields */
188
+
#define I2CCTL2_ENABLE BIT(0)
189
+
#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1)
190
+
191
+
/* NPCM_I2CCTL3 reg fields */
192
+
#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0)
193
+
#define I2CCTL3_ARPMEN BIT(2)
194
+
#define I2CCTL3_IDL_START BIT(3)
195
+
#define I2CCTL3_400K_MODE BIT(4)
196
+
#define I2CCTL3_BNK_SEL BIT(5)
197
+
#define I2CCTL3_SDA_LVL BIT(6)
198
+
#define I2CCTL3_SCL_LVL BIT(7)
199
+
200
+
/* NPCM_I2CCST2 reg fields */
201
+
#define NPCM_I2CCST2_MATCHA1F BIT(0)
202
+
#define NPCM_I2CCST2_MATCHA2F BIT(1)
203
+
#define NPCM_I2CCST2_MATCHA3F BIT(2)
204
+
#define NPCM_I2CCST2_MATCHA4F BIT(3)
205
+
#define NPCM_I2CCST2_MATCHA5F BIT(4)
206
+
#define NPCM_I2CCST2_MATCHA6F BIT(5)
207
+
#define NPCM_I2CCST2_MATCHA7F BIT(5)
208
+
#define NPCM_I2CCST2_INTSTS BIT(7)
209
+
210
+
/* NPCM_I2CCST3 reg fields */
211
+
#define NPCM_I2CCST3_MATCHA8F BIT(0)
212
+
#define NPCM_I2CCST3_MATCHA9F BIT(1)
213
+
#define NPCM_I2CCST3_MATCHA10F BIT(2)
214
+
#define NPCM_I2CCST3_EO_BUSY BIT(7)
215
+
216
+
/* NPCM_I2CCTL4 reg fields */
217
+
#define I2CCTL4_HLDT GENMASK(5, 0)
218
+
#define I2CCTL4_LVL_WE BIT(7)
219
+
220
+
/* NPCM_I2CCTL5 reg fields */
221
+
#define I2CCTL5_DBNCT GENMASK(3, 0)
222
+
223
+
/* NPCM_I2CFIF_CTS reg fields */
224
+
#define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
225
+
#define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
226
+
#define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
227
+
#define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
228
+
229
+
/* NPCM_I2CTXF_CTL reg fields */
230
+
#define NPCM_I2CTXF_CTL_TX_THR GENMASK(4, 0)
231
+
#define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
232
+
233
+
/* NPCM_I2CT_OUT reg fields */
234
+
#define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
235
+
#define NPCM_I2CT_OUT_T_OUTIE BIT(6)
236
+
#define NPCM_I2CT_OUT_T_OUTST BIT(7)
237
+
238
+
/* NPCM_I2CTXF_STS reg fields */
239
+
#define NPCM_I2CTXF_STS_TX_BYTES GENMASK(4, 0)
240
+
#define NPCM_I2CTXF_STS_TX_THST BIT(6)
241
+
242
+
/* NPCM_I2CRXF_STS reg fields */
243
+
#define NPCM_I2CRXF_STS_RX_BYTES GENMASK(4, 0)
244
+
#define NPCM_I2CRXF_STS_RX_THST BIT(6)
245
+
246
+
/* NPCM_I2CFIF_CTL reg fields */
247
+
#define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
248
+
249
+
/* NPCM_I2CRXF_CTL reg fields */
250
+
#define NPCM_I2CRXF_CTL_RX_THR GENMASK(4, 0)
251
+
#define NPCM_I2CRXF_CTL_LAST_PEC BIT(5)
252
+
#define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
253
+
254
+
#define I2C_HW_FIFO_SIZE 16
255
+
256
+
/* I2C_VER reg fields */
257
+
#define I2C_VER_VERSION GENMASK(6, 0)
258
+
#define I2C_VER_FIFO_EN BIT(7)
259
+
260
+
/* stall/stuck timeout in us */
261
+
#define DEFAULT_STALL_COUNT 25
262
+
263
+
/* SCLFRQ field position */
264
+
#define SCLFRQ_0_TO_6 GENMASK(6, 0)
265
+
#define SCLFRQ_7_TO_8 GENMASK(8, 7)
266
+
267
+
/* supported clk settings. values in Hz. */
268
+
#define I2C_FREQ_MIN_HZ 10000
269
+
#define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
270
+
271
+
/* Status of one I2C module */
272
+
struct npcm_i2c {
273
+
struct i2c_adapter adap;
274
+
struct device *dev;
275
+
unsigned char __iomem *reg;
276
+
spinlock_t lock; /* IRQ synchronization */
277
+
struct completion cmd_complete;
278
+
int cmd_err;
279
+
struct i2c_msg *msgs;
280
+
int msgs_num;
281
+
int num;
282
+
u32 apb_clk;
283
+
struct i2c_bus_recovery_info rinfo;
284
+
enum i2c_state state;
285
+
enum i2c_oper operation;
286
+
enum i2c_mode master_or_slave;
287
+
enum i2c_state_ind stop_ind;
288
+
u8 dest_addr;
289
+
u8 *rd_buf;
290
+
u16 rd_size;
291
+
u16 rd_ind;
292
+
u8 *wr_buf;
293
+
u16 wr_size;
294
+
u16 wr_ind;
295
+
bool fifo_use;
296
+
u16 PEC_mask; /* PEC bit mask per slave address */
297
+
bool PEC_use;
298
+
bool read_block_use;
299
+
unsigned long int_time_stamp;
300
+
unsigned long bus_freq; /* in Hz */
301
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
302
+
u8 own_slave_addr;
303
+
struct i2c_client *slave;
304
+
int slv_rd_size;
305
+
int slv_rd_ind;
306
+
int slv_wr_size;
307
+
int slv_wr_ind;
308
+
u8 slv_rd_buf[I2C_HW_FIFO_SIZE];
309
+
u8 slv_wr_buf[I2C_HW_FIFO_SIZE];
310
+
#endif
311
+
struct dentry *debugfs; /* debugfs device directory */
312
+
u64 ber_cnt;
313
+
u64 rec_succ_cnt;
314
+
u64 rec_fail_cnt;
315
+
u64 nack_cnt;
316
+
u64 timeout_cnt;
317
+
};
318
+
319
+
static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
320
+
enum i2c_bank bank)
321
+
{
322
+
u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
323
+
324
+
if (bank == I2C_BANK_0)
325
+
i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
326
+
else
327
+
i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
328
+
iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
329
+
}
330
+
331
+
static void npcm_i2c_init_params(struct npcm_i2c *bus)
332
+
{
333
+
bus->stop_ind = I2C_NO_STATUS_IND;
334
+
bus->rd_size = 0;
335
+
bus->wr_size = 0;
336
+
bus->rd_ind = 0;
337
+
bus->wr_ind = 0;
338
+
bus->read_block_use = false;
339
+
bus->int_time_stamp = 0;
340
+
bus->PEC_use = false;
341
+
bus->PEC_mask = 0;
342
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
343
+
if (bus->slave)
344
+
bus->master_or_slave = I2C_SLAVE;
345
+
#endif
346
+
}
347
+
348
+
static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
349
+
{
350
+
iowrite8(data, bus->reg + NPCM_I2CSDA);
351
+
}
352
+
353
+
static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
354
+
{
355
+
return ioread8(bus->reg + NPCM_I2CSDA);
356
+
}
357
+
358
+
static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
359
+
{
360
+
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
361
+
362
+
return !!(I2CCTL3_SCL_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
363
+
}
364
+
365
+
static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
366
+
{
367
+
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
368
+
369
+
return !!(I2CCTL3_SDA_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
370
+
}
371
+
372
+
static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
373
+
{
374
+
if (bus->operation == I2C_READ_OPER)
375
+
return bus->rd_ind;
376
+
if (bus->operation == I2C_WRITE_OPER)
377
+
return bus->wr_ind;
378
+
return 0;
379
+
}
380
+
381
+
/* quick protocol (just address) */
382
+
static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
383
+
{
384
+
return bus->wr_size == 0 && bus->rd_size == 0;
385
+
}
386
+
387
+
static void npcm_i2c_disable(struct npcm_i2c *bus)
388
+
{
389
+
u8 i2cctl2;
390
+
391
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
392
+
int i;
393
+
394
+
/* select bank 0 for I2C addresses */
395
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
396
+
397
+
/* Slave addresses removal */
398
+
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++)
399
+
iowrite8(0, bus->reg + npcm_i2caddr[i]);
400
+
401
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
402
+
#endif
403
+
/* Disable module */
404
+
i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
405
+
i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
406
+
iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
407
+
408
+
bus->state = I2C_DISABLE;
409
+
}
410
+
411
+
static void npcm_i2c_enable(struct npcm_i2c *bus)
412
+
{
413
+
u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
414
+
415
+
i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
416
+
iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
417
+
bus->state = I2C_IDLE;
418
+
}
419
+
420
+
/* enable\disable end of busy (EOB) interrupts */
421
+
static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
422
+
{
423
+
u8 val;
424
+
425
+
/* Clear EO_BUSY pending bit: */
426
+
val = ioread8(bus->reg + NPCM_I2CCST3);
427
+
val = val | NPCM_I2CCST3_EO_BUSY;
428
+
iowrite8(val, bus->reg + NPCM_I2CCST3);
429
+
430
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
431
+
val &= ~NPCM_I2CCTL1_RWS;
432
+
if (enable)
433
+
val |= NPCM_I2CCTL1_EOBINTE;
434
+
else
435
+
val &= ~NPCM_I2CCTL1_EOBINTE;
436
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
437
+
}
438
+
439
+
static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
440
+
{
441
+
u8 tx_fifo_sts;
442
+
443
+
tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
444
+
/* check if TX FIFO is not empty */
445
+
if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0)
446
+
return false;
447
+
448
+
/* check if TX FIFO status bit is set: */
449
+
return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
450
+
}
451
+
452
+
static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
453
+
{
454
+
u8 rx_fifo_sts;
455
+
456
+
rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
457
+
/* check if RX FIFO is not empty: */
458
+
if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0)
459
+
return false;
460
+
461
+
/* check if rx fifo full status is set: */
462
+
return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
463
+
}
464
+
465
+
static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
466
+
{
467
+
u8 val;
468
+
469
+
val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
470
+
val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
471
+
iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
472
+
}
473
+
474
+
static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
475
+
{
476
+
u8 val;
477
+
478
+
val = ioread8(bus->reg + NPCM_I2CTXF_STS);
479
+
val = val | NPCM_I2CTXF_STS_TX_THST;
480
+
iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
481
+
}
482
+
483
+
static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
484
+
{
485
+
u8 val;
486
+
487
+
val = ioread8(bus->reg + NPCM_I2CRXF_STS);
488
+
val = val | NPCM_I2CRXF_STS_RX_THST;
489
+
iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
490
+
}
491
+
492
+
static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
493
+
{
494
+
u8 val;
495
+
496
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
497
+
val &= ~NPCM_I2CCTL1_RWS;
498
+
if (enable)
499
+
val |= NPCM_I2CCTL1_INTEN;
500
+
else
501
+
val &= ~NPCM_I2CCTL1_INTEN;
502
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
503
+
}
504
+
505
+
static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
506
+
{
507
+
u8 val;
508
+
509
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
510
+
val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
511
+
val |= NPCM_I2CCTL1_START;
512
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
513
+
}
514
+
515
+
static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
516
+
{
517
+
u8 val;
518
+
519
+
/*
520
+
* override HW issue: I2C may fail to supply stop condition in Master
521
+
* Write operation.
522
+
* Need to delay at least 5 us from the last int, before issueing a stop
523
+
*/
524
+
udelay(10); /* function called from interrupt, can't sleep */
525
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
526
+
val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
527
+
val |= NPCM_I2CCTL1_STOP;
528
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
529
+
530
+
if (!bus->fifo_use)
531
+
return;
532
+
533
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
534
+
535
+
if (bus->operation == I2C_READ_OPER)
536
+
npcm_i2c_clear_rx_fifo(bus);
537
+
else
538
+
npcm_i2c_clear_tx_fifo(bus);
539
+
npcm_i2c_clear_fifo_int(bus);
540
+
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
541
+
}
542
+
543
+
static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
544
+
{
545
+
u8 val;
546
+
547
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
548
+
val &= ~NPCM_I2CCTL1_RWS;
549
+
if (stall)
550
+
val |= NPCM_I2CCTL1_STASTRE;
551
+
else
552
+
val &= ~NPCM_I2CCTL1_STASTRE;
553
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
554
+
}
555
+
556
+
static inline void npcm_i2c_nack(struct npcm_i2c *bus)
557
+
{
558
+
u8 val;
559
+
560
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
561
+
val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
562
+
val |= NPCM_I2CCTL1_ACK;
563
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
564
+
}
565
+
566
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
567
+
static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
568
+
{
569
+
u8 i2cctl1;
570
+
571
+
/* enable interrupt on slave match: */
572
+
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
573
+
i2cctl1 &= ~NPCM_I2CCTL1_RWS;
574
+
if (enable)
575
+
i2cctl1 |= NPCM_I2CCTL1_NMINTE;
576
+
else
577
+
i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
578
+
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
579
+
}
580
+
581
+
static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
582
+
u8 addr, bool enable)
583
+
{
584
+
u8 i2cctl1;
585
+
u8 i2cctl3;
586
+
u8 sa_reg;
587
+
588
+
sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
589
+
if (addr_type == I2C_GC_ADDR) {
590
+
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
591
+
if (enable)
592
+
i2cctl1 |= NPCM_I2CCTL1_GCMEN;
593
+
else
594
+
i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
595
+
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
596
+
return 0;
597
+
}
598
+
if (addr_type == I2C_ARP_ADDR) {
599
+
i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
600
+
if (enable)
601
+
i2cctl3 |= I2CCTL3_ARPMEN;
602
+
else
603
+
i2cctl3 &= ~I2CCTL3_ARPMEN;
604
+
iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
605
+
return 0;
606
+
}
607
+
if (addr_type >= I2C_ARP_ADDR)
608
+
return -EFAULT;
609
+
/* select bank 0 for address 3 to 10 */
610
+
if (addr_type > I2C_SLAVE_ADDR2)
611
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
612
+
/* Set and enable the address */
613
+
iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
614
+
npcm_i2c_slave_int_enable(bus, enable);
615
+
if (addr_type > I2C_SLAVE_ADDR2)
616
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
617
+
return 0;
618
+
}
619
+
#endif
620
+
621
+
static void npcm_i2c_reset(struct npcm_i2c *bus)
622
+
{
623
+
/*
624
+
* Save I2CCTL1 relevant bits. It is being cleared when the module
625
+
* is disabled.
626
+
*/
627
+
u8 i2cctl1;
628
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
629
+
u8 addr;
630
+
#endif
631
+
632
+
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
633
+
634
+
npcm_i2c_disable(bus);
635
+
npcm_i2c_enable(bus);
636
+
637
+
/* Restore NPCM_I2CCTL1 Status */
638
+
i2cctl1 &= ~NPCM_I2CCTL1_RWS;
639
+
iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
640
+
641
+
/* Clear BB (BUS BUSY) bit */
642
+
iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
643
+
iowrite8(0xFF, bus->reg + NPCM_I2CST);
644
+
645
+
/* Clear EOB bit */
646
+
iowrite8(NPCM_I2CCST3_EO_BUSY, bus->reg + NPCM_I2CCST3);
647
+
648
+
/* Clear all fifo bits: */
649
+
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
650
+
651
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
652
+
if (bus->slave) {
653
+
addr = bus->slave->addr;
654
+
npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
655
+
}
656
+
#endif
657
+
658
+
bus->state = I2C_IDLE;
659
+
}
660
+
661
+
static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
662
+
{
663
+
return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
664
+
}
665
+
666
+
static void npcm_i2c_callback(struct npcm_i2c *bus,
667
+
enum i2c_state_ind op_status, u16 info)
668
+
{
669
+
struct i2c_msg *msgs;
670
+
int msgs_num;
671
+
672
+
msgs = bus->msgs;
673
+
msgs_num = bus->msgs_num;
674
+
/*
675
+
* check that transaction was not timed-out, and msgs still
676
+
* holds a valid value.
677
+
*/
678
+
if (!msgs)
679
+
return;
680
+
681
+
if (completion_done(&bus->cmd_complete))
682
+
return;
683
+
684
+
switch (op_status) {
685
+
case I2C_MASTER_DONE_IND:
686
+
bus->cmd_err = bus->msgs_num;
687
+
fallthrough;
688
+
case I2C_BLOCK_BYTES_ERR_IND:
689
+
/* Master tx finished and all transmit bytes were sent */
690
+
if (bus->msgs) {
691
+
if (msgs[0].flags & I2C_M_RD)
692
+
msgs[0].len = info;
693
+
else if (msgs_num == 2 &&
694
+
msgs[1].flags & I2C_M_RD)
695
+
msgs[1].len = info;
696
+
}
697
+
if (completion_done(&bus->cmd_complete) == false)
698
+
complete(&bus->cmd_complete);
699
+
break;
700
+
701
+
case I2C_NACK_IND:
702
+
/* MASTER transmit got a NACK before tx all bytes */
703
+
bus->cmd_err = -ENXIO;
704
+
if (bus->master_or_slave == I2C_MASTER)
705
+
complete(&bus->cmd_complete);
706
+
707
+
break;
708
+
case I2C_BUS_ERR_IND:
709
+
/* Bus error */
710
+
bus->cmd_err = -EAGAIN;
711
+
if (bus->master_or_slave == I2C_MASTER)
712
+
complete(&bus->cmd_complete);
713
+
714
+
break;
715
+
case I2C_WAKE_UP_IND:
716
+
/* I2C wake up */
717
+
break;
718
+
default:
719
+
break;
720
+
}
721
+
722
+
bus->operation = I2C_NO_OPER;
723
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
724
+
if (bus->slave)
725
+
bus->master_or_slave = I2C_SLAVE;
726
+
#endif
727
+
}
728
+
729
+
static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
730
+
{
731
+
if (bus->operation == I2C_WRITE_OPER)
732
+
return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
733
+
ioread8(bus->reg + NPCM_I2CTXF_STS));
734
+
if (bus->operation == I2C_READ_OPER)
735
+
return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES,
736
+
ioread8(bus->reg + NPCM_I2CRXF_STS));
737
+
return 0;
738
+
}
739
+
740
+
static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
741
+
{
742
+
u8 size_free_fifo;
743
+
744
+
/*
745
+
* Fill the FIFO, while the FIFO is not full and there are more bytes
746
+
* to write
747
+
*/
748
+
size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
749
+
while (max_bytes-- && size_free_fifo) {
750
+
if (bus->wr_ind < bus->wr_size)
751
+
npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
752
+
else
753
+
npcm_i2c_wr_byte(bus, 0xFF);
754
+
size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
755
+
}
756
+
}
757
+
758
+
/*
759
+
* npcm_i2c_set_fifo:
760
+
* configure the FIFO before using it. If nread is -1 RX FIFO will not be
761
+
* configured. same for nwrite
762
+
*/
763
+
static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
764
+
{
765
+
u8 rxf_ctl = 0;
766
+
767
+
if (!bus->fifo_use)
768
+
return;
769
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
770
+
npcm_i2c_clear_tx_fifo(bus);
771
+
npcm_i2c_clear_rx_fifo(bus);
772
+
773
+
/* configure RX FIFO */
774
+
if (nread > 0) {
775
+
rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE);
776
+
777
+
/* set LAST bit. if LAST is set next FIFO packet is nacked */
778
+
if (nread <= I2C_HW_FIFO_SIZE)
779
+
rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC;
780
+
781
+
/*
782
+
* if we are about to read the first byte in blk rd mode,
783
+
* don't NACK it. If slave returns zero size HW can't NACK
784
+
* it immidiattly, it will read extra byte and then NACK.
785
+
*/
786
+
if (bus->rd_ind == 0 && bus->read_block_use) {
787
+
/* set fifo to read one byte, no last: */
788
+
rxf_ctl = 1;
789
+
}
790
+
791
+
/* set fifo size: */
792
+
iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
793
+
}
794
+
795
+
/* configure TX FIFO */
796
+
if (nwrite > 0) {
797
+
if (nwrite > I2C_HW_FIFO_SIZE)
798
+
/* data to send is more then FIFO size. */
799
+
iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
800
+
else
801
+
iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
802
+
803
+
npcm_i2c_clear_tx_fifo(bus);
804
+
}
805
+
}
806
+
807
+
static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
808
+
{
809
+
u8 data;
810
+
811
+
while (bytes_in_fifo--) {
812
+
data = npcm_i2c_rd_byte(bus);
813
+
if (bus->rd_ind < bus->rd_size)
814
+
bus->rd_buf[bus->rd_ind++] = data;
815
+
}
816
+
}
817
+
818
+
static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
819
+
{
820
+
u8 val;
821
+
822
+
/* Clear NEGACK, STASTR and BER bits */
823
+
val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
824
+
iowrite8(val, bus->reg + NPCM_I2CST);
825
+
}
826
+
827
+
static void npcm_i2c_master_abort(struct npcm_i2c *bus)
828
+
{
829
+
/* Only current master is allowed to issue a stop condition */
830
+
if (!npcm_i2c_is_master(bus))
831
+
return;
832
+
833
+
npcm_i2c_eob_int(bus, true);
834
+
npcm_i2c_master_stop(bus);
835
+
npcm_i2c_clear_master_status(bus);
836
+
}
837
+
838
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
839
+
static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
840
+
{
841
+
u8 slave_add;
842
+
843
+
/* select bank 0 for address 3 to 10 */
844
+
if (addr_type > I2C_SLAVE_ADDR2)
845
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
846
+
847
+
slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
848
+
849
+
if (addr_type > I2C_SLAVE_ADDR2)
850
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
851
+
852
+
return slave_add;
853
+
}
854
+
855
+
static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
856
+
{
857
+
int i;
858
+
859
+
/* Set the enable bit */
860
+
slave_add |= 0x80;
861
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
862
+
for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) {
863
+
if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
864
+
iowrite8(0, bus->reg + npcm_i2caddr[i]);
865
+
}
866
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
867
+
return 0;
868
+
}
869
+
870
+
static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
871
+
{
872
+
/*
873
+
* Fill the FIFO, while the FIFO is not full and there are more bytes
874
+
* to write
875
+
*/
876
+
npcm_i2c_clear_fifo_int(bus);
877
+
npcm_i2c_clear_tx_fifo(bus);
878
+
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
879
+
while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
880
+
if (bus->slv_wr_size <= 0)
881
+
break;
882
+
bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
883
+
npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
884
+
bus->slv_wr_ind++;
885
+
bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
886
+
bus->slv_wr_size--;
887
+
}
888
+
}
889
+
890
+
static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
891
+
{
892
+
u8 data;
893
+
894
+
if (!bus->slave)
895
+
return;
896
+
897
+
while (bytes_in_fifo--) {
898
+
data = npcm_i2c_rd_byte(bus);
899
+
900
+
bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
901
+
bus->slv_rd_buf[bus->slv_rd_ind] = data;
902
+
bus->slv_rd_ind++;
903
+
904
+
/* 1st byte is length in block protocol: */
905
+
if (bus->slv_rd_ind == 1 && bus->read_block_use)
906
+
bus->slv_rd_size = data + bus->PEC_use + 1;
907
+
}
908
+
}
909
+
910
+
static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
911
+
{
912
+
int i;
913
+
u8 value;
914
+
int ind;
915
+
int ret = bus->slv_wr_ind;
916
+
917
+
/* fill a cyclic buffer */
918
+
for (i = 0; i < I2C_HW_FIFO_SIZE; i++) {
919
+
if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
920
+
break;
921
+
i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
922
+
ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
923
+
bus->slv_wr_buf[ind] = value;
924
+
bus->slv_wr_size++;
925
+
i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
926
+
}
927
+
return I2C_HW_FIFO_SIZE - ret;
928
+
}
929
+
930
+
static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
931
+
{
932
+
int i;
933
+
934
+
for (i = 0; i < bus->slv_rd_ind; i++)
935
+
i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
936
+
&bus->slv_rd_buf[i]);
937
+
/*
938
+
* once we send bytes up, need to reset the counter of the wr buf
939
+
* got data from master (new offset in device), ignore wr fifo:
940
+
*/
941
+
if (bus->slv_rd_ind) {
942
+
bus->slv_wr_size = 0;
943
+
bus->slv_wr_ind = 0;
944
+
}
945
+
946
+
bus->slv_rd_ind = 0;
947
+
bus->slv_rd_size = bus->adap.quirks->max_read_len;
948
+
949
+
npcm_i2c_clear_fifo_int(bus);
950
+
npcm_i2c_clear_rx_fifo(bus);
951
+
}
952
+
953
+
static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
954
+
u8 *read_data)
955
+
{
956
+
bus->state = I2C_OPER_STARTED;
957
+
bus->operation = I2C_READ_OPER;
958
+
bus->slv_rd_size = nread;
959
+
bus->slv_rd_ind = 0;
960
+
961
+
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
962
+
iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
963
+
npcm_i2c_clear_tx_fifo(bus);
964
+
npcm_i2c_clear_rx_fifo(bus);
965
+
}
966
+
967
+
static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
968
+
u8 *write_data)
969
+
{
970
+
if (nwrite == 0)
971
+
return;
972
+
973
+
bus->state = I2C_OPER_STARTED;
974
+
bus->operation = I2C_WRITE_OPER;
975
+
976
+
/* get the next buffer */
977
+
npcm_i2c_slave_get_wr_buf(bus);
978
+
npcm_i2c_write_fifo_slave(bus, nwrite);
979
+
}
980
+
981
+
/*
982
+
* npcm_i2c_slave_wr_buf_sync:
983
+
* currently slave IF only supports single byte operations.
984
+
* in order to utilyze the npcm HW FIFO, the driver will ask for 16 bytes
985
+
* at a time, pack them in buffer, and then transmit them all together
986
+
* to the FIFO and onward to the bus.
987
+
* NACK on read will be once reached to bus->adap->quirks->max_read_len.
988
+
* sending a NACK wherever the backend requests for it is not supported.
989
+
* the next two functions allow reading to local buffer before writing it all
990
+
* to the HW FIFO.
991
+
*/
992
+
static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
993
+
{
994
+
int left_in_fifo;
995
+
996
+
left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
997
+
ioread8(bus->reg + NPCM_I2CTXF_STS));
998
+
999
+
/* fifo already full: */
1000
+
if (left_in_fifo >= I2C_HW_FIFO_SIZE ||
1001
+
bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
1002
+
return;
1003
+
1004
+
/* update the wr fifo index back to the untransmitted bytes: */
1005
+
bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1006
+
bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1007
+
1008
+
if (bus->slv_wr_ind < 0)
1009
+
bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
1010
+
}
1011
+
1012
+
static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1013
+
{
1014
+
if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1015
+
/*
1016
+
* Slave got an address match with direction bit 1 so it should
1017
+
* transmit data. Write till the master will NACK
1018
+
*/
1019
+
bus->operation = I2C_WRITE_OPER;
1020
+
npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1021
+
bus->slv_wr_buf);
1022
+
} else {
1023
+
/*
1024
+
* Slave got an address match with direction bit 0 so it should
1025
+
* receive data.
1026
+
* this module does not support saying no to bytes.
1027
+
* it will always ACK.
1028
+
*/
1029
+
bus->operation = I2C_READ_OPER;
1030
+
npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1031
+
bus->stop_ind = I2C_SLAVE_RCV_IND;
1032
+
npcm_i2c_slave_send_rd_buf(bus);
1033
+
npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1034
+
bus->slv_rd_buf);
1035
+
}
1036
+
}
1037
+
1038
+
static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1039
+
{
1040
+
u8 val;
1041
+
irqreturn_t ret = IRQ_NONE;
1042
+
u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1043
+
1044
+
/* Slave: A NACK has occurred */
1045
+
if (NPCM_I2CST_NEGACK & i2cst) {
1046
+
bus->stop_ind = I2C_NACK_IND;
1047
+
npcm_i2c_slave_wr_buf_sync(bus);
1048
+
if (bus->fifo_use)
1049
+
/* clear the FIFO */
1050
+
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1051
+
bus->reg + NPCM_I2CFIF_CTS);
1052
+
1053
+
/* In slave write, NACK is OK, otherwise it is a problem */
1054
+
bus->stop_ind = I2C_NO_STATUS_IND;
1055
+
bus->operation = I2C_NO_OPER;
1056
+
bus->own_slave_addr = 0xFF;
1057
+
1058
+
/*
1059
+
* Slave has to wait for STOP to decide this is the end
1060
+
* of the transaction. tx is not yet considered as done
1061
+
*/
1062
+
iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1063
+
1064
+
ret = IRQ_HANDLED;
1065
+
}
1066
+
1067
+
/* Slave mode: a Bus Error (BER) has been identified */
1068
+
if (NPCM_I2CST_BER & i2cst) {
1069
+
/*
1070
+
* Check whether bus arbitration or Start or Stop during data
1071
+
* xfer bus arbitration problem should not result in recovery
1072
+
*/
1073
+
bus->stop_ind = I2C_BUS_ERR_IND;
1074
+
1075
+
/* wait for bus busy before clear fifo */
1076
+
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1077
+
1078
+
bus->state = I2C_IDLE;
1079
+
1080
+
/*
1081
+
* in BER case we might get 2 interrupts: one for slave one for
1082
+
* master ( for a channel which is master\slave switching)
1083
+
*/
1084
+
if (completion_done(&bus->cmd_complete) == false) {
1085
+
bus->cmd_err = -EIO;
1086
+
complete(&bus->cmd_complete);
1087
+
}
1088
+
bus->own_slave_addr = 0xFF;
1089
+
iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1090
+
ret = IRQ_HANDLED;
1091
+
}
1092
+
1093
+
/* A Slave Stop Condition has been identified */
1094
+
if (NPCM_I2CST_SLVSTP & i2cst) {
1095
+
u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1096
+
1097
+
bus->stop_ind = I2C_SLAVE_DONE_IND;
1098
+
1099
+
if (bus->operation == I2C_READ_OPER)
1100
+
npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1101
+
1102
+
/* if the buffer is empty nothing will be sent */
1103
+
npcm_i2c_slave_send_rd_buf(bus);
1104
+
1105
+
/* Slave done transmitting or receiving */
1106
+
bus->stop_ind = I2C_NO_STATUS_IND;
1107
+
1108
+
/*
1109
+
* Note, just because we got here, it doesn't mean we through
1110
+
* away the wr buffer.
1111
+
* we keep it until the next received offset.
1112
+
*/
1113
+
bus->operation = I2C_NO_OPER;
1114
+
bus->own_slave_addr = 0xFF;
1115
+
i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1116
+
iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1117
+
if (bus->fifo_use) {
1118
+
npcm_i2c_clear_fifo_int(bus);
1119
+
npcm_i2c_clear_rx_fifo(bus);
1120
+
npcm_i2c_clear_tx_fifo(bus);
1121
+
1122
+
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1123
+
bus->reg + NPCM_I2CFIF_CTS);
1124
+
}
1125
+
bus->state = I2C_IDLE;
1126
+
ret = IRQ_HANDLED;
1127
+
}
1128
+
1129
+
/* restart condition occurred and Rx-FIFO was not empty */
1130
+
if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1131
+
ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1132
+
bus->stop_ind = I2C_SLAVE_RESTART_IND;
1133
+
bus->master_or_slave = I2C_SLAVE;
1134
+
if (bus->operation == I2C_READ_OPER)
1135
+
npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1136
+
bus->operation = I2C_WRITE_OPER;
1137
+
iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1138
+
val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1139
+
NPCM_I2CFIF_CTS_RXF_TXE;
1140
+
iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1141
+
npcm_i2c_slave_rd_wr(bus);
1142
+
ret = IRQ_HANDLED;
1143
+
}
1144
+
1145
+
/* A Slave Address Match has been identified */
1146
+
if (NPCM_I2CST_NMATCH & i2cst) {
1147
+
u8 info = 0;
1148
+
1149
+
/* Address match automatically implies slave mode */
1150
+
bus->master_or_slave = I2C_SLAVE;
1151
+
npcm_i2c_clear_fifo_int(bus);
1152
+
npcm_i2c_clear_rx_fifo(bus);
1153
+
npcm_i2c_clear_tx_fifo(bus);
1154
+
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1155
+
iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
1156
+
if (NPCM_I2CST_XMIT & i2cst) {
1157
+
bus->operation = I2C_WRITE_OPER;
1158
+
} else {
1159
+
i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1160
+
&info);
1161
+
bus->operation = I2C_READ_OPER;
1162
+
}
1163
+
if (bus->own_slave_addr == 0xFF) {
1164
+
/* Check which type of address match */
1165
+
val = ioread8(bus->reg + NPCM_I2CCST);
1166
+
if (NPCM_I2CCST_MATCH & val) {
1167
+
u16 addr;
1168
+
enum i2c_addr eaddr;
1169
+
u8 i2ccst2;
1170
+
u8 i2ccst3;
1171
+
1172
+
i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1173
+
i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1174
+
1175
+
/*
1176
+
* the i2c module can response to 10 own SA.
1177
+
* check which one was addressed by the master.
1178
+
* repond to the first one.
1179
+
*/
1180
+
addr = ((i2ccst3 & 0x07) << 7) |
1181
+
(i2ccst2 & 0x7F);
1182
+
info = ffs(addr);
1183
+
eaddr = (enum i2c_addr)info;
1184
+
addr = npcm_i2c_get_slave_addr(bus, eaddr);
1185
+
addr &= 0x7F;
1186
+
bus->own_slave_addr = addr;
1187
+
if (bus->PEC_mask & BIT(info))
1188
+
bus->PEC_use = true;
1189
+
else
1190
+
bus->PEC_use = false;
1191
+
} else {
1192
+
if (NPCM_I2CCST_GCMATCH & val)
1193
+
bus->own_slave_addr = 0;
1194
+
if (NPCM_I2CCST_ARPMATCH & val)
1195
+
bus->own_slave_addr = 0x61;
1196
+
}
1197
+
} else {
1198
+
/*
1199
+
* Slave match can happen in two options:
1200
+
* 1. Start, SA, read (slave read without further ado)
1201
+
* 2. Start, SA, read, data, restart, SA, read, ...
1202
+
* (slave read in fragmented mode)
1203
+
* 3. Start, SA, write, data, restart, SA, read, ..
1204
+
* (regular write-read mode)
1205
+
*/
1206
+
if ((bus->state == I2C_OPER_STARTED &&
1207
+
bus->operation == I2C_READ_OPER &&
1208
+
bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1209
+
bus->stop_ind == I2C_SLAVE_RCV_IND) {
1210
+
/* slave tx after slave rx w/o STOP */
1211
+
bus->stop_ind = I2C_SLAVE_RESTART_IND;
1212
+
}
1213
+
}
1214
+
1215
+
if (NPCM_I2CST_XMIT & i2cst)
1216
+
bus->stop_ind = I2C_SLAVE_XMIT_IND;
1217
+
else
1218
+
bus->stop_ind = I2C_SLAVE_RCV_IND;
1219
+
bus->state = I2C_SLAVE_MATCH;
1220
+
npcm_i2c_slave_rd_wr(bus);
1221
+
iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1222
+
ret = IRQ_HANDLED;
1223
+
}
1224
+
1225
+
/* Slave SDA status is set - tx or rx */
1226
+
if ((NPCM_I2CST_SDAST & i2cst) ||
1227
+
(bus->fifo_use &&
1228
+
(npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1229
+
npcm_i2c_slave_rd_wr(bus);
1230
+
iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1231
+
ret = IRQ_HANDLED;
1232
+
} /* SDAST */
1233
+
1234
+
return ret;
1235
+
}
1236
+
1237
+
static int npcm_i2c_reg_slave(struct i2c_client *client)
1238
+
{
1239
+
unsigned long lock_flags;
1240
+
struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1241
+
1242
+
bus->slave = client;
1243
+
1244
+
if (!bus->slave)
1245
+
return -EINVAL;
1246
+
1247
+
if (client->flags & I2C_CLIENT_TEN)
1248
+
return -EAFNOSUPPORT;
1249
+
1250
+
spin_lock_irqsave(&bus->lock, lock_flags);
1251
+
1252
+
npcm_i2c_init_params(bus);
1253
+
bus->slv_rd_size = 0;
1254
+
bus->slv_wr_size = 0;
1255
+
bus->slv_rd_ind = 0;
1256
+
bus->slv_wr_ind = 0;
1257
+
if (client->flags & I2C_CLIENT_PEC)
1258
+
bus->PEC_use = true;
1259
+
1260
+
dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1261
+
client->addr, bus->PEC_use);
1262
+
1263
+
npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1264
+
npcm_i2c_clear_fifo_int(bus);
1265
+
npcm_i2c_clear_rx_fifo(bus);
1266
+
npcm_i2c_clear_tx_fifo(bus);
1267
+
npcm_i2c_slave_int_enable(bus, true);
1268
+
1269
+
spin_unlock_irqrestore(&bus->lock, lock_flags);
1270
+
return 0;
1271
+
}
1272
+
1273
+
static int npcm_i2c_unreg_slave(struct i2c_client *client)
1274
+
{
1275
+
struct npcm_i2c *bus = client->adapter->algo_data;
1276
+
unsigned long lock_flags;
1277
+
1278
+
spin_lock_irqsave(&bus->lock, lock_flags);
1279
+
if (!bus->slave) {
1280
+
spin_unlock_irqrestore(&bus->lock, lock_flags);
1281
+
return -EINVAL;
1282
+
}
1283
+
npcm_i2c_slave_int_enable(bus, false);
1284
+
npcm_i2c_remove_slave_addr(bus, client->addr);
1285
+
bus->slave = NULL;
1286
+
spin_unlock_irqrestore(&bus->lock, lock_flags);
1287
+
return 0;
1288
+
}
1289
+
#endif /* CONFIG_I2C_SLAVE */
1290
+
1291
+
static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1292
+
{
1293
+
int rcount;
1294
+
int fifo_bytes;
1295
+
enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1296
+
1297
+
fifo_bytes = npcm_i2c_fifo_usage(bus);
1298
+
rcount = bus->rd_size - bus->rd_ind;
1299
+
1300
+
/*
1301
+
* In order not to change the RX_TRH during transaction (we found that
1302
+
* this might be problematic if it takes too much time to read the FIFO)
1303
+
* we read the data in the following way. If the number of bytes to
1304
+
* read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1305
+
* and in the next int we read rest of the data.
1306
+
*/
1307
+
if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE)
1308
+
fifo_bytes = rcount - I2C_HW_FIFO_SIZE;
1309
+
1310
+
if (rcount <= fifo_bytes) {
1311
+
/* last bytes are about to be read - end of tx */
1312
+
bus->state = I2C_STOP_PENDING;
1313
+
bus->stop_ind = ind;
1314
+
npcm_i2c_eob_int(bus, true);
1315
+
/* Stop should be set before reading last byte. */
1316
+
npcm_i2c_master_stop(bus);
1317
+
npcm_i2c_read_fifo(bus, fifo_bytes);
1318
+
} else {
1319
+
npcm_i2c_read_fifo(bus, fifo_bytes);
1320
+
rcount = bus->rd_size - bus->rd_ind;
1321
+
npcm_i2c_set_fifo(bus, rcount, -1);
1322
+
}
1323
+
}
1324
+
1325
+
static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1326
+
{
1327
+
u16 wcount;
1328
+
1329
+
if (bus->fifo_use)
1330
+
npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1331
+
1332
+
/* Master write operation - last byte handling */
1333
+
if (bus->wr_ind == bus->wr_size) {
1334
+
if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1335
+
/*
1336
+
* No more bytes to send (to add to the FIFO),
1337
+
* however the FIFO is not empty yet. It is
1338
+
* still in the middle of tx. Currently there's nothing
1339
+
* to do except for waiting to the end of the tx
1340
+
* We will get an int when the FIFO will get empty.
1341
+
*/
1342
+
return;
1343
+
1344
+
if (bus->rd_size == 0) {
1345
+
/* all bytes have been written, in wr only operation */
1346
+
npcm_i2c_eob_int(bus, true);
1347
+
bus->state = I2C_STOP_PENDING;
1348
+
bus->stop_ind = I2C_MASTER_DONE_IND;
1349
+
npcm_i2c_master_stop(bus);
1350
+
/* Clear SDA Status bit (by writing dummy byte) */
1351
+
npcm_i2c_wr_byte(bus, 0xFF);
1352
+
1353
+
} else {
1354
+
/* last write-byte written on previous int - restart */
1355
+
npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1356
+
/* Generate repeated start upon next write to SDA */
1357
+
npcm_i2c_master_start(bus);
1358
+
1359
+
/*
1360
+
* Receiving one byte only - stall after successful
1361
+
* completion of send address byte. If we NACK here, and
1362
+
* slave doesn't ACK the address, we might
1363
+
* unintentionally NACK the next multi-byte read.
1364
+
*/
1365
+
if (bus->rd_size == 1)
1366
+
npcm_i2c_stall_after_start(bus, true);
1367
+
1368
+
/* Next int will occur on read */
1369
+
bus->operation = I2C_READ_OPER;
1370
+
/* send the slave address in read direction */
1371
+
npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1372
+
}
1373
+
} else {
1374
+
/* write next byte not last byte and not slave address */
1375
+
if (!bus->fifo_use || bus->wr_size == 1) {
1376
+
npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1377
+
} else {
1378
+
wcount = bus->wr_size - bus->wr_ind;
1379
+
npcm_i2c_set_fifo(bus, -1, wcount);
1380
+
if (wcount)
1381
+
npcm_i2c_write_to_fifo_master(bus, wcount);
1382
+
}
1383
+
}
1384
+
}
1385
+
1386
+
static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1387
+
{
1388
+
u16 block_extra_bytes_size;
1389
+
u8 data;
1390
+
1391
+
/* added bytes to the packet: */
1392
+
block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1393
+
1394
+
/*
1395
+
* Perform master read, distinguishing between last byte and the rest of
1396
+
* the bytes. The last byte should be read when the clock is stopped
1397
+
*/
1398
+
if (bus->rd_ind == 0) { /* first byte handling: */
1399
+
if (bus->read_block_use) {
1400
+
/* first byte in block protocol is the size: */
1401
+
data = npcm_i2c_rd_byte(bus);
1402
+
data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1403
+
bus->rd_size = data + block_extra_bytes_size;
1404
+
bus->rd_buf[bus->rd_ind++] = data;
1405
+
1406
+
/* clear RX FIFO interrupt status: */
1407
+
if (bus->fifo_use) {
1408
+
data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1409
+
data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1410
+
iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1411
+
}
1412
+
1413
+
npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1414
+
npcm_i2c_stall_after_start(bus, false);
1415
+
} else {
1416
+
npcm_i2c_clear_tx_fifo(bus);
1417
+
npcm_i2c_master_fifo_read(bus);
1418
+
}
1419
+
} else {
1420
+
if (bus->rd_size == block_extra_bytes_size &&
1421
+
bus->read_block_use) {
1422
+
bus->state = I2C_STOP_PENDING;
1423
+
bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1424
+
bus->cmd_err = -EIO;
1425
+
npcm_i2c_eob_int(bus, true);
1426
+
npcm_i2c_master_stop(bus);
1427
+
npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1428
+
} else {
1429
+
npcm_i2c_master_fifo_read(bus);
1430
+
}
1431
+
}
1432
+
}
1433
+
1434
+
static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1435
+
{
1436
+
iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1437
+
npcm_i2c_nack(bus);
1438
+
bus->stop_ind = I2C_BUS_ERR_IND;
1439
+
npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1440
+
}
1441
+
1442
+
/* A NACK has occurred */
1443
+
static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1444
+
{
1445
+
u8 val;
1446
+
1447
+
if (bus->nack_cnt < ULLONG_MAX)
1448
+
bus->nack_cnt++;
1449
+
1450
+
if (bus->fifo_use) {
1451
+
/*
1452
+
* if there are still untransmitted bytes in TX FIFO
1453
+
* reduce them from wr_ind
1454
+
*/
1455
+
if (bus->operation == I2C_WRITE_OPER)
1456
+
bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1457
+
1458
+
/* clear the FIFO */
1459
+
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1460
+
}
1461
+
1462
+
/* In master write operation, got unexpected NACK */
1463
+
bus->stop_ind = I2C_NACK_IND;
1464
+
/* Only current master is allowed to issue Stop Condition */
1465
+
if (npcm_i2c_is_master(bus)) {
1466
+
/* stopping in the middle */
1467
+
npcm_i2c_eob_int(bus, false);
1468
+
npcm_i2c_master_stop(bus);
1469
+
1470
+
/*
1471
+
* The bus is released from stall only after the SW clears
1472
+
* NEGACK bit. Then a Stop condition is sent.
1473
+
*/
1474
+
npcm_i2c_clear_master_status(bus);
1475
+
readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1476
+
!(val & NPCM_I2CCST_BUSY), 10, 200);
1477
+
}
1478
+
bus->state = I2C_IDLE;
1479
+
1480
+
/*
1481
+
* In Master mode, NACK should be cleared only after STOP.
1482
+
* In such case, the bus is released from stall only after the
1483
+
* software clears NACK bit. Then a Stop condition is sent.
1484
+
*/
1485
+
npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1486
+
}
1487
+
1488
+
/* Master mode: a Bus Error has been identified */
1489
+
static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1490
+
{
1491
+
if (bus->ber_cnt < ULLONG_MAX)
1492
+
bus->ber_cnt++;
1493
+
bus->stop_ind = I2C_BUS_ERR_IND;
1494
+
if (npcm_i2c_is_master(bus)) {
1495
+
npcm_i2c_master_abort(bus);
1496
+
} else {
1497
+
npcm_i2c_clear_master_status(bus);
1498
+
1499
+
/* Clear BB (BUS BUSY) bit */
1500
+
iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1501
+
1502
+
bus->cmd_err = -EAGAIN;
1503
+
npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1504
+
}
1505
+
bus->state = I2C_IDLE;
1506
+
}
1507
+
1508
+
/* EOB: a master End Of Busy (meaning STOP completed) */
1509
+
static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1510
+
{
1511
+
npcm_i2c_eob_int(bus, false);
1512
+
bus->state = I2C_IDLE;
1513
+
npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1514
+
}
1515
+
1516
+
/* Address sent and requested stall occurred (Master mode) */
1517
+
static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1518
+
{
1519
+
if (npcm_i2c_is_quick(bus)) {
1520
+
bus->state = I2C_STOP_PENDING;
1521
+
bus->stop_ind = I2C_MASTER_DONE_IND;
1522
+
npcm_i2c_eob_int(bus, true);
1523
+
npcm_i2c_master_stop(bus);
1524
+
} else if ((bus->rd_size == 1) && !bus->read_block_use) {
1525
+
/*
1526
+
* Receiving one byte only - set NACK after ensuring
1527
+
* slave ACKed the address byte.
1528
+
*/
1529
+
npcm_i2c_nack(bus);
1530
+
}
1531
+
1532
+
/* Reset stall-after-address-byte */
1533
+
npcm_i2c_stall_after_start(bus, false);
1534
+
1535
+
/* Clear stall only after setting STOP */
1536
+
iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1537
+
}
1538
+
1539
+
/* SDA status is set - TX or RX, master */
1540
+
static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1541
+
{
1542
+
u8 fif_cts;
1543
+
1544
+
if (!npcm_i2c_is_master(bus))
1545
+
return;
1546
+
1547
+
if (bus->state == I2C_IDLE) {
1548
+
bus->stop_ind = I2C_WAKE_UP_IND;
1549
+
1550
+
if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1551
+
/*
1552
+
* Need to stall after successful
1553
+
* completion of sending address byte
1554
+
*/
1555
+
npcm_i2c_stall_after_start(bus, true);
1556
+
else
1557
+
npcm_i2c_stall_after_start(bus, false);
1558
+
1559
+
/*
1560
+
* Receiving one byte only - stall after successful completion
1561
+
* of sending address byte If we NACK here, and slave doesn't
1562
+
* ACK the address, we might unintentionally NACK the next
1563
+
* multi-byte read
1564
+
*/
1565
+
if (bus->wr_size == 0 && bus->rd_size == 1)
1566
+
npcm_i2c_stall_after_start(bus, true);
1567
+
1568
+
/* Initiate I2C master tx */
1569
+
1570
+
/* select bank 1 for FIFO regs */
1571
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
1572
+
1573
+
fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1574
+
fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1575
+
1576
+
/* clear FIFO and relevant status bits. */
1577
+
fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1578
+
iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1579
+
1580
+
/* re-enable */
1581
+
fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1582
+
iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1583
+
1584
+
/*
1585
+
* Configure the FIFO threshold:
1586
+
* according to the needed # of bytes to read.
1587
+
* Note: due to HW limitation can't config the rx fifo before it
1588
+
* got and ACK on the restart. LAST bit will not be reset unless
1589
+
* RX completed. It will stay set on the next tx.
1590
+
*/
1591
+
if (bus->wr_size)
1592
+
npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1593
+
else
1594
+
npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1595
+
1596
+
bus->state = I2C_OPER_STARTED;
1597
+
1598
+
if (npcm_i2c_is_quick(bus) || bus->wr_size)
1599
+
npcm_i2c_wr_byte(bus, bus->dest_addr);
1600
+
else
1601
+
npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1602
+
/* SDA interrupt, after start\restart */
1603
+
} else {
1604
+
if (NPCM_I2CST_XMIT & i2cst) {
1605
+
bus->operation = I2C_WRITE_OPER;
1606
+
npcm_i2c_irq_master_handler_write(bus);
1607
+
} else {
1608
+
bus->operation = I2C_READ_OPER;
1609
+
npcm_i2c_irq_master_handler_read(bus);
1610
+
}
1611
+
}
1612
+
}
1613
+
1614
+
static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1615
+
{
1616
+
u8 i2cst;
1617
+
int ret = -EIO;
1618
+
1619
+
i2cst = ioread8(bus->reg + NPCM_I2CST);
1620
+
1621
+
if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1622
+
npcm_i2c_irq_handle_nmatch(bus);
1623
+
return 0;
1624
+
}
1625
+
/* A NACK has occurred */
1626
+
if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1627
+
npcm_i2c_irq_handle_nack(bus);
1628
+
return 0;
1629
+
}
1630
+
1631
+
/* Master mode: a Bus Error has been identified */
1632
+
if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1633
+
npcm_i2c_irq_handle_ber(bus);
1634
+
return 0;
1635
+
}
1636
+
1637
+
/* EOB: a master End Of Busy (meaning STOP completed) */
1638
+
if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1639
+
ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1640
+
(FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1641
+
ioread8(bus->reg + NPCM_I2CCST3)))) {
1642
+
npcm_i2c_irq_handle_eob(bus);
1643
+
return 0;
1644
+
}
1645
+
1646
+
/* Address sent and requested stall occurred (Master mode) */
1647
+
if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1648
+
npcm_i2c_irq_handle_stall_after_start(bus);
1649
+
ret = 0;
1650
+
}
1651
+
1652
+
/* SDA status is set - TX or RX, master */
1653
+
if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1654
+
(bus->fifo_use &&
1655
+
(npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1656
+
npcm_i2c_irq_handle_sda(bus, i2cst);
1657
+
ret = 0;
1658
+
}
1659
+
1660
+
return ret;
1661
+
}
1662
+
1663
+
/* recovery using TGCLK functionality of the module */
1664
+
static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1665
+
{
1666
+
u8 val;
1667
+
u8 fif_cts;
1668
+
bool done = false;
1669
+
int status = -ENOTRECOVERABLE;
1670
+
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1671
+
/* Allow 3 bytes (27 toggles) to be read from the slave: */
1672
+
int iter = 27;
1673
+
1674
+
if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1675
+
dev_dbg(bus->dev, "bus%d recovery skipped, bus not stuck",
1676
+
bus->num);
1677
+
npcm_i2c_reset(bus);
1678
+
return status;
1679
+
}
1680
+
1681
+
npcm_i2c_int_enable(bus, false);
1682
+
npcm_i2c_disable(bus);
1683
+
npcm_i2c_enable(bus);
1684
+
iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1685
+
npcm_i2c_clear_tx_fifo(bus);
1686
+
npcm_i2c_clear_rx_fifo(bus);
1687
+
iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1688
+
iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1689
+
npcm_i2c_stall_after_start(bus, false);
1690
+
1691
+
/* select bank 1 for FIFO regs */
1692
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
1693
+
1694
+
/* clear FIFO and relevant status bits. */
1695
+
fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1696
+
fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1697
+
fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1698
+
iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1699
+
npcm_i2c_set_fifo(bus, -1, 0);
1700
+
1701
+
/* Repeat the following sequence until SDA is released */
1702
+
do {
1703
+
/* Issue a single SCL toggle */
1704
+
iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1705
+
usleep_range(20, 30);
1706
+
/* If SDA line is inactive (high), stop */
1707
+
if (npcm_i2c_get_SDA(_adap)) {
1708
+
done = true;
1709
+
status = 0;
1710
+
}
1711
+
} while (!done && iter--);
1712
+
1713
+
/* If SDA line is released: send start-addr-stop, to re-sync. */
1714
+
if (npcm_i2c_get_SDA(_adap)) {
1715
+
/* Send an address byte in write direction: */
1716
+
npcm_i2c_wr_byte(bus, bus->dest_addr);
1717
+
npcm_i2c_master_start(bus);
1718
+
/* Wait until START condition is sent */
1719
+
status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1720
+
20, 200);
1721
+
/* If START condition was sent */
1722
+
if (npcm_i2c_is_master(bus) > 0) {
1723
+
usleep_range(20, 30);
1724
+
npcm_i2c_master_stop(bus);
1725
+
usleep_range(200, 500);
1726
+
}
1727
+
}
1728
+
npcm_i2c_reset(bus);
1729
+
npcm_i2c_int_enable(bus, true);
1730
+
1731
+
if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1732
+
status = 0;
1733
+
else
1734
+
status = -ENOTRECOVERABLE;
1735
+
if (status) {
1736
+
if (bus->rec_fail_cnt < ULLONG_MAX)
1737
+
bus->rec_fail_cnt++;
1738
+
} else {
1739
+
if (bus->rec_succ_cnt < ULLONG_MAX)
1740
+
bus->rec_succ_cnt++;
1741
+
}
1742
+
return status;
1743
+
}
1744
+
1745
+
/* recovery using bit banging functionality of the module */
1746
+
static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1747
+
{
1748
+
struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1749
+
struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1750
+
1751
+
rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1752
+
1753
+
/*
1754
+
* npcm i2c HW allows direct reading of SCL and SDA.
1755
+
* However, it does not support setting SCL and SDA directly.
1756
+
* The recovery function can togle SCL when SDA is low (but not set)
1757
+
* Getter functions used internally, and can be used externaly.
1758
+
*/
1759
+
rinfo->get_scl = npcm_i2c_get_SCL;
1760
+
rinfo->get_sda = npcm_i2c_get_SDA;
1761
+
_adap->bus_recovery_info = rinfo;
1762
+
}
1763
+
1764
+
/* SCLFRQ min/max field values */
1765
+
#define SCLFRQ_MIN 10
1766
+
#define SCLFRQ_MAX 511
1767
+
#define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000)
1768
+
1769
+
/*
1770
+
* npcm_i2c_init_clk: init HW timing parameters.
1771
+
* NPCM7XX i2c module timing parameters are depenent on module core clk (APB)
1772
+
* and bus frequency.
1773
+
* 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric.
1774
+
* 400kHz bus requires assymetric HT and LT. A different equation is recomended
1775
+
* by the HW designer, given core clock range (equations in comments below).
1776
+
*
1777
+
*/
1778
+
static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1779
+
{
1780
+
u32 k1 = 0;
1781
+
u32 k2 = 0;
1782
+
u8 dbnct = 0;
1783
+
u32 sclfrq = 0;
1784
+
u8 hldt = 7;
1785
+
u8 fast_mode = 0;
1786
+
u32 src_clk_khz;
1787
+
u32 bus_freq_khz;
1788
+
1789
+
src_clk_khz = bus->apb_clk / 1000;
1790
+
bus_freq_khz = bus_freq_hz / 1000;
1791
+
bus->bus_freq = bus_freq_hz;
1792
+
1793
+
/* 100KHz and below: */
1794
+
if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1795
+
sclfrq = src_clk_khz / (bus_freq_khz * 4);
1796
+
1797
+
if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1798
+
return -EDOM;
1799
+
1800
+
if (src_clk_khz >= 40000)
1801
+
hldt = 17;
1802
+
else if (src_clk_khz >= 12500)
1803
+
hldt = 15;
1804
+
else
1805
+
hldt = 7;
1806
+
}
1807
+
1808
+
/* 400KHz: */
1809
+
else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1810
+
sclfrq = 0;
1811
+
fast_mode = I2CCTL3_400K_MODE;
1812
+
1813
+
if (src_clk_khz < 7500)
1814
+
/* 400KHZ cannot be supported for core clock < 7.5MHz */
1815
+
return -EDOM;
1816
+
1817
+
else if (src_clk_khz >= 50000) {
1818
+
k1 = 80;
1819
+
k2 = 48;
1820
+
hldt = 12;
1821
+
dbnct = 7;
1822
+
}
1823
+
1824
+
/* Master or Slave with frequency > 25MHz */
1825
+
else if (src_clk_khz > 25000) {
1826
+
hldt = clk_coef(src_clk_khz, 300) + 7;
1827
+
k1 = clk_coef(src_clk_khz, 1600);
1828
+
k2 = clk_coef(src_clk_khz, 900);
1829
+
}
1830
+
}
1831
+
1832
+
/* 1MHz: */
1833
+
else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1834
+
sclfrq = 0;
1835
+
fast_mode = I2CCTL3_400K_MODE;
1836
+
1837
+
/* 1MHZ cannot be supported for core clock < 24 MHz */
1838
+
if (src_clk_khz < 24000)
1839
+
return -EDOM;
1840
+
1841
+
k1 = clk_coef(src_clk_khz, 620);
1842
+
k2 = clk_coef(src_clk_khz, 380);
1843
+
1844
+
/* Core clk > 40 MHz */
1845
+
if (src_clk_khz > 40000) {
1846
+
/*
1847
+
* Set HLDT:
1848
+
* SDA hold time: (HLDT-7) * T(CLK) >= 120
1849
+
* HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1850
+
*/
1851
+
hldt = clk_coef(src_clk_khz, 120) + 7;
1852
+
} else {
1853
+
hldt = 7;
1854
+
dbnct = 2;
1855
+
}
1856
+
}
1857
+
1858
+
/* Frequency larger than 1 MHz is not supported */
1859
+
else
1860
+
return -EINVAL;
1861
+
1862
+
if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1863
+
k1 = round_up(k1, 2);
1864
+
k2 = round_up(k2 + 1, 2);
1865
+
if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1866
+
k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1867
+
return -EDOM;
1868
+
}
1869
+
1870
+
/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1871
+
iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1872
+
bus->reg + NPCM_I2CCTL2);
1873
+
1874
+
/* bits [8:7] are in I2CCTL3 reg */
1875
+
iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1876
+
bus->reg + NPCM_I2CCTL3);
1877
+
1878
+
/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1879
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
1880
+
1881
+
if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1882
+
/*
1883
+
* Set SCL Low/High Time:
1884
+
* k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
1885
+
* k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1886
+
*/
1887
+
iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1888
+
iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1889
+
1890
+
iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1891
+
}
1892
+
1893
+
iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1894
+
1895
+
/* Return to Bank 1, and stay there by default: */
1896
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
1897
+
1898
+
return 0;
1899
+
}
1900
+
1901
+
static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1902
+
u32 bus_freq_hz)
1903
+
{
1904
+
u8 val;
1905
+
int ret;
1906
+
1907
+
/* Check whether module already enabled or frequency is out of bounds */
1908
+
if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1909
+
bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1910
+
return -EINVAL;
1911
+
1912
+
npcm_i2c_disable(bus);
1913
+
1914
+
/* Configure FIFO mode : */
1915
+
if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1916
+
bus->fifo_use = true;
1917
+
npcm_i2c_select_bank(bus, I2C_BANK_0);
1918
+
val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1919
+
val |= NPCM_I2CFIF_CTL_FIFO_EN;
1920
+
iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1921
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
1922
+
} else {
1923
+
bus->fifo_use = false;
1924
+
}
1925
+
1926
+
/* Configure I2C module clock frequency */
1927
+
ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1928
+
if (ret) {
1929
+
dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1930
+
return ret;
1931
+
}
1932
+
1933
+
/* Enable module (before configuring CTL1) */
1934
+
npcm_i2c_enable(bus);
1935
+
bus->state = I2C_IDLE;
1936
+
val = ioread8(bus->reg + NPCM_I2CCTL1);
1937
+
val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1938
+
iowrite8(val, bus->reg + NPCM_I2CCTL1);
1939
+
1940
+
npcm_i2c_int_enable(bus, true);
1941
+
1942
+
npcm_i2c_reset(bus);
1943
+
1944
+
return 0;
1945
+
}
1946
+
1947
+
static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1948
+
{
1949
+
u32 clk_freq_hz;
1950
+
int ret;
1951
+
1952
+
/* Initialize the internal data structures */
1953
+
bus->state = I2C_DISABLE;
1954
+
bus->master_or_slave = I2C_SLAVE;
1955
+
bus->int_time_stamp = 0;
1956
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
1957
+
bus->slave = NULL;
1958
+
#endif
1959
+
1960
+
ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1961
+
&clk_freq_hz);
1962
+
if (ret) {
1963
+
dev_info(&pdev->dev, "Could not read clock-frequency property");
1964
+
clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
1965
+
}
1966
+
1967
+
ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
1968
+
if (ret) {
1969
+
dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
1970
+
return ret;
1971
+
}
1972
+
1973
+
return 0;
1974
+
}
1975
+
1976
+
static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
1977
+
{
1978
+
struct npcm_i2c *bus = dev_id;
1979
+
1980
+
if (npcm_i2c_is_master(bus))
1981
+
bus->master_or_slave = I2C_MASTER;
1982
+
1983
+
if (bus->master_or_slave == I2C_MASTER) {
1984
+
bus->int_time_stamp = jiffies;
1985
+
if (!npcm_i2c_int_master_handler(bus))
1986
+
return IRQ_HANDLED;
1987
+
}
1988
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
1989
+
if (bus->slave) {
1990
+
bus->master_or_slave = I2C_SLAVE;
1991
+
return npcm_i2c_int_slave_handler(bus);
1992
+
}
1993
+
#endif
1994
+
return IRQ_NONE;
1995
+
}
1996
+
1997
+
static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
1998
+
u8 slave_addr, u16 nwrite, u16 nread,
1999
+
u8 *write_data, u8 *read_data,
2000
+
bool use_PEC, bool use_read_block)
2001
+
{
2002
+
if (bus->state != I2C_IDLE) {
2003
+
bus->cmd_err = -EBUSY;
2004
+
return false;
2005
+
}
2006
+
bus->dest_addr = slave_addr << 1;
2007
+
bus->wr_buf = write_data;
2008
+
bus->wr_size = nwrite;
2009
+
bus->wr_ind = 0;
2010
+
bus->rd_buf = read_data;
2011
+
bus->rd_size = nread;
2012
+
bus->rd_ind = 0;
2013
+
bus->PEC_use = 0;
2014
+
2015
+
/* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2016
+
if (nread)
2017
+
bus->PEC_use = use_PEC;
2018
+
2019
+
bus->read_block_use = use_read_block;
2020
+
if (nread && !nwrite)
2021
+
bus->operation = I2C_READ_OPER;
2022
+
else
2023
+
bus->operation = I2C_WRITE_OPER;
2024
+
if (bus->fifo_use) {
2025
+
u8 i2cfif_cts;
2026
+
2027
+
npcm_i2c_select_bank(bus, I2C_BANK_1);
2028
+
/* clear FIFO and relevant status bits. */
2029
+
i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2030
+
i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2031
+
i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2032
+
iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2033
+
}
2034
+
2035
+
bus->state = I2C_IDLE;
2036
+
npcm_i2c_stall_after_start(bus, true);
2037
+
npcm_i2c_master_start(bus);
2038
+
return true;
2039
+
}
2040
+
2041
+
static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2042
+
int num)
2043
+
{
2044
+
struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2045
+
struct i2c_msg *msg0, *msg1;
2046
+
unsigned long time_left, flags;
2047
+
u16 nwrite, nread;
2048
+
u8 *write_data, *read_data;
2049
+
u8 slave_addr;
2050
+
int timeout;
2051
+
int ret = 0;
2052
+
bool read_block = false;
2053
+
bool read_PEC = false;
2054
+
u8 bus_busy;
2055
+
unsigned long timeout_usec;
2056
+
2057
+
if (bus->state == I2C_DISABLE) {
2058
+
dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2059
+
return -EINVAL;
2060
+
}
2061
+
2062
+
msg0 = &msgs[0];
2063
+
slave_addr = msg0->addr;
2064
+
if (msg0->flags & I2C_M_RD) { /* read */
2065
+
nwrite = 0;
2066
+
write_data = NULL;
2067
+
read_data = msg0->buf;
2068
+
if (msg0->flags & I2C_M_RECV_LEN) {
2069
+
nread = 1;
2070
+
read_block = true;
2071
+
if (msg0->flags & I2C_CLIENT_PEC)
2072
+
read_PEC = true;
2073
+
} else {
2074
+
nread = msg0->len;
2075
+
}
2076
+
} else { /* write */
2077
+
nwrite = msg0->len;
2078
+
write_data = msg0->buf;
2079
+
nread = 0;
2080
+
read_data = NULL;
2081
+
if (num == 2) {
2082
+
msg1 = &msgs[1];
2083
+
read_data = msg1->buf;
2084
+
if (msg1->flags & I2C_M_RECV_LEN) {
2085
+
nread = 1;
2086
+
read_block = true;
2087
+
if (msg1->flags & I2C_CLIENT_PEC)
2088
+
read_PEC = true;
2089
+
} else {
2090
+
nread = msg1->len;
2091
+
read_block = false;
2092
+
}
2093
+
}
2094
+
}
2095
+
2096
+
/* Adaptive TimeOut: astimated time in usec + 100% margin */
2097
+
timeout_usec = (2 * 10000 / bus->bus_freq) * (2 + nread + nwrite);
2098
+
timeout = max(msecs_to_jiffies(35), usecs_to_jiffies(timeout_usec));
2099
+
if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2100
+
dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2101
+
return -EINVAL;
2102
+
}
2103
+
2104
+
time_left = jiffies + msecs_to_jiffies(DEFAULT_STALL_COUNT) + 1;
2105
+
do {
2106
+
/*
2107
+
* we must clear slave address immediately when the bus is not
2108
+
* busy, so we spinlock it, but we don't keep the lock for the
2109
+
* entire while since it is too long.
2110
+
*/
2111
+
spin_lock_irqsave(&bus->lock, flags);
2112
+
bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2113
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
2114
+
if (!bus_busy && bus->slave)
2115
+
iowrite8((bus->slave->addr & 0x7F),
2116
+
bus->reg + NPCM_I2CADDR1);
2117
+
#endif
2118
+
spin_unlock_irqrestore(&bus->lock, flags);
2119
+
2120
+
} while (time_is_after_jiffies(time_left) && bus_busy);
2121
+
2122
+
if (bus_busy) {
2123
+
iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2124
+
npcm_i2c_reset(bus);
2125
+
i2c_recover_bus(adap);
2126
+
return -EAGAIN;
2127
+
}
2128
+
2129
+
npcm_i2c_init_params(bus);
2130
+
bus->dest_addr = slave_addr;
2131
+
bus->msgs = msgs;
2132
+
bus->msgs_num = num;
2133
+
bus->cmd_err = 0;
2134
+
bus->read_block_use = read_block;
2135
+
2136
+
reinit_completion(&bus->cmd_complete);
2137
+
if (!npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2138
+
write_data, read_data, read_PEC,
2139
+
read_block))
2140
+
ret = -EBUSY;
2141
+
2142
+
if (ret != -EBUSY) {
2143
+
time_left = wait_for_completion_timeout(&bus->cmd_complete,
2144
+
timeout);
2145
+
2146
+
if (time_left == 0) {
2147
+
if (bus->timeout_cnt < ULLONG_MAX)
2148
+
bus->timeout_cnt++;
2149
+
if (bus->master_or_slave == I2C_MASTER) {
2150
+
i2c_recover_bus(adap);
2151
+
bus->cmd_err = -EIO;
2152
+
bus->state = I2C_IDLE;
2153
+
}
2154
+
}
2155
+
}
2156
+
ret = bus->cmd_err;
2157
+
2158
+
/* if there was BER, check if need to recover the bus: */
2159
+
if (bus->cmd_err == -EAGAIN)
2160
+
ret = i2c_recover_bus(adap);
2161
+
2162
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
2163
+
/* reenable slave if it was enabled */
2164
+
if (bus->slave)
2165
+
iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2166
+
bus->reg + NPCM_I2CADDR1);
2167
+
#endif
2168
+
return bus->cmd_err;
2169
+
}
2170
+
2171
+
static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2172
+
{
2173
+
return I2C_FUNC_I2C |
2174
+
I2C_FUNC_SMBUS_EMUL |
2175
+
I2C_FUNC_SMBUS_BLOCK_DATA |
2176
+
I2C_FUNC_SMBUS_PEC |
2177
+
I2C_FUNC_SLAVE;
2178
+
}
2179
+
2180
+
static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2181
+
.max_read_len = 32768,
2182
+
.max_write_len = 32768,
2183
+
.flags = I2C_AQ_COMB_WRITE_THEN_READ,
2184
+
};
2185
+
2186
+
static const struct i2c_algorithm npcm_i2c_algo = {
2187
+
.master_xfer = npcm_i2c_master_xfer,
2188
+
.functionality = npcm_i2c_functionality,
2189
+
#if IS_ENABLED(CONFIG_I2C_SLAVE)
2190
+
.reg_slave = npcm_i2c_reg_slave,
2191
+
.unreg_slave = npcm_i2c_unreg_slave,
2192
+
#endif
2193
+
};
2194
+
2195
+
/* i2c debugfs directory: used to keep health monitor of i2c devices */
2196
+
static struct dentry *npcm_i2c_debugfs_dir;
2197
+
2198
+
static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2199
+
struct npcm_i2c *bus)
2200
+
{
2201
+
struct dentry *d;
2202
+
2203
+
if (!npcm_i2c_debugfs_dir)
2204
+
return;
2205
+
d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2206
+
if (IS_ERR_OR_NULL(d))
2207
+
return;
2208
+
debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2209
+
debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2210
+
debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2211
+
debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2212
+
debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2213
+
2214
+
bus->debugfs = d;
2215
+
}
2216
+
2217
+
static int npcm_i2c_probe_bus(struct platform_device *pdev)
2218
+
{
2219
+
struct npcm_i2c *bus;
2220
+
struct i2c_adapter *adap;
2221
+
struct clk *i2c_clk;
2222
+
static struct regmap *gcr_regmap;
2223
+
static struct regmap *clk_regmap;
2224
+
int irq;
2225
+
int ret;
2226
+
2227
+
bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2228
+
if (!bus)
2229
+
return -ENOMEM;
2230
+
2231
+
bus->dev = &pdev->dev;
2232
+
2233
+
bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2234
+
/* core clk must be acquired to calculate module timing settings */
2235
+
i2c_clk = devm_clk_get(&pdev->dev, NULL);
2236
+
if (IS_ERR(i2c_clk))
2237
+
return PTR_ERR(i2c_clk);
2238
+
bus->apb_clk = clk_get_rate(i2c_clk);
2239
+
2240
+
gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2241
+
if (IS_ERR(gcr_regmap))
2242
+
return PTR_ERR(gcr_regmap);
2243
+
regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL);
2244
+
2245
+
clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk");
2246
+
if (IS_ERR(clk_regmap))
2247
+
return PTR_ERR(clk_regmap);
2248
+
2249
+
bus->reg = devm_platform_ioremap_resource(pdev, 0);
2250
+
if (IS_ERR(bus->reg))
2251
+
return PTR_ERR(bus->reg);
2252
+
2253
+
spin_lock_init(&bus->lock);
2254
+
init_completion(&bus->cmd_complete);
2255
+
2256
+
adap = &bus->adap;
2257
+
adap->owner = THIS_MODULE;
2258
+
adap->retries = 3;
2259
+
adap->timeout = HZ;
2260
+
adap->algo = &npcm_i2c_algo;
2261
+
adap->quirks = &npcm_i2c_quirks;
2262
+
adap->algo_data = bus;
2263
+
adap->dev.parent = &pdev->dev;
2264
+
adap->dev.of_node = pdev->dev.of_node;
2265
+
adap->nr = pdev->id;
2266
+
2267
+
irq = platform_get_irq(pdev, 0);
2268
+
if (irq < 0)
2269
+
return irq;
2270
+
2271
+
ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2272
+
dev_name(bus->dev), bus);
2273
+
if (ret)
2274
+
return ret;
2275
+
2276
+
ret = __npcm_i2c_init(bus, pdev);
2277
+
if (ret)
2278
+
return ret;
2279
+
2280
+
npcm_i2c_recovery_init(adap);
2281
+
2282
+
i2c_set_adapdata(adap, bus);
2283
+
2284
+
snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2285
+
bus->num);
2286
+
ret = i2c_add_numbered_adapter(&bus->adap);
2287
+
if (ret)
2288
+
return ret;
2289
+
2290
+
platform_set_drvdata(pdev, bus);
2291
+
npcm_i2c_init_debugfs(pdev, bus);
2292
+
return 0;
2293
+
}
2294
+
2295
+
static int npcm_i2c_remove_bus(struct platform_device *pdev)
2296
+
{
2297
+
unsigned long lock_flags;
2298
+
struct npcm_i2c *bus = platform_get_drvdata(pdev);
2299
+
2300
+
debugfs_remove_recursive(bus->debugfs);
2301
+
spin_lock_irqsave(&bus->lock, lock_flags);
2302
+
npcm_i2c_disable(bus);
2303
+
spin_unlock_irqrestore(&bus->lock, lock_flags);
2304
+
i2c_del_adapter(&bus->adap);
2305
+
return 0;
2306
+
}
2307
+
2308
+
static const struct of_device_id npcm_i2c_bus_of_table[] = {
2309
+
{ .compatible = "nuvoton,npcm750-i2c", },
2310
+
{}
2311
+
};
2312
+
MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2313
+
2314
+
static struct platform_driver npcm_i2c_bus_driver = {
2315
+
.probe = npcm_i2c_probe_bus,
2316
+
.remove = npcm_i2c_remove_bus,
2317
+
.driver = {
2318
+
.name = "nuvoton-i2c",
2319
+
.of_match_table = npcm_i2c_bus_of_table,
2320
+
}
2321
+
};
2322
+
2323
+
static int __init npcm_i2c_init(void)
2324
+
{
2325
+
npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2326
+
platform_driver_register(&npcm_i2c_bus_driver);
2327
+
return 0;
2328
+
}
2329
+
module_init(npcm_i2c_init);
2330
+
2331
+
static void __exit npcm_i2c_exit(void)
2332
+
{
2333
+
platform_driver_unregister(&npcm_i2c_bus_driver);
2334
+
debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2335
+
}
2336
+
module_exit(npcm_i2c_exit);
2337
+
2338
+
MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2339
+
MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2340
+
MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2341
+
MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2342
+
MODULE_LICENSE("GPL v2");
+1
-4
drivers/i2c/busses/i2c-nvidia-gpu.c
+1
-4
drivers/i2c/busses/i2c-nvidia-gpu.c
···
277
277
i2cd->gpu_ccgx_ucsi->irq = irq;
278
278
i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
279
279
i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
280
-
if (IS_ERR(i2cd->ccgx_client))
281
-
return PTR_ERR(i2cd->ccgx_client);
282
-
283
-
return 0;
280
+
return PTR_ERR_OR_ZERO(i2cd->ccgx_client);
284
281
}
285
282
286
283
static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+1
-3
drivers/i2c/busses/i2c-octeon-platdrv.c
+1
-3
drivers/i2c/busses/i2c-octeon-platdrv.c
···
136
136
{
137
137
struct device_node *node = pdev->dev.of_node;
138
138
int irq, result = 0, hlc_irq = 0;
139
-
struct resource *res_mem;
140
139
struct octeon_i2c *i2c;
141
140
bool cn78xx_style;
142
141
···
166
167
i2c->roff.twsi_int = 0x10;
167
168
i2c->roff.sw_twsi_ext = 0x18;
168
169
169
-
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
170
-
i2c->twsi_base = devm_ioremap_resource(&pdev->dev, res_mem);
170
+
i2c->twsi_base = devm_platform_ioremap_resource(pdev, 0);
171
171
if (IS_ERR(i2c->twsi_base)) {
172
172
result = PTR_ERR(i2c->twsi_base);
173
173
goto out;
+1
-3
drivers/i2c/busses/i2c-omap.c
+1
-3
drivers/i2c/busses/i2c-omap.c
···
1365
1365
u16 minor, major;
1366
1366
1367
1367
irq = platform_get_irq(pdev, 0);
1368
-
if (irq < 0) {
1369
-
dev_err(&pdev->dev, "no irq resource?\n");
1368
+
if (irq < 0)
1370
1369
return irq;
1371
-
}
1372
1370
1373
1371
omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1374
1372
if (!omap)
+2
-6
drivers/i2c/busses/i2c-owl.c
+2
-6
drivers/i2c/busses/i2c-owl.c
···
396
396
{
397
397
struct device *dev = &pdev->dev;
398
398
struct owl_i2c_dev *i2c_dev;
399
-
struct resource *res;
400
399
int ret, irq;
401
400
402
401
i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
403
402
if (!i2c_dev)
404
403
return -ENOMEM;
405
404
406
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407
-
i2c_dev->base = devm_ioremap_resource(dev, res);
405
+
i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
408
406
if (IS_ERR(i2c_dev->base))
409
407
return PTR_ERR(i2c_dev->base);
410
408
411
409
irq = platform_get_irq(pdev, 0);
412
-
if (irq < 0) {
413
-
dev_err(dev, "failed to get IRQ number\n");
410
+
if (irq < 0)
414
411
return irq;
415
-
}
416
412
417
413
if (of_property_read_u32(dev->of_node, "clock-frequency",
418
414
&i2c_dev->bus_freq))
+1
-2
drivers/i2c/busses/i2c-pca-platform.c
+1
-2
drivers/i2c/busses/i2c-pca-platform.c
···
149
149
if (!i2c)
150
150
return -ENOMEM;
151
151
152
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
153
-
i2c->reg_base = devm_ioremap_resource(&pdev->dev, res);
152
+
i2c->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
154
153
if (IS_ERR(i2c->reg_base))
155
154
return PTR_ERR(i2c->reg_base);
156
155
+2
-1
drivers/i2c/busses/i2c-piix4.c
+2
-1
drivers/i2c/busses/i2c-piix4.c
···
977
977
}
978
978
979
979
if (dev->vendor == PCI_VENDOR_ID_AMD &&
980
-
dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
980
+
(dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
981
+
dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
981
982
retval = piix4_setup_sb800(dev, id, 1);
982
983
}
983
984
-1
drivers/i2c/busses/i2c-pnx.c
-1
drivers/i2c/busses/i2c-pnx.c
+9
-9
drivers/i2c/busses/i2c-powermac.c
+9
-9
drivers/i2c/busses/i2c-powermac.c
···
207
207
struct pmac_i2c_bus *bus,
208
208
struct device_node *node)
209
209
{
210
-
const __be32 *prop;
211
-
int len;
210
+
u32 prop;
211
+
int ret;
212
212
213
213
/* First check for valid "reg" */
214
-
prop = of_get_property(node, "reg", &len);
215
-
if (prop && (len >= sizeof(int)))
216
-
return (be32_to_cpup(prop) & 0xff) >> 1;
214
+
ret = of_property_read_u32(node, "reg", &prop);
215
+
if (ret == 0)
216
+
return (prop & 0xff) >> 1;
217
217
218
218
/* Then check old-style "i2c-address" */
219
-
prop = of_get_property(node, "i2c-address", &len);
220
-
if (prop && (len >= sizeof(int)))
221
-
return (be32_to_cpup(prop) & 0xff) >> 1;
219
+
ret = of_property_read_u32(node, "i2c-address", &prop);
220
+
if (ret == 0)
221
+
return (prop & 0xff) >> 1;
222
222
223
223
/* Now handle some devices with missing "reg" properties */
224
224
if (of_node_name_eq(node, "cereal"))
···
315
315
{
316
316
struct i2c_client *newdev;
317
317
struct device_node *node;
318
-
bool found_onyx = 0;
318
+
bool found_onyx = false;
319
319
320
320
/*
321
321
* In some cases we end up with the via-pmu node itself, in this
+487
-317
drivers/i2c/busses/i2c-pxa.c
+487
-317
drivers/i2c/busses/i2c-pxa.c
···
16
16
* Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
17
17
* Feb 2005: Rework slave mode handling [RMK]
18
18
*/
19
-
#include <linux/kernel.h>
20
-
#include <linux/module.h>
19
+
#include <linux/clk.h>
20
+
#include <linux/delay.h>
21
+
#include <linux/err.h>
22
+
#include <linux/errno.h>
23
+
#include <linux/gpio/consumer.h>
21
24
#include <linux/i2c.h>
22
25
#include <linux/init.h>
23
-
#include <linux/time.h>
24
-
#include <linux/sched.h>
25
-
#include <linux/delay.h>
26
-
#include <linux/errno.h>
27
26
#include <linux/interrupt.h>
27
+
#include <linux/io.h>
28
+
#include <linux/kernel.h>
29
+
#include <linux/module.h>
28
30
#include <linux/of.h>
29
31
#include <linux/of_device.h>
32
+
#include <linux/pinctrl/consumer.h>
30
33
#include <linux/platform_device.h>
31
-
#include <linux/err.h>
32
-
#include <linux/clk.h>
33
-
#include <linux/slab.h>
34
-
#include <linux/io.h>
35
34
#include <linux/platform_data/i2c-pxa.h>
35
+
#include <linux/slab.h>
36
36
37
-
#include <asm/irq.h>
37
+
/* I2C register field definitions */
38
+
#define IBMR_SDAS (1 << 0)
39
+
#define IBMR_SCLS (1 << 1)
40
+
41
+
#define ICR_START (1 << 0) /* start bit */
42
+
#define ICR_STOP (1 << 1) /* stop bit */
43
+
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
44
+
#define ICR_TB (1 << 3) /* transfer byte bit */
45
+
#define ICR_MA (1 << 4) /* master abort */
46
+
#define ICR_SCLE (1 << 5) /* master clock enable */
47
+
#define ICR_IUE (1 << 6) /* unit enable */
48
+
#define ICR_GCD (1 << 7) /* general call disable */
49
+
#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
50
+
#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
51
+
#define ICR_BEIE (1 << 10) /* enable bus error ints */
52
+
#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
53
+
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
54
+
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
55
+
#define ICR_UR (1 << 14) /* unit reset */
56
+
#define ICR_FM (1 << 15) /* fast mode */
57
+
#define ICR_HS (1 << 16) /* High Speed mode */
58
+
#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
59
+
#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
60
+
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
61
+
62
+
#define ISR_RWM (1 << 0) /* read/write mode */
63
+
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
64
+
#define ISR_UB (1 << 2) /* unit busy */
65
+
#define ISR_IBB (1 << 3) /* bus busy */
66
+
#define ISR_SSD (1 << 4) /* slave stop detected */
67
+
#define ISR_ALD (1 << 5) /* arbitration loss detected */
68
+
#define ISR_ITE (1 << 6) /* tx buffer empty */
69
+
#define ISR_IRF (1 << 7) /* rx buffer full */
70
+
#define ISR_GCAD (1 << 8) /* general call address detected */
71
+
#define ISR_SAD (1 << 9) /* slave address detected */
72
+
#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
73
+
74
+
#define ILCR_SLV_SHIFT 0
75
+
#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
76
+
#define ILCR_FLV_SHIFT 9
77
+
#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
78
+
#define ILCR_HLVL_SHIFT 18
79
+
#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
80
+
#define ILCR_HLVH_SHIFT 27
81
+
#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
82
+
83
+
#define IWCR_CNT_SHIFT 0
84
+
#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
85
+
#define IWCR_HS_CNT1_SHIFT 5
86
+
#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
87
+
#define IWCR_HS_CNT2_SHIFT 10
88
+
#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
89
+
90
+
/* need a longer timeout if we're dealing with the fact we may well be
91
+
* looking at a multi-master environment
92
+
*/
93
+
#define DEF_TIMEOUT 32
94
+
95
+
#define NO_SLAVE (-ENXIO)
96
+
#define BUS_ERROR (-EREMOTEIO)
97
+
#define XFER_NAKED (-ECONNREFUSED)
98
+
#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
99
+
100
+
/* ICR initialize bit values
101
+
*
102
+
* 15 FM 0 (100 kHz operation)
103
+
* 14 UR 0 (No unit reset)
104
+
* 13 SADIE 0 (Disables the unit from interrupting on slave addresses
105
+
* matching its slave address)
106
+
* 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
107
+
* in master mode)
108
+
* 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
109
+
* 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
110
+
* 9 IRFIE 1 (Enable interrupts from full buffer received)
111
+
* 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
112
+
* 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
113
+
* 6 IUE 0 (Disable unit until we change settings)
114
+
* 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
115
+
* 4 MA 0 (Only send stop with the ICR stop bit)
116
+
* 3 TB 0 (We are not transmitting a byte initially)
117
+
* 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
118
+
* 1 STOP 0 (Do not send a STOP)
119
+
* 0 START 0 (Do not send a START)
120
+
*/
121
+
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
122
+
123
+
/* I2C status register init values
124
+
*
125
+
* 10 BED 1 (Clear bus error detected)
126
+
* 9 SAD 1 (Clear slave address detected)
127
+
* 7 IRF 1 (Clear IDBR Receive Full)
128
+
* 6 ITE 1 (Clear IDBR Transmit Empty)
129
+
* 5 ALD 1 (Clear Arbitration Loss Detected)
130
+
* 4 SSD 1 (Clear Slave Stop Detected)
131
+
*/
132
+
#define I2C_ISR_INIT 0x7FF /* status register init */
38
133
39
134
struct pxa_reg_layout {
40
135
u32 ibmr;
···
151
56
REGS_A3700,
152
57
};
153
58
154
-
#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
155
-
#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
156
-
157
-
/*
158
-
* I2C registers definitions
159
-
*/
59
+
/* I2C register layout definitions */
160
60
static struct pxa_reg_layout pxa_reg_layout[] = {
161
61
[REGS_PXA2XX] = {
162
62
.ibmr = 0x00,
···
159
69
.icr = 0x10,
160
70
.isr = 0x18,
161
71
.isar = 0x20,
72
+
.fm = ICR_FM,
73
+
.hs = ICR_HS,
162
74
},
163
75
[REGS_PXA3XX] = {
164
76
.ibmr = 0x00,
···
168
76
.icr = 0x08,
169
77
.isr = 0x0c,
170
78
.isar = 0x10,
79
+
.fm = ICR_FM,
80
+
.hs = ICR_HS,
171
81
},
172
82
[REGS_CE4100] = {
173
83
.ibmr = 0x14,
···
177
83
.icr = 0x00,
178
84
.isr = 0x04,
179
85
/* no isar register */
86
+
.fm = ICR_FM,
87
+
.hs = ICR_HS,
180
88
},
181
89
[REGS_PXA910] = {
182
90
.ibmr = 0x00,
···
188
92
.isar = 0x20,
189
93
.ilcr = 0x28,
190
94
.iwcr = 0x30,
95
+
.fm = ICR_FM,
96
+
.hs = ICR_HS,
191
97
},
192
98
[REGS_A3700] = {
193
99
.ibmr = 0x00,
···
197
99
.icr = 0x08,
198
100
.isr = 0x0c,
199
101
.isar = 0x10,
200
-
.fm = ICR_BUSMODE_FM,
201
-
.hs = ICR_BUSMODE_HS,
102
+
.fm = ICR_A3700_FM,
103
+
.hs = ICR_A3700_HS,
202
104
},
203
105
};
106
+
107
+
static const struct of_device_id i2c_pxa_dt_ids[] = {
108
+
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
109
+
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
110
+
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
111
+
{ .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
112
+
{}
113
+
};
114
+
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
204
115
205
116
static const struct platform_device_id i2c_pxa_id_table[] = {
206
117
{ "pxa2xx-i2c", REGS_PXA2XX },
···
220
113
{ },
221
114
};
222
115
MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
223
-
224
-
/*
225
-
* I2C bit definitions
226
-
*/
227
-
228
-
#define ICR_START (1 << 0) /* start bit */
229
-
#define ICR_STOP (1 << 1) /* stop bit */
230
-
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
231
-
#define ICR_TB (1 << 3) /* transfer byte bit */
232
-
#define ICR_MA (1 << 4) /* master abort */
233
-
#define ICR_SCLE (1 << 5) /* master clock enable */
234
-
#define ICR_IUE (1 << 6) /* unit enable */
235
-
#define ICR_GCD (1 << 7) /* general call disable */
236
-
#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
237
-
#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
238
-
#define ICR_BEIE (1 << 10) /* enable bus error ints */
239
-
#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
240
-
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
241
-
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
242
-
#define ICR_UR (1 << 14) /* unit reset */
243
-
#define ICR_FM (1 << 15) /* fast mode */
244
-
#define ICR_HS (1 << 16) /* High Speed mode */
245
-
#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
246
-
247
-
#define ISR_RWM (1 << 0) /* read/write mode */
248
-
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
249
-
#define ISR_UB (1 << 2) /* unit busy */
250
-
#define ISR_IBB (1 << 3) /* bus busy */
251
-
#define ISR_SSD (1 << 4) /* slave stop detected */
252
-
#define ISR_ALD (1 << 5) /* arbitration loss detected */
253
-
#define ISR_ITE (1 << 6) /* tx buffer empty */
254
-
#define ISR_IRF (1 << 7) /* rx buffer full */
255
-
#define ISR_GCAD (1 << 8) /* general call address detected */
256
-
#define ISR_SAD (1 << 9) /* slave address detected */
257
-
#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
258
-
259
-
/* bit field shift & mask */
260
-
#define ILCR_SLV_SHIFT 0
261
-
#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
262
-
#define ILCR_FLV_SHIFT 9
263
-
#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
264
-
#define ILCR_HLVL_SHIFT 18
265
-
#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
266
-
#define ILCR_HLVH_SHIFT 27
267
-
#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
268
-
269
-
#define IWCR_CNT_SHIFT 0
270
-
#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
271
-
#define IWCR_HS_CNT1_SHIFT 5
272
-
#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
273
-
#define IWCR_HS_CNT2_SHIFT 10
274
-
#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
275
116
276
117
struct pxa_i2c {
277
118
spinlock_t lock;
···
262
207
bool highmode_enter;
263
208
u32 fm_mask;
264
209
u32 hs_mask;
210
+
211
+
struct i2c_bus_recovery_info recovery;
212
+
struct pinctrl *pinctrl;
213
+
struct pinctrl_state *pinctrl_default;
214
+
struct pinctrl_state *pinctrl_recovery;
265
215
};
266
216
267
217
#define _IBMR(i2c) ((i2c)->reg_ibmr)
···
294
234
static inline void
295
235
decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
296
236
{
297
-
printk("%s %08x: ", prefix, val);
237
+
printk("%s %08x:", prefix, val);
298
238
while (num--) {
299
239
const char *str = val & bits->mask ? bits->set : bits->unset;
300
240
if (str)
301
-
printk("%s ", str);
241
+
pr_cont(" %s", str);
302
242
bits++;
303
243
}
244
+
pr_cont("\n");
304
245
}
305
246
306
247
static const struct bits isr_bits[] = {
···
321
260
static void decode_ISR(unsigned int val)
322
261
{
323
262
decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
324
-
printk("\n");
325
263
}
326
264
327
265
static const struct bits icr_bits[] = {
···
345
285
static void decode_ICR(unsigned int val)
346
286
{
347
287
decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
348
-
printk("\n");
349
288
}
350
289
#endif
351
290
···
370
311
dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
371
312
readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
372
313
readl(_ISR(i2c)));
373
-
dev_dbg(dev, "log: ");
314
+
dev_err(dev, "log:");
374
315
for (i = 0; i < i2c->irqlogidx; i++)
375
-
pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
376
-
377
-
pr_debug("\n");
316
+
pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
317
+
pr_cont("\n");
378
318
}
379
319
380
320
#else /* ifdef DEBUG */
···
388
330
#endif /* ifdef DEBUG / else */
389
331
390
332
static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
391
-
static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
392
333
393
334
static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
394
335
{
···
403
346
return;
404
347
}
405
348
406
-
while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
349
+
while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
407
350
unsigned long icr = readl(_ICR(i2c));
408
351
409
352
icr &= ~ICR_START;
···
424
367
static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
425
368
{
426
369
int timeout = DEF_TIMEOUT;
370
+
u32 isr;
427
371
428
-
while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
429
-
if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
372
+
while (1) {
373
+
isr = readl(_ISR(i2c));
374
+
if (!(isr & (ISR_IBB | ISR_UB)))
375
+
return 0;
376
+
377
+
if (isr & ISR_SAD)
430
378
timeout += 4;
379
+
380
+
if (!timeout--)
381
+
break;
431
382
432
383
msleep(2);
433
384
show_state(i2c);
434
385
}
435
386
436
-
if (timeout < 0)
437
-
show_state(i2c);
387
+
show_state(i2c);
438
388
439
-
return timeout < 0 ? I2C_RETRY : 0;
389
+
return I2C_RETRY;
440
390
}
441
391
442
392
static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
···
465
401
* quick check of the i2c lines themselves to ensure they've
466
402
* gone high...
467
403
*/
468
-
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
404
+
if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
405
+
readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
469
406
if (i2c_debug > 0)
470
407
dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
471
408
return 1;
···
566
501
#define i2c_pxa_set_slave(i2c, err) do { } while (0)
567
502
#endif
568
503
569
-
static void i2c_pxa_reset(struct pxa_i2c *i2c)
504
+
static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
570
505
{
571
-
pr_debug("Resetting I2C Controller Unit\n");
572
-
573
-
/* abort any transfer currently under way */
574
-
i2c_pxa_abort(i2c);
575
-
576
506
/* reset according to 9.8 */
577
507
writel(ICR_UR, _ICR(i2c));
578
508
writel(I2C_ISR_INIT, _ISR(i2c));
···
586
526
#endif
587
527
588
528
i2c_pxa_set_slave(i2c, 0);
529
+
}
589
530
531
+
static void i2c_pxa_enable(struct pxa_i2c *i2c)
532
+
{
590
533
/* enable unit */
591
534
writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
592
535
udelay(100);
536
+
}
537
+
538
+
static void i2c_pxa_reset(struct pxa_i2c *i2c)
539
+
{
540
+
pr_debug("Resetting I2C Controller Unit\n");
541
+
542
+
/* abort any transfer currently under way */
543
+
i2c_pxa_abort(i2c);
544
+
i2c_pxa_do_reset(i2c);
545
+
i2c_pxa_enable(i2c);
593
546
}
594
547
595
548
···
669
596
timeout = 0x10000;
670
597
671
598
while (1) {
672
-
if ((readl(_IBMR(i2c)) & 2) == 2)
599
+
if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
673
600
break;
674
601
675
602
timeout--;
···
764
691
timeout = 0x10000;
765
692
766
693
while (1) {
767
-
if ((readl(_IBMR(i2c)) & 2) == 2)
694
+
if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
768
695
break;
769
696
770
697
timeout--;
···
789
716
* PXA I2C Master mode
790
717
*/
791
718
792
-
static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
793
-
{
794
-
unsigned int addr = (msg->addr & 0x7f) << 1;
795
-
796
-
if (msg->flags & I2C_M_RD)
797
-
addr |= 1;
798
-
799
-
return addr;
800
-
}
801
-
802
719
static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
803
720
{
804
721
u32 icr;
···
796
733
/*
797
734
* Step 1: target slave address into IDBR
798
735
*/
799
-
writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
800
-
i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
736
+
i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
737
+
writel(i2c->req_slave_addr, _IDBR(i2c));
801
738
802
739
/*
803
740
* Step 2: initiate the write.
···
810
747
{
811
748
u32 icr;
812
749
813
-
/*
814
-
* Clear the STOP and ACK flags
815
-
*/
750
+
/* Clear the START, STOP, ACK, TB and MA flags */
816
751
icr = readl(_ICR(i2c));
817
-
icr &= ~(ICR_STOP | ICR_ACKNAK);
752
+
icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
818
753
writel(icr, _ICR(i2c));
819
-
}
820
-
821
-
static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
822
-
{
823
-
/* make timeout the same as for interrupt based functions */
824
-
long timeout = 2 * DEF_TIMEOUT;
825
-
826
-
/*
827
-
* Wait for the bus to become free.
828
-
*/
829
-
while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
830
-
udelay(1000);
831
-
show_state(i2c);
832
-
}
833
-
834
-
if (timeout < 0) {
835
-
show_state(i2c);
836
-
dev_err(&i2c->adap.dev,
837
-
"i2c_pxa: timeout waiting for bus free\n");
838
-
return I2C_RETRY;
839
-
}
840
-
841
-
/*
842
-
* Set master mode.
843
-
*/
844
-
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
845
-
846
-
return 0;
847
754
}
848
755
849
756
/*
···
842
809
i2c->highmode_enter = false;
843
810
844
811
return (timeout == 0) ? I2C_RETRY : 0;
845
-
}
846
-
847
-
static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
848
-
struct i2c_msg *msg, int num)
849
-
{
850
-
unsigned long timeout = 500000; /* 5 seconds */
851
-
int ret = 0;
852
-
853
-
ret = i2c_pxa_pio_set_master(i2c);
854
-
if (ret)
855
-
goto out;
856
-
857
-
i2c->msg = msg;
858
-
i2c->msg_num = num;
859
-
i2c->msg_idx = 0;
860
-
i2c->msg_ptr = 0;
861
-
i2c->irqlogidx = 0;
862
-
863
-
i2c_pxa_start_message(i2c);
864
-
865
-
while (i2c->msg_num > 0 && --timeout) {
866
-
i2c_pxa_handler(0, i2c);
867
-
udelay(10);
868
-
}
869
-
870
-
i2c_pxa_stop_message(i2c);
871
-
872
-
/*
873
-
* We place the return code in i2c->msg_idx.
874
-
*/
875
-
ret = i2c->msg_idx;
876
-
877
-
out:
878
-
if (timeout == 0) {
879
-
i2c_pxa_scream_blue_murder(i2c, "timeout");
880
-
ret = I2C_RETRY;
881
-
}
882
-
883
-
return ret;
884
-
}
885
-
886
-
/*
887
-
* We are protected by the adapter bus mutex.
888
-
*/
889
-
static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
890
-
{
891
-
long timeout;
892
-
int ret;
893
-
894
-
/*
895
-
* Wait for the bus to become free.
896
-
*/
897
-
ret = i2c_pxa_wait_bus_not_busy(i2c);
898
-
if (ret) {
899
-
dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
900
-
goto out;
901
-
}
902
-
903
-
/*
904
-
* Set master mode.
905
-
*/
906
-
ret = i2c_pxa_set_master(i2c);
907
-
if (ret) {
908
-
dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
909
-
goto out;
910
-
}
911
-
912
-
if (i2c->high_mode) {
913
-
ret = i2c_pxa_send_mastercode(i2c);
914
-
if (ret) {
915
-
dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
916
-
goto out;
917
-
}
918
-
}
919
-
920
-
spin_lock_irq(&i2c->lock);
921
-
922
-
i2c->msg = msg;
923
-
i2c->msg_num = num;
924
-
i2c->msg_idx = 0;
925
-
i2c->msg_ptr = 0;
926
-
i2c->irqlogidx = 0;
927
-
928
-
i2c_pxa_start_message(i2c);
929
-
930
-
spin_unlock_irq(&i2c->lock);
931
-
932
-
/*
933
-
* The rest of the processing occurs in the interrupt handler.
934
-
*/
935
-
timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
936
-
i2c_pxa_stop_message(i2c);
937
-
938
-
/*
939
-
* We place the return code in i2c->msg_idx.
940
-
*/
941
-
ret = i2c->msg_idx;
942
-
943
-
if (!timeout && i2c->msg_num) {
944
-
i2c_pxa_scream_blue_murder(i2c, "timeout");
945
-
ret = I2C_RETRY;
946
-
}
947
-
948
-
out:
949
-
return ret;
950
-
}
951
-
952
-
static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
953
-
struct i2c_msg msgs[], int num)
954
-
{
955
-
struct pxa_i2c *i2c = adap->algo_data;
956
-
int ret, i;
957
-
958
-
/* If the I2C controller is disabled we need to reset it
959
-
(probably due to a suspend/resume destroying state). We do
960
-
this here as we can then avoid worrying about resuming the
961
-
controller before its users. */
962
-
if (!(readl(_ICR(i2c)) & ICR_IUE))
963
-
i2c_pxa_reset(i2c);
964
-
965
-
for (i = adap->retries; i >= 0; i--) {
966
-
ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
967
-
if (ret != I2C_RETRY)
968
-
goto out;
969
-
970
-
if (i2c_debug)
971
-
dev_dbg(&adap->dev, "Retrying transmission\n");
972
-
udelay(100);
973
-
}
974
-
i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
975
-
ret = -EREMOTEIO;
976
-
out:
977
-
i2c_pxa_set_slave(i2c, ret);
978
-
return ret;
979
812
}
980
813
981
814
/*
···
895
996
*/
896
997
if (isr & ISR_ACKNAK) {
897
998
if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
898
-
ret = I2C_RETRY;
999
+
ret = NO_SLAVE;
899
1000
else
900
1001
ret = XFER_NAKED;
901
1002
}
···
946
1047
/*
947
1048
* Write the next address.
948
1049
*/
949
-
writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
950
-
i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
1050
+
i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
1051
+
writel(i2c->req_slave_addr, _IDBR(i2c));
951
1052
952
1053
/*
953
1054
* And trigger a repeated start, and send the byte.
···
955
1056
icr &= ~ICR_ALDIE;
956
1057
icr |= ICR_START | ICR_TB;
957
1058
} else {
958
-
if (i2c->msg->len == 0) {
959
-
/*
960
-
* Device probes have a message length of zero
961
-
* and need the bus to be reset before it can
962
-
* be used again.
963
-
*/
964
-
i2c_pxa_reset(i2c);
965
-
}
1059
+
if (i2c->msg->len == 0)
1060
+
icr |= ICR_MA;
966
1061
i2c_pxa_master_complete(i2c, 0);
967
1062
}
968
1063
···
1044
1151
return IRQ_HANDLED;
1045
1152
}
1046
1153
1047
-
1048
-
static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1154
+
/*
1155
+
* We are protected by the adapter bus mutex.
1156
+
*/
1157
+
static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1049
1158
{
1050
-
struct pxa_i2c *i2c = adap->algo_data;
1159
+
long timeout;
1160
+
int ret;
1161
+
1162
+
/*
1163
+
* Wait for the bus to become free.
1164
+
*/
1165
+
ret = i2c_pxa_wait_bus_not_busy(i2c);
1166
+
if (ret) {
1167
+
dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1168
+
i2c_recover_bus(&i2c->adap);
1169
+
goto out;
1170
+
}
1171
+
1172
+
/*
1173
+
* Set master mode.
1174
+
*/
1175
+
ret = i2c_pxa_set_master(i2c);
1176
+
if (ret) {
1177
+
dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1178
+
goto out;
1179
+
}
1180
+
1181
+
if (i2c->high_mode) {
1182
+
ret = i2c_pxa_send_mastercode(i2c);
1183
+
if (ret) {
1184
+
dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1185
+
goto out;
1186
+
}
1187
+
}
1188
+
1189
+
spin_lock_irq(&i2c->lock);
1190
+
1191
+
i2c->msg = msg;
1192
+
i2c->msg_num = num;
1193
+
i2c->msg_idx = 0;
1194
+
i2c->msg_ptr = 0;
1195
+
i2c->irqlogidx = 0;
1196
+
1197
+
i2c_pxa_start_message(i2c);
1198
+
1199
+
spin_unlock_irq(&i2c->lock);
1200
+
1201
+
/*
1202
+
* The rest of the processing occurs in the interrupt handler.
1203
+
*/
1204
+
timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1205
+
i2c_pxa_stop_message(i2c);
1206
+
1207
+
/*
1208
+
* We place the return code in i2c->msg_idx.
1209
+
*/
1210
+
ret = i2c->msg_idx;
1211
+
1212
+
if (!timeout && i2c->msg_num) {
1213
+
i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1214
+
i2c_recover_bus(&i2c->adap);
1215
+
ret = I2C_RETRY;
1216
+
}
1217
+
1218
+
out:
1219
+
return ret;
1220
+
}
1221
+
1222
+
static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1223
+
struct i2c_msg *msgs, int num,
1224
+
int (*xfer)(struct pxa_i2c *,
1225
+
struct i2c_msg *, int num))
1226
+
{
1051
1227
int ret, i;
1052
1228
1053
-
for (i = adap->retries; i >= 0; i--) {
1054
-
ret = i2c_pxa_do_xfer(i2c, msgs, num);
1055
-
if (ret != I2C_RETRY)
1229
+
for (i = 0; ; ) {
1230
+
ret = xfer(i2c, msgs, num);
1231
+
if (ret != I2C_RETRY && ret != NO_SLAVE)
1056
1232
goto out;
1233
+
if (++i >= i2c->adap.retries)
1234
+
break;
1057
1235
1058
1236
if (i2c_debug)
1059
-
dev_dbg(&adap->dev, "Retrying transmission\n");
1237
+
dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1060
1238
udelay(100);
1061
1239
}
1062
-
i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1240
+
if (ret != NO_SLAVE)
1241
+
i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1063
1242
ret = -EREMOTEIO;
1064
1243
out:
1065
1244
i2c_pxa_set_slave(i2c, ret);
1066
1245
return ret;
1246
+
}
1247
+
1248
+
static int i2c_pxa_xfer(struct i2c_adapter *adap,
1249
+
struct i2c_msg msgs[], int num)
1250
+
{
1251
+
struct pxa_i2c *i2c = adap->algo_data;
1252
+
1253
+
return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1067
1254
}
1068
1255
1069
1256
static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
···
1161
1188
#endif
1162
1189
};
1163
1190
1191
+
/* Non-interrupt mode support */
1192
+
static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1193
+
{
1194
+
/* make timeout the same as for interrupt based functions */
1195
+
long timeout = 2 * DEF_TIMEOUT;
1196
+
1197
+
/*
1198
+
* Wait for the bus to become free.
1199
+
*/
1200
+
while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1201
+
udelay(1000);
1202
+
1203
+
if (timeout < 0) {
1204
+
show_state(i2c);
1205
+
dev_err(&i2c->adap.dev,
1206
+
"i2c_pxa: timeout waiting for bus free (set_master)\n");
1207
+
return I2C_RETRY;
1208
+
}
1209
+
1210
+
/*
1211
+
* Set master mode.
1212
+
*/
1213
+
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1214
+
1215
+
return 0;
1216
+
}
1217
+
1218
+
static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1219
+
struct i2c_msg *msg, int num)
1220
+
{
1221
+
unsigned long timeout = 500000; /* 5 seconds */
1222
+
int ret = 0;
1223
+
1224
+
ret = i2c_pxa_pio_set_master(i2c);
1225
+
if (ret)
1226
+
goto out;
1227
+
1228
+
i2c->msg = msg;
1229
+
i2c->msg_num = num;
1230
+
i2c->msg_idx = 0;
1231
+
i2c->msg_ptr = 0;
1232
+
i2c->irqlogidx = 0;
1233
+
1234
+
i2c_pxa_start_message(i2c);
1235
+
1236
+
while (i2c->msg_num > 0 && --timeout) {
1237
+
i2c_pxa_handler(0, i2c);
1238
+
udelay(10);
1239
+
}
1240
+
1241
+
i2c_pxa_stop_message(i2c);
1242
+
1243
+
/*
1244
+
* We place the return code in i2c->msg_idx.
1245
+
*/
1246
+
ret = i2c->msg_idx;
1247
+
1248
+
out:
1249
+
if (timeout == 0) {
1250
+
i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1251
+
ret = I2C_RETRY;
1252
+
}
1253
+
1254
+
return ret;
1255
+
}
1256
+
1257
+
static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1258
+
struct i2c_msg msgs[], int num)
1259
+
{
1260
+
struct pxa_i2c *i2c = adap->algo_data;
1261
+
1262
+
/* If the I2C controller is disabled we need to reset it
1263
+
(probably due to a suspend/resume destroying state). We do
1264
+
this here as we can then avoid worrying about resuming the
1265
+
controller before its users. */
1266
+
if (!(readl(_ICR(i2c)) & ICR_IUE))
1267
+
i2c_pxa_reset(i2c);
1268
+
1269
+
return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1270
+
}
1271
+
1164
1272
static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1165
1273
.master_xfer = i2c_pxa_pio_xfer,
1166
1274
.functionality = i2c_pxa_functionality,
···
1250
1196
.unreg_slave = i2c_pxa_slave_unreg,
1251
1197
#endif
1252
1198
};
1253
-
1254
-
static const struct of_device_id i2c_pxa_dt_ids[] = {
1255
-
{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1256
-
{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1257
-
{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
1258
-
{ .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
1259
-
{}
1260
-
};
1261
-
MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1262
1199
1263
1200
static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1264
1201
enum pxa_i2c_types *i2c_types)
···
1294
1249
return 0;
1295
1250
}
1296
1251
1252
+
static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1253
+
{
1254
+
struct pxa_i2c *i2c = adap->algo_data;
1255
+
u32 ibmr = readl(_IBMR(i2c));
1256
+
1257
+
/*
1258
+
* Program the GPIOs to reflect the current I2C bus state while
1259
+
* we transition to recovery; this avoids glitching the bus.
1260
+
*/
1261
+
gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1262
+
gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1263
+
1264
+
WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
1265
+
}
1266
+
1267
+
static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1268
+
{
1269
+
struct pxa_i2c *i2c = adap->algo_data;
1270
+
u32 isr;
1271
+
1272
+
/*
1273
+
* The bus should now be free. Clear up the I2C controller before
1274
+
* handing control of the bus back to avoid the bus changing state.
1275
+
*/
1276
+
isr = readl(_ISR(i2c));
1277
+
if (isr & (ISR_UB | ISR_IBB)) {
1278
+
dev_dbg(&i2c->adap.dev,
1279
+
"recovery: resetting controller, ISR=0x%08x\n", isr);
1280
+
i2c_pxa_do_reset(i2c);
1281
+
}
1282
+
1283
+
WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
1284
+
1285
+
dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1286
+
readl(_IBMR(i2c)), readl(_ISR(i2c)));
1287
+
1288
+
i2c_pxa_enable(i2c);
1289
+
}
1290
+
1291
+
static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1292
+
{
1293
+
struct i2c_bus_recovery_info *bri = &i2c->recovery;
1294
+
struct device *dev = i2c->adap.dev.parent;
1295
+
1296
+
/*
1297
+
* When slave mode is enabled, we are not the only master on the bus.
1298
+
* Bus recovery can only be performed when we are the master, which
1299
+
* we can't be certain of. Therefore, when slave mode is enabled, do
1300
+
* not configure bus recovery.
1301
+
*/
1302
+
if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1303
+
return 0;
1304
+
1305
+
i2c->pinctrl = devm_pinctrl_get(dev);
1306
+
if (PTR_ERR(i2c->pinctrl) == -ENODEV)
1307
+
i2c->pinctrl = NULL;
1308
+
if (IS_ERR(i2c->pinctrl))
1309
+
return PTR_ERR(i2c->pinctrl);
1310
+
1311
+
if (!i2c->pinctrl)
1312
+
return 0;
1313
+
1314
+
i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
1315
+
PINCTRL_STATE_DEFAULT);
1316
+
i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
1317
+
1318
+
if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
1319
+
dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
1320
+
PTR_ERR(i2c->pinctrl_default),
1321
+
PTR_ERR(i2c->pinctrl_recovery));
1322
+
return 0;
1323
+
}
1324
+
1325
+
/*
1326
+
* Claiming GPIOs can influence the pinmux state, and may glitch the
1327
+
* I2C bus. Do this carefully.
1328
+
*/
1329
+
bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1330
+
if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
1331
+
return -EPROBE_DEFER;
1332
+
if (IS_ERR(bri->scl_gpiod)) {
1333
+
dev_info(dev, "missing scl gpio recovery information: %pe\n",
1334
+
bri->scl_gpiod);
1335
+
return 0;
1336
+
}
1337
+
1338
+
/*
1339
+
* We have SCL. Pull SCL low and wait a bit so that SDA glitches
1340
+
* have no effect.
1341
+
*/
1342
+
gpiod_direction_output(bri->scl_gpiod, 0);
1343
+
udelay(10);
1344
+
bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
1345
+
1346
+
/* Wait a bit in case of a SDA glitch, and then release SCL. */
1347
+
udelay(10);
1348
+
gpiod_direction_output(bri->scl_gpiod, 1);
1349
+
1350
+
if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
1351
+
return -EPROBE_DEFER;
1352
+
1353
+
if (IS_ERR(bri->sda_gpiod)) {
1354
+
dev_info(dev, "missing sda gpio recovery information: %pe\n",
1355
+
bri->sda_gpiod);
1356
+
return 0;
1357
+
}
1358
+
1359
+
bri->prepare_recovery = i2c_pxa_prepare_recovery;
1360
+
bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1361
+
bri->recover_bus = i2c_generic_scl_recovery;
1362
+
1363
+
i2c->adap.bus_recovery_info = bri;
1364
+
1365
+
/*
1366
+
* Claiming GPIOs can change the pinmux state, which confuses the
1367
+
* pinctrl since pinctrl's idea of the current setting is unaffected
1368
+
* by the pinmux change caused by claiming the GPIO. Work around that
1369
+
* by switching pinctrl to the GPIO state here. We do it this way to
1370
+
* avoid glitching the I2C bus.
1371
+
*/
1372
+
pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
1373
+
1374
+
return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
1375
+
}
1376
+
1297
1377
static int i2c_pxa_probe(struct platform_device *dev)
1298
1378
{
1299
1379
struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
···
1431
1261
if (!i2c)
1432
1262
return -ENOMEM;
1433
1263
1264
+
/* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1265
+
i2c->adap.nr = dev->id;
1266
+
i2c->adap.owner = THIS_MODULE;
1267
+
i2c->adap.retries = 5;
1268
+
i2c->adap.algo_data = i2c;
1269
+
i2c->adap.dev.parent = &dev->dev;
1270
+
#ifdef CONFIG_OF
1271
+
i2c->adap.dev.of_node = dev->dev.of_node;
1272
+
#endif
1273
+
1434
1274
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1435
1275
i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1436
1276
if (IS_ERR(i2c->reg_base))
1437
1277
return PTR_ERR(i2c->reg_base);
1438
1278
1439
1279
irq = platform_get_irq(dev, 0);
1440
-
if (irq < 0) {
1441
-
dev_err(&dev->dev, "no irq resource: %d\n", irq);
1280
+
if (irq < 0)
1442
1281
return irq;
1443
-
}
1444
1282
1445
-
/* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1446
-
i2c->adap.nr = dev->id;
1283
+
ret = i2c_pxa_init_recovery(i2c);
1284
+
if (ret)
1285
+
return ret;
1447
1286
1448
1287
ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1449
1288
if (ret > 0)
1450
1289
ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1451
1290
if (ret < 0)
1452
1291
return ret;
1453
-
1454
-
i2c->adap.owner = THIS_MODULE;
1455
-
i2c->adap.retries = 5;
1456
1292
1457
1293
spin_lock_init(&i2c->lock);
1458
1294
init_waitqueue_head(&i2c->wait);
···
1475
1299
i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1476
1300
i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1477
1301
i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1478
-
i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM;
1479
-
i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS;
1302
+
i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1303
+
i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1480
1304
1481
1305
if (i2c_type != REGS_CE4100)
1482
1306
i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
···
1524
1348
}
1525
1349
1526
1350
i2c_pxa_reset(i2c);
1527
-
1528
-
i2c->adap.algo_data = i2c;
1529
-
i2c->adap.dev.parent = &dev->dev;
1530
-
#ifdef CONFIG_OF
1531
-
i2c->adap.dev.of_node = dev->dev.of_node;
1532
-
#endif
1533
1351
1534
1352
ret = i2c_add_numbered_adapter(&i2c->adap);
1535
1353
if (ret < 0)
+791
drivers/i2c/busses/i2c-qcom-cci.c
+791
drivers/i2c/busses/i2c-qcom-cci.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
// Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
3
+
// Copyright (c) 2017-20 Linaro Limited.
4
+
5
+
#include <linux/clk.h>
6
+
#include <linux/completion.h>
7
+
#include <linux/i2c.h>
8
+
#include <linux/io.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/pm_runtime.h>
14
+
15
+
#define CCI_HW_VERSION 0x0
16
+
#define CCI_RESET_CMD 0x004
17
+
#define CCI_RESET_CMD_MASK 0x0f73f3f7
18
+
#define CCI_RESET_CMD_M0_MASK 0x000003f1
19
+
#define CCI_RESET_CMD_M1_MASK 0x0003f001
20
+
#define CCI_QUEUE_START 0x008
21
+
#define CCI_HALT_REQ 0x034
22
+
#define CCI_HALT_REQ_I2C_M0_Q0Q1 BIT(0)
23
+
#define CCI_HALT_REQ_I2C_M1_Q0Q1 BIT(1)
24
+
25
+
#define CCI_I2C_Mm_SCL_CTL(m) (0x100 + 0x100 * (m))
26
+
#define CCI_I2C_Mm_SDA_CTL_0(m) (0x104 + 0x100 * (m))
27
+
#define CCI_I2C_Mm_SDA_CTL_1(m) (0x108 + 0x100 * (m))
28
+
#define CCI_I2C_Mm_SDA_CTL_2(m) (0x10c + 0x100 * (m))
29
+
#define CCI_I2C_Mm_MISC_CTL(m) (0x110 + 0x100 * (m))
30
+
31
+
#define CCI_I2C_Mm_READ_DATA(m) (0x118 + 0x100 * (m))
32
+
#define CCI_I2C_Mm_READ_BUF_LEVEL(m) (0x11c + 0x100 * (m))
33
+
#define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n) (0x300 + 0x200 * (m) + 0x100 * (n))
34
+
#define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n) (0x304 + 0x200 * (m) + 0x100 * (n))
35
+
#define CCI_I2C_Mm_Qn_CUR_CMD(m, n) (0x308 + 0x200 * (m) + 0x100 * (n))
36
+
#define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n) (0x30c + 0x200 * (m) + 0x100 * (n))
37
+
#define CCI_I2C_Mm_Qn_LOAD_DATA(m, n) (0x310 + 0x200 * (m) + 0x100 * (n))
38
+
39
+
#define CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00
40
+
#define CCI_IRQ_MASK_0 0xc04
41
+
#define CCI_IRQ_MASK_0_I2C_M0_RD_DONE BIT(0)
42
+
#define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT BIT(4)
43
+
#define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT BIT(8)
44
+
#define CCI_IRQ_MASK_0_I2C_M1_RD_DONE BIT(12)
45
+
#define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT BIT(16)
46
+
#define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT BIT(20)
47
+
#define CCI_IRQ_MASK_0_RST_DONE_ACK BIT(24)
48
+
#define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
49
+
#define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
50
+
#define CCI_IRQ_MASK_0_I2C_M0_ERROR 0x18000ee6
51
+
#define CCI_IRQ_MASK_0_I2C_M1_ERROR 0x60ee6000
52
+
#define CCI_IRQ_CLEAR_0 0xc08
53
+
#define CCI_IRQ_STATUS_0 0xc0c
54
+
#define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0)
55
+
#define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4)
56
+
#define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8)
57
+
#define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12)
58
+
#define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16)
59
+
#define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20)
60
+
#define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24)
61
+
#define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
62
+
#define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
63
+
#define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR BIT(27)
64
+
#define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR BIT(28)
65
+
#define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR BIT(29)
66
+
#define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR BIT(30)
67
+
#define CCI_IRQ_STATUS_0_I2C_M0_ERROR 0x18000ee6
68
+
#define CCI_IRQ_STATUS_0_I2C_M1_ERROR 0x60ee6000
69
+
70
+
#define CCI_TIMEOUT (msecs_to_jiffies(100))
71
+
#define NUM_MASTERS 2
72
+
#define NUM_QUEUES 2
73
+
74
+
/* Max number of resources + 1 for a NULL terminator */
75
+
#define CCI_RES_MAX 6
76
+
77
+
#define CCI_I2C_SET_PARAM 1
78
+
#define CCI_I2C_REPORT 8
79
+
#define CCI_I2C_WRITE 9
80
+
#define CCI_I2C_READ 10
81
+
82
+
#define CCI_I2C_REPORT_IRQ_EN BIT(8)
83
+
84
+
enum {
85
+
I2C_MODE_STANDARD,
86
+
I2C_MODE_FAST,
87
+
I2C_MODE_FAST_PLUS,
88
+
};
89
+
90
+
enum cci_i2c_queue_t {
91
+
QUEUE_0,
92
+
QUEUE_1
93
+
};
94
+
95
+
struct hw_params {
96
+
u16 thigh; /* HIGH period of the SCL clock in clock ticks */
97
+
u16 tlow; /* LOW period of the SCL clock */
98
+
u16 tsu_sto; /* set-up time for STOP condition */
99
+
u16 tsu_sta; /* set-up time for a repeated START condition */
100
+
u16 thd_dat; /* data hold time */
101
+
u16 thd_sta; /* hold time (repeated) START condition */
102
+
u16 tbuf; /* bus free time between a STOP and START condition */
103
+
u8 scl_stretch_en;
104
+
u16 trdhld;
105
+
u16 tsp; /* pulse width of spikes suppressed by the input filter */
106
+
};
107
+
108
+
struct cci;
109
+
110
+
struct cci_master {
111
+
struct i2c_adapter adap;
112
+
u16 master;
113
+
u8 mode;
114
+
int status;
115
+
struct completion irq_complete;
116
+
struct cci *cci;
117
+
};
118
+
119
+
struct cci_data {
120
+
unsigned int num_masters;
121
+
struct i2c_adapter_quirks quirks;
122
+
u16 queue_size[NUM_QUEUES];
123
+
unsigned long cci_clk_rate;
124
+
struct hw_params params[3];
125
+
};
126
+
127
+
struct cci {
128
+
struct device *dev;
129
+
void __iomem *base;
130
+
unsigned int irq;
131
+
const struct cci_data *data;
132
+
struct clk_bulk_data *clocks;
133
+
int nclocks;
134
+
struct cci_master master[NUM_MASTERS];
135
+
};
136
+
137
+
static irqreturn_t cci_isr(int irq, void *dev)
138
+
{
139
+
struct cci *cci = dev;
140
+
u32 val, reset = 0;
141
+
int ret = IRQ_NONE;
142
+
143
+
val = readl(cci->base + CCI_IRQ_STATUS_0);
144
+
writel(val, cci->base + CCI_IRQ_CLEAR_0);
145
+
writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
146
+
147
+
if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
148
+
complete(&cci->master[0].irq_complete);
149
+
if (cci->master[1].master)
150
+
complete(&cci->master[1].irq_complete);
151
+
ret = IRQ_HANDLED;
152
+
}
153
+
154
+
if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
155
+
val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
156
+
val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
157
+
cci->master[0].status = 0;
158
+
complete(&cci->master[0].irq_complete);
159
+
ret = IRQ_HANDLED;
160
+
}
161
+
162
+
if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
163
+
val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
164
+
val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
165
+
cci->master[1].status = 0;
166
+
complete(&cci->master[1].irq_complete);
167
+
ret = IRQ_HANDLED;
168
+
}
169
+
170
+
if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
171
+
reset = CCI_RESET_CMD_M0_MASK;
172
+
ret = IRQ_HANDLED;
173
+
}
174
+
175
+
if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
176
+
reset = CCI_RESET_CMD_M1_MASK;
177
+
ret = IRQ_HANDLED;
178
+
}
179
+
180
+
if (unlikely(reset))
181
+
writel(reset, cci->base + CCI_RESET_CMD);
182
+
183
+
if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
184
+
if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR ||
185
+
val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR)
186
+
cci->master[0].status = -ENXIO;
187
+
else
188
+
cci->master[0].status = -EIO;
189
+
190
+
writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
191
+
ret = IRQ_HANDLED;
192
+
}
193
+
194
+
if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
195
+
if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR ||
196
+
val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR)
197
+
cci->master[0].status = -ENXIO;
198
+
else
199
+
cci->master[0].status = -EIO;
200
+
201
+
writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
202
+
ret = IRQ_HANDLED;
203
+
}
204
+
205
+
return ret;
206
+
}
207
+
208
+
static int cci_halt(struct cci *cci, u8 master_num)
209
+
{
210
+
struct cci_master *master;
211
+
u32 val;
212
+
213
+
if (master_num >= cci->data->num_masters) {
214
+
dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
215
+
return -EINVAL;
216
+
}
217
+
218
+
val = BIT(master_num);
219
+
master = &cci->master[master_num];
220
+
221
+
reinit_completion(&master->irq_complete);
222
+
writel(val, cci->base + CCI_HALT_REQ);
223
+
224
+
if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) {
225
+
dev_err(cci->dev, "CCI halt timeout\n");
226
+
return -ETIMEDOUT;
227
+
}
228
+
229
+
return 0;
230
+
}
231
+
232
+
static int cci_reset(struct cci *cci)
233
+
{
234
+
/*
235
+
* we reset the whole controller, here and for implicity use
236
+
* master[0].xxx for waiting on it.
237
+
*/
238
+
reinit_completion(&cci->master[0].irq_complete);
239
+
writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
240
+
241
+
if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
242
+
CCI_TIMEOUT)) {
243
+
dev_err(cci->dev, "CCI reset timeout\n");
244
+
return -ETIMEDOUT;
245
+
}
246
+
247
+
return 0;
248
+
}
249
+
250
+
static int cci_init(struct cci *cci)
251
+
{
252
+
u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE |
253
+
CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT |
254
+
CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT |
255
+
CCI_IRQ_MASK_0_I2C_M1_RD_DONE |
256
+
CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT |
257
+
CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT |
258
+
CCI_IRQ_MASK_0_RST_DONE_ACK |
259
+
CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK |
260
+
CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK |
261
+
CCI_IRQ_MASK_0_I2C_M0_ERROR |
262
+
CCI_IRQ_MASK_0_I2C_M1_ERROR;
263
+
int i;
264
+
265
+
writel(val, cci->base + CCI_IRQ_MASK_0);
266
+
267
+
for (i = 0; i < cci->data->num_masters; i++) {
268
+
int mode = cci->master[i].mode;
269
+
const struct hw_params *hw;
270
+
271
+
if (!cci->master[i].cci)
272
+
continue;
273
+
274
+
hw = &cci->data->params[mode];
275
+
276
+
val = hw->thigh << 16 | hw->tlow;
277
+
writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
278
+
279
+
val = hw->tsu_sto << 16 | hw->tsu_sta;
280
+
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
281
+
282
+
val = hw->thd_dat << 16 | hw->thd_sta;
283
+
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
284
+
285
+
val = hw->tbuf;
286
+
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
287
+
288
+
val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp;
289
+
writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
290
+
}
291
+
292
+
return 0;
293
+
}
294
+
295
+
static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
296
+
{
297
+
u32 val;
298
+
299
+
val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
300
+
writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
301
+
302
+
reinit_completion(&cci->master[master].irq_complete);
303
+
val = BIT(master * 2 + queue);
304
+
writel(val, cci->base + CCI_QUEUE_START);
305
+
306
+
if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
307
+
CCI_TIMEOUT)) {
308
+
dev_err(cci->dev, "master %d queue %d timeout\n",
309
+
master, queue);
310
+
cci_reset(cci);
311
+
cci_init(cci);
312
+
return -ETIMEDOUT;
313
+
}
314
+
315
+
return cci->master[master].status;
316
+
}
317
+
318
+
static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
319
+
{
320
+
u32 val;
321
+
322
+
val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
323
+
if (val == cci->data->queue_size[queue])
324
+
return -EINVAL;
325
+
326
+
if (!val)
327
+
return 0;
328
+
329
+
val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
330
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
331
+
332
+
return cci_run_queue(cci, master, queue);
333
+
}
334
+
335
+
static int cci_i2c_read(struct cci *cci, u16 master,
336
+
u16 addr, u8 *buf, u16 len)
337
+
{
338
+
u32 val, words_read, words_exp;
339
+
u8 queue = QUEUE_1;
340
+
int i, index = 0, ret;
341
+
bool first = true;
342
+
343
+
/*
344
+
* Call validate queue to make sure queue is empty before starting.
345
+
* This is to avoid overflow / underflow of queue.
346
+
*/
347
+
ret = cci_validate_queue(cci, master, queue);
348
+
if (ret < 0)
349
+
return ret;
350
+
351
+
val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
352
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
353
+
354
+
val = CCI_I2C_READ | len << 4;
355
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
356
+
357
+
ret = cci_run_queue(cci, master, queue);
358
+
if (ret < 0)
359
+
return ret;
360
+
361
+
words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
362
+
words_exp = len / 4 + 1;
363
+
if (words_read != words_exp) {
364
+
dev_err(cci->dev, "words read = %d, words expected = %d\n",
365
+
words_read, words_exp);
366
+
return -EIO;
367
+
}
368
+
369
+
do {
370
+
val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
371
+
372
+
for (i = 0; i < 4 && index < len; i++) {
373
+
if (first) {
374
+
/* The LS byte of this register represents the
375
+
* first byte read from the slave during a read
376
+
* access.
377
+
*/
378
+
first = false;
379
+
continue;
380
+
}
381
+
buf[index++] = (val >> (i * 8)) & 0xff;
382
+
}
383
+
} while (--words_read);
384
+
385
+
return 0;
386
+
}
387
+
388
+
static int cci_i2c_write(struct cci *cci, u16 master,
389
+
u16 addr, u8 *buf, u16 len)
390
+
{
391
+
u8 queue = QUEUE_0;
392
+
u8 load[12] = { 0 };
393
+
int i = 0, j, ret;
394
+
u32 val;
395
+
396
+
/*
397
+
* Call validate queue to make sure queue is empty before starting.
398
+
* This is to avoid overflow / underflow of queue.
399
+
*/
400
+
ret = cci_validate_queue(cci, master, queue);
401
+
if (ret < 0)
402
+
return ret;
403
+
404
+
val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
405
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
406
+
407
+
load[i++] = CCI_I2C_WRITE | len << 4;
408
+
409
+
for (j = 0; j < len; j++)
410
+
load[i++] = buf[j];
411
+
412
+
for (j = 0; j < i; j += 4) {
413
+
val = load[j];
414
+
val |= load[j + 1] << 8;
415
+
val |= load[j + 2] << 16;
416
+
val |= load[j + 3] << 24;
417
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
418
+
}
419
+
420
+
val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
421
+
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
422
+
423
+
return cci_run_queue(cci, master, queue);
424
+
}
425
+
426
+
static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
427
+
{
428
+
struct cci_master *cci_master = i2c_get_adapdata(adap);
429
+
struct cci *cci = cci_master->cci;
430
+
int i, ret;
431
+
432
+
ret = pm_runtime_get_sync(cci->dev);
433
+
if (ret < 0)
434
+
goto err;
435
+
436
+
for (i = 0; i < num; i++) {
437
+
if (msgs[i].flags & I2C_M_RD)
438
+
ret = cci_i2c_read(cci, cci_master->master,
439
+
msgs[i].addr, msgs[i].buf,
440
+
msgs[i].len);
441
+
else
442
+
ret = cci_i2c_write(cci, cci_master->master,
443
+
msgs[i].addr, msgs[i].buf,
444
+
msgs[i].len);
445
+
446
+
if (ret < 0)
447
+
break;
448
+
}
449
+
450
+
if (!ret)
451
+
ret = num;
452
+
453
+
err:
454
+
pm_runtime_mark_last_busy(cci->dev);
455
+
pm_runtime_put_autosuspend(cci->dev);
456
+
457
+
return ret;
458
+
}
459
+
460
+
static u32 cci_func(struct i2c_adapter *adap)
461
+
{
462
+
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
463
+
}
464
+
465
+
static const struct i2c_algorithm cci_algo = {
466
+
.master_xfer = cci_xfer,
467
+
.functionality = cci_func,
468
+
};
469
+
470
+
static int cci_enable_clocks(struct cci *cci)
471
+
{
472
+
return clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
473
+
}
474
+
475
+
static void cci_disable_clocks(struct cci *cci)
476
+
{
477
+
clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
478
+
}
479
+
480
+
static int __maybe_unused cci_suspend_runtime(struct device *dev)
481
+
{
482
+
struct cci *cci = dev_get_drvdata(dev);
483
+
484
+
cci_disable_clocks(cci);
485
+
return 0;
486
+
}
487
+
488
+
static int __maybe_unused cci_resume_runtime(struct device *dev)
489
+
{
490
+
struct cci *cci = dev_get_drvdata(dev);
491
+
int ret;
492
+
493
+
ret = cci_enable_clocks(cci);
494
+
if (ret)
495
+
return ret;
496
+
497
+
cci_init(cci);
498
+
return 0;
499
+
}
500
+
501
+
static int __maybe_unused cci_suspend(struct device *dev)
502
+
{
503
+
if (!pm_runtime_suspended(dev))
504
+
return cci_suspend_runtime(dev);
505
+
506
+
return 0;
507
+
}
508
+
509
+
static int __maybe_unused cci_resume(struct device *dev)
510
+
{
511
+
cci_resume_runtime(dev);
512
+
pm_runtime_mark_last_busy(dev);
513
+
pm_request_autosuspend(dev);
514
+
515
+
return 0;
516
+
}
517
+
518
+
static const struct dev_pm_ops qcom_cci_pm = {
519
+
SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume)
520
+
SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL)
521
+
};
522
+
523
+
static int cci_probe(struct platform_device *pdev)
524
+
{
525
+
struct device *dev = &pdev->dev;
526
+
unsigned long cci_clk_rate = 0;
527
+
struct device_node *child;
528
+
struct resource *r;
529
+
struct cci *cci;
530
+
int ret, i;
531
+
u32 val;
532
+
533
+
cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
534
+
if (!cci)
535
+
return -ENOMEM;
536
+
537
+
cci->dev = dev;
538
+
platform_set_drvdata(pdev, cci);
539
+
cci->data = device_get_match_data(dev);
540
+
if (!cci->data)
541
+
return -ENOENT;
542
+
543
+
for_each_available_child_of_node(dev->of_node, child) {
544
+
u32 idx;
545
+
546
+
ret = of_property_read_u32(child, "reg", &idx);
547
+
if (ret) {
548
+
dev_err(dev, "%pOF invalid 'reg' property", child);
549
+
continue;
550
+
}
551
+
552
+
if (idx >= cci->data->num_masters) {
553
+
dev_err(dev, "%pOF invalid 'reg' value: %u (max is %u)",
554
+
child, idx, cci->data->num_masters - 1);
555
+
continue;
556
+
}
557
+
558
+
cci->master[idx].adap.quirks = &cci->data->quirks;
559
+
cci->master[idx].adap.algo = &cci_algo;
560
+
cci->master[idx].adap.dev.parent = dev;
561
+
cci->master[idx].adap.dev.of_node = child;
562
+
cci->master[idx].master = idx;
563
+
cci->master[idx].cci = cci;
564
+
565
+
i2c_set_adapdata(&cci->master[idx].adap, &cci->master[idx]);
566
+
snprintf(cci->master[idx].adap.name,
567
+
sizeof(cci->master[idx].adap.name), "Qualcomm-CCI");
568
+
569
+
cci->master[idx].mode = I2C_MODE_STANDARD;
570
+
ret = of_property_read_u32(child, "clock-frequency", &val);
571
+
if (!ret) {
572
+
if (val == 400000)
573
+
cci->master[idx].mode = I2C_MODE_FAST;
574
+
else if (val == 1000000)
575
+
cci->master[idx].mode = I2C_MODE_FAST_PLUS;
576
+
}
577
+
578
+
init_completion(&cci->master[idx].irq_complete);
579
+
}
580
+
581
+
/* Memory */
582
+
583
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584
+
cci->base = devm_ioremap_resource(dev, r);
585
+
if (IS_ERR(cci->base))
586
+
return PTR_ERR(cci->base);
587
+
588
+
/* Clocks */
589
+
590
+
ret = devm_clk_bulk_get_all(dev, &cci->clocks);
591
+
if (ret < 1) {
592
+
dev_err(dev, "failed to get clocks %d\n", ret);
593
+
return ret;
594
+
}
595
+
cci->nclocks = ret;
596
+
597
+
/* Retrieve CCI clock rate */
598
+
for (i = 0; i < cci->nclocks; i++) {
599
+
if (!strcmp(cci->clocks[i].id, "cci")) {
600
+
cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
601
+
break;
602
+
}
603
+
}
604
+
605
+
if (cci_clk_rate != cci->data->cci_clk_rate) {
606
+
/* cci clock set by the bootloader or via assigned clock rate
607
+
* in DT.
608
+
*/
609
+
dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
610
+
cci_clk_rate, cci->data->cci_clk_rate);
611
+
}
612
+
613
+
ret = cci_enable_clocks(cci);
614
+
if (ret < 0)
615
+
return ret;
616
+
617
+
/* Interrupt */
618
+
619
+
ret = platform_get_irq(pdev, 0);
620
+
if (ret < 0)
621
+
goto disable_clocks;
622
+
cci->irq = ret;
623
+
624
+
ret = devm_request_irq(dev, cci->irq, cci_isr, 0, dev_name(dev), cci);
625
+
if (ret < 0) {
626
+
dev_err(dev, "request_irq failed, ret: %d\n", ret);
627
+
goto disable_clocks;
628
+
}
629
+
630
+
val = readl(cci->base + CCI_HW_VERSION);
631
+
dev_dbg(dev, "CCI HW version = 0x%08x", val);
632
+
633
+
ret = cci_reset(cci);
634
+
if (ret < 0)
635
+
goto error;
636
+
637
+
ret = cci_init(cci);
638
+
if (ret < 0)
639
+
goto error;
640
+
641
+
for (i = 0; i < cci->data->num_masters; i++) {
642
+
if (!cci->master[i].cci)
643
+
continue;
644
+
645
+
ret = i2c_add_adapter(&cci->master[i].adap);
646
+
if (ret < 0)
647
+
goto error_i2c;
648
+
}
649
+
650
+
pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
651
+
pm_runtime_use_autosuspend(dev);
652
+
pm_runtime_set_active(dev);
653
+
pm_runtime_enable(dev);
654
+
655
+
return 0;
656
+
657
+
error_i2c:
658
+
for (; i >= 0; i--) {
659
+
if (cci->master[i].cci)
660
+
i2c_del_adapter(&cci->master[i].adap);
661
+
}
662
+
error:
663
+
disable_irq(cci->irq);
664
+
disable_clocks:
665
+
cci_disable_clocks(cci);
666
+
667
+
return ret;
668
+
}
669
+
670
+
static int cci_remove(struct platform_device *pdev)
671
+
{
672
+
struct cci *cci = platform_get_drvdata(pdev);
673
+
int i;
674
+
675
+
for (i = 0; i < cci->data->num_masters; i++) {
676
+
if (cci->master[i].cci)
677
+
i2c_del_adapter(&cci->master[i].adap);
678
+
cci_halt(cci, i);
679
+
}
680
+
681
+
disable_irq(cci->irq);
682
+
pm_runtime_disable(&pdev->dev);
683
+
pm_runtime_set_suspended(&pdev->dev);
684
+
685
+
return 0;
686
+
}
687
+
688
+
static const struct cci_data cci_v1_data = {
689
+
.num_masters = 1,
690
+
.queue_size = { 64, 16 },
691
+
.quirks = {
692
+
.max_write_len = 10,
693
+
.max_read_len = 12,
694
+
},
695
+
.cci_clk_rate = 19200000,
696
+
.params[I2C_MODE_STANDARD] = {
697
+
.thigh = 78,
698
+
.tlow = 114,
699
+
.tsu_sto = 28,
700
+
.tsu_sta = 28,
701
+
.thd_dat = 10,
702
+
.thd_sta = 77,
703
+
.tbuf = 118,
704
+
.scl_stretch_en = 0,
705
+
.trdhld = 6,
706
+
.tsp = 1
707
+
},
708
+
.params[I2C_MODE_FAST] = {
709
+
.thigh = 20,
710
+
.tlow = 28,
711
+
.tsu_sto = 21,
712
+
.tsu_sta = 21,
713
+
.thd_dat = 13,
714
+
.thd_sta = 18,
715
+
.tbuf = 32,
716
+
.scl_stretch_en = 0,
717
+
.trdhld = 6,
718
+
.tsp = 3
719
+
},
720
+
};
721
+
722
+
static const struct cci_data cci_v2_data = {
723
+
.num_masters = 2,
724
+
.queue_size = { 64, 16 },
725
+
.quirks = {
726
+
.max_write_len = 11,
727
+
.max_read_len = 12,
728
+
},
729
+
.cci_clk_rate = 37500000,
730
+
.params[I2C_MODE_STANDARD] = {
731
+
.thigh = 201,
732
+
.tlow = 174,
733
+
.tsu_sto = 204,
734
+
.tsu_sta = 231,
735
+
.thd_dat = 22,
736
+
.thd_sta = 162,
737
+
.tbuf = 227,
738
+
.scl_stretch_en = 0,
739
+
.trdhld = 6,
740
+
.tsp = 3
741
+
},
742
+
.params[I2C_MODE_FAST] = {
743
+
.thigh = 38,
744
+
.tlow = 56,
745
+
.tsu_sto = 40,
746
+
.tsu_sta = 40,
747
+
.thd_dat = 22,
748
+
.thd_sta = 35,
749
+
.tbuf = 62,
750
+
.scl_stretch_en = 0,
751
+
.trdhld = 6,
752
+
.tsp = 3
753
+
},
754
+
.params[I2C_MODE_FAST_PLUS] = {
755
+
.thigh = 16,
756
+
.tlow = 22,
757
+
.tsu_sto = 17,
758
+
.tsu_sta = 18,
759
+
.thd_dat = 16,
760
+
.thd_sta = 15,
761
+
.tbuf = 24,
762
+
.scl_stretch_en = 0,
763
+
.trdhld = 3,
764
+
.tsp = 3
765
+
},
766
+
};
767
+
768
+
static const struct of_device_id cci_dt_match[] = {
769
+
{ .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
770
+
{ .compatible = "qcom,msm8996-cci", .data = &cci_v2_data},
771
+
{ .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
772
+
{}
773
+
};
774
+
MODULE_DEVICE_TABLE(of, cci_dt_match);
775
+
776
+
static struct platform_driver qcom_cci_driver = {
777
+
.probe = cci_probe,
778
+
.remove = cci_remove,
779
+
.driver = {
780
+
.name = "i2c-qcom-cci",
781
+
.of_match_table = cci_dt_match,
782
+
.pm = &qcom_cci_pm,
783
+
},
784
+
};
785
+
786
+
module_platform_driver(qcom_cci_driver);
787
+
788
+
MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver");
789
+
MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
790
+
MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
791
+
MODULE_LICENSE("GPL v2");
+6
-12
drivers/i2c/busses/i2c-qup.c
+6
-12
drivers/i2c/busses/i2c-qup.c
···
956
956
u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
957
957
u32 io_mode = QUP_REPACK_EN;
958
958
959
-
blk->is_tx_blk_mode =
960
-
blk->total_tx_len > qup->out_fifo_sz ? true : false;
961
-
blk->is_rx_blk_mode =
962
-
blk->total_rx_len > qup->in_fifo_sz ? true : false;
959
+
blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz;
960
+
blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz;
963
961
964
962
if (blk->is_tx_blk_mode) {
965
963
io_mode |= QUP_OUTPUT_BLK_MODE;
···
1526
1528
qup->use_dma = true;
1527
1529
} else {
1528
1530
qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1529
-
QUP_MAX_TAGS_LEN ? true : false;
1531
+
QUP_MAX_TAGS_LEN;
1530
1532
qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1531
-
READ_RX_TAGS_LEN ? true : false;
1533
+
READ_RX_TAGS_LEN;
1532
1534
}
1533
1535
1534
1536
return 0;
···
1658
1660
static const int blk_sizes[] = {4, 16, 32};
1659
1661
struct qup_i2c_dev *qup;
1660
1662
unsigned long one_bit_t;
1661
-
struct resource *res;
1662
1663
u32 io_mode, hw_ver, size;
1663
1664
int ret, fs_div, hs_div;
1664
1665
u32 src_clk_freq = DEFAULT_SRC_CLK;
···
1754
1757
return -EINVAL;
1755
1758
}
1756
1759
1757
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758
-
qup->base = devm_ioremap_resource(qup->dev, res);
1760
+
qup->base = devm_platform_ioremap_resource(pdev, 0);
1759
1761
if (IS_ERR(qup->base))
1760
1762
return PTR_ERR(qup->base);
1761
1763
1762
1764
qup->irq = platform_get_irq(pdev, 0);
1763
-
if (qup->irq < 0) {
1764
-
dev_err(qup->dev, "No IRQ defined\n");
1765
+
if (qup->irq < 0)
1765
1766
return qup->irq;
1766
-
}
1767
1767
1768
1768
if (has_acpi_companion(qup->dev)) {
1769
1769
ret = device_property_read_u32(qup->dev,
+1
-3
drivers/i2c/busses/i2c-rcar.c
+1
-3
drivers/i2c/busses/i2c-rcar.c
···
938
938
return PTR_ERR(priv->clk);
939
939
}
940
940
941
-
priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
942
-
943
-
priv->io = devm_ioremap_resource(dev, priv->res);
941
+
priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
944
942
if (IS_ERR(priv->io))
945
943
return PTR_ERR(priv->io);
946
944
+2
-6
drivers/i2c/busses/i2c-rk3x.c
+2
-6
drivers/i2c/busses/i2c-rk3x.c
···
1193
1193
struct device_node *np = pdev->dev.of_node;
1194
1194
const struct of_device_id *match;
1195
1195
struct rk3x_i2c *i2c;
1196
-
struct resource *mem;
1197
1196
int ret = 0;
1198
1197
int bus_nr;
1199
1198
u32 value;
···
1222
1223
spin_lock_init(&i2c->lock);
1223
1224
init_waitqueue_head(&i2c->wait);
1224
1225
1225
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1226
-
i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
1226
+
i2c->regs = devm_platform_ioremap_resource(pdev, 0);
1227
1227
if (IS_ERR(i2c->regs))
1228
1228
return PTR_ERR(i2c->regs);
1229
1229
···
1260
1262
1261
1263
/* IRQ setup */
1262
1264
irq = platform_get_irq(pdev, 0);
1263
-
if (irq < 0) {
1264
-
dev_err(&pdev->dev, "cannot find rk3x IRQ\n");
1265
+
if (irq < 0)
1265
1266
return irq;
1266
-
}
1267
1267
1268
1268
ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1269
1269
0, dev_name(&pdev->dev), i2c);
+1
-1
drivers/i2c/busses/i2c-s3c2410.c
+1
-1
drivers/i2c/busses/i2c-s3c2410.c
+2
-5
drivers/i2c/busses/i2c-sh_mobile.c
+2
-5
drivers/i2c/busses/i2c-sh_mobile.c
···
366
366
367
367
static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
368
368
{
369
-
unsigned char data;
370
369
int real_pos;
371
370
372
371
/* switch from TX (address) to RX (data) adds two interrupts */
···
386
387
if (real_pos < 0)
387
388
i2c_op(pd, OP_RX_STOP);
388
389
else
389
-
data = i2c_op(pd, OP_RX_STOP_DATA);
390
+
pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA);
390
391
} else if (real_pos >= 0) {
391
-
data = i2c_op(pd, OP_RX);
392
+
pd->msg->buf[real_pos] = i2c_op(pd, OP_RX);
392
393
}
393
394
394
-
if (real_pos >= 0)
395
-
pd->msg->buf[real_pos] = data;
396
395
done:
397
396
pd->pos++;
398
397
return pd->pos == (pd->msg->len + 2);
+1
-3
drivers/i2c/busses/i2c-sirf.c
+1
-3
drivers/i2c/busses/i2c-sirf.c
···
271
271
{
272
272
struct sirfsoc_i2c *siic;
273
273
struct i2c_adapter *adap;
274
-
struct resource *mem_res;
275
274
struct clk *clk;
276
275
int bitrate;
277
276
int ctrl_speed;
···
308
309
adap = &siic->adapter;
309
310
adap->class = I2C_CLASS_DEPRECATED;
310
311
311
-
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
312
-
siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
312
+
siic->base = devm_platform_ioremap_resource(pdev, 0);
313
313
if (IS_ERR(siic->base)) {
314
314
err = PTR_ERR(siic->base);
315
315
goto out;
+1
-3
drivers/i2c/busses/i2c-sprd.c
+1
-3
drivers/i2c/busses/i2c-sprd.c
···
492
492
return PTR_ERR(i2c_dev->base);
493
493
494
494
i2c_dev->irq = platform_get_irq(pdev, 0);
495
-
if (i2c_dev->irq < 0) {
496
-
dev_err(&pdev->dev, "failed to get irq resource\n");
495
+
if (i2c_dev->irq < 0)
497
496
return i2c_dev->irq;
498
-
}
499
497
500
498
i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
501
499
init_completion(&i2c_dev->complete);
+7
-3
drivers/i2c/busses/i2c-stm32.c
+7
-3
drivers/i2c/busses/i2c-stm32.c
···
25
25
/* Request and configure I2C TX dma channel */
26
26
dma->chan_tx = dma_request_chan(dev, "tx");
27
27
if (IS_ERR(dma->chan_tx)) {
28
-
dev_dbg(dev, "can't request DMA tx channel\n");
29
28
ret = PTR_ERR(dma->chan_tx);
29
+
if (ret != -EPROBE_DEFER)
30
+
dev_err(dev, "can't request DMA tx channel\n");
30
31
goto fail_al;
31
32
}
32
33
···
45
44
/* Request and configure I2C RX dma channel */
46
45
dma->chan_rx = dma_request_chan(dev, "rx");
47
46
if (IS_ERR(dma->chan_rx)) {
48
-
dev_err(dev, "can't request DMA rx channel\n");
49
47
ret = PTR_ERR(dma->chan_rx);
48
+
if (ret != -EPROBE_DEFER)
49
+
dev_err(dev, "can't request DMA rx channel\n");
50
+
50
51
goto fail_tx;
51
52
}
52
53
···
76
73
dma_release_channel(dma->chan_tx);
77
74
fail_al:
78
75
devm_kfree(dev, dma);
79
-
dev_info(dev, "can't use DMA\n");
76
+
if (ret != -EPROBE_DEFER)
77
+
dev_info(dev, "can't use DMA\n");
80
78
81
79
return ERR_PTR(ret);
82
80
}
+3
-1
drivers/i2c/busses/i2c-stm32f4.c
+3
-1
drivers/i2c/busses/i2c-stm32f4.c
···
797
797
798
798
rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
799
799
if (IS_ERR(rst)) {
800
-
dev_err(&pdev->dev, "Error: Missing controller reset\n");
801
800
ret = PTR_ERR(rst);
801
+
if (ret != -EPROBE_DEFER)
802
+
dev_err(&pdev->dev, "Error: Missing reset ctrl\n");
803
+
802
804
goto clk_free;
803
805
}
804
806
reset_control_assert(rst);
+72
-66
drivers/i2c/busses/i2c-stm32f7.c
+72
-66
drivers/i2c/busses/i2c-stm32f7.c
···
189
189
/**
190
190
* struct stm32f7_i2c_spec - private i2c specification timing
191
191
* @rate: I2C bus speed (Hz)
192
-
* @rate_min: 80% of I2C bus speed (Hz)
193
-
* @rate_max: 100% of I2C bus speed (Hz)
194
192
* @fall_max: Max fall time of both SDA and SCL signals (ns)
195
193
* @rise_max: Max rise time of both SDA and SCL signals (ns)
196
194
* @hddat_min: Min data hold time (ns)
···
199
201
*/
200
202
struct stm32f7_i2c_spec {
201
203
u32 rate;
202
-
u32 rate_min;
203
-
u32 rate_max;
204
204
u32 fall_max;
205
205
u32 rise_max;
206
206
u32 hddat_min;
···
210
214
211
215
/**
212
216
* struct stm32f7_i2c_setup - private I2C timing setup parameters
213
-
* @speed: I2C speed mode (standard, Fast Plus)
214
217
* @speed_freq: I2C speed frequency (Hz)
215
218
* @clock_src: I2C clock source frequency (Hz)
216
219
* @rise_time: Rise time (ns)
···
219
224
* @fmp_clr_offset: Fast Mode Plus clear register offset from set register
220
225
*/
221
226
struct stm32f7_i2c_setup {
222
-
enum stm32_i2c_speed speed;
223
227
u32 speed_freq;
224
228
u32 clock_src;
225
229
u32 rise_time;
···
281
287
* @base: virtual memory area
282
288
* @complete: completion of I2C message
283
289
* @clk: hw i2c clock
284
-
* @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
290
+
* @bus_rate: I2C clock frequency of the controller
285
291
* @msg: Pointer to data to be written
286
292
* @msg_num: number of I2C messages to be executed
287
293
* @msg_id: message identifiant
···
308
314
void __iomem *base;
309
315
struct completion complete;
310
316
struct clk *clk;
311
-
int speed;
317
+
unsigned int bus_rate;
312
318
struct i2c_msg *msg;
313
319
unsigned int msg_num;
314
320
unsigned int msg_id;
···
336
342
* Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
337
343
* and Fast-mode Plus I2C-bus devices
338
344
*/
339
-
static struct stm32f7_i2c_spec i2c_specs[] = {
340
-
[STM32_I2C_SPEED_STANDARD] = {
345
+
static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
346
+
{
341
347
.rate = I2C_MAX_STANDARD_MODE_FREQ,
342
-
.rate_min = I2C_MAX_STANDARD_MODE_FREQ * 8 / 10, /* 80% */
343
-
.rate_max = I2C_MAX_STANDARD_MODE_FREQ,
344
348
.fall_max = 300,
345
349
.rise_max = 1000,
346
350
.hddat_min = 0,
···
347
355
.l_min = 4700,
348
356
.h_min = 4000,
349
357
},
350
-
[STM32_I2C_SPEED_FAST] = {
358
+
{
351
359
.rate = I2C_MAX_FAST_MODE_FREQ,
352
-
.rate_min = I2C_MAX_FAST_MODE_FREQ * 8 / 10, /* 80% */
353
-
.rate_max = I2C_MAX_FAST_MODE_FREQ,
354
360
.fall_max = 300,
355
361
.rise_max = 300,
356
362
.hddat_min = 0,
···
357
367
.l_min = 1300,
358
368
.h_min = 600,
359
369
},
360
-
[STM32_I2C_SPEED_FAST_PLUS] = {
370
+
{
361
371
.rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
362
-
.rate_min = I2C_MAX_FAST_MODE_PLUS_FREQ * 8 / 10, /* 80% */
363
-
.rate_max = I2C_MAX_FAST_MODE_PLUS_FREQ,
364
372
.fall_max = 100,
365
373
.rise_max = 120,
366
374
.hddat_min = 0,
···
399
411
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
400
412
}
401
413
414
+
static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
415
+
{
416
+
int i;
417
+
418
+
for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
419
+
if (rate <= stm32f7_i2c_specs[i].rate)
420
+
return &stm32f7_i2c_specs[i];
421
+
422
+
return ERR_PTR(-EINVAL);
423
+
}
424
+
425
+
#define RATE_MIN(rate) ((rate) * 8 / 10)
402
426
static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
403
427
struct stm32f7_i2c_setup *setup,
404
428
struct stm32f7_i2c_timings *output)
405
429
{
430
+
struct stm32f7_i2c_spec *specs;
406
431
u32 p_prev = STM32F7_PRESC_MAX;
407
432
u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
408
433
setup->clock_src);
···
433
432
u16 p, l, a, h;
434
433
int ret = 0;
435
434
436
-
if (setup->speed >= STM32_I2C_SPEED_END) {
437
-
dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
438
-
setup->speed, STM32_I2C_SPEED_END - 1);
435
+
specs = stm32f7_get_specs(setup->speed_freq);
436
+
if (specs == ERR_PTR(-EINVAL)) {
437
+
dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
438
+
setup->speed_freq);
439
439
return -EINVAL;
440
440
}
441
441
442
-
if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
443
-
(setup->fall_time > i2c_specs[setup->speed].fall_max)) {
442
+
if ((setup->rise_time > specs->rise_max) ||
443
+
(setup->fall_time > specs->fall_max)) {
444
444
dev_err(i2c_dev->dev,
445
445
"timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
446
-
setup->rise_time, i2c_specs[setup->speed].rise_max,
447
-
setup->fall_time, i2c_specs[setup->speed].fall_max);
446
+
setup->rise_time, specs->rise_max,
447
+
setup->fall_time, specs->fall_max);
448
448
return -EINVAL;
449
449
}
450
450
···
453
451
dev_err(i2c_dev->dev,
454
452
"DNF out of bound %d/%d\n",
455
453
setup->dnf, STM32F7_I2C_DNF_MAX);
456
-
return -EINVAL;
457
-
}
458
-
459
-
if (setup->speed_freq > i2c_specs[setup->speed].rate) {
460
-
dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
461
-
setup->speed_freq, i2c_specs[setup->speed].rate);
462
454
return -EINVAL;
463
455
}
464
456
···
465
469
STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
466
470
dnf_delay = setup->dnf * i2cclk;
467
471
468
-
sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
472
+
sdadel_min = specs->hddat_min + setup->fall_time -
469
473
af_delay_min - (setup->dnf + 3) * i2cclk;
470
474
471
-
sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
475
+
sdadel_max = specs->vddat_max - setup->rise_time -
472
476
af_delay_max - (setup->dnf + 4) * i2cclk;
473
477
474
-
scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
478
+
scldel_min = setup->rise_time + specs->sudat_min;
475
479
476
480
if (sdadel_min < 0)
477
481
sdadel_min = 0;
···
526
530
527
531
tsync = af_delay_min + dnf_delay + (2 * i2cclk);
528
532
s = NULL;
529
-
clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
530
-
clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
533
+
clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
534
+
clk_min = NSEC_PER_SEC / setup->speed_freq;
531
535
532
536
/*
533
537
* Among Prescaler possibilities discovered above figures out SCL Low
···
545
549
for (l = 0; l < STM32F7_SCLL_MAX; l++) {
546
550
u32 tscl_l = (l + 1) * prescaler + tsync;
547
551
548
-
if ((tscl_l < i2c_specs[setup->speed].l_min) ||
552
+
if ((tscl_l < specs->l_min) ||
549
553
(i2cclk >=
550
554
((tscl_l - af_delay_min - dnf_delay) / 4))) {
551
555
continue;
···
557
561
setup->rise_time + setup->fall_time;
558
562
559
563
if ((tscl >= clk_min) && (tscl <= clk_max) &&
560
-
(tscl_h >= i2c_specs[setup->speed].h_min) &&
564
+
(tscl_h >= specs->h_min) &&
561
565
(i2cclk < tscl_h)) {
562
566
int clk_error = tscl - i2cbus;
563
567
···
603
607
return ret;
604
608
}
605
609
610
+
static u32 stm32f7_get_lower_rate(u32 rate)
611
+
{
612
+
int i = ARRAY_SIZE(stm32f7_i2c_specs);
613
+
614
+
while (--i)
615
+
if (stm32f7_i2c_specs[i].rate < rate)
616
+
break;
617
+
618
+
return stm32f7_i2c_specs[i].rate;
619
+
}
620
+
606
621
static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
607
622
struct stm32f7_i2c_setup *setup)
608
623
{
···
626
619
627
620
i2c_parse_fw_timings(i2c_dev->dev, t, false);
628
621
629
-
if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_PLUS_FREQ)
630
-
i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
631
-
else if (t->bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ)
632
-
i2c_dev->speed = STM32_I2C_SPEED_FAST;
633
-
else
634
-
i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
622
+
if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
623
+
dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
624
+
t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
625
+
return -EINVAL;
626
+
}
635
627
628
+
setup->speed_freq = t->bus_freq_hz;
636
629
i2c_dev->setup.rise_time = t->scl_rise_ns;
637
630
i2c_dev->setup.fall_time = t->scl_fall_ns;
638
-
639
-
setup->speed = i2c_dev->speed;
640
-
setup->speed_freq = i2c_specs[setup->speed].rate;
641
631
setup->clock_src = clk_get_rate(i2c_dev->clk);
642
632
643
633
if (!setup->clock_src) {
···
648
644
if (ret) {
649
645
dev_err(i2c_dev->dev,
650
646
"failed to compute I2C timings.\n");
651
-
if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
652
-
i2c_dev->speed--;
653
-
setup->speed = i2c_dev->speed;
654
-
setup->speed_freq =
655
-
i2c_specs[setup->speed].rate;
656
-
dev_warn(i2c_dev->dev,
657
-
"downgrade I2C Speed Freq to (%i)\n",
658
-
i2c_specs[setup->speed].rate);
659
-
} else {
647
+
if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
660
648
break;
661
-
}
649
+
setup->speed_freq =
650
+
stm32f7_get_lower_rate(setup->speed_freq);
651
+
dev_warn(i2c_dev->dev,
652
+
"downgrade I2C Speed Freq to (%i)\n",
653
+
setup->speed_freq);
662
654
}
663
655
} while (ret);
664
656
···
663
663
return ret;
664
664
}
665
665
666
-
dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
667
-
setup->speed, setup->speed_freq, setup->clock_src);
666
+
dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
667
+
setup->speed_freq, setup->clock_src);
668
668
dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
669
669
setup->rise_time, setup->fall_time);
670
670
dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
671
671
(setup->analog_filter ? "On" : "Off"), setup->dnf);
672
+
673
+
i2c_dev->bus_rate = setup->speed_freq;
672
674
673
675
return 0;
674
676
}
···
1464
1462
1465
1463
/* NACK received */
1466
1464
if (status & STM32F7_I2C_ISR_NACKF) {
1467
-
dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1465
+
dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1466
+
__func__, f7_msg->addr);
1468
1467
writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1469
1468
f7_msg->result = -ENXIO;
1470
1469
}
···
1869
1866
{
1870
1867
int ret;
1871
1868
1872
-
if (i2c_dev->speed != STM32_I2C_SPEED_FAST_PLUS ||
1869
+
if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1873
1870
IS_ERR_OR_NULL(i2c_dev->regmap))
1874
1871
/* Optional */
1875
1872
return 0;
···
1943
1940
if (!i2c_dev)
1944
1941
return -ENOMEM;
1945
1942
1946
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1947
-
i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1943
+
i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1948
1944
if (IS_ERR(i2c_dev->base))
1949
1945
return PTR_ERR(i2c_dev->base);
1950
1946
phy_addr = (dma_addr_t)res->start;
···
1969
1967
1970
1968
i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1971
1969
if (IS_ERR(i2c_dev->clk)) {
1972
-
dev_err(&pdev->dev, "Error: Missing controller clock\n");
1970
+
if (PTR_ERR(i2c_dev->clk) != -EPROBE_DEFER)
1971
+
dev_err(&pdev->dev, "Failed to get controller clock\n");
1973
1972
return PTR_ERR(i2c_dev->clk);
1974
1973
}
1975
1974
···
1982
1979
1983
1980
rst = devm_reset_control_get(&pdev->dev, NULL);
1984
1981
if (IS_ERR(rst)) {
1985
-
dev_err(&pdev->dev, "Error: Missing controller reset\n");
1986
1982
ret = PTR_ERR(rst);
1983
+
if (ret != -EPROBE_DEFER)
1984
+
dev_err(&pdev->dev, "Error: Missing reset ctrl\n");
1985
+
1987
1986
goto clk_free;
1988
1987
}
1989
1988
reset_control_assert(rst);
···
2025
2020
if (ret)
2026
2021
goto clk_free;
2027
2022
2028
-
if (i2c_dev->speed == STM32_I2C_SPEED_FAST_PLUS) {
2023
+
/* Setup Fast mode plus if necessary */
2024
+
if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2029
2025
ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2030
2026
if (ret)
2031
2027
goto clk_free;
+1
-3
drivers/i2c/busses/i2c-stu300.c
+1
-3
drivers/i2c/busses/i2c-stu300.c
···
860
860
{
861
861
struct stu300_dev *dev;
862
862
struct i2c_adapter *adap;
863
-
struct resource *res;
864
863
int bus_nr;
865
864
int ret = 0;
866
865
···
875
876
}
876
877
877
878
dev->pdev = pdev;
878
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879
-
dev->virtbase = devm_ioremap_resource(&pdev->dev, res);
879
+
dev->virtbase = devm_platform_ioremap_resource(pdev, 0);
880
880
dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
881
881
"base %p\n", bus_nr, dev->virtbase);
882
882
if (IS_ERR(dev->virtbase))
+2
-6
drivers/i2c/busses/i2c-sun6i-p2wi.c
+2
-6
drivers/i2c/busses/i2c-sun6i-p2wi.c
···
187
187
struct device_node *childnp;
188
188
unsigned long parent_clk_freq;
189
189
u32 clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
190
-
struct resource *r;
191
190
struct p2wi *p2wi;
192
191
u32 slave_addr;
193
192
int clk_div;
···
230
231
p2wi->slave_addr = slave_addr;
231
232
}
232
233
233
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
234
-
p2wi->regs = devm_ioremap_resource(dev, r);
234
+
p2wi->regs = devm_platform_ioremap_resource(pdev, 0);
235
235
if (IS_ERR(p2wi->regs))
236
236
return PTR_ERR(p2wi->regs);
237
237
238
238
strlcpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name));
239
239
irq = platform_get_irq(pdev, 0);
240
-
if (irq < 0) {
241
-
dev_err(dev, "failed to retrieve irq: %d\n", irq);
240
+
if (irq < 0)
242
241
return irq;
243
-
}
244
242
245
243
p2wi->clk = devm_clk_get(dev, NULL);
246
244
if (IS_ERR(p2wi->clk)) {
+2
-6
drivers/i2c/busses/i2c-synquacer.c
+2
-6
drivers/i2c/busses/i2c-synquacer.c
···
536
536
static int synquacer_i2c_probe(struct platform_device *pdev)
537
537
{
538
538
struct synquacer_i2c *i2c;
539
-
struct resource *r;
540
539
u32 bus_speed;
541
540
int ret;
542
541
···
573
574
return -EINVAL;
574
575
}
575
576
576
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577
-
i2c->base = devm_ioremap_resource(&pdev->dev, r);
577
+
i2c->base = devm_platform_ioremap_resource(pdev, 0);
578
578
if (IS_ERR(i2c->base))
579
579
return PTR_ERR(i2c->base);
580
580
581
581
i2c->irq = platform_get_irq(pdev, 0);
582
-
if (i2c->irq < 0) {
583
-
dev_err(&pdev->dev, "no IRQ resource found\n");
582
+
if (i2c->irq < 0)
584
583
return -ENODEV;
585
-
}
586
584
587
585
ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
588
586
0, dev_name(&pdev->dev), i2c);
+179
-69
drivers/i2c/busses/i2c-tegra.c
+179
-69
drivers/i2c/busses/i2c-tegra.c
···
6
6
* Author: Colin Cross <ccross@android.com>
7
7
*/
8
8
9
+
#include <linux/bitfield.h>
9
10
#include <linux/clk.h>
10
11
#include <linux/delay.h>
11
12
#include <linux/dmaengine.h>
···
30
29
#define BYTES_PER_FIFO_WORD 4
31
30
32
31
#define I2C_CNFG 0x000
33
-
#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
32
+
#define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
34
33
#define I2C_CNFG_PACKET_MODE_EN BIT(10)
35
34
#define I2C_CNFG_NEW_MASTER_FSM BIT(11)
36
35
#define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
37
-
#define I2C_STATUS 0x01C
36
+
#define I2C_STATUS 0x01c
38
37
#define I2C_SL_CNFG 0x020
39
38
#define I2C_SL_CNFG_NACK BIT(1)
40
39
#define I2C_SL_CNFG_NEWSL BIT(2)
41
40
#define I2C_SL_ADDR1 0x02c
42
41
#define I2C_SL_ADDR2 0x030
42
+
#define I2C_TLOW_SEXT 0x034
43
43
#define I2C_TX_FIFO 0x050
44
44
#define I2C_RX_FIFO 0x054
45
45
#define I2C_PACKET_TRANSFER_STATUS 0x058
···
50
48
#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
51
49
#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
52
50
#define I2C_FIFO_STATUS 0x060
53
-
#define I2C_FIFO_STATUS_TX_MASK 0xF0
54
-
#define I2C_FIFO_STATUS_TX_SHIFT 4
55
-
#define I2C_FIFO_STATUS_RX_MASK 0x0F
56
-
#define I2C_FIFO_STATUS_RX_SHIFT 0
51
+
#define I2C_FIFO_STATUS_TX GENMASK(7, 4)
52
+
#define I2C_FIFO_STATUS_RX GENMASK(3, 0)
57
53
#define I2C_INT_MASK 0x064
58
54
#define I2C_INT_STATUS 0x068
59
55
#define I2C_INT_BUS_CLR_DONE BIT(11)
···
61
61
#define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
62
62
#define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
63
63
#define I2C_CLK_DIVISOR 0x06c
64
-
#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
64
+
#define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
65
+
#define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
65
66
66
67
#define DVC_CTRL_REG1 0x000
67
68
#define DVC_CTRL_REG1_INTR_EN BIT(10)
···
78
77
#define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
79
78
#define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
80
79
81
-
#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
82
-
#define PACKET_HEADER0_PACKET_ID_SHIFT 16
83
-
#define PACKET_HEADER0_CONT_ID_SHIFT 12
84
-
#define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
80
+
#define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
81
+
#define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
82
+
#define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
83
+
#define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
84
+
#define PACKET_HEADER0_PROTOCOL_I2C 1
85
85
86
86
#define I2C_HEADER_CONT_ON_NAK BIT(21)
87
87
#define I2C_HEADER_READ BIT(19)
···
93
91
#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
94
92
95
93
#define I2C_BUS_CLEAR_CNFG 0x084
96
-
#define I2C_BC_SCLK_THRESHOLD 9
97
-
#define I2C_BC_SCLK_THRESHOLD_SHIFT 16
94
+
#define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
98
95
#define I2C_BC_STOP_COND BIT(2)
99
96
#define I2C_BC_TERMINATE BIT(1)
100
97
#define I2C_BC_ENABLE BIT(0)
101
98
#define I2C_BUS_CLEAR_STATUS 0x088
102
99
#define I2C_BC_STATUS BIT(0)
103
100
104
-
#define I2C_CONFIG_LOAD 0x08C
101
+
#define I2C_CONFIG_LOAD 0x08c
105
102
#define I2C_MSTR_CONFIG_LOAD BIT(0)
106
103
107
104
#define I2C_CLKEN_OVERRIDE 0x090
108
105
#define I2C_MST_CORE_CLKEN_OVR BIT(0)
109
106
110
-
#define I2C_CONFIG_LOAD_TIMEOUT 1000000
107
+
#define I2C_INTERFACE_TIMING_0 0x094
108
+
#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
109
+
#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
110
+
#define I2C_INTERFACE_TIMING_1 0x098
111
+
#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
112
+
#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
113
+
#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
114
+
#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
115
+
116
+
#define I2C_HS_INTERFACE_TIMING_0 0x09c
117
+
#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
118
+
#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
119
+
#define I2C_HS_INTERFACE_TIMING_1 0x0a0
120
+
#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
121
+
#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
122
+
#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
111
123
112
124
#define I2C_MST_FIFO_CONTROL 0x0b4
113
125
#define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
···
130
114
#define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
131
115
132
116
#define I2C_MST_FIFO_STATUS 0x0b8
133
-
#define I2C_MST_FIFO_STATUS_RX_MASK 0xff
134
-
#define I2C_MST_FIFO_STATUS_RX_SHIFT 0
135
-
#define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000
136
-
#define I2C_MST_FIFO_STATUS_TX_SHIFT 16
117
+
#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
118
+
#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
137
119
138
-
#define I2C_INTERFACE_TIMING_0 0x94
139
-
#define I2C_THIGH_SHIFT 8
140
-
#define I2C_INTERFACE_TIMING_1 0x98
120
+
/* configuration load timeout in microseconds */
121
+
#define I2C_CONFIG_LOAD_TIMEOUT 1000000
141
122
142
123
/* Packet header size in bytes */
143
124
#define I2C_PACKET_HEADER_SIZE 12
···
243
230
* @cont_id: I2C controller ID, used for packet header
244
231
* @irq: IRQ number of transfer complete interrupt
245
232
* @is_dvc: identifies the DVC I2C controller, has a different register layout
233
+
* @is_vi: identifies the VI I2C controller, has a different register layout
246
234
* @msg_complete: transfer completion notifier
247
235
* @msg_err: error code for completed message
248
236
* @msg_buf: pointer to current message data
···
267
253
struct i2c_adapter adapter;
268
254
struct clk *div_clk;
269
255
struct clk *fast_clk;
256
+
struct clk *slow_clk;
270
257
struct reset_control *rst;
271
258
void __iomem *base;
272
259
phys_addr_t base_phys;
273
260
int cont_id;
274
261
int irq;
275
262
int is_dvc;
263
+
bool is_vi;
276
264
struct completion msg_complete;
277
265
int msg_err;
278
266
u8 *msg_buf;
···
313
297
{
314
298
if (i2c_dev->is_dvc)
315
299
reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
300
+
else if (i2c_dev->is_vi)
301
+
reg = 0xc00 + (reg << 2);
316
302
return reg;
317
303
}
318
304
···
513
495
514
496
if (i2c_dev->hw->has_mst_fifo) {
515
497
val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
516
-
rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
517
-
I2C_MST_FIFO_STATUS_RX_SHIFT;
498
+
rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
518
499
} else {
519
500
val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
520
-
rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
521
-
I2C_FIFO_STATUS_RX_SHIFT;
501
+
rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
522
502
}
523
503
524
504
/* Rounds down to not include partial word at the end of buf */
···
567
551
568
552
if (i2c_dev->hw->has_mst_fifo) {
569
553
val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
570
-
tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
571
-
I2C_MST_FIFO_STATUS_TX_SHIFT;
554
+
tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
572
555
} else {
573
556
val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
574
-
tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
575
-
I2C_FIFO_STATUS_TX_SHIFT;
557
+
tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
576
558
}
577
559
578
560
/* Rounds down to not include partial word at the end of buf */
···
664
650
}
665
651
}
666
652
653
+
if (i2c_dev->slow_clk) {
654
+
ret = clk_enable(i2c_dev->slow_clk);
655
+
if (ret < 0) {
656
+
dev_err(dev, "failed to enable slow clock: %d\n", ret);
657
+
return ret;
658
+
}
659
+
}
660
+
667
661
ret = clk_enable(i2c_dev->div_clk);
668
662
if (ret < 0) {
669
663
dev_err(i2c_dev->dev,
···
688
666
struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
689
667
690
668
clk_disable(i2c_dev->div_clk);
669
+
670
+
if (i2c_dev->slow_clk)
671
+
clk_disable(i2c_dev->slow_clk);
672
+
691
673
if (!i2c_dev->hw->has_single_clk_source)
692
674
clk_disable(i2c_dev->fast_clk);
693
675
···
729
703
return 0;
730
704
}
731
705
706
+
static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
707
+
{
708
+
u32 value;
709
+
710
+
value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
711
+
FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
712
+
i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
713
+
714
+
value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
715
+
FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
716
+
FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
717
+
FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
718
+
i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
719
+
720
+
value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
721
+
FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
722
+
i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
723
+
724
+
value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
725
+
FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
726
+
FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
727
+
i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
728
+
729
+
value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
730
+
i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
731
+
732
+
i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
733
+
}
734
+
732
735
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
733
736
{
734
737
u32 val;
···
774
719
tegra_dvc_init(i2c_dev);
775
720
776
721
val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
777
-
(0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
722
+
FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
778
723
779
724
if (i2c_dev->hw->has_multi_master_mode)
780
725
val |= I2C_CNFG_MULTI_MASTER_MODE;
···
782
727
i2c_writel(i2c_dev, val, I2C_CNFG);
783
728
i2c_writel(i2c_dev, 0, I2C_INT_MASK);
784
729
730
+
if (i2c_dev->is_vi)
731
+
tegra_i2c_vi_init(i2c_dev);
732
+
785
733
/* Make sure clock divisor programmed correctly */
786
-
clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
787
-
clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
788
-
I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
734
+
clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
735
+
i2c_dev->hw->clk_divisor_hs_mode) |
736
+
FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE,
737
+
i2c_dev->clk_divisor_non_hs_mode);
789
738
i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
790
739
791
740
if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
···
804
745
}
805
746
806
747
if (i2c_dev->hw->has_interface_timing_reg) {
807
-
val = (thigh << I2C_THIGH_SHIFT) | tlow;
748
+
val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
749
+
FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
808
750
i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
809
751
}
810
752
···
828
768
}
829
769
}
830
770
831
-
if (!i2c_dev->is_dvc) {
771
+
if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
832
772
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
833
773
834
774
sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
···
1056
996
do {
1057
997
u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1058
998
1059
-
if (status) {
999
+
if (status)
1060
1000
tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1061
1001
1062
-
if (completion_done(complete)) {
1063
-
s64 delta = ktime_ms_delta(ktimeout, ktime);
1002
+
if (completion_done(complete)) {
1003
+
s64 delta = ktime_ms_delta(ktimeout, ktime);
1064
1004
1065
-
return msecs_to_jiffies(delta) ?: 1;
1066
-
}
1005
+
return msecs_to_jiffies(delta) ?: 1;
1067
1006
}
1068
1007
1069
1008
ktime = ktime_get();
···
1089
1030
disable_irq(i2c_dev->irq);
1090
1031
1091
1032
/*
1092
-
* There is a chance that completion may happen after IRQ
1093
-
* synchronization, which is done by disable_irq().
1033
+
* Under some rare circumstances (like running KASAN +
1034
+
* NFS root) CPU, which handles interrupt, may stuck in
1035
+
* uninterruptible state for a significant time. In this
1036
+
* case we will get timeout if I2C transfer is running on
1037
+
* a sibling CPU, despite of IRQ being raised.
1038
+
*
1039
+
* In order to handle this rare condition, the IRQ status
1040
+
* needs to be checked after timeout.
1094
1041
*/
1095
-
if (ret == 0 && completion_done(complete)) {
1096
-
dev_warn(i2c_dev->dev,
1097
-
"completion done after timeout\n");
1098
-
ret = 1;
1099
-
}
1042
+
if (ret == 0)
1043
+
ret = tegra_i2c_poll_completion_timeout(i2c_dev,
1044
+
complete, 0);
1100
1045
}
1101
1046
1102
1047
return ret;
···
1114
1051
u32 reg;
1115
1052
1116
1053
reinit_completion(&i2c_dev->msg_complete);
1117
-
reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) |
1118
-
I2C_BC_STOP_COND | I2C_BC_TERMINATE;
1054
+
reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1055
+
I2C_BC_TERMINATE;
1119
1056
i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1120
1057
if (i2c_dev->hw->has_config_load_reg) {
1121
1058
err = tegra_i2c_wait_for_config_load(i2c_dev);
···
1208
1145
}
1209
1146
}
1210
1147
1211
-
packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
1212
-
PACKET_HEADER0_PROTOCOL_I2C |
1213
-
(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
1214
-
(1 << PACKET_HEADER0_PACKET_ID_SHIFT);
1148
+
packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1149
+
FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1150
+
PACKET_HEADER0_PROTOCOL_I2C) |
1151
+
FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1152
+
FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1215
1153
if (dma && !i2c_dev->msg_read)
1216
1154
*buffer++ = packet_header;
1217
1155
else
···
1279
1215
if (dma) {
1280
1216
time_left = tegra_i2c_wait_completion_timeout(
1281
1217
i2c_dev, &i2c_dev->dma_complete, xfer_time);
1218
+
1219
+
/*
1220
+
* Synchronize DMA first, since dmaengine_terminate_sync()
1221
+
* performs synchronization after the transfer's termination
1222
+
* and we want to get a completion if transfer succeeded.
1223
+
*/
1224
+
dmaengine_synchronize(i2c_dev->msg_read ?
1225
+
i2c_dev->rx_dma_chan :
1226
+
i2c_dev->tx_dma_chan);
1282
1227
1283
1228
dmaengine_terminate_sync(i2c_dev->msg_read ?
1284
1229
i2c_dev->rx_dma_chan :
···
1617
1544
static const struct of_device_id tegra_i2c_of_match[] = {
1618
1545
{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1619
1546
{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1547
+
{ .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1620
1548
{ .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1621
1549
{ .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1622
1550
{ .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
···
1630
1556
1631
1557
static int tegra_i2c_probe(struct platform_device *pdev)
1632
1558
{
1559
+
struct device *dev = &pdev->dev;
1633
1560
struct tegra_i2c_dev *i2c_dev;
1634
1561
struct resource *res;
1635
1562
struct clk *div_clk;
···
1686
1611
i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1687
1612
i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1688
1613
"nvidia,tegra20-i2c-dvc");
1614
+
i2c_dev->is_vi = of_device_is_compatible(dev->of_node,
1615
+
"nvidia,tegra210-i2c-vi");
1689
1616
i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1690
1617
i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1691
1618
I2C_PACKET_HEADER_SIZE;
···
1703
1626
i2c_dev->fast_clk = fast_clk;
1704
1627
}
1705
1628
1629
+
if (i2c_dev->is_vi) {
1630
+
i2c_dev->slow_clk = devm_clk_get(dev, "slow");
1631
+
if (IS_ERR(i2c_dev->slow_clk)) {
1632
+
if (PTR_ERR(i2c_dev->slow_clk) != -EPROBE_DEFER)
1633
+
dev_err(dev, "failed to get slow clock: %ld\n",
1634
+
PTR_ERR(i2c_dev->slow_clk));
1635
+
1636
+
return PTR_ERR(i2c_dev->slow_clk);
1637
+
}
1638
+
}
1639
+
1706
1640
platform_set_drvdata(pdev, i2c_dev);
1707
1641
1708
1642
if (!i2c_dev->hw->has_single_clk_source) {
···
1721
1633
if (ret < 0) {
1722
1634
dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1723
1635
return ret;
1636
+
}
1637
+
}
1638
+
1639
+
if (i2c_dev->slow_clk) {
1640
+
ret = clk_prepare(i2c_dev->slow_clk);
1641
+
if (ret < 0) {
1642
+
dev_err(dev, "failed to prepare slow clock: %d\n", ret);
1643
+
goto unprepare_fast_clk;
1724
1644
}
1725
1645
}
1726
1646
···
1747
1651
ret = clk_prepare(i2c_dev->div_clk);
1748
1652
if (ret < 0) {
1749
1653
dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1750
-
goto unprepare_fast_clk;
1654
+
goto unprepare_slow_clk;
1751
1655
}
1752
1656
1753
1657
pm_runtime_irq_safe(&pdev->dev);
···
1790
1694
1791
1695
irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1792
1696
1793
-
ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1794
-
tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1697
+
ret = devm_request_irq(&pdev->dev, i2c_dev->irq, tegra_i2c_isr,
1698
+
IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c_dev);
1795
1699
if (ret) {
1796
1700
dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1797
1701
goto release_dma;
···
1834
1738
unprepare_div_clk:
1835
1739
clk_unprepare(i2c_dev->div_clk);
1836
1740
1741
+
unprepare_slow_clk:
1742
+
if (i2c_dev->is_vi)
1743
+
clk_unprepare(i2c_dev->slow_clk);
1744
+
1837
1745
unprepare_fast_clk:
1838
1746
if (!i2c_dev->hw->has_single_clk_source)
1839
1747
clk_unprepare(i2c_dev->fast_clk);
···
1859
1759
tegra_i2c_runtime_suspend(&pdev->dev);
1860
1760
1861
1761
clk_unprepare(i2c_dev->div_clk);
1762
+
1763
+
if (i2c_dev->slow_clk)
1764
+
clk_unprepare(i2c_dev->slow_clk);
1765
+
1862
1766
if (!i2c_dev->hw->has_single_clk_source)
1863
1767
clk_unprepare(i2c_dev->fast_clk);
1864
1768
···
1873
1769
static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1874
1770
{
1875
1771
struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1876
-
int err;
1772
+
int err = 0;
1877
1773
1878
1774
i2c_mark_adapter_suspended(&i2c_dev->adapter);
1879
1775
1880
-
err = pm_runtime_force_suspend(dev);
1881
-
if (err < 0)
1882
-
return err;
1776
+
if (!pm_runtime_status_suspended(dev))
1777
+
err = tegra_i2c_runtime_suspend(dev);
1883
1778
1884
-
return 0;
1779
+
return err;
1885
1780
}
1886
1781
1887
1782
static int __maybe_unused tegra_i2c_resume(struct device *dev)
···
1888
1785
struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1889
1786
int err;
1890
1787
1788
+
/*
1789
+
* We need to ensure that clocks are enabled so that registers can be
1790
+
* restored in tegra_i2c_init().
1791
+
*/
1891
1792
err = tegra_i2c_runtime_resume(dev);
1892
1793
if (err)
1893
1794
return err;
···
1900
1793
if (err)
1901
1794
return err;
1902
1795
1903
-
err = tegra_i2c_runtime_suspend(dev);
1904
-
if (err)
1905
-
return err;
1906
-
1907
-
err = pm_runtime_force_resume(dev);
1908
-
if (err < 0)
1909
-
return err;
1796
+
/*
1797
+
* In case we are runtime suspended, disable clocks again so that we
1798
+
* don't unbalance the clock reference counts during the next runtime
1799
+
* resume transition.
1800
+
*/
1801
+
if (pm_runtime_status_suspended(dev)) {
1802
+
err = tegra_i2c_runtime_suspend(dev);
1803
+
if (err)
1804
+
return err;
1805
+
}
1910
1806
1911
1807
i2c_mark_adapter_resumed(&i2c_dev->adapter);
1912
1808
+1
-3
drivers/i2c/busses/i2c-uniphier-f.c
+1
-3
drivers/i2c/busses/i2c-uniphier-f.c
···
529
529
return PTR_ERR(priv->membase);
530
530
531
531
irq = platform_get_irq(pdev, 0);
532
-
if (irq < 0) {
533
-
dev_err(dev, "failed to get IRQ number\n");
532
+
if (irq < 0)
534
533
return irq;
535
-
}
536
534
537
535
if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
538
536
bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
+1
-3
drivers/i2c/busses/i2c-uniphier.c
+1
-3
drivers/i2c/busses/i2c-uniphier.c
···
324
324
return PTR_ERR(priv->membase);
325
325
326
326
irq = platform_get_irq(pdev, 0);
327
-
if (irq < 0) {
328
-
dev_err(dev, "failed to get IRQ number\n");
327
+
if (irq < 0)
329
328
return irq;
330
-
}
331
329
332
330
if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
333
331
bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
+2
-6
drivers/i2c/busses/i2c-xlp9xx.c
+2
-6
drivers/i2c/busses/i2c-xlp9xx.c
···
506
506
static int xlp9xx_i2c_probe(struct platform_device *pdev)
507
507
{
508
508
struct xlp9xx_i2c_dev *priv;
509
-
struct resource *res;
510
509
int err = 0;
511
510
512
511
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
513
512
if (!priv)
514
513
return -ENOMEM;
515
514
516
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
517
-
priv->base = devm_ioremap_resource(&pdev->dev, res);
515
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
518
516
if (IS_ERR(priv->base))
519
517
return PTR_ERR(priv->base);
520
518
521
519
priv->irq = platform_get_irq(pdev, 0);
522
-
if (priv->irq <= 0) {
523
-
dev_err(&pdev->dev, "invalid irq!\n");
520
+
if (priv->irq <= 0)
524
521
return priv->irq;
525
-
}
526
522
/* SMBAlert irq */
527
523
priv->alert_data.irq = platform_get_irq(pdev, 1);
528
524
if (priv->alert_data.irq <= 0)
+1
-3
drivers/i2c/busses/i2c-xlr.c
+1
-3
drivers/i2c/busses/i2c-xlr.c
···
362
362
{
363
363
const struct of_device_id *match;
364
364
struct xlr_i2c_private *priv;
365
-
struct resource *res;
366
365
struct clk *clk;
367
366
unsigned long clk_rate;
368
367
unsigned long clk_div;
···
379
380
else
380
381
priv->cfg = &xlr_i2c_config_default;
381
382
382
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383
-
priv->iobase = devm_ioremap_resource(&pdev->dev, res);
383
+
priv->iobase = devm_platform_ioremap_resource(pdev, 0);
384
384
if (IS_ERR(priv->iobase))
385
385
return PTR_ERR(priv->iobase);
386
386
+1
-3
drivers/i2c/busses/i2c-zx2967.c
+1
-3
drivers/i2c/busses/i2c-zx2967.c
···
502
502
{
503
503
struct zx2967_i2c *i2c;
504
504
void __iomem *reg_base;
505
-
struct resource *res;
506
505
struct clk *clk;
507
506
int ret;
508
507
···
509
510
if (!i2c)
510
511
return -ENOMEM;
511
512
512
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
513
-
reg_base = devm_ioremap_resource(&pdev->dev, res);
513
+
reg_base = devm_platform_ioremap_resource(pdev, 0);
514
514
if (IS_ERR(reg_base))
515
515
return PTR_ERR(reg_base);
516
516
+1
-5
drivers/i2c/i2c-core-acpi.c
+1
-5
drivers/i2c/i2c-core-acpi.c
···
468
468
struct i2c_client *i2c_acpi_new_device(struct device *dev, int index,
469
469
struct i2c_board_info *info)
470
470
{
471
+
struct acpi_device *adev = ACPI_COMPANION(dev);
471
472
struct i2c_acpi_lookup lookup;
472
473
struct i2c_adapter *adapter;
473
-
struct acpi_device *adev;
474
474
LIST_HEAD(resource_list);
475
475
int ret;
476
-
477
-
adev = ACPI_COMPANION(dev);
478
-
if (!adev)
479
-
return ERR_PTR(-EINVAL);
480
476
481
477
memset(&lookup, 0, sizeof(lookup));
482
478
lookup.info = info;
+31
-41
drivers/i2c/i2c-core-base.c
+31
-41
drivers/i2c/i2c-core-base.c
···
1598
1598
}
1599
1599
EXPORT_SYMBOL(i2c_del_adapter);
1600
1600
1601
+
static void i2c_parse_timing(struct device *dev, char *prop_name, u32 *cur_val_p,
1602
+
u32 def_val, bool use_def)
1603
+
{
1604
+
int ret;
1605
+
1606
+
ret = device_property_read_u32(dev, prop_name, cur_val_p);
1607
+
if (ret && use_def)
1608
+
*cur_val_p = def_val;
1609
+
1610
+
dev_dbg(dev, "%s: %u\n", prop_name, *cur_val_p);
1611
+
}
1612
+
1601
1613
/**
1602
1614
* i2c_parse_fw_timings - get I2C related timing parameters from firmware
1603
1615
* @dev: The device to scan for I2C timing properties
···
1628
1616
*/
1629
1617
void i2c_parse_fw_timings(struct device *dev, struct i2c_timings *t, bool use_defaults)
1630
1618
{
1631
-
int ret;
1619
+
bool u = use_defaults;
1620
+
u32 d;
1632
1621
1633
-
ret = device_property_read_u32(dev, "clock-frequency", &t->bus_freq_hz);
1634
-
if (ret && use_defaults)
1635
-
t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
1622
+
i2c_parse_timing(dev, "clock-frequency", &t->bus_freq_hz,
1623
+
I2C_MAX_STANDARD_MODE_FREQ, u);
1636
1624
1637
-
ret = device_property_read_u32(dev, "i2c-scl-rising-time-ns", &t->scl_rise_ns);
1638
-
if (ret && use_defaults) {
1639
-
if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ)
1640
-
t->scl_rise_ns = 1000;
1641
-
else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ)
1642
-
t->scl_rise_ns = 300;
1643
-
else
1644
-
t->scl_rise_ns = 120;
1645
-
}
1625
+
d = t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ ? 1000 :
1626
+
t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120;
1627
+
i2c_parse_timing(dev, "i2c-scl-rising-time-ns", &t->scl_rise_ns, d, u);
1646
1628
1647
-
ret = device_property_read_u32(dev, "i2c-scl-falling-time-ns", &t->scl_fall_ns);
1648
-
if (ret && use_defaults) {
1649
-
if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ)
1650
-
t->scl_fall_ns = 300;
1651
-
else
1652
-
t->scl_fall_ns = 120;
1653
-
}
1629
+
d = t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ ? 300 : 120;
1630
+
i2c_parse_timing(dev, "i2c-scl-falling-time-ns", &t->scl_fall_ns, d, u);
1654
1631
1655
-
ret = device_property_read_u32(dev, "i2c-scl-internal-delay-ns", &t->scl_int_delay_ns);
1656
-
if (ret && use_defaults)
1657
-
t->scl_int_delay_ns = 0;
1658
-
1659
-
ret = device_property_read_u32(dev, "i2c-sda-falling-time-ns", &t->sda_fall_ns);
1660
-
if (ret && use_defaults)
1661
-
t->sda_fall_ns = t->scl_fall_ns;
1662
-
1663
-
ret = device_property_read_u32(dev, "i2c-sda-hold-time-ns", &t->sda_hold_ns);
1664
-
if (ret && use_defaults)
1665
-
t->sda_hold_ns = 0;
1666
-
1667
-
ret = device_property_read_u32(dev, "i2c-digital-filter-width-ns", &t->digital_filter_width_ns);
1668
-
if (ret && use_defaults)
1669
-
t->digital_filter_width_ns = 0;
1670
-
1671
-
ret = device_property_read_u32(dev, "i2c-analog-filter-cutoff-frequency", &t->analog_filter_cutoff_freq_hz);
1672
-
if (ret && use_defaults)
1673
-
t->analog_filter_cutoff_freq_hz = 0;
1632
+
i2c_parse_timing(dev, "i2c-scl-internal-delay-ns",
1633
+
&t->scl_int_delay_ns, 0, u);
1634
+
i2c_parse_timing(dev, "i2c-sda-falling-time-ns", &t->sda_fall_ns,
1635
+
t->scl_fall_ns, u);
1636
+
i2c_parse_timing(dev, "i2c-sda-hold-time-ns", &t->sda_hold_ns, 0, u);
1637
+
i2c_parse_timing(dev, "i2c-digital-filter-width-ns",
1638
+
&t->digital_filter_width_ns, 0, u);
1639
+
i2c_parse_timing(dev, "i2c-analog-filter-cutoff-frequency",
1640
+
&t->analog_filter_cutoff_freq_hz, 0, u);
1674
1641
}
1675
1642
EXPORT_SYMBOL_GPL(i2c_parse_fw_timings);
1676
1643
···
2186
2195
const unsigned short *address_list;
2187
2196
struct i2c_client *temp_client;
2188
2197
int i, err = 0;
2189
-
int adap_id = i2c_adapter_id(adapter);
2190
2198
2191
2199
address_list = driver->address_list;
2192
2200
if (!driver->detect || !address_list)
···
2213
2223
for (i = 0; address_list[i] != I2C_CLIENT_END; i += 1) {
2214
2224
dev_dbg(&adapter->dev,
2215
2225
"found normal entry for adapter %d, addr 0x%02x\n",
2216
-
adap_id, address_list[i]);
2226
+
i2c_adapter_id(adapter), address_list[i]);
2217
2227
temp_client->addr = address_list[i];
2218
2228
err = i2c_detect_address(temp_client, driver);
2219
2229
if (unlikely(err))
+3
-3
drivers/i2c/i2c-core.h
+3
-3
drivers/i2c/i2c-core.h
···
23
23
unsigned int num_resources);
24
24
25
25
/*
26
-
* We only allow atomic transfers for very late communication, e.g. to send
27
-
* the powerdown command to a PMIC. Atomic transfers are a corner case and not
28
-
* for generic use!
26
+
* We only allow atomic transfers for very late communication, e.g. to access a
27
+
* PMIC when powering down. Atomic transfers are a corner case and not for
28
+
* generic use!
29
29
*/
30
30
static inline bool i2c_in_atomic_xfer_mode(void)
31
31
{
+32
-7
drivers/i2c/i2c-slave-eeprom.c
+32
-7
drivers/i2c/i2c-slave-eeprom.c
···
5
5
* Copyright (C) 2014 by Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6
6
* Copyright (C) 2014 by Renesas Electronics Corporation
7
7
*
8
-
* Because most IP blocks can only detect one I2C slave address anyhow, this
9
-
* driver does not support simulating EEPROM types which take more than one
10
-
* address. It is prepared to simulate bigger EEPROMs with an internal 16 bit
11
-
* pointer, yet implementation is deferred until the need actually arises.
8
+
* Because most slave IP cores can only detect one I2C slave address anyhow,
9
+
* this driver does not support simulating EEPROM types which take more than
10
+
* one address.
12
11
*/
13
12
14
13
/*
···
17
18
*/
18
19
19
20
#include <linux/bitfield.h>
21
+
#include <linux/firmware.h>
20
22
#include <linux/i2c.h>
21
23
#include <linux/init.h>
22
24
#include <linux/module.h>
···
40
40
#define I2C_SLAVE_BYTELEN GENMASK(15, 0)
41
41
#define I2C_SLAVE_FLAG_ADDR16 BIT(16)
42
42
#define I2C_SLAVE_FLAG_RO BIT(17)
43
-
#define I2C_SLAVE_DEVICE_MAGIC(_len, _flags) ((_flags) | (_len))
43
+
#define I2C_SLAVE_DEVICE_MAGIC(_len, _flags) ((_flags) | ((_len) - 1))
44
44
45
45
static int i2c_slave_eeprom_slave_cb(struct i2c_client *client,
46
46
enum i2c_slave_event event, u8 *val)
···
120
120
return count;
121
121
}
122
122
123
+
static int i2c_slave_init_eeprom_data(struct eeprom_data *eeprom, struct i2c_client *client,
124
+
unsigned int size)
125
+
{
126
+
const struct firmware *fw;
127
+
const char *eeprom_data;
128
+
int ret = device_property_read_string(&client->dev, "firmware-name", &eeprom_data);
129
+
130
+
if (!ret) {
131
+
ret = request_firmware_into_buf(&fw, eeprom_data, &client->dev,
132
+
eeprom->buffer, size);
133
+
if (ret)
134
+
return ret;
135
+
release_firmware(fw);
136
+
} else {
137
+
/* An empty eeprom typically has all bits set to 1 */
138
+
memset(eeprom->buffer, 0xff, size);
139
+
}
140
+
return 0;
141
+
}
142
+
123
143
static int i2c_slave_eeprom_probe(struct i2c_client *client, const struct i2c_device_id *id)
124
144
{
125
145
struct eeprom_data *eeprom;
126
146
int ret;
127
-
unsigned int size = FIELD_GET(I2C_SLAVE_BYTELEN, id->driver_data);
147
+
unsigned int size = FIELD_GET(I2C_SLAVE_BYTELEN, id->driver_data) + 1;
128
148
unsigned int flag_addr16 = FIELD_GET(I2C_SLAVE_FLAG_ADDR16, id->driver_data);
129
149
130
150
eeprom = devm_kzalloc(&client->dev, sizeof(struct eeprom_data) + size, GFP_KERNEL);
131
151
if (!eeprom)
132
152
return -ENOMEM;
133
153
134
-
eeprom->idx_write_cnt = 0;
135
154
eeprom->num_address_bytes = flag_addr16 ? 2 : 1;
136
155
eeprom->address_mask = size - 1;
137
156
eeprom->read_only = FIELD_GET(I2C_SLAVE_FLAG_RO, id->driver_data);
138
157
spin_lock_init(&eeprom->buffer_lock);
139
158
i2c_set_clientdata(client, eeprom);
159
+
160
+
ret = i2c_slave_init_eeprom_data(eeprom, client, size);
161
+
if (ret)
162
+
return ret;
140
163
141
164
sysfs_bin_attr_init(&eeprom->bin);
142
165
eeprom->bin.attr.name = "slave-eeprom";
···
198
175
{ "slave-24c32ro", I2C_SLAVE_DEVICE_MAGIC(32768 / 8, I2C_SLAVE_FLAG_ADDR16 | I2C_SLAVE_FLAG_RO) },
199
176
{ "slave-24c64", I2C_SLAVE_DEVICE_MAGIC(65536 / 8, I2C_SLAVE_FLAG_ADDR16) },
200
177
{ "slave-24c64ro", I2C_SLAVE_DEVICE_MAGIC(65536 / 8, I2C_SLAVE_FLAG_ADDR16 | I2C_SLAVE_FLAG_RO) },
178
+
{ "slave-24c512", I2C_SLAVE_DEVICE_MAGIC(524288 / 8, I2C_SLAVE_FLAG_ADDR16) },
179
+
{ "slave-24c512ro", I2C_SLAVE_DEVICE_MAGIC(524288 / 8, I2C_SLAVE_FLAG_ADDR16 | I2C_SLAVE_FLAG_RO) },
201
180
{ }
202
181
};
203
182
MODULE_DEVICE_TABLE(i2c, i2c_slave_eeprom_id);
+103
-1
drivers/i2c/i2c-smbus.c
+103
-1
drivers/i2c/i2c-smbus.c
···
3
3
* i2c-smbus.c - SMBus extensions to the I2C protocol
4
4
*
5
5
* Copyright (C) 2008 David Brownell
6
-
* Copyright (C) 2010 Jean Delvare <jdelvare@suse.de>
6
+
* Copyright (C) 2010-2019 Jean Delvare <jdelvare@suse.de>
7
7
*/
8
8
9
9
#include <linux/device.h>
10
+
#include <linux/dmi.h>
10
11
#include <linux/i2c.h>
11
12
#include <linux/i2c-smbus.h>
12
13
#include <linux/interrupt.h>
···
196
195
EXPORT_SYMBOL_GPL(i2c_handle_smbus_alert);
197
196
198
197
module_i2c_driver(smbalert_driver);
198
+
199
+
/*
200
+
* SPD is not part of SMBus but we include it here for convenience as the
201
+
* target systems are the same.
202
+
* Restrictions to automatic SPD instantiation:
203
+
* - Only works if all filled slots have the same memory type
204
+
* - Only works for DDR2, DDR3 and DDR4 for now
205
+
* - Only works on systems with 1 to 4 memory slots
206
+
*/
207
+
#if IS_ENABLED(CONFIG_DMI)
208
+
void i2c_register_spd(struct i2c_adapter *adap)
209
+
{
210
+
int n, slot_count = 0, dimm_count = 0;
211
+
u16 handle;
212
+
u8 common_mem_type = 0x0, mem_type;
213
+
u64 mem_size;
214
+
const char *name;
215
+
216
+
while ((handle = dmi_memdev_handle(slot_count)) != 0xffff) {
217
+
slot_count++;
218
+
219
+
/* Skip empty slots */
220
+
mem_size = dmi_memdev_size(handle);
221
+
if (!mem_size)
222
+
continue;
223
+
224
+
/* Skip undefined memory type */
225
+
mem_type = dmi_memdev_type(handle);
226
+
if (mem_type <= 0x02) /* Invalid, Other, Unknown */
227
+
continue;
228
+
229
+
if (!common_mem_type) {
230
+
/* First filled slot */
231
+
common_mem_type = mem_type;
232
+
} else {
233
+
/* Check that all filled slots have the same type */
234
+
if (mem_type != common_mem_type) {
235
+
dev_warn(&adap->dev,
236
+
"Different memory types mixed, not instantiating SPD\n");
237
+
return;
238
+
}
239
+
}
240
+
dimm_count++;
241
+
}
242
+
243
+
/* No useful DMI data, bail out */
244
+
if (!dimm_count)
245
+
return;
246
+
247
+
dev_info(&adap->dev, "%d/%d memory slots populated (from DMI)\n",
248
+
dimm_count, slot_count);
249
+
250
+
if (slot_count > 4) {
251
+
dev_warn(&adap->dev,
252
+
"Systems with more than 4 memory slots not supported yet, not instantiating SPD\n");
253
+
return;
254
+
}
255
+
256
+
switch (common_mem_type) {
257
+
case 0x13: /* DDR2 */
258
+
case 0x18: /* DDR3 */
259
+
case 0x1C: /* LPDDR2 */
260
+
case 0x1D: /* LPDDR3 */
261
+
name = "spd";
262
+
break;
263
+
case 0x1A: /* DDR4 */
264
+
case 0x1E: /* LPDDR4 */
265
+
name = "ee1004";
266
+
break;
267
+
default:
268
+
dev_info(&adap->dev,
269
+
"Memory type 0x%02x not supported yet, not instantiating SPD\n",
270
+
common_mem_type);
271
+
return;
272
+
}
273
+
274
+
/*
275
+
* We don't know in which slots the memory modules are. We could
276
+
* try to guess from the slot names, but that would be rather complex
277
+
* and unreliable, so better probe all possible addresses until we
278
+
* have found all memory modules.
279
+
*/
280
+
for (n = 0; n < slot_count && dimm_count; n++) {
281
+
struct i2c_board_info info;
282
+
unsigned short addr_list[2];
283
+
284
+
memset(&info, 0, sizeof(struct i2c_board_info));
285
+
strlcpy(info.type, name, I2C_NAME_SIZE);
286
+
addr_list[0] = 0x50 + n;
287
+
addr_list[1] = I2C_CLIENT_END;
288
+
289
+
if (!IS_ERR(i2c_new_scanned_device(adap, &info, addr_list, NULL))) {
290
+
dev_info(&adap->dev,
291
+
"Successfully instantiated SPD at 0x%hx\n",
292
+
addr_list[0]);
293
+
dimm_count--;
294
+
}
295
+
}
296
+
}
297
+
EXPORT_SYMBOL_GPL(i2c_register_spd);
298
+
#endif
199
299
200
300
MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
201
301
MODULE_DESCRIPTION("SMBus protocol extensions support");
+16
-28
drivers/i2c/muxes/i2c-mux-pca954x.c
+16
-28
drivers/i2c/muxes/i2c-mux-pca954x.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
1
2
/*
2
3
* I2C multiplexer
3
4
*
4
5
* Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it>
5
6
* Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it>
6
7
*
7
-
* This module supports the PCA954x and PCA954x series of I2C multiplexer/switch
8
+
* This module supports the PCA954x and PCA984x series of I2C multiplexer/switch
8
9
* chips made by NXP Semiconductors.
9
10
* This includes the:
10
11
* PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547,
···
30
29
* i2c-virtual_cb.c from Brian Kuschak <bkuschak@yahoo.com>
31
30
* and
32
31
* pca9540.c from Jean Delvare <jdelvare@suse.de>.
33
-
*
34
-
* This file is licensed under the terms of the GNU General Public
35
-
* License version 2. This program is licensed "as is" without any
36
-
* warranty of any kind, whether express or implied.
37
32
*/
38
33
39
34
#include <linux/device.h>
···
40
43
#include <linux/interrupt.h>
41
44
#include <linux/irq.h>
42
45
#include <linux/module.h>
43
-
#include <linux/of.h>
44
-
#include <linux/of_device.h>
45
-
#include <linux/of_irq.h>
46
46
#include <linux/pm.h>
47
+
#include <linux/property.h>
47
48
#include <linux/slab.h>
48
49
#include <linux/spinlock.h>
49
50
#include <dt-bindings/mux/mux.h>
···
193
198
};
194
199
MODULE_DEVICE_TABLE(i2c, pca954x_id);
195
200
196
-
#ifdef CONFIG_OF
197
201
static const struct of_device_id pca954x_of_match[] = {
198
202
{ .compatible = "nxp,pca9540", .data = &chips[pca_9540] },
199
203
{ .compatible = "nxp,pca9542", .data = &chips[pca_9542] },
···
209
215
{}
210
216
};
211
217
MODULE_DEVICE_TABLE(of, pca954x_of_match);
212
-
#endif
213
218
214
219
/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer()
215
220
for this as they will try to lock adapter a second time */
···
320
327
static irqreturn_t pca954x_irq_handler(int irq, void *dev_id)
321
328
{
322
329
struct pca954x *data = dev_id;
323
-
unsigned int child_irq;
324
-
int ret, i, handled = 0;
330
+
unsigned long pending;
331
+
int ret, i;
325
332
326
333
ret = i2c_smbus_read_byte(data->client);
327
334
if (ret < 0)
328
335
return IRQ_NONE;
329
336
330
-
for (i = 0; i < data->chip->nchans; i++) {
331
-
if (ret & BIT(PCA954X_IRQ_OFFSET + i)) {
332
-
child_irq = irq_linear_revmap(data->irq, i);
333
-
handle_nested_irq(child_irq);
334
-
handled++;
335
-
}
336
-
}
337
-
return handled ? IRQ_HANDLED : IRQ_NONE;
337
+
pending = (ret >> PCA954X_IRQ_OFFSET) & (BIT(data->chip->nchans) - 1);
338
+
for_each_set_bit(i, &pending, data->chip->nchans)
339
+
handle_nested_irq(irq_linear_revmap(data->irq, i));
340
+
341
+
return IRQ_RETVAL(pending);
338
342
}
339
343
340
344
static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type)
···
380
390
static void pca954x_cleanup(struct i2c_mux_core *muxc)
381
391
{
382
392
struct pca954x *data = i2c_mux_priv(muxc);
383
-
struct i2c_client *client = data->client;
384
393
int c, irq;
385
-
386
-
device_remove_file(&client->dev, &dev_attr_idle_state);
387
394
388
395
if (data->irq) {
389
396
for (c = 0; c < data->chip->nchans; c++) {
···
416
429
{
417
430
struct i2c_adapter *adap = client->adapter;
418
431
struct device *dev = &client->dev;
419
-
struct device_node *np = dev->of_node;
420
432
struct gpio_desc *gpio;
421
433
struct i2c_mux_core *muxc;
422
434
struct pca954x *data;
···
445
459
udelay(1);
446
460
}
447
461
448
-
data->chip = of_device_get_match_data(dev);
462
+
data->chip = device_get_match_data(dev);
449
463
if (!data->chip)
450
464
data->chip = &chips[id->driver_data];
451
465
···
467
481
}
468
482
469
483
data->idle_state = MUX_IDLE_AS_IS;
470
-
if (of_property_read_u32(np, "idle-state", &data->idle_state)) {
471
-
if (np && of_property_read_bool(np, "i2c-mux-idle-disconnect"))
484
+
if (device_property_read_u32(dev, "idle-state", &data->idle_state)) {
485
+
if (device_property_read_bool(dev, "i2c-mux-idle-disconnect"))
472
486
data->idle_state = MUX_IDLE_DISCONNECT;
473
487
}
474
488
···
525
539
{
526
540
struct i2c_mux_core *muxc = i2c_get_clientdata(client);
527
541
542
+
device_remove_file(&client->dev, &dev_attr_idle_state);
543
+
528
544
pca954x_cleanup(muxc);
529
545
return 0;
530
546
}
···
553
565
.driver = {
554
566
.name = "pca954x",
555
567
.pm = &pca954x_pm,
556
-
.of_match_table = of_match_ptr(pca954x_of_match),
568
+
.of_match_table = pca954x_of_match,
557
569
},
558
570
.probe = pca954x_probe,
559
571
.remove = pca954x_remove,
+7
-4
drivers/platform/mellanox/mlxreg-hotplug.c
+7
-4
drivers/platform/mellanox/mlxreg-hotplug.c
···
101
101
struct mlxreg_core_data *data)
102
102
{
103
103
struct mlxreg_core_hotplug_platform_data *pdata;
104
+
struct i2c_client *client;
104
105
105
106
/* Notify user by sending hwmon uevent. */
106
107
kobject_uevent(&priv->hwmon->kobj, KOBJ_CHANGE);
···
122
121
return -EFAULT;
123
122
}
124
123
125
-
data->hpdev.client = i2c_new_device(data->hpdev.adapter,
126
-
data->hpdev.brdinfo);
127
-
if (!data->hpdev.client) {
124
+
client = i2c_new_client_device(data->hpdev.adapter,
125
+
data->hpdev.brdinfo);
126
+
if (IS_ERR(client)) {
128
127
dev_err(priv->dev, "Failed to create client %s at bus %d at addr 0x%02x\n",
129
128
data->hpdev.brdinfo->type, data->hpdev.nr +
130
129
pdata->shift_nr, data->hpdev.brdinfo->addr);
131
130
132
131
i2c_put_adapter(data->hpdev.adapter);
133
132
data->hpdev.adapter = NULL;
134
-
return -EFAULT;
133
+
return PTR_ERR(client);
135
134
}
135
+
136
+
data->hpdev.client = client;
136
137
137
138
return 0;
138
139
}
+7
-1
include/linux/i2c-smbus.h
+7
-1
include/linux/i2c-smbus.h
···
2
2
/*
3
3
* i2c-smbus.h - SMBus extensions to the I2C protocol
4
4
*
5
-
* Copyright (C) 2010 Jean Delvare <jdelvare@suse.de>
5
+
* Copyright (C) 2010-2019 Jean Delvare <jdelvare@suse.de>
6
6
*/
7
7
8
8
#ifndef _LINUX_I2C_SMBUS_H
···
37
37
{
38
38
return 0;
39
39
}
40
+
#endif
41
+
42
+
#if IS_ENABLED(CONFIG_I2C_SMBUS) && IS_ENABLED(CONFIG_DMI)
43
+
void i2c_register_spd(struct i2c_adapter *adap);
44
+
#else
45
+
static inline void i2c_register_spd(struct i2c_adapter *adap) { }
40
46
#endif
41
47
42
48
#endif /* _LINUX_I2C_SMBUS_H */
+4
-4
include/linux/i2c.h
+4
-4
include/linux/i2c.h
···
351
351
return to_i2c_client(dev);
352
352
}
353
353
354
-
static inline void *i2c_get_clientdata(const struct i2c_client *dev)
354
+
static inline void *i2c_get_clientdata(const struct i2c_client *client)
355
355
{
356
-
return dev_get_drvdata(&dev->dev);
356
+
return dev_get_drvdata(&client->dev);
357
357
}
358
358
359
-
static inline void i2c_set_clientdata(struct i2c_client *dev, void *data)
359
+
static inline void i2c_set_clientdata(struct i2c_client *client, void *data)
360
360
{
361
-
dev_set_drvdata(&dev->dev, data);
361
+
dev_set_drvdata(&client->dev, data);
362
362
}
363
363
364
364
/* I2C slave support */
-48
include/linux/platform_data/i2c-pxa.h
-48
include/linux/platform_data/i2c-pxa.h
···
7
7
#ifndef _I2C_PXA_H_
8
8
#define _I2C_PXA_H_
9
9
10
-
#if 0
11
-
#define DEF_TIMEOUT 3
12
-
#else
13
-
/* need a longer timeout if we're dealing with the fact we may well be
14
-
* looking at a multi-master environment
15
-
*/
16
-
#define DEF_TIMEOUT 32
17
-
#endif
18
-
19
-
#define BUS_ERROR (-EREMOTEIO)
20
-
#define XFER_NAKED (-ECONNREFUSED)
21
-
#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
22
-
23
-
/* ICR initialize bit values
24
-
*
25
-
* 15. FM 0 (100 Khz operation)
26
-
* 14. UR 0 (No unit reset)
27
-
* 13. SADIE 0 (Disables the unit from interrupting on slave addresses
28
-
* matching its slave address)
29
-
* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration
30
-
* in master mode)
31
-
* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
32
-
* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
33
-
* 9. IRFIE 1 (Enable interrupts from full buffer received)
34
-
* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
35
-
* 7. GCD 1 (Disables i2c unit response to general call messages as a slave)
36
-
* 6. IUE 0 (Disable unit until we change settings)
37
-
* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
38
-
* 4. MA 0 (Only send stop with the ICR stop bit)
39
-
* 3. TB 0 (We are not transmitting a byte initially)
40
-
* 2. ACKNAK 0 (Send an ACK after the unit receives a byte)
41
-
* 1. STOP 0 (Do not send a STOP)
42
-
* 0. START 0 (Do not send a START)
43
-
*
44
-
*/
45
-
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
46
-
47
-
/* I2C status register init values
48
-
*
49
-
* 10. BED 1 (Clear bus error detected)
50
-
* 9. SAD 1 (Clear slave address detected)
51
-
* 7. IRF 1 (Clear IDBR Receive Full)
52
-
* 6. ITE 1 (Clear IDBR Transmit Empty)
53
-
* 5. ALD 1 (Clear Arbitration Loss Detected)
54
-
* 4. SSD 1 (Clear Slave Stop Detected)
55
-
*/
56
-
#define I2C_ISR_INIT 0x7FF /* status register init */
57
-
58
10
struct i2c_pxa_platform_data {
59
11
unsigned int class;
60
12
unsigned int use_pio :1;