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drm/i915/cx0: Toggle powerdown states for C10 on HDMI

A new step has been added to Bspec with respect to the C10 PHY, which
instructs the driver to toggle powerdown value for boths PHY lanes to P0
and then P2 when driving an HDMI connector. This update in the Bspec
reflects the changes required by Wa_14026084006, so document it.

Note that, unlike other display workarounds, this one is actually tied
to the C10 PHY and not to a specific display IP. As such, let's just
document it in intel_cx0_phy.c instead of adding it to
intel_display_wa.c.

Bspec: 64568, 74489
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20251216-wa_14026084006-c10-hdmi-toggle-powerdown-v1-2-08677b03e2f1@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Gustavo Sousa 9236cf0a c954d3b5

+15
+15
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 3302 3302 * Frequency Change. We handle this step in bxt_set_cdclk(). 3303 3303 */ 3304 3304 3305 + /* 3306 + * 12. Toggle powerdown if HDMI is enabled on C10 PHY. 3307 + * 3308 + * Wa_13013502646: 3309 + * Fixes: HDMI lane to lane skew violations on C10 display PHYs. 3310 + * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both 3311 + * PHY lanes. 3312 + */ 3313 + if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) { 3314 + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3315 + XELPDP_P0_STATE_ACTIVE); 3316 + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3317 + XELPDP_P2_STATE_READY); 3318 + } 3319 + 3305 3320 intel_cx0_phy_transaction_end(encoder, wakeref); 3306 3321 } 3307 3322