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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: clock: document Amlogic S4 SoC PLL clock controller
Add the S4 PLL clock controller dt-bindings in the S4 SoC family.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230904075504.23263-2-yu.tu@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Yu Tu
and committed by
Jerome Brunet
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0bb80ecc
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Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
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Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic S4 PLL Clock Controller
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maintainers:
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- Yu Tu <yu.tu@amlogic.com>
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properties:
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compatible:
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const: amlogic,s4-pll-clkc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: xtal
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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clkc_pll: clock-controller@fe008000 {
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compatible = "amlogic,s4-pll-clkc";
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reg = <0xfe008000 0x1e8>;
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clocks = <&xtal>;
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clock-names = "xtal";
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#clock-cells = <1>;
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};
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...
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include/dt-bindings/clock/amlogic,s4-pll-clkc.h
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include/dt-bindings/clock/amlogic,s4-pll-clkc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
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* Author: Yu Tu <yu.tu@amlogic.com>
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
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#define CLKID_FIXED_PLL_DCO 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2_DIV 2
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#define CLKID_FCLK_DIV2 3
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#define CLKID_FCLK_DIV3_DIV 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4_DIV 6
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#define CLKID_FCLK_DIV4 7
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#define CLKID_FCLK_DIV5_DIV 8
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#define CLKID_FCLK_DIV5 9
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#define CLKID_FCLK_DIV7_DIV 10
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#define CLKID_FCLK_DIV7 11
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#define CLKID_FCLK_DIV2P5_DIV 12
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#define CLKID_FCLK_DIV2P5 13
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#define CLKID_GP0_PLL_DCO 14
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#define CLKID_GP0_PLL 15
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#define CLKID_HIFI_PLL_DCO 16
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#define CLKID_HIFI_PLL 17
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#define CLKID_HDMI_PLL_DCO 18
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#define CLKID_HDMI_PLL_OD 19
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#define CLKID_HDMI_PLL 20
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#define CLKID_MPLL_50M_DIV 21
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#define CLKID_MPLL_50M 22
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#define CLKID_MPLL_PREDIV 23
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#define CLKID_MPLL0_DIV 24
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#define CLKID_MPLL0 25
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#define CLKID_MPLL1_DIV 26
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#define CLKID_MPLL1 27
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#define CLKID_MPLL2_DIV 28
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#define CLKID_MPLL2 29
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#define CLKID_MPLL3_DIV 30
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#define CLKID_MPLL3 31
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */