Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes
Fix the naming inconsistencies for some of the functions and global
variables:
* Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable
* Replace '_ropll_tmds_' with '_tmds_ropll_' globally
* Replace 'hdtpx' with 'hdptx' globally
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-4-8d5f97419c0b@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Cristian Ciocaltea
and committed by
Vinod Koul
925f26a4
4f310f18
+31
-31
+31
-31
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+31
-31
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
···
32
32
#define HDPTX_O_PHY_RDY BIT(1)
33
33
#define HDPTX_O_SB_RDY BIT(0)
34
34
35
-
#define HDTPX_REG(_n, _min, _max) \
35
+
#define HDPTX_REG(_n, _min, _max) \
36
36
( \
37
37
BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
38
38
BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
39
39
((0x##_n) * 4) \
40
40
)
41
41
42
-
#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
43
-
#define SB_REG(n) HDTPX_REG(n, 0100, 0129)
44
-
#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
45
-
#define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
42
+
#define CMN_REG(n) HDPTX_REG(n, 0000, 00a7)
43
+
#define SB_REG(n) HDPTX_REG(n, 0100, 0129)
44
+
#define LNTOP_REG(n) HDPTX_REG(n, 0200, 0229)
45
+
#define LANE_REG(n) HDPTX_REG(n, 0300, 062d)
46
46
47
47
/* CMN_REG(0008) */
48
48
#define OVRD_LCPLL_EN_MASK BIT(7)
···
397
397
unsigned int lanes;
398
398
};
399
399
400
-
static const struct ropll_config ropll_tmds_cfg[] = {
400
+
static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
401
401
/* | pms | sdm | sdc | */
402
402
/* rate, mdiv, mdafc, pdiv, rdiv, sdiv, en, deno, nsig, num, n, num, deno, */
403
403
{ 594000000ULL, 124, 124, 1, 1, 0, 1, 62, 1, 16, 5, 0, 1, },
···
424
424
{ 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, 1, 1, },
425
425
};
426
426
427
-
static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
427
+
static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
428
428
REG_SEQ0(CMN_REG(0009), 0x0c),
429
429
REG_SEQ0(CMN_REG(000a), 0x83),
430
430
REG_SEQ0(CMN_REG(000b), 0x06),
···
514
514
REG_SEQ0(CMN_REG(009b), 0x10),
515
515
};
516
516
517
-
static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
517
+
static const struct reg_sequence rk_hdptx_tmds_cmn_init_seq[] = {
518
518
REG_SEQ0(CMN_REG(0008), 0x00),
519
519
REG_SEQ0(CMN_REG(0011), 0x01),
520
520
REG_SEQ0(CMN_REG(0017), 0x20),
···
556
556
REG_SEQ0(CMN_REG(009b), 0x00),
557
557
};
558
558
559
-
static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
559
+
static const struct reg_sequence rk_hdptx_common_sb_init_seq[] = {
560
560
REG_SEQ0(SB_REG(0114), 0x00),
561
561
REG_SEQ0(SB_REG(0115), 0x00),
562
562
REG_SEQ0(SB_REG(0116), 0x00),
563
563
REG_SEQ0(SB_REG(0117), 0x00),
564
564
};
565
565
566
-
static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
566
+
static const struct reg_sequence rk_hdptx_tmds_lntop_highbr_seq[] = {
567
567
REG_SEQ0(LNTOP_REG(0201), 0x00),
568
568
REG_SEQ0(LNTOP_REG(0202), 0x00),
569
569
REG_SEQ0(LNTOP_REG(0203), 0x0f),
···
571
571
REG_SEQ0(LNTOP_REG(0205), 0xff),
572
572
};
573
573
574
-
static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
574
+
static const struct reg_sequence rk_hdptx_tmds_lntop_lowbr_seq[] = {
575
575
REG_SEQ0(LNTOP_REG(0201), 0x07),
576
576
REG_SEQ0(LNTOP_REG(0202), 0xc1),
577
577
REG_SEQ0(LNTOP_REG(0203), 0xf0),
···
579
579
REG_SEQ0(LNTOP_REG(0205), 0x1f),
580
580
};
581
581
582
-
static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
582
+
static const struct reg_sequence rk_hdptx_common_lane_init_seq[] = {
583
583
REG_SEQ0(LANE_REG(0303), 0x0c),
584
584
REG_SEQ0(LANE_REG(0307), 0x20),
585
585
REG_SEQ0(LANE_REG(030a), 0x17),
···
634
634
REG_SEQ0(LANE_REG(0620), 0xa0),
635
635
};
636
636
637
-
static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
637
+
static const struct reg_sequence rk_hdptx_tmds_lane_init_seq[] = {
638
638
REG_SEQ0(LANE_REG(0312), 0x00),
639
639
REG_SEQ0(LANE_REG(0412), 0x00),
640
640
REG_SEQ0(LANE_REG(0512), 0x00),
···
938
938
return true;
939
939
}
940
940
941
-
static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
941
+
static int rk_hdptx_tmds_ropll_cmn_config(struct rk_hdptx_phy *hdptx)
942
942
{
943
943
const struct ropll_config *cfg = NULL;
944
944
struct ropll_config rc = {0};
···
947
947
if (!hdptx->hdmi_cfg.tmds_char_rate)
948
948
return 0;
949
949
950
-
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
951
-
if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
952
-
cfg = &ropll_tmds_cfg[i];
950
+
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
951
+
if (hdptx->hdmi_cfg.tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate) {
952
+
cfg = &rk_hdptx_tmds_ropll_cfg[i];
953
953
break;
954
954
}
955
955
···
969
969
970
970
rk_hdptx_pre_power_up(hdptx);
971
971
972
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
973
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
972
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq);
973
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq);
974
974
975
975
regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
976
976
regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
···
1012
1012
return ret;
1013
1013
}
1014
1014
1015
-
static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
1015
+
static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
1016
1016
{
1017
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
1017
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_sb_init_seq);
1018
1018
1019
1019
regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
1020
1020
1021
1021
if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
1022
1022
/* For 1/40 bitrate clk */
1023
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
1023
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_highbr_seq);
1024
1024
} else {
1025
1025
/* For 1/10 bitrate clk */
1026
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
1026
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lntop_lowbr_seq);
1027
1027
}
1028
1028
1029
1029
regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
1030
1030
regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
1031
1031
1032
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
1033
-
rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
1032
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq);
1033
+
rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq);
1034
1034
1035
1035
return rk_hdptx_post_enable_lane(hdptx);
1036
1036
}
···
1089
1089
if (mode == PHY_MODE_DP) {
1090
1090
rk_hdptx_dp_reset(hdptx);
1091
1091
} else {
1092
-
ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
1092
+
ret = rk_hdptx_tmds_ropll_cmn_config(hdptx);
1093
1093
if (ret)
1094
1094
goto dec_usage;
1095
1095
}
···
1436
1436
regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1437
1437
HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1438
1438
1439
-
ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
1439
+
ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
1440
1440
if (ret)
1441
1441
rk_hdptx_phy_consumer_put(hdptx, true);
1442
1442
}
···
1459
1459
if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
1460
1460
return -EINVAL;
1461
1461
1462
-
for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1463
-
if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate)
1462
+
for (i = 0; i < ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg); i++)
1463
+
if (hdmi->tmds_char_rate == rk_hdptx_tmds_ropll_cfg[i].rate)
1464
1464
break;
1465
1465
1466
-
if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
1466
+
if (i == ARRAY_SIZE(rk_hdptx_tmds_ropll_cfg) &&
1467
1467
!rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
1468
1468
return -EINVAL;
1469
1469
···
1891
1891
* while the latter being executed only once, i.e. when clock remains
1892
1892
* in the prepared state during rate changes.
1893
1893
*/
1894
-
return rk_hdptx_ropll_tmds_cmn_config(hdptx);
1894
+
return rk_hdptx_tmds_ropll_cmn_config(hdptx);
1895
1895
}
1896
1896
1897
1897
static const struct clk_ops hdptx_phy_clk_ops = {