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dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector

Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined
in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector
provides interfaces like PCIe and SATA to attach the Solid State Drives
(SSDs) to the host machine along with additional interfaces like USB, and
SMBus for debugging and supplementary features.

The connector provides a primary power supply of 3.3v, along with an
optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at
1.8v sideband signaling.

The connector also supplies optional signals in the form of GPIOs for fine
grained power management.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260122-pci-m2-v6-1-575da9f97239@oss.qualcomm.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

authored by

Manivannan Sadhasivam and committed by
Bartosz Golaszewski 926194a6 0eb85f46

+145
+145
Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: PCIe M.2 Mechanical Key M Connector 8 + 9 + maintainers: 10 + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> 11 + 12 + description: 13 + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M 14 + connector. The Mechanical Key M connectors are used to connect SSDs to the 15 + host system over PCIe/SATA interfaces. These connectors also offer optional 16 + interfaces like USB, SMBus. 17 + 18 + properties: 19 + compatible: 20 + const: pcie-m2-m-connector 21 + 22 + vpcie3v3-supply: 23 + description: A phandle to the regulator for 3.3v supply. 24 + 25 + vpcie1v8-supply: 26 + description: A phandle to the regulator for VIO 1.8v supply. 27 + 28 + ports: 29 + $ref: /schemas/graph.yaml#/properties/ports 30 + description: OF graph bindings modeling the interfaces exposed on the 31 + connector. Since a single connector can have multiple interfaces, every 32 + interface has an assigned OF graph port number as described below. 33 + 34 + properties: 35 + port@0: 36 + $ref: /schemas/graph.yaml#/properties/port 37 + description: PCIe interface 38 + 39 + port@1: 40 + $ref: /schemas/graph.yaml#/properties/port 41 + description: SATA interface 42 + 43 + port@2: 44 + $ref: /schemas/graph.yaml#/properties/port 45 + description: USB 2.0 interface 46 + 47 + anyOf: 48 + - required: 49 + - port@0 50 + - required: 51 + - port@1 52 + 53 + i2c-parent: 54 + $ref: /schemas/types.yaml#/definitions/phandle 55 + description: I2C interface 56 + 57 + clocks: 58 + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to 59 + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for 60 + more details. 61 + maxItems: 1 62 + 63 + pedet-gpios: 64 + description: GPIO input to PEDET signal. This signal is used by the host 65 + systems to determine the communication protocol that the M.2 card uses; 66 + SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2 67 + Specification r4.0, sec 3.3.4.2 for more details. 68 + maxItems: 1 69 + 70 + viocfg-gpios: 71 + description: GPIO input to IO voltage configuration (VIO_CFG) signal. This 72 + signal is used by the host systems to determine whether the card supports 73 + an independent IO voltage domain for the sideband signals or not. Refer, 74 + PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details. 75 + maxItems: 1 76 + 77 + pwrdis-gpios: 78 + description: GPIO output to Power Disable (PWRDIS) signal. This signal is 79 + used by the host system to disable power on the M.2 card. Refer, PCI 80 + Express M.2 Specification r4.0, sec 3.3.5.2 for more details. 81 + maxItems: 1 82 + 83 + pln-gpios: 84 + description: GPIO output to Power Loss Notification (PLN#) signal. This 85 + signal is used by the host system to notify the M.2 card that the power 86 + loss event is about to occur. Refer, PCI Express M.2 Specification r4.0, 87 + sec 3.2.17.1 for more details. 88 + maxItems: 1 89 + 90 + plas3-gpios: 91 + description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. This 92 + signal is used by the host system to receive the acknowledgment of the M.2 93 + card's preparation for power loss. 94 + maxItems: 1 95 + 96 + required: 97 + - compatible 98 + - vpcie3v3-supply 99 + 100 + additionalProperties: false 101 + 102 + examples: 103 + # PCI M.2 Key M connector for SSDs with PCIe interface 104 + - | 105 + #include <dt-bindings/gpio/gpio.h> 106 + 107 + connector { 108 + compatible = "pcie-m2-m-connector"; 109 + vpcie3v3-supply = <&vreg_nvme>; 110 + i2c-parent = <&i2c0>; 111 + pedet-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 112 + viocfg-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 113 + pwrdis-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>; 114 + pln-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; 115 + plas3-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; 116 + 117 + ports { 118 + #address-cells = <1>; 119 + #size-cells = <0>; 120 + 121 + port@0 { 122 + #address-cells = <1>; 123 + #size-cells = <0>; 124 + 125 + reg = <0>; 126 + 127 + endpoint@0 { 128 + reg = <0>; 129 + remote-endpoint = <&pcie6_port0_ep>; 130 + }; 131 + }; 132 + 133 + port@2 { 134 + #address-cells = <1>; 135 + #size-cells = <0>; 136 + 137 + reg = <2>; 138 + 139 + endpoint@0 { 140 + reg = <0>; 141 + remote-endpoint = <&usb_hs_ep>; 142 + }; 143 + }; 144 + }; 145 + };