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clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100

X1E80100 videocc is identical to the one in SM8550, aside from slightly
different recommended PLL frequencies. Add the separate frequency tables
for that and apply them if the qcom,x1e80100-videocc compatible is used.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-3-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Stephan Gerhold and committed by
Bjorn Andersson 92640a6d b7b0799f

+30 -1
+1 -1
drivers/clk/qcom/Kconfig
··· 1429 1429 select QCOM_GDSC 1430 1430 help 1431 1431 Support for the video clock controller on Qualcomm Technologies, Inc. 1432 - SM8550 or SM8650 devices. 1432 + SM8550 or SM8650 or X1E80100 devices. 1433 1433 Say Y if you want to support video devices and functionality such as 1434 1434 video encode/decode. 1435 1435
+29
drivers/clk/qcom/videocc-sm8550.c
··· 145 145 { } 146 146 }; 147 147 148 + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_x1e80100[] = { 149 + F(576000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 150 + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 151 + F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 152 + F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 153 + F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 154 + F(1443000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), 155 + { } 156 + }; 157 + 148 158 static struct clk_rcg2 video_cc_mvs0_clk_src = { 149 159 .cmd_rcgr = 0x8000, 150 160 .mnd_width = 0, ··· 181 171 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { 182 172 F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 183 173 F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 174 + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 175 + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 176 + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 177 + { } 178 + }; 179 + 180 + static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_x1e80100[] = { 181 + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 182 + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 184 183 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 185 184 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), 186 185 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), ··· 578 559 static const struct of_device_id video_cc_sm8550_match_table[] = { 579 560 { .compatible = "qcom,sm8550-videocc" }, 580 561 { .compatible = "qcom,sm8650-videocc" }, 562 + { .compatible = "qcom,x1e80100-videocc" }, 581 563 { } 582 564 }; 583 565 MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); 584 566 585 567 static int video_cc_sm8550_probe(struct platform_device *pdev) 586 568 { 569 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,x1e80100-videocc")) { 570 + video_cc_pll0_config.l = 0x1e; 571 + video_cc_pll0_config.alpha = 0x0000; 572 + video_cc_pll1_config.l = 0x2b; 573 + video_cc_pll1_config.alpha = 0xc000; 574 + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_x1e80100; 575 + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_x1e80100; 576 + } 577 + 587 578 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { 588 579 video_cc_pll0_config.l = 0x1e; 589 580 video_cc_pll0_config.alpha = 0xa000;