Merge patch series "Update lpfc to revision 15.0.0.0"

+4 -5

drivers/scsi/lpfc/lpfc.h

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 810 810 #define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */ 811 811 #define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */ 812 812 #define LPFC_USER_LINK_SPEED_64G 64 /* 64 Gigabaud */ 813 - #define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_64G 813 + #define LPFC_USER_LINK_SPEED_128G 128 /* 128 Gigabaud */ 814 + #define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_128G 814 815 815 - #define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32, 64" 816 + #define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32, 64, 128" 816 817 817 818 enum nemb_type { 818 819 nemb_mse = 1, ··· 1016 1015 #define LPFC_SLI3_CRP_ENABLED 0x08 1017 1016 #define LPFC_SLI3_BG_ENABLED 0x20 1018 1017 #define LPFC_SLI3_DSS_ENABLED 0x40 1019 - #define LPFC_SLI4_PERFH_ENABLED 0x80 1020 1018 #define LPFC_SLI4_PHWQ_ENABLED 0x100 1021 1019 uint32_t iocb_cmd_size; 1022 1020 uint32_t iocb_rsp_size; ··· 1188 1188 uint32_t cfg_ras_fwlog_func; 1189 1189 uint32_t cfg_enable_bbcr; /* Enable BB Credit Recovery */ 1190 1190 uint32_t cfg_enable_dpp; /* Enable Direct Packet Push */ 1191 - uint32_t cfg_enable_pbde; 1192 1191 uint32_t cfg_enable_mi; 1193 1192 struct nvmet_fc_target_port *targetport; 1194 1193 lpfc_vpd_t vpd; /* vital product data */

+14 -13

drivers/scsi/lpfc/lpfc_attr.c

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 - * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * 8 8 * www.broadcom.com * ··· 4415 4415 /* 4416 4416 # lpfc_link_speed: Link speed selection for initializing the Fibre Channel 4417 4417 # connection. 4418 - # Value range is [0,16]. Default value is 0. 4418 + # Value range is [0,128]. Default value is 0. 4419 4419 */ 4420 4420 /** 4421 4421 * lpfc_link_speed_store - Set the adapters link speed ··· 4468 4468 "3055 lpfc_link_speed changed from %d to %d %s\n", 4469 4469 phba->cfg_link_speed, val, nolip ? "(nolip)" : "(lip)"); 4470 4470 4471 - if (((val == LPFC_USER_LINK_SPEED_1G) && !(phba->lmt & LMT_1Gb)) || 4472 - ((val == LPFC_USER_LINK_SPEED_2G) && !(phba->lmt & LMT_2Gb)) || 4473 - ((val == LPFC_USER_LINK_SPEED_4G) && !(phba->lmt & LMT_4Gb)) || 4474 - ((val == LPFC_USER_LINK_SPEED_8G) && !(phba->lmt & LMT_8Gb)) || 4475 - ((val == LPFC_USER_LINK_SPEED_10G) && !(phba->lmt & LMT_10Gb)) || 4476 - ((val == LPFC_USER_LINK_SPEED_16G) && !(phba->lmt & LMT_16Gb)) || 4477 - ((val == LPFC_USER_LINK_SPEED_32G) && !(phba->lmt & LMT_32Gb)) || 4478 - ((val == LPFC_USER_LINK_SPEED_64G) && !(phba->lmt & LMT_64Gb))) { 4471 + if ((val == LPFC_USER_LINK_SPEED_1G && !(phba->lmt & LMT_1Gb)) || 4472 + (val == LPFC_USER_LINK_SPEED_2G && !(phba->lmt & LMT_2Gb)) || 4473 + (val == LPFC_USER_LINK_SPEED_4G && !(phba->lmt & LMT_4Gb)) || 4474 + (val == LPFC_USER_LINK_SPEED_8G && !(phba->lmt & LMT_8Gb)) || 4475 + (val == LPFC_USER_LINK_SPEED_10G && !(phba->lmt & LMT_10Gb)) || 4476 + (val == LPFC_USER_LINK_SPEED_16G && !(phba->lmt & LMT_16Gb)) || 4477 + (val == LPFC_USER_LINK_SPEED_32G && !(phba->lmt & LMT_32Gb)) || 4478 + (val == LPFC_USER_LINK_SPEED_64G && !(phba->lmt & LMT_64Gb)) || 4479 + (val == LPFC_USER_LINK_SPEED_128G && !(phba->lmt & LMT_128Gb))) { 4479 4480 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, 4480 4481 "2879 lpfc_link_speed attribute cannot be set " 4481 4482 "to %d. Speed is not supported by this port.\n", ··· 4501 4500 case LPFC_USER_LINK_SPEED_16G: 4502 4501 case LPFC_USER_LINK_SPEED_32G: 4503 4502 case LPFC_USER_LINK_SPEED_64G: 4503 + case LPFC_USER_LINK_SPEED_128G: 4504 4504 prev_val = phba->cfg_link_speed; 4505 4505 phba->cfg_link_speed = val; 4506 4506 if (nolip) ··· 4566 4564 case LPFC_USER_LINK_SPEED_16G: 4567 4565 case LPFC_USER_LINK_SPEED_32G: 4568 4566 case LPFC_USER_LINK_SPEED_64G: 4567 + case LPFC_USER_LINK_SPEED_128G: 4569 4568 phba->cfg_link_speed = val; 4570 4569 return 0; 4571 4570 default: ··· 7469 7466 } 7470 7467 7471 7468 phba->cfg_auto_imax = (phba->cfg_fcp_imax) ? 0 : 1; 7472 - 7473 - phba->cfg_enable_pbde = 0; 7474 7469 7475 7470 /* A value of 0 means use the number of CPUs found in the system */ 7476 7471 if (phba->cfg_hdw_queue == 0)

+15 -5

drivers/scsi/lpfc/lpfc_els.c

··· 4329 4329 static bool 4330 4330 lpfc_link_is_lds_capable(struct lpfc_hba *phba) 4331 4331 { 4332 - if (!(phba->lmt & LMT_64Gb)) 4332 + if (!(phba->lmt & (LMT_64Gb | LMT_128Gb))) 4333 4333 return false; 4334 4334 if (phba->sli_rev != LPFC_SLI_REV4) 4335 4335 return false; 4336 4336 4337 4337 if (phba->sli4_hba.conf_trunk) { 4338 - if (phba->trunk_link.phy_lnk_speed == LPFC_USER_LINK_SPEED_64G) 4338 + switch (phba->trunk_link.phy_lnk_speed) { 4339 + case LPFC_USER_LINK_SPEED_128G: 4340 + case LPFC_USER_LINK_SPEED_64G: 4339 4341 return true; 4340 - } else if (phba->fc_linkspeed == LPFC_LINK_SPEED_64GHZ) { 4341 - return true; 4342 + default: 4343 + return false; 4344 + } 4342 4345 } 4343 - return false; 4346 + 4347 + switch (phba->fc_linkspeed) { 4348 + case LPFC_LINK_SPEED_128GHZ: 4349 + case LPFC_LINK_SPEED_64GHZ: 4350 + return true; 4351 + default: 4352 + return false; 4353 + } 4344 4354 } 4345 4355 4346 4356 /**

+2 -2

drivers/scsi/lpfc/lpfc_hbadisc.c

··· 3817 3817 if (phba->cmf_active_mode != LPFC_CFG_OFF) 3818 3818 lpfc_cmf_signal_init(phba); 3819 3819 3820 - if (phba->lmt & LMT_64Gb) 3820 + if (phba->lmt & (LMT_64Gb | LMT_128Gb)) 3821 3821 lpfc_read_lds_params(phba); 3822 3822 3823 3823 } else if (attn_type == LPFC_ATT_LINK_DOWN || ··· 4410 4410 LOG_INIT | LOG_ELS | LOG_DISCOVERY, 4411 4411 "4220 Issue EDC status x%x Data x%x\n", 4412 4412 rc, phba->cgn_init_reg_signal); 4413 - } else if (phba->lmt & LMT_64Gb) { 4413 + } else if (phba->lmt & (LMT_64Gb | LMT_128Gb)) { 4414 4414 /* may send link fault capability descriptor */ 4415 4415 lpfc_issue_els_edc(vport, 0); 4416 4416 } else {

+2 -1

drivers/scsi/lpfc/lpfc_hw.h

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 1771 1771 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1772 1772 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1773 1773 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1774 + #define PCI_DEVICE_ID_LANCER_G8_FC 0xd300 1774 1775 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1775 1776 #define PCI_DEVICE_ID_SAT_MID 0xf015 1776 1777 #define PCI_DEVICE_ID_RFLY 0xf095

+20 -17

drivers/scsi/lpfc/lpfc_hw4.h

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 - * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * 8 8 * www.broadcom.com * ··· 100 100 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 101 101 #define lpfc_sli_intf_sli_family_WORD word0 102 102 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 103 - #define LPFC_SLI_INTF_FAMILY_BE3 0x1 103 + #define LPFC_SLI_INTF_ASIC_ID 0x1 /* Refer to ASIC_ID register */ 104 + #define LPFC_SLI_INTF_FAMILY_BE3 0x3 104 105 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 105 106 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 106 107 #define LPFC_SLI_INTF_FAMILY_G6 0xc ··· 117 116 #define lpfc_sli_intf_func_type_WORD word0 118 117 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 119 118 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 119 + }; 120 + 121 + struct lpfc_asic_id { 122 + u32 word0; 123 + #define lpfc_asic_id_gen_num_SHIFT 8 124 + #define lpfc_asic_id_gen_num_MASK 0x000000FF 125 + #define lpfc_asic_id_gen_num_WORD word0 126 + #define LPFC_SLI_INTF_FAMILY_G8 0x10 127 + #define lpfc_asic_id_rev_num_SHIFT 0 128 + #define lpfc_asic_id_rev_num_MASK 0x000000FF 129 + #define lpfc_asic_id_rev_num_WORD word0 120 130 }; 121 131 122 132 #define LPFC_SLI4_MBX_EMBED true ··· 636 624 637 625 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 638 626 #define LPFC_PORT_SEM_MASK 0xF000 627 + 628 + /* The following are config space register offsets */ 629 + #define LPFC_ASIC_ID_OFFSET 0x0308 630 + 639 631 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 640 632 #define LPFC_UERR_STATUS_HI 0x00A4 641 633 #define LPFC_UERR_STATUS_LO 0x00A0 ··· 648 632 649 633 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 650 634 #define LPFC_SLI_INTF 0x0058 651 - #define LPFC_SLI_ASIC_VER 0x009C 652 635 653 636 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 654 637 #define lpfc_port_smphr_perr_SHIFT 31 ··· 3077 3062 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3078 3063 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3079 3064 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3080 - #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3081 - #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3082 - #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3083 3065 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3084 3066 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3085 3067 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 ··· 3108 3096 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3109 3097 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3110 3098 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3111 - #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3112 - #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3113 - #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3114 3099 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3115 3100 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3116 3101 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 ··· 3469 3460 #define cfg_pvl_SHIFT 13 3470 3461 #define cfg_pvl_MASK 0x00000001 3471 3462 #define cfg_pvl_WORD word19 3472 - 3473 - #define cfg_pbde_SHIFT 20 3474 - #define cfg_pbde_MASK 0x00000001 3475 - #define cfg_pbde_WORD word19 3476 3463 3477 3464 uint32_t word20; 3478 3465 #define cfg_max_tow_xri_SHIFT 0 ··· 4489 4484 #define wqe_irsp_SHIFT 4 4490 4485 #define wqe_irsp_MASK 0x00000001 4491 4486 #define wqe_irsp_WORD word11 4492 - #define wqe_pbde_SHIFT 5 4493 - #define wqe_pbde_MASK 0x00000001 4494 - #define wqe_pbde_WORD word11 4495 4487 #define wqe_sup_SHIFT 6 4496 4488 #define wqe_sup_MASK 0x00000001 4497 4489 #define wqe_sup_WORD word11 ··· 4980 4978 #define MAGIC_NUMBER_G6 0xFEAA0003 4981 4979 #define MAGIC_NUMBER_G7 0xFEAA0005 4982 4980 #define MAGIC_NUMBER_G7P 0xFEAA0020 4981 + #define MAGIC_NUMBER_G8 0xFEAA0070 4983 4982 4984 4983 struct lpfc_grp_hdr { 4985 4984 uint32_t size;

+3 -1

drivers/scsi/lpfc/lpfc_ids.h

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 117 117 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_G7_FC, 118 118 PCI_ANY_ID, PCI_ANY_ID, }, 119 119 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_G7P_FC, 120 + PCI_ANY_ID, PCI_ANY_ID, }, 121 + {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_G8_FC, 120 122 PCI_ANY_ID, PCI_ANY_ID, }, 121 123 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SKYHAWK, 122 124 PCI_ANY_ID, PCI_ANY_ID, },

+40 -13

drivers/scsi/lpfc/lpfc_init.c

··· 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 4 * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 - * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 5 + * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * 8 8 * www.broadcom.com * ··· 789 789 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) && 790 790 !(phba->lmt & LMT_32Gb)) || 791 791 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) && 792 - !(phba->lmt & LMT_64Gb))) { 792 + !(phba->lmt & LMT_64Gb)) || 793 + ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_128G) && 794 + !(phba->lmt & LMT_128Gb))) { 793 795 /* Reset link speed to auto */ 794 796 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, 795 797 "1302 Invalid speed for this board:%d " ··· 2537 2535 return; 2538 2536 } 2539 2537 2540 - if (phba->lmt & LMT_64Gb) 2538 + if (phba->lmt & LMT_128Gb) 2539 + max_speed = 128; 2540 + else if (phba->lmt & LMT_64Gb) 2541 2541 max_speed = 64; 2542 2542 else if (phba->lmt & LMT_32Gb) 2543 2543 max_speed = 32; ··· 2756 2752 break; 2757 2753 case PCI_DEVICE_ID_LANCER_G7P_FC: 2758 2754 m = (typeof(m)){"LPe38000", "PCIe", "Fibre Channel Adapter"}; 2755 + break; 2756 + case PCI_DEVICE_ID_LANCER_G8_FC: 2757 + m = (typeof(m)){"LPe42100", "PCIe", "Fibre Channel Adapter"}; 2759 2758 break; 2760 2759 case PCI_DEVICE_ID_SKYHAWK: 2761 2760 case PCI_DEVICE_ID_SKYHAWK_VF: ··· 10151 10144 phba->cfg_link_speed = 10152 10145 LPFC_USER_LINK_SPEED_64G; 10153 10146 break; 10147 + case LINK_SPEED_128G: 10148 + phba->cfg_link_speed = 10149 + LPFC_USER_LINK_SPEED_128G; 10150 + break; 10154 10151 case 0xffff: 10155 10152 phba->cfg_link_speed = 10156 10153 LPFC_USER_LINK_SPEED_AUTO; ··· 11804 11793 unsigned long bar0map_len, bar1map_len, bar2map_len; 11805 11794 int error; 11806 11795 uint32_t if_type; 11796 + u8 sli_family; 11807 11797 11808 11798 if (!pdev) 11809 11799 return -ENODEV; ··· 11833 11821 "sli_intf reg 0x%x\n", 11834 11822 phba->sli4_hba.sli_intf.word0); 11835 11823 return -ENODEV; 11824 + } 11825 + 11826 + /* Check if ASIC_ID register should be read */ 11827 + sli_family = bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf); 11828 + if (sli_family == LPFC_SLI_INTF_ASIC_ID) { 11829 + if (pci_read_config_dword(pdev, LPFC_ASIC_ID_OFFSET, 11830 + &phba->sli4_hba.asic_id.word0)) 11831 + return -ENODEV; 11836 11832 } 11837 11833 11838 11834 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf); ··· 13061 13041 /* Iterate to next offline or online cpu in aff_mask */ 13062 13042 cpu = cpumask_next(cpu, aff_mask); 13063 13043 13044 + /* Reached the end of the aff_mask */ 13045 + if (cpu >= nr_cpu_ids) 13046 + break; 13047 + 13064 13048 /* Find next online cpu in aff_mask to set affinity */ 13065 13049 cpu_select = lpfc_next_online_cpu(aff_mask, cpu); 13066 13050 } else if (vectors == 1) { ··· 13738 13714 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters); 13739 13715 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters); 13740 13716 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters); 13741 - sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters); 13717 + sli4_params->rqv = 13718 + (sli4_params->if_type < LPFC_SLI_INTF_IF_TYPE_2) ? 13719 + LPFC_Q_CREATE_VERSION_0 : LPFC_Q_CREATE_VERSION_1; 13742 13720 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters); 13743 13721 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters); 13744 13722 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters); ··· 13802 13776 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) 13803 13777 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT; 13804 13778 13805 - /* Enable embedded Payload BDE if support is indicated */ 13806 - if (bf_get(cfg_pbde, mbx_sli4_parameters)) 13807 - phba->cfg_enable_pbde = 1; 13808 - else 13809 - phba->cfg_enable_pbde = 0; 13810 - 13811 13779 /* 13812 13780 * To support Suppress Response feature we must satisfy 3 conditions. 13813 13781 * lpfc_suppress_rsp module parameter must be set (default). ··· 13836 13816 phba->fcp_embed_io = 0; 13837 13817 13838 13818 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME, 13839 - "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n", 13819 + "6422 XIB %d: FCP %d NVME %d %d %d\n", 13840 13820 bf_get(cfg_xib, mbx_sli4_parameters), 13841 - phba->cfg_enable_pbde, 13842 13821 phba->fcp_embed_io, sli4_params->nvme, 13843 13822 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp); 13844 13823 ··· 14502 14483 u8 sli_family; 14503 14484 14504 14485 sli_family = bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf); 14486 + 14487 + /* Refer to ASIC_ID register case */ 14488 + if (sli_family == LPFC_SLI_INTF_ASIC_ID) 14489 + sli_family = bf_get(lpfc_asic_id_gen_num, 14490 + &phba->sli4_hba.asic_id); 14491 + 14505 14492 /* Three cases: (1) FW was not supported on the detected adapter. 14506 14493 * (2) FW update has been locked out administratively. 14507 14494 * (3) Some other error during FW update. ··· 14520 14495 (sli_family == LPFC_SLI_INTF_FAMILY_G7 && 14521 14496 magic_number != MAGIC_NUMBER_G7) || 14522 14497 (sli_family == LPFC_SLI_INTF_FAMILY_G7P && 14523 - magic_number != MAGIC_NUMBER_G7P)) { 14498 + magic_number != MAGIC_NUMBER_G7P) || 14499 + (sli_family == LPFC_SLI_INTF_FAMILY_G8 && 14500 + magic_number != MAGIC_NUMBER_G8)) { 14524 14501 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, 14525 14502 "3030 This firmware version is not supported on" 14526 14503 " this HBA model. Device:%x Magic:%x Type:%x "

+5 -2

drivers/scsi/lpfc/lpfc_mbox.c

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 624 624 case LPFC_USER_LINK_SPEED_64G: 625 625 mb->un.varInitLnk.link_flags |= FLAGS_LINK_SPEED; 626 626 mb->un.varInitLnk.link_speed = LINK_SPEED_64G; 627 + break; 628 + case LPFC_USER_LINK_SPEED_128G: 629 + mb->un.varInitLnk.link_flags |= FLAGS_LINK_SPEED; 630 + mb->un.varInitLnk.link_speed = LINK_SPEED_128G; 627 631 break; 628 632 case LPFC_USER_LINK_SPEED_AUTO: 629 633 default: ··· 2143 2139 2144 2140 /* Set up host requested features. */ 2145 2141 bf_set(lpfc_mbx_rq_ftr_rq_fcpi, &mboxq->u.mqe.un.req_ftrs, 1); 2146 - bf_set(lpfc_mbx_rq_ftr_rq_perfh, &mboxq->u.mqe.un.req_ftrs, 1); 2147 2142 2148 2143 /* Enable DIF (block guard) only if configured to do so. */ 2149 2144 if (phba->cfg_enable_bg)

+20 -18

drivers/scsi/lpfc/lpfc_nportdisc.c

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 316 316 struct lpfc_iocbq *save_iocb; 317 317 struct lpfc_nodelist *ndlp; 318 318 MAILBOX_t *mb = &login_mbox->u.mb; 319 - 320 - int rc; 319 + int rc = 0; 321 320 322 321 ndlp = login_mbox->ctx_ndlp; 323 322 save_iocb = login_mbox->ctx_u.save_iocb; ··· 345 346 * completes. This ensures, in Pt2Pt, that the PLOGI LS_ACC is sent 346 347 * before the PRLI. 347 348 */ 348 - if (!test_bit(FC_PT2PT, &ndlp->vport->fc_flag)) { 349 + if (!test_bit(FC_PT2PT, &ndlp->vport->fc_flag) || mb->mbxStatus || rc) { 349 350 /* Now process the REG_RPI cmpl */ 350 351 lpfc_mbx_cmpl_reg_login(phba, login_mbox); 351 352 clear_bit(NLP_ACC_REGLOGIN, &ndlp->nlp_flag); ··· 524 525 /* Issue CONFIG_LINK for SLI3 or REG_VFI for SLI4, 525 526 * to account for updated TOV's / parameters 526 527 */ 527 - if (phba->sli_rev == LPFC_SLI_REV4) 528 - lpfc_issue_reg_vfi(vport); 529 - else { 528 + if (phba->sli_rev == LPFC_SLI_REV4) { 529 + rc = lpfc_issue_reg_vfi(vport); 530 + } else { 530 531 link_mbox = mempool_alloc(phba->mbox_mem_pool, 531 532 GFP_KERNEL); 532 533 if (!link_mbox) 533 - goto out; 534 + goto rsp_rjt; 534 535 lpfc_config_link(phba, link_mbox); 535 536 link_mbox->mbox_cmpl = lpfc_sli_def_mbox_cmpl; 536 537 link_mbox->vport = vport; ··· 543 544 rc = lpfc_sli_issue_mbox(phba, link_mbox, MBX_NOWAIT); 544 545 if (rc == MBX_NOT_FINISHED) { 545 546 mempool_free(link_mbox, phba->mbox_mem_pool); 546 - goto out; 547 + goto rsp_rjt; 547 548 } 548 549 } 549 550 550 551 lpfc_can_disctmo(vport); 552 + if (rc) 553 + goto rsp_rjt; 551 554 } 552 555 553 556 clear_bit(NLP_SUPPRESS_RSP, &ndlp->nlp_flag); ··· 563 562 564 563 login_mbox = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL); 565 564 if (!login_mbox) 566 - goto out; 565 + goto rsp_rjt; 567 566 568 567 save_iocb = kzalloc_obj(*save_iocb); 569 568 if (!save_iocb) 570 - goto out; 569 + goto free_login_mbox; 571 570 572 571 /* Save info from cmd IOCB to be used in rsp after all mbox completes */ 573 572 memcpy((uint8_t *)save_iocb, (uint8_t *)cmdiocb, ··· 587 586 rc = lpfc_reg_rpi(phba, vport->vpi, remote_did, 588 587 (uint8_t *)sp, login_mbox, ndlp->nlp_rpi); 589 588 if (rc) 590 - goto out; 589 + goto free_save_iocb; 591 590 592 591 login_mbox->mbox_cmpl = lpfc_mbx_cmpl_reg_login; 593 592 login_mbox->vport = vport; ··· 660 659 login_mbox->mbox_cmpl = lpfc_defer_plogi_acc; 661 660 login_mbox->ctx_ndlp = lpfc_nlp_get(ndlp); 662 661 if (!login_mbox->ctx_ndlp) 663 - goto out; 662 + goto free_save_iocb; 664 663 665 664 login_mbox->ctx_u.save_iocb = save_iocb; /* For PLOGI ACC */ 666 665 ··· 671 670 rc = lpfc_sli_issue_mbox(phba, login_mbox, MBX_NOWAIT); 672 671 if (rc == MBX_NOT_FINISHED) { 673 672 lpfc_nlp_put(ndlp); 674 - goto out; 673 + goto free_save_iocb; 675 674 } 676 675 lpfc_nlp_set_state(vport, ndlp, NLP_STE_REG_LOGIN_ISSUE); 677 676 678 677 return 1; 679 - out: 680 - kfree(save_iocb); 681 - if (login_mbox) 682 - mempool_free(login_mbox, phba->mbox_mem_pool); 683 678 679 + free_save_iocb: 680 + kfree(save_iocb); 681 + free_login_mbox: 682 + mempool_free(login_mbox, phba->mbox_mem_pool); 683 + rsp_rjt: 684 684 stat.un.b.lsRjtRsnCode = LSRJT_UNABLE_TPC; 685 685 stat.un.b.lsRjtRsnCodeExp = LSEXP_OUT_OF_RESOURCE; 686 686 lpfc_els_rsp_reject(vport, stat.un.lsRjtError, cmdiocb, ndlp, NULL);

+19 -37

drivers/scsi/lpfc/lpfc_nvme.c

··· 1296 1296 /* Word 10 */ 1297 1297 bf_set(wqe_xchg, &wqe->fcp_iwrite.wqe_com, LPFC_NVME_XCHG); 1298 1298 1299 - /* Words 13 14 15 are for PBDE support */ 1300 - 1301 1299 /* add the VMID tags as per switch response */ 1302 1300 if (unlikely(lpfc_ncmd->cur_iocbq.cmd_flag & LPFC_IO_VMID)) { 1303 1301 if (phba->pport->vmid_priority_tagging) { ··· 1333 1335 { 1334 1336 struct lpfc_hba *phba = vport->phba; 1335 1337 struct nvmefc_fcp_req *nCmd = lpfc_ncmd->nvmeCmd; 1336 - union lpfc_wqe128 *wqe = &lpfc_ncmd->cur_iocbq.wqe; 1337 1338 struct sli4_sge *sgl = lpfc_ncmd->dma_sgl; 1338 1339 struct sli4_hybrid_sgl *sgl_xtra = NULL; 1339 1340 struct scatterlist *data_sg; 1340 - struct sli4_sge *first_data_sgl; 1341 - struct ulp_bde64 *bde; 1342 1341 dma_addr_t physaddr = 0; 1343 1342 uint32_t dma_len = 0; 1344 1343 uint32_t dma_offset = 0; 1345 - int nseg, i, j; 1344 + int nseg, i, j, k; 1346 1345 bool lsp_just_set = false; 1347 1346 1348 1347 /* Fix up the command and response DMA stuff. */ ··· 1356 1361 */ 1357 1362 sgl += 2; 1358 1363 1359 - first_data_sgl = sgl; 1360 1364 lpfc_ncmd->seg_cnt = nCmd->sg_cnt; 1361 1365 if (lpfc_ncmd->seg_cnt > lpfc_nvme_template.max_sgl_segments) { 1362 1366 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, ··· 1379 1385 1380 1386 /* for tracking the segment boundaries */ 1381 1387 j = 2; 1388 + k = 5; 1389 + if (unlikely(!phba->cfg_xpsgl)) 1390 + k = 1; 1382 1391 for (i = 0; i < nseg; i++) { 1383 1392 if (data_sg == NULL) { 1384 1393 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, ··· 1400 1403 bf_set(lpfc_sli4_sge_last, sgl, 0); 1401 1404 1402 1405 /* expand the segment */ 1403 - if (!lsp_just_set && 1404 - !((j + 1) % phba->border_sge_num) && 1405 - ((nseg - 1) != i)) { 1406 + if (!lsp_just_set && (nseg != (i + k)) && 1407 + !((j + k) % phba->border_sge_num)) { 1406 1408 /* set LSP type */ 1407 1409 bf_set(lpfc_sli4_sge_type, sgl, 1408 1410 LPFC_SGE_TYPE_LSP); ··· 1424 1428 } 1425 1429 } 1426 1430 1427 - if (!(bf_get(lpfc_sli4_sge_type, sgl) & 1428 - LPFC_SGE_TYPE_LSP)) { 1431 + if (bf_get(lpfc_sli4_sge_type, sgl) != 1432 + LPFC_SGE_TYPE_LSP) { 1429 1433 if ((nseg - 1) == i) 1430 1434 bf_set(lpfc_sli4_sge_last, sgl, 1); 1431 1435 ··· 1446 1450 sgl++; 1447 1451 1448 1452 lsp_just_set = false; 1453 + j++; 1449 1454 } else { 1450 1455 sgl->word2 = cpu_to_le32(sgl->word2); 1451 - 1452 - sgl->sge_len = cpu_to_le32( 1453 - phba->cfg_sg_dma_buf_size); 1456 + /* will remaining SGEs fill the next SGL? */ 1457 + if ((nseg - i) < phba->border_sge_num) 1458 + sgl->sge_len = 1459 + cpu_to_le32((nseg - i) * 1460 + sizeof(*sgl)); 1461 + else 1462 + sgl->sge_len = 1463 + cpu_to_le32(phba->cfg_sg_dma_buf_size); 1454 1464 1455 1465 sgl = (struct sli4_sge *)sgl_xtra->dma_sgl; 1456 1466 i = i - 1; 1457 1467 1458 1468 lsp_just_set = true; 1469 + j += k; 1470 + k = 1; 1459 1471 } 1460 - 1461 - j++; 1462 1472 } 1463 - 1464 - /* PBDE support for first data SGE only */ 1465 - if (nseg == 1 && phba->cfg_enable_pbde) { 1466 - /* Words 13-15 */ 1467 - bde = (struct ulp_bde64 *) 1468 - &wqe->words[13]; 1469 - bde->addrLow = first_data_sgl->addr_lo; 1470 - bde->addrHigh = first_data_sgl->addr_hi; 1471 - bde->tus.f.bdeSize = 1472 - le32_to_cpu(first_data_sgl->sge_len); 1473 - bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64; 1474 - bde->tus.w = cpu_to_le32(bde->tus.w); 1475 - 1476 - /* Word 11 - set PBDE bit */ 1477 - bf_set(wqe_pbde, &wqe->generic.wqe_com, 1); 1478 - } else { 1479 - memset(&wqe->words[13], 0, (sizeof(uint32_t) * 3)); 1480 - /* Word 11 - PBDE bit disabled by default template */ 1481 - } 1482 - 1483 1473 } else { 1484 1474 lpfc_ncmd->seg_cnt = 0; 1485 1475

+4 -31

drivers/scsi/lpfc/lpfc_nvmet.c

··· 1 1 /******************************************************************* 2 2 * This file is part of the Emulex Linux Device Driver for * 3 3 * Fibre Channel Host Bus Adapters. * 4 - * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term * 4 + * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term * 5 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 7 * EMULEX and SLI are trademarks of Emulex. * ··· 118 118 bf_set(wqe_sup, &wqe->fcp_tsend.wqe_com, 0); 119 119 bf_set(wqe_irsp, &wqe->fcp_tsend.wqe_com, 0); 120 120 bf_set(wqe_irsplen, &wqe->fcp_tsend.wqe_com, 0); 121 - bf_set(wqe_pbde, &wqe->fcp_tsend.wqe_com, 0); 122 121 123 122 /* Word 12 - fcp_data_len is variable */ 124 - 125 - /* Word 13, 14, 15 - PBDE is zero */ 126 123 127 124 /* TRECEIVE template */ 128 125 wqe = &lpfc_treceive_cmd_template; ··· 155 158 bf_set(wqe_lenloc, &wqe->fcp_treceive.wqe_com, LPFC_WQE_LENLOC_WORD12); 156 159 bf_set(wqe_xc, &wqe->fcp_tsend.wqe_com, 1); 157 160 158 - /* Word 11 - pbde is variable */ 161 + /* Word 11 */ 159 162 bf_set(wqe_cmd_type, &wqe->fcp_treceive.wqe_com, FCP_COMMAND_TRECEIVE); 160 163 bf_set(wqe_cqid, &wqe->fcp_treceive.wqe_com, LPFC_WQE_CQ_ID_DEFAULT); 161 164 bf_set(wqe_sup, &wqe->fcp_treceive.wqe_com, 0); 162 165 bf_set(wqe_irsp, &wqe->fcp_treceive.wqe_com, 0); 163 166 bf_set(wqe_irsplen, &wqe->fcp_treceive.wqe_com, 0); 164 - bf_set(wqe_pbde, &wqe->fcp_treceive.wqe_com, 1); 165 167 166 168 /* Word 12 - fcp_data_len is variable */ 167 - 168 - /* Word 13, 14, 15 - PBDE is variable */ 169 169 170 170 /* TRSP template */ 171 171 wqe = &lpfc_trsp_cmd_template; ··· 201 207 bf_set(wqe_sup, &wqe->fcp_trsp.wqe_com, 0); 202 208 bf_set(wqe_irsp, &wqe->fcp_trsp.wqe_com, 0); 203 209 bf_set(wqe_irsplen, &wqe->fcp_trsp.wqe_com, 0); 204 - bf_set(wqe_pbde, &wqe->fcp_trsp.wqe_com, 0); 205 210 206 211 /* Word 12, 13, 14, 15 - is zero */ 207 212 } ··· 2715 2722 struct ulp_bde64 *bde; 2716 2723 dma_addr_t physaddr; 2717 2724 int i, cnt, nsegs; 2718 - bool use_pbde = false; 2719 2725 int xc = 1; 2720 2726 2721 2727 if (!lpfc_is_link_up(phba)) { ··· 2899 2907 if (!xc) 2900 2908 bf_set(wqe_xc, &wqe->fcp_treceive.wqe_com, 0); 2901 2909 2902 - /* Word 11 - check for pbde */ 2903 - if (nsegs == 1 && phba->cfg_enable_pbde) { 2904 - use_pbde = true; 2905 - /* Word 11 - PBDE bit already preset by template */ 2906 - } else { 2907 - /* Overwrite default template setting */ 2908 - bf_set(wqe_pbde, &wqe->fcp_treceive.wqe_com, 0); 2909 - } 2910 - 2911 2910 /* Word 12 */ 2912 2911 wqe->fcp_tsend.fcp_data_len = rsp->transfer_length; 2913 2912 ··· 3006 3023 } 3007 3024 3008 3025 bde = (struct ulp_bde64 *)&wqe->words[13]; 3009 - if (use_pbde) { 3010 - /* decrement sgl ptr backwards once to first data sge */ 3011 - sgl--; 3012 3026 3013 - /* Words 13-15 (PBDE) */ 3014 - bde->addrLow = sgl->addr_lo; 3015 - bde->addrHigh = sgl->addr_hi; 3016 - bde->tus.f.bdeSize = le32_to_cpu(sgl->sge_len); 3017 - bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64; 3018 - bde->tus.w = cpu_to_le32(bde->tus.w); 3019 - } else { 3020 - memset(bde, 0, sizeof(struct ulp_bde64)); 3021 - } 3027 + memset(bde, 0, sizeof(struct ulp_bde64)); 3028 + 3022 3029 ctxp->state = LPFC_NVME_STE_DATA; 3023 3030 ctxp->entry_cnt++; 3024 3031 return nvmewqe;

+68 -69

drivers/scsi/lpfc/lpfc_scsi.c

··· 1938 1938 uint32_t dma_len; 1939 1939 uint32_t dma_offset = 0; 1940 1940 struct sli4_hybrid_sgl *sgl_xtra = NULL; 1941 - int j; 1941 + int j, k; 1942 1942 bool lsp_just_set = false; 1943 1943 1944 1944 status = lpfc_sc_to_bg_opcodes(phba, sc, &txop, &rxop); ··· 2001 2001 /* assumption: caller has already run dma_map_sg on command data */ 2002 2002 sgde = scsi_sglist(sc); 2003 2003 j = 3; 2004 + k = 5; 2005 + if (unlikely(!phba->cfg_xpsgl)) 2006 + k = 1; 2004 2007 for (i = 0; i < datasegcnt; i++) { 2005 2008 /* clear it */ 2006 2009 sgl->word2 = 0; 2007 2010 2008 - /* do we need to expand the segment */ 2009 - if (!lsp_just_set && !((j + 1) % phba->border_sge_num) && 2010 - ((datasegcnt - 1) != i)) { 2011 + /* do we need to expand the segment? */ 2012 + if (!lsp_just_set && (datasegcnt != (i + k)) && 2013 + !((j + k) % phba->border_sge_num)) { 2011 2014 /* set LSP type */ 2012 2015 bf_set(lpfc_sli4_sge_type, sgl, LPFC_SGE_TYPE_LSP); 2013 2016 ··· 2029 2026 bf_set(lpfc_sli4_sge_type, sgl, LPFC_SGE_TYPE_DATA); 2030 2027 } 2031 2028 2032 - if (!(bf_get(lpfc_sli4_sge_type, sgl) & LPFC_SGE_TYPE_LSP)) { 2029 + if (bf_get(lpfc_sli4_sge_type, sgl) != LPFC_SGE_TYPE_LSP) { 2033 2030 if ((datasegcnt - 1) == i) 2034 2031 bf_set(lpfc_sli4_sge_last, sgl, 1); 2035 2032 physaddr = sg_dma_address(sgde); ··· 2046 2043 2047 2044 sgl++; 2048 2045 num_sge++; 2046 + j++; 2049 2047 lsp_just_set = false; 2050 - 2051 2048 } else { 2052 2049 sgl->word2 = cpu_to_le32(sgl->word2); 2053 - sgl->sge_len = cpu_to_le32(phba->cfg_sg_dma_buf_size); 2054 - 2050 + /* will remaining SGEs fill the next SGL? */ 2051 + if ((datasegcnt - i) < phba->border_sge_num) 2052 + sgl->sge_len = cpu_to_le32((datasegcnt - i) * 2053 + sizeof(*sgl)); 2054 + else 2055 + sgl->sge_len = 2056 + cpu_to_le32(phba->cfg_sg_dma_buf_size); 2055 2057 sgl = (struct sli4_sge *)sgl_xtra->dma_sgl; 2056 2058 i = i - 1; 2057 - 2059 + j += k; 2058 2060 lsp_just_set = true; 2061 + k = 1; 2059 2062 } 2060 - 2061 - j++; 2062 - 2063 2063 } 2064 2064 2065 2065 out: ··· 2115 2109 struct scatterlist *sgde = NULL; /* s/g data entry */ 2116 2110 struct scatterlist *sgpe = NULL; /* s/g prot entry */ 2117 2111 struct sli4_sge_diseed *diseed = NULL; 2112 + struct sli4_sge_le *lsp_sgl = NULL; 2118 2113 dma_addr_t dataphysaddr, protphysaddr; 2119 2114 unsigned short curr_prot = 0; 2120 2115 unsigned int split_offset; ··· 2132 2125 uint32_t rc; 2133 2126 #endif 2134 2127 uint32_t checking = 1; 2135 - uint32_t dma_offset = 0, num_sge = 0; 2136 - int j = 2; 2128 + uint32_t dma_offset = 0, num_sge = 0, lsp_len; 2129 + int j = 2, k = 4; 2137 2130 struct sli4_hybrid_sgl *sgl_xtra = NULL; 2138 2131 2139 2132 sgpe = scsi_prot_sglist(sc); ··· 2164 2157 } 2165 2158 #endif 2166 2159 2160 + if (unlikely(!phba->cfg_xpsgl)) 2161 + k = 0; 2167 2162 split_offset = 0; 2168 2163 do { 2169 2164 /* Check to see if we ran out of space */ ··· 2173 2164 !(phba->cfg_xpsgl)) 2174 2165 return num_sge + 3; 2175 2166 2176 - /* DISEED and DIF have to be together */ 2177 - if (!((j + 1) % phba->border_sge_num) || 2178 - !((j + 2) % phba->border_sge_num) || 2179 - !((j + 3) % phba->border_sge_num)) { 2167 + /* DISEED and DIF have to be together */ 2168 + if (!((j + k + 1) % phba->border_sge_num) || 2169 + !((j + k + 2) % phba->border_sge_num) || 2170 + !((j + k + 3) % phba->border_sge_num)) { 2180 2171 sgl->word2 = 0; 2181 2172 2182 2173 /* set LSP type */ ··· 2195 2186 2196 2187 sgl->word2 = cpu_to_le32(sgl->word2); 2197 2188 sgl->sge_len = cpu_to_le32(phba->cfg_sg_dma_buf_size); 2189 + if (lsp_sgl) { 2190 + j++; 2191 + if (j % phba->border_sge_num) { 2192 + lsp_len = j * (sizeof(*sgl)); 2193 + lsp_sgl->sge_len = cpu_to_le32(lsp_len); 2194 + } 2195 + } 2196 + lsp_sgl = (struct sli4_sge_le *)sgl; 2198 2197 2199 2198 sgl = (struct sli4_sge *)sgl_xtra->dma_sgl; 2200 2199 j = 0; 2200 + k = 0; 2201 2201 } 2202 2202 2203 2203 /* setup DISEED with what we have */ ··· 2309 2291 return 0; 2310 2292 } 2311 2293 2312 - if (!((j + 1) % phba->border_sge_num)) { 2294 + if (!((j + k + 1) % phba->border_sge_num)) { 2313 2295 sgl->word2 = 0; 2314 2296 2315 2297 /* set LSP type */ ··· 2331 2313 sgl->word2 = cpu_to_le32(sgl->word2); 2332 2314 sgl->sge_len = cpu_to_le32( 2333 2315 phba->cfg_sg_dma_buf_size); 2316 + lsp_sgl = (struct sli4_sge_le *)sgl; 2334 2317 2335 2318 sgl = (struct sli4_sge *)sgl_xtra->dma_sgl; 2319 + j = 0; 2320 + k = 0; 2336 2321 } else { 2337 2322 dataphysaddr = sg_dma_address(sgde) + 2338 2323 split_offset; ··· 2383 2362 2384 2363 /* Move to the next s/g segment if possible */ 2385 2364 sgde = sg_next(sgde); 2386 - 2387 2365 sgl++; 2366 + j++; 2388 2367 } 2389 - 2390 - j++; 2391 2368 } 2392 2369 2393 2370 if (protgroup_offset) { ··· 2400 2381 sgl--; 2401 2382 bf_set(lpfc_sli4_sge_last, sgl, 1); 2402 2383 alldone = 1; 2384 + 2385 + /* Reset length in previous LSP where necessary */ 2386 + if (lsp_sgl) { 2387 + if (j % phba->border_sge_num) { 2388 + lsp_len = j * (sizeof(*sgl)); 2389 + lsp_sgl->sge_len = cpu_to_le32(lsp_len); 2390 + } 2391 + } 2403 2392 } else if (curr_prot < protcnt) { 2404 2393 /* advance to next prot buffer */ 2405 2394 sgpe = sg_next(sgpe); ··· 2419 2392 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, 2420 2393 "9085 BLKGRD: bug in %s\n", __func__); 2421 2394 } 2422 - 2423 2395 } while (!alldone); 2424 2396 2425 2397 out: ··· 3076 3050 struct scatterlist *sgel = NULL; 3077 3051 struct fcp_cmnd *fcp_cmnd = lpfc_cmd->fcp_cmnd; 3078 3052 struct sli4_sge *sgl = (struct sli4_sge *)lpfc_cmd->dma_sgl; 3079 - struct sli4_sge *first_data_sgl; 3080 3053 struct lpfc_iocbq *pwqeq = &lpfc_cmd->cur_iocbq; 3081 3054 struct lpfc_vport *vport = phba->pport; 3082 3055 union lpfc_wqe128 *wqe = &pwqeq->wqe; 3083 3056 dma_addr_t physaddr; 3084 3057 uint32_t dma_len; 3085 3058 uint32_t dma_offset = 0; 3086 - int nseg, i, j; 3087 - struct ulp_bde64 *bde; 3059 + int nseg, i, j, k; 3088 3060 bool lsp_just_set = false; 3089 3061 struct sli4_hybrid_sgl *sgl_xtra = NULL; 3090 3062 ··· 3109 3085 bf_set(lpfc_sli4_sge_last, sgl, 0); 3110 3086 sgl->word2 = cpu_to_le32(sgl->word2); 3111 3087 sgl += 1; 3112 - first_data_sgl = sgl; 3113 3088 lpfc_cmd->seg_cnt = nseg; 3114 3089 if (!phba->cfg_xpsgl && 3115 3090 lpfc_cmd->seg_cnt > phba->cfg_sg_seg_cnt) { ··· 3137 3114 /* for tracking segment boundaries */ 3138 3115 sgel = scsi_sglist(scsi_cmnd); 3139 3116 j = 2; 3117 + k = 5; 3118 + if (unlikely(!phba->cfg_xpsgl)) 3119 + k = 1; 3140 3120 for (i = 0; i < nseg; i++) { 3141 3121 sgl->word2 = 0; 3142 3122 if (nseg == 1) { ··· 3150 3124 bf_set(lpfc_sli4_sge_last, sgl, 0); 3151 3125 3152 3126 /* do we need to expand the segment */ 3153 - if (!lsp_just_set && 3154 - !((j + 1) % phba->border_sge_num) && 3155 - ((nseg - 1) != i)) { 3127 + if (!lsp_just_set && (nseg != (i + k)) && 3128 + !((j + k) % phba->border_sge_num)) { 3156 3129 /* set LSP type */ 3157 3130 bf_set(lpfc_sli4_sge_type, sgl, 3158 3131 LPFC_SGE_TYPE_LSP); ··· 3175 3150 } 3176 3151 } 3177 3152 3178 - if (!(bf_get(lpfc_sli4_sge_type, sgl) & 3179 - LPFC_SGE_TYPE_LSP)) { 3153 + if (bf_get(lpfc_sli4_sge_type, sgl) != 3154 + LPFC_SGE_TYPE_LSP) { 3180 3155 if ((nseg - 1) == i) 3181 3156 bf_set(lpfc_sli4_sge_last, sgl, 1); 3182 3157 ··· 3196 3171 3197 3172 sgl++; 3198 3173 lsp_just_set = false; 3199 - 3174 + j++; 3200 3175 } else { 3201 3176 sgl->word2 = cpu_to_le32(sgl->word2); 3202 - sgl->sge_len = cpu_to_le32( 3203 - phba->cfg_sg_dma_buf_size); 3204 - 3177 + /* will remaining SGEs fill the next SGL? */ 3178 + if ((nseg - i) < phba->border_sge_num) 3179 + sgl->sge_len = 3180 + cpu_to_le32((nseg - i) * 3181 + sizeof(*sgl)); 3182 + else 3183 + sgl->sge_len = 3184 + cpu_to_le32(phba->cfg_sg_dma_buf_size); 3205 3185 sgl = (struct sli4_sge *)sgl_xtra->dma_sgl; 3206 3186 i = i - 1; 3207 3187 3208 3188 lsp_just_set = true; 3189 + j += k; 3190 + k = 1; 3209 3191 } 3210 - 3211 - j++; 3212 - } 3213 - 3214 - /* PBDE support for first data SGE only. 3215 - * For FCoE, we key off Performance Hints. 3216 - * For FC, we key off lpfc_enable_pbde. 3217 - */ 3218 - if (nseg == 1 && 3219 - ((phba->sli3_options & LPFC_SLI4_PERFH_ENABLED) || 3220 - phba->cfg_enable_pbde)) { 3221 - /* Words 13-15 */ 3222 - bde = (struct ulp_bde64 *) 3223 - &wqe->words[13]; 3224 - bde->addrLow = first_data_sgl->addr_lo; 3225 - bde->addrHigh = first_data_sgl->addr_hi; 3226 - bde->tus.f.bdeSize = 3227 - le32_to_cpu(first_data_sgl->sge_len); 3228 - bde->tus.f.bdeFlags = BUFF_TYPE_BDE_64; 3229 - bde->tus.w = cpu_to_le32(bde->tus.w); 3230 - 3231 - /* Word 11 - set PBDE bit */ 3232 - bf_set(wqe_pbde, &wqe->generic.wqe_com, 1); 3233 - } else { 3234 - memset(&wqe->words[13], 0, (sizeof(uint32_t) * 3)); 3235 - /* Word 11 - PBDE bit disabled by default template */ 3236 3192 } 3237 3193 } else { 3238 3194 sgl += 1; ··· 3221 3215 sgl->word2 = le32_to_cpu(sgl->word2); 3222 3216 bf_set(lpfc_sli4_sge_last, sgl, 1); 3223 3217 sgl->word2 = cpu_to_le32(sgl->word2); 3224 - 3225 - if ((phba->sli3_options & LPFC_SLI4_PERFH_ENABLED) || 3226 - phba->cfg_enable_pbde) { 3227 - bde = (struct ulp_bde64 *) 3228 - &wqe->words[13]; 3229 - memset(bde, 0, (sizeof(uint32_t) * 3)); 3230 - } 3231 3218 } 3232 3219 3233 3220 /*

+7 -20

drivers/scsi/lpfc/lpfc_sli.c

··· 136 136 bf_set(wqe_dbde, &wqe->fcp_iread.wqe_com, 0); 137 137 bf_set(wqe_wqes, &wqe->fcp_iread.wqe_com, 1); 138 138 139 - /* Word 11 - pbde is variable */ 139 + /* Word 11 */ 140 140 bf_set(wqe_cmd_type, &wqe->fcp_iread.wqe_com, COMMAND_DATA_IN); 141 141 bf_set(wqe_cqid, &wqe->fcp_iread.wqe_com, LPFC_WQE_CQ_ID_DEFAULT); 142 - bf_set(wqe_pbde, &wqe->fcp_iread.wqe_com, 0); 143 142 144 143 /* Word 12 - is zero */ 145 - 146 - /* Word 13, 14, 15 - PBDE is variable */ 147 144 148 145 /* IWRITE template */ 149 146 wqe = &lpfc_iwrite_cmd_template; ··· 173 176 bf_set(wqe_dbde, &wqe->fcp_iwrite.wqe_com, 0); 174 177 bf_set(wqe_wqes, &wqe->fcp_iwrite.wqe_com, 1); 175 178 176 - /* Word 11 - pbde is variable */ 179 + /* Word 11 */ 177 180 bf_set(wqe_cmd_type, &wqe->fcp_iwrite.wqe_com, COMMAND_DATA_OUT); 178 181 bf_set(wqe_cqid, &wqe->fcp_iwrite.wqe_com, LPFC_WQE_CQ_ID_DEFAULT); 179 - bf_set(wqe_pbde, &wqe->fcp_iwrite.wqe_com, 0); 180 182 181 183 /* Word 12 - is zero */ 182 - 183 - /* Word 13, 14, 15 - PBDE is variable */ 184 184 185 185 /* ICMND template */ 186 186 wqe = &lpfc_icmnd_cmd_template; ··· 211 217 /* Word 11 */ 212 218 bf_set(wqe_cmd_type, &wqe->fcp_icmd.wqe_com, COMMAND_DATA_IN); 213 219 bf_set(wqe_cqid, &wqe->fcp_icmd.wqe_com, LPFC_WQE_CQ_ID_DEFAULT); 214 - bf_set(wqe_pbde, &wqe->fcp_icmd.wqe_com, 0); 215 220 216 221 /* Word 12, 13, 14, 15 - is zero */ 217 222 } ··· 8725 8732 ftr_rsp++; 8726 8733 } 8727 8734 8728 - /* Performance Hints are ONLY for FCoE */ 8729 - if (test_bit(HBA_FCOE_MODE, &phba->hba_flag)) { 8730 - if (bf_get(lpfc_mbx_rq_ftr_rsp_perfh, &mqe->un.req_ftrs)) 8731 - phba->sli3_options |= LPFC_SLI4_PERFH_ENABLED; 8732 - else 8733 - phba->sli3_options &= ~LPFC_SLI4_PERFH_ENABLED; 8734 - } 8735 - 8736 8735 /* 8737 8736 * If the port cannot support the host's requested features 8738 8737 * then turn off the global config parameters to disable the ··· 14322 14337 /* Get the reference to the active mbox command */ 14323 14338 spin_lock_irqsave(&phba->hbalock, iflags); 14324 14339 pmb = phba->sli.mbox_active; 14340 + spin_unlock_irqrestore(&phba->hbalock, iflags); 14325 14341 if (unlikely(!pmb)) { 14326 14342 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT, 14327 - "1832 No pending MBOX command to handle\n"); 14328 - spin_unlock_irqrestore(&phba->hbalock, iflags); 14343 + "1832 No pending MBOX command to handle, " 14344 + "mcqe: x%08x x%08x x%08x x%08x\n", 14345 + mcqe->word0, mcqe->mcqe_tag0, 14346 + mcqe->mcqe_tag1, mcqe->trailer); 14329 14347 goto out_no_mqe_complete; 14330 14348 } 14331 - spin_unlock_irqrestore(&phba->hbalock, iflags); 14332 14349 mqe = &pmb->u.mqe; 14333 14350 pmbox = (MAILBOX_t *)&pmb->u.mqe; 14334 14351 mbox = phba->mbox;

+1

drivers/scsi/lpfc/lpfc_sli4.h

··· 841 841 uint32_t ue_to_sr; 842 842 uint32_t ue_to_rp; 843 843 struct lpfc_register sli_intf; 844 + struct lpfc_register asic_id; 844 845 struct lpfc_pc_sli4_params pc_sli4_params; 845 846 struct lpfc_bbscn_params bbscn_params; 846 847 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */

+1 -1

drivers/scsi/lpfc/lpfc_version.h

··· 20 20 * included with this package. * 21 21 *******************************************************************/ 22 22 23 - #define LPFC_DRIVER_VERSION "14.4.0.14" 23 + #define LPFC_DRIVER_VERSION "15.0.0.0" 24 24 #define LPFC_DRIVER_NAME "lpfc" 25 25 26 26 /* Used for SLI 2/3 */

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