Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
remoteproc: mediatek: Support MT8188 SCP core 1
MT8188 SCP has two RISC-V cores which is similar to MT8195 but without
L1TCM. We've added MT8188-specific functions to configure L1TCM in
multicore setups.
Signed-off-by: Olivia Wen <olivia.wen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240430011534.9587-3-olivia.wen@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
authored by
Olivia Wen
and committed by
Mathieu Poirier
928a55ab
91e0d560
+143
-3
+143
-3
drivers/remoteproc/mtk_scp.c
+143
-3
drivers/remoteproc/mtk_scp.c
···
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return 0;
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}
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+
static int mt8188_scp_l2tcm_on(struct mtk_scp *scp)
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{
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struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
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+
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mutex_lock(&scp_cluster->cluster_lock);
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+
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if (scp_cluster->l2tcm_refcnt == 0) {
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/* clear SPM interrupt, SCP2SPM_IPC_CLR */
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writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
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+
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/* Power on L2TCM */
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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}
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scp_cluster->l2tcm_refcnt += 1;
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mutex_unlock(&scp_cluster->cluster_lock);
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return 0;
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}
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+
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static int mt8188_scp_before_load(struct mtk_scp *scp)
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{
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writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
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mt8188_scp_l2tcm_on(scp);
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+
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scp_sram_power_on(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
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+
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/* enable MPU for all memory regions */
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writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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return 0;
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}
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static int mt8188_scp_c1_before_load(struct mtk_scp *scp)
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{
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u32 sec_ctrl;
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struct mtk_scp *scp_c0;
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struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
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+
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scp->data->scp_reset_assert(scp);
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+
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mt8188_scp_l2tcm_on(scp);
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+
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scp_sram_power_on(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
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+
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/* enable MPU for all memory regions */
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writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
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+
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/*
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* The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address
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* on SRAM when SCP core 1 accesses SRAM.
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*
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* This configuration solves booting the SCP core 0 and core 1 from
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* different SRAM address because core 0 and core 1 both boot from
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* the head of SRAM by default. this must be configured before boot SCP core 1.
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*
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* The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1.
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* When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE),
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* the address will be added with a fixed offset (L2TCM_OFFSET) on the bus.
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* The shift action is tranparent to software.
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*/
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writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
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writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
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+
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scp_c0 = list_first_entry(&scp_cluster->mtk_scp_list, struct mtk_scp, elem);
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writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET);
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+
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/* enable SRAM offset when fetching instruction and data */
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sec_ctrl = readl(scp->cluster->reg_base + MT8195_SEC_CTRL);
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sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D;
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writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL);
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+
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return 0;
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}
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+
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static int mt8192_scp_before_load(struct mtk_scp *scp)
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{
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/* clear SPM interrupt, SCP2SPM_IPC_CLR */
···
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{
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/* Disable SCP watchdog */
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writel(0, scp->cluster->reg_base + MT8183_WDT_CFG);
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}
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static void mt8188_scp_l2tcm_off(struct mtk_scp *scp)
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{
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struct mtk_scp_of_cluster *scp_cluster = scp->cluster;
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mutex_lock(&scp_cluster->cluster_lock);
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+
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if (scp_cluster->l2tcm_refcnt > 0)
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scp_cluster->l2tcm_refcnt -= 1;
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if (scp_cluster->l2tcm_refcnt == 0) {
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/* Power off L2TCM */
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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}
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mutex_unlock(&scp_cluster->cluster_lock);
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}
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static void mt8188_scp_stop(struct mtk_scp *scp)
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{
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mt8188_scp_l2tcm_off(scp);
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scp_sram_power_off(scp->cluster->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* Disable SCP watchdog */
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writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
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}
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+
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static void mt8188_scp_c1_stop(struct mtk_scp *scp)
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{
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mt8188_scp_l2tcm_off(scp);
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/* Power off CPU SRAM */
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scp_sram_power_off(scp->cluster->reg_base + MT8195_CPU1_SRAM_PD, 0);
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+
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/* Disable SCP watchdog */
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writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG);
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}
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static void mt8192_scp_stop(struct mtk_scp *scp)
···
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static const struct mtk_scp_of_data mt8188_of_data = {
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.scp_clk_get = mt8195_scp_clk_get,
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-
.scp_before_load = mt8192_scp_before_load,
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.scp_irq_handler = mt8192_scp_irq_handler,
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.scp_before_load = mt8188_scp_before_load,
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.scp_irq_handler = mt8195_scp_irq_handler,
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.scp_reset_assert = mt8192_scp_reset_assert,
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.scp_reset_deassert = mt8192_scp_reset_deassert,
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.scp_stop = mt8192_scp_stop,
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.scp_stop = mt8188_scp_stop,
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.scp_da_to_va = mt8192_scp_da_to_va,
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.host_to_scp_reg = MT8192_GIPC_IN_SET,
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.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
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};
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static const struct mtk_scp_of_data mt8188_of_data_c1 = {
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.scp_clk_get = mt8195_scp_clk_get,
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.scp_before_load = mt8188_scp_c1_before_load,
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.scp_irq_handler = mt8195_scp_c1_irq_handler,
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.scp_reset_assert = mt8195_scp_c1_reset_assert,
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.scp_reset_deassert = mt8195_scp_c1_reset_deassert,
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.scp_stop = mt8188_scp_c1_stop,
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.scp_da_to_va = mt8192_scp_da_to_va,
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.host_to_scp_reg = MT8192_GIPC_IN_SET,
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.host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT,
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};
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static const struct mtk_scp_of_data mt8192_of_data = {
···
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.host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT,
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};
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static const struct mtk_scp_of_data *mt8188_of_data_cores[] = {
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&mt8188_of_data,
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&mt8188_of_data_c1,
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NULL
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};
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+
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static const struct mtk_scp_of_data *mt8195_of_data_cores[] = {
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&mt8195_of_data,
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&mt8195_of_data_c1,
···
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{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },
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{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },
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{ .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data },
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{ .compatible = "mediatek,mt8188-scp-dual", .data = &mt8188_of_data_cores },
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{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },
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{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },
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{ .compatible = "mediatek,mt8195-scp-dual", .data = &mt8195_of_data_cores },