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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/dp: Add drm_dp_dsc_sink_slice_count_mask()
A DSC sink supporting DSC slice count N, not necessarily supports slice
counts less than N. Hence the driver should check the sink's support for
a particular slice count before using that slice count. Add the helper
functions required for this.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-3-imre.deak@intel.com
+69
-32
+66
-32
drivers/gpu/drm/display/drm_dp_helper.c
+66
-32
drivers/gpu/drm/display/drm_dp_helper.c
···
2705
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EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
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/**
2708
+
* drm_dp_dsc_slice_count_to_mask() - Convert a slice count to a slice count mask
2709
+
* @slice_count: slice count
2710
+
*
2711
+
* Convert @slice_count to a slice count mask.
2712
+
*
2713
+
* Returns the slice count mask.
2714
+
*/
2715
+
u32 drm_dp_dsc_slice_count_to_mask(int slice_count)
2716
+
{
2717
+
return BIT(slice_count - 1);
2718
+
}
2719
+
EXPORT_SYMBOL(drm_dp_dsc_slice_count_to_mask);
2720
+
2721
+
/**
2722
+
* drm_dp_dsc_sink_slice_count_mask() - Get the mask of valid DSC sink slice counts
2723
+
* @dsc_dpcd: the sink's DSC DPCD capabilities
2724
+
* @is_edp: %true for an eDP sink
2725
+
*
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* Get the mask of supported slice counts from the sink's DSC DPCD register.
2727
+
*
2728
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* Returns:
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* Mask of slice counts supported by the DSC sink:
2730
+
* - > 0: bit#0,1,3,5..,23 set if the sink supports 1,2,4,6..,24 slices
2731
+
* - 0: if the sink doesn't support any slices
2732
+
*/
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+
u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2734
+
bool is_edp)
2735
+
{
2736
+
u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2737
+
u32 mask = 0;
2738
+
2739
+
if (!is_edp) {
2740
+
/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
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u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2742
+
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if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(24);
2745
+
if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2746
+
mask |= drm_dp_dsc_slice_count_to_mask(20);
2747
+
if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2748
+
mask |= drm_dp_dsc_slice_count_to_mask(16);
2749
+
}
2750
+
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/* DP, eDP v1.5+ */
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if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
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+
mask |= drm_dp_dsc_slice_count_to_mask(12);
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+
if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(10);
2756
+
if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(8);
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+
if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(6);
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+
/* DP, eDP v1.4+ */
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if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(4);
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if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(2);
2765
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if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
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mask |= drm_dp_dsc_slice_count_to_mask(1);
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+
2768
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return mask;
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}
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EXPORT_SYMBOL(drm_dp_dsc_sink_slice_count_mask);
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+
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/**
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* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
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* supported by the DSC sink.
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* @dsc_dpcd: DSC capabilities from DPCD
···
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u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2789
2724
bool is_edp)
2790
2725
{
2791
-
u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2792
-
2793
-
if (!is_edp) {
2794
-
/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2795
-
u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2796
-
2797
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if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
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return 24;
2799
-
if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2800
-
return 20;
2801
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if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
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return 16;
2803
-
}
2804
-
2805
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/* DP, eDP v1.5+ */
2806
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if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2807
-
return 12;
2808
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if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2809
-
return 10;
2810
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if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2811
-
return 8;
2812
-
if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2813
-
return 6;
2814
-
/* DP, eDP v1.4+ */
2815
-
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2816
-
return 4;
2817
-
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2818
-
return 2;
2819
-
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2820
-
return 1;
2821
-
2822
-
return 0;
2726
+
return fls(drm_dp_dsc_sink_slice_count_mask(dsc_dpcd, is_edp));
2823
2727
}
2824
2728
EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2825
2729
+3
include/drm/display/drm_dp_helper.h
+3
include/drm/display/drm_dp_helper.h
···
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/* DP/eDP DSC support */
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u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
209
+
u32 drm_dp_dsc_slice_count_to_mask(int slice_count);
210
+
u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
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+
bool is_edp);
209
212
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
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bool is_edp);
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u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);