Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls
For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
VCPU config and registers from user-space.
We have three types of VCPU registers:
1. CONFIG - these are VCPU config and capabilities
2. CORE - these are VCPU general purpose registers
3. CSR - these are VCPU control and status registers
The CONFIG register available to user-space is ISA. The ISA register is
a read and write register where user-space can only write the desired
VCPU ISA capabilities before running the VCPU.
The CORE registers available to user-space are PC, RA, SP, GP, TP, A0-A7,
T0-T6, S0-S11 and MODE. Most of these are RISC-V general registers except
PC and MODE. The PC register represents program counter whereas the MODE
register represent VCPU privilege mode (i.e. S/U-mode).
The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
In future, more VCPU register types will be added (such as FP) for the
KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
authored by
Anup Patel
and committed by
Anup Patel
92ad8200
cce69aff
+290
-4
+52
-1
arch/riscv/include/uapi/asm/kvm.h
+52
-1
arch/riscv/include/uapi/asm/kvm.h
···
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struct kvm_sync_regs {
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};
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-
/* dummy definition */
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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};
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/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_config {
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unsigned long isa;
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};
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/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_core {
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struct user_regs_struct regs;
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unsigned long mode;
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};
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/* Possible privilege modes for kvm_riscv_core */
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#define KVM_RISCV_MODE_S 1
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#define KVM_RISCV_MODE_U 0
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/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_csr {
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unsigned long sstatus;
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unsigned long sie;
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unsigned long stvec;
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unsigned long sscratch;
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unsigned long sepc;
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unsigned long scause;
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unsigned long stval;
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unsigned long sip;
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unsigned long satp;
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unsigned long scounteren;
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};
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
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#define KVM_REG_RISCV_TYPE_SHIFT 24
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/* Config registers are mapped as type 1 */
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#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CONFIG_REG(name) \
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(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
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/* Core registers are mapped as type 2 */
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#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CORE_REG(name) \
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(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
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/* Control and status registers are mapped as type 3 */
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#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_REG(name) \
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(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
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#endif
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+238
-3
arch/riscv/kvm/vcpu.c
+238
-3
arch/riscv/kvm/vcpu.c
···
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#include <linux/fs.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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-
#include <asm/delay.h>
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#include <asm/hwcap.h>
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const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
···
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return VM_FAULT_SIGBUS;
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}
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static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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reg_val = vcpu->arch.isa;
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break;
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default:
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return -EINVAL;
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};
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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if (!vcpu->arch.ran_atleast_once) {
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vcpu->arch.isa = reg_val;
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vcpu->arch.isa &= riscv_isa_extension_base(NULL);
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vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
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} else {
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return -EOPNOTSUPP;
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}
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break;
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default:
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return -EINVAL;
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};
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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reg_val = cntx->sepc;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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reg_val = ((unsigned long *)cntx)[reg_num];
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
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reg_val = (cntx->sstatus & SR_SPP) ?
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KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
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else
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return -EINVAL;
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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cntx->sepc = reg_val;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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((unsigned long *)cntx)[reg_num] = reg_val;
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
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if (reg_val == KVM_RISCV_MODE_S)
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cntx->sstatus |= SR_SPP;
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else
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cntx->sstatus &= ~SR_SPP;
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} else
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return -EINVAL;
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CSR);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
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return -EINVAL;
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+
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
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kvm_riscv_vcpu_flush_interrupts(vcpu);
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reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
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} else
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reg_val = ((unsigned long *)csr)[reg_num];
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CSR);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
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reg_val &= VSIP_VALID_MASK;
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reg_val <<= VSIP_TO_HVIP_SHIFT;
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}
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((unsigned long *)csr)[reg_num] = reg_val;
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if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
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WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
329
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{
330
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if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
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return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
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return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
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return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
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return -EINVAL;
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}
339
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static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
341
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const struct kvm_one_reg *reg)
342
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{
343
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if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
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return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
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return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
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else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
348
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return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
349
+
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return -EINVAL;
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}
352
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long kvm_arch_vcpu_async_ioctl(struct file *filp,
139
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unsigned int ioctl, unsigned long arg)
140
355
{
···
373
160
long kvm_arch_vcpu_ioctl(struct file *filp,
374
161
unsigned int ioctl, unsigned long arg)
375
162
{
376
-
/* TODO: */
377
-
return -EINVAL;
163
+
struct kvm_vcpu *vcpu = filp->private_data;
164
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void __user *argp = (void __user *)arg;
165
+
long r = -EINVAL;
166
+
167
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switch (ioctl) {
168
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case KVM_SET_ONE_REG:
169
+
case KVM_GET_ONE_REG: {
170
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struct kvm_one_reg reg;
171
+
172
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r = -EFAULT;
173
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if (copy_from_user(®, argp, sizeof(reg)))
174
+
break;
175
+
176
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if (ioctl == KVM_SET_ONE_REG)
177
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r = kvm_riscv_vcpu_set_reg(vcpu, ®);
178
+
else
179
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r = kvm_riscv_vcpu_get_reg(vcpu, ®);
180
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break;
181
+
}
182
+
default:
183
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break;
184
+
}
185
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186
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return r;
378
187
}
379
188
380
189
int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,