tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY

The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Rohit Agarwal and committed by
Vinod Koul 92bd868f 0d678713

+193
+165
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1270 1270 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1271 1271 }; 1272 1272 1273 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1274 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1275 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1276 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1277 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1278 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1279 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1280 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1281 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1282 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1283 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1284 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1285 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1286 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1287 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1288 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1289 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1290 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1291 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1292 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1293 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1294 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1295 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1296 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1297 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1298 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1299 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1300 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1301 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1302 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1303 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1304 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1305 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1306 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1307 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1308 + }; 1309 + 1310 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1311 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1312 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1313 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1314 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1315 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1316 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1317 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1318 + QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1319 + }; 1320 + 1321 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1322 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1323 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1324 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1325 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1326 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1327 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1328 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1329 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1330 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1331 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1332 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1333 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1334 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1335 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1336 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1337 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1338 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1339 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1340 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1341 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1342 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1343 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1344 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1345 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1346 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1347 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1348 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1349 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1350 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1351 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1352 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1353 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1354 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1355 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1356 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1357 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1358 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1359 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1360 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1361 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1362 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1363 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1364 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1365 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 1366 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1367 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1368 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1369 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1370 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 1371 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1372 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1373 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 1374 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1375 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1376 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 1377 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 1378 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1379 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1380 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1381 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1382 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1383 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 1384 + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1385 + }; 1386 + 1387 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 1388 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1389 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 1390 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 1391 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1392 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1393 + }; 1394 + 1395 + static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 1396 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1397 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1398 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1399 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1400 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1401 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1402 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1403 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1404 + }; 1405 + 1273 1406 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1274 1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1275 1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), ··· 2581 2448 .phy_status = PHYSTATUS, 2582 2449 }; 2583 2450 2451 + static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 2452 + .lanes = 2, 2453 + 2454 + .offsets = &qmp_pcie_offsets_v6_20, 2455 + 2456 + .tbls = { 2457 + .serdes = sdx65_qmp_pcie_serdes_tbl, 2458 + .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 2459 + .tx = sdx65_qmp_pcie_tx_tbl, 2460 + .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 2461 + .rx = sdx65_qmp_pcie_rx_tbl, 2462 + .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 2463 + .pcs = sdx65_qmp_pcie_pcs_tbl, 2464 + .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 2465 + .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 2466 + .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 2467 + }, 2468 + .clk_list = sdm845_pciephy_clk_l, 2469 + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2470 + .reset_list = sdm845_pciephy_reset_l, 2471 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2472 + .vreg_list = qmp_phy_vreg_l, 2473 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2474 + .regs = pciephy_v5_regs_layout, 2475 + 2476 + .pwrdn_ctrl = SW_PWRDN, 2477 + .phy_status = PHYSTATUS_4_20, 2478 + }; 2479 + 2584 2480 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2585 2481 .lanes = 1, 2586 2482 ··· 3403 3241 }, { 3404 3242 .compatible = "qcom,sdx55-qmp-pcie-phy", 3405 3243 .data = &sdx55_qmp_pciephy_cfg, 3244 + }, { 3245 + .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 3246 + .data = &sdx65_qmp_pciephy_cfg, 3406 3247 }, { 3407 3248 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 3408 3249 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
+3
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
··· 12 12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 13 13 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 14 14 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 15 + #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 15 16 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 16 17 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 17 18 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 19 + #define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24 20 + #define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28 18 21 19 22 #endif
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
··· 8 8 9 9 #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170 10 10 #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188 11 + #define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8 11 12 #define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0 12 13 #define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4 13 14
+24
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h
··· 11 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 + #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 15 + #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 16 + #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 17 + #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 14 18 15 19 /* Only for QMP V5_20 PHY - RX registers */ 16 20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 ··· 23 19 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 24 20 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 25 21 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 22 + #define QSERDES_V5_20_RX_DFE_1 0x088 23 + #define QSERDES_V5_20_RX_DFE_2 0x08c 26 24 #define QSERDES_V5_20_RX_DFE_3 0x090 27 25 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 26 + #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc 27 + #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c0 28 28 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 29 29 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 30 + #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc 31 + #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d0 32 + #define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d4 33 + #define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d8 30 34 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 31 35 #define QSERDES_V5_20_RX_GM_CAL 0x0ec 36 + #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x100 37 + #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x104 32 38 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 39 + #define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x118 40 + #define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c 41 + #define QSERDES_V5_20_RX_SIGDET_ENABLES 0x120 42 + #define QSERDES_V5_20_RX_SIGDET_CNTRL 0x124 43 + #define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c 44 + #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x160 33 45 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 34 46 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 35 47 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 48 + #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x170 36 49 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 37 50 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 38 51 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c ··· 67 46 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 68 47 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 69 48 #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 49 + #define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b8 50 + #define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc 70 51 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 52 + #define QSERDES_V5_20_RX_DCC_CTRL1 0x1c4 71 53 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 72 54 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 73 55 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc