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x86/apic: Remove pointless fence in lapic_next_deadline()

lapic_next_deadline() contains a fence before the TSC read and the write to
the TSC_DEADLINE MSR with a content free and therefore useless comment:

/* This MSR is special and need a special fence: */

The MSR is not really special. It is just not a serializing MSR, but that
does not matter at all in this context as all of these operations are
strictly CPU local.

The only thing the fence prevents is that the RDTSC is speculated ahead,
but that's not really relevant as the delta is calculated way before based
on a previous TSC read and therefore inaccurate by definition.

So removing the fence is just making it slightly more inaccurate in the
worst case, but that is irrelevant as it's way below the actual system
immanent latencies and variations.

Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260224163429.809059527@kernel.org

authored by

Thomas Gleixner and committed by
Peter Zijlstra 92d0e753 b2780118

+7 -9
+7 -9
arch/x86/kernel/apic/apic.c
··· 412 412 /* 413 413 * Program the next event, relative to now 414 414 */ 415 - static int lapic_next_event(unsigned long delta, 416 - struct clock_event_device *evt) 415 + static int lapic_next_event(unsigned long delta, struct clock_event_device *evt) 417 416 { 418 417 apic_write(APIC_TMICT, delta); 419 418 return 0; 420 419 } 421 420 422 - static int lapic_next_deadline(unsigned long delta, 423 - struct clock_event_device *evt) 421 + static int lapic_next_deadline(unsigned long delta, struct clock_event_device *evt) 424 422 { 425 - u64 tsc; 423 + /* 424 + * There is no weak_wrmsr_fence() required here as all of this is purely 425 + * CPU local. Avoid the [ml]fence overhead. 426 + */ 427 + u64 tsc = rdtsc(); 426 428 427 - /* This MSR is special and need a special fence: */ 428 - weak_wrmsr_fence(); 429 - 430 - tsc = rdtsc(); 431 429 wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 432 430 return 0; 433 431 }