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dt-bindings: interrupt-controller: Convert arm,nvic to DT schema
Convert the Arm NVIC interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.
Link: https://lore.kernel.org/r/20250505144553.1286730-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt
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Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt
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* ARM Nested Vector Interrupt Controller (NVIC)
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The NVIC provides an interrupt controller that is tightly coupled to
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Cortex-M based processor cores. The NVIC implemented on different SoCs
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vary in the number of interrupts and priority bits per interrupt.
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Main node required properties:
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-
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- compatible : should be one of:
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"arm,v6m-nvic"
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"arm,v7m-nvic"
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"arm,v8m-nvic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 2.
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The 1st cell contains the interrupt number for the interrupt type.
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The 2nd cell is the priority of the interrupt.
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- reg : Specifies base physical address(s) and size of the NVIC registers.
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This is at a fixed address (0xe000e100) and size (0xc00).
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- arm,num-irq-priority-bits: The number of priority bits implemented by the
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given SoC
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Example:
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intc: interrupt-controller@e000e100 {
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compatible = "arm,v7m-nvic";
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#interrupt-cells = <2>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xe000e100 0xc00>;
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arm,num-irq-priority-bits = <4>;
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};
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Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
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Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Nested Vector Interrupt Controller (NVIC)
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maintainers:
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- Rob Herring <robh@kernel.org>
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description:
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The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
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based processor cores. The NVIC implemented on different SoCs vary in the
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number of interrupts and priority bits per interrupt.
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properties:
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compatible:
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enum:
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- arm,v6m-nvic
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- arm,v7m-nvic
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- arm,v8m-nvic
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reg:
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maxItems: 1
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'#address-cells':
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const: 0
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description: |
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Number of cells to encode an interrupt source:
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first = interrupt number, second = priority.
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arm,num-irq-priority-bits:
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description: Number of priority bits implemented by the SoC
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minimum: 1
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maximum: 8
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- arm,num-irq-priority-bits
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additionalProperties: false
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examples:
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- |
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interrupt-controller@e000e100 {
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compatible = "arm,v7m-nvic";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe000e100 0xc00>;
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arm,num-irq-priority-bits = <4>;
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};