Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Radeon and intel fixes mostly, one fix to the mgag200 driver to not
hang on certain server variants."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (32 commits)
drm/radeon: fix typo in function header comment
drm/radeon/kms: implement timestamp userspace query (v2)
drm/radeon/kms: add MSAA texture support for r600-evergreen
drm/radeon/kms: reorder code in r600_check_texture_resource
drm/radeon: fence virtual address and free it once idle v4
drm/radeon: fix some missing parens in asic macros
drm/radeon: add some new SI pci ids
drm/radeon: fix ordering in pll picking on dce4+
drm/radeon: do not reenable crtc after moving vram start address
drm/radeon: fix bank tiling parameters on cayman
drm/radeon: fix bank tiling parameters on evergreen
drm/radeon: fix bank tiling parameters on SI
drm/radeon: properly handle crtc powergating
drm/radeon: properly handle SS overrides on TN (v2)
drm/radeon/dce4+: set a more reasonable cursor watermark
drm/radeon: fix handling for ddc type 5 on combios
drm/mgag200: fix G200ER pll picking algorithm
drm/edid: Fix potential memory leak in edid_load()
drm/udl: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(.. [1]
drm/radeon/kms: allow "invalid" DB formats as a means to disable DB
...
+516
-239
+34
-5
drivers/char/agp/intel-agp.h
+34
-5
drivers/char/agp/intel-agp.h
···
239
239
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
240
240
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
241
241
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
242
-
#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
242
+
#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
243
243
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
244
244
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
245
-
#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
245
+
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422
246
+
#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
246
247
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
247
248
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
248
-
#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
249
+
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426
250
+
#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
249
251
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
250
252
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
251
-
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV 0x0c16 /* SDV */
252
-
#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
253
+
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a
254
+
#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
255
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02
256
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12
257
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22
258
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06
259
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16
260
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26
261
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A
262
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A
263
+
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A
264
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02
265
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12
266
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22
267
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06
268
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16
269
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26
270
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A
271
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A
272
+
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A
273
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12
274
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22
275
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32
276
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16
277
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26
278
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36
279
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A
280
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A
281
+
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A
253
282
254
283
#endif
+59
-1
drivers/char/agp/intel-gtt.c
+59
-1
drivers/char/agp/intel-gtt.c
···
1502
1502
"Haswell", &sandybridge_gtt_driver },
1503
1503
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
1504
1504
"Haswell", &sandybridge_gtt_driver },
1505
+
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
1506
+
"Haswell", &sandybridge_gtt_driver },
1505
1507
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
1506
1508
"Haswell", &sandybridge_gtt_driver },
1507
1509
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
1510
+
"Haswell", &sandybridge_gtt_driver },
1511
+
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
1508
1512
"Haswell", &sandybridge_gtt_driver },
1509
1513
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
1510
1514
"Haswell", &sandybridge_gtt_driver },
1511
1515
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
1512
1516
"Haswell", &sandybridge_gtt_driver },
1513
-
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
1517
+
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
1518
+
"Haswell", &sandybridge_gtt_driver },
1519
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
1520
+
"Haswell", &sandybridge_gtt_driver },
1521
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
1522
+
"Haswell", &sandybridge_gtt_driver },
1523
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
1524
+
"Haswell", &sandybridge_gtt_driver },
1525
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
1526
+
"Haswell", &sandybridge_gtt_driver },
1527
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
1528
+
"Haswell", &sandybridge_gtt_driver },
1529
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
1530
+
"Haswell", &sandybridge_gtt_driver },
1531
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
1532
+
"Haswell", &sandybridge_gtt_driver },
1533
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
1534
+
"Haswell", &sandybridge_gtt_driver },
1535
+
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
1536
+
"Haswell", &sandybridge_gtt_driver },
1537
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
1538
+
"Haswell", &sandybridge_gtt_driver },
1539
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
1540
+
"Haswell", &sandybridge_gtt_driver },
1541
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
1542
+
"Haswell", &sandybridge_gtt_driver },
1543
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
1544
+
"Haswell", &sandybridge_gtt_driver },
1545
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
1546
+
"Haswell", &sandybridge_gtt_driver },
1547
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
1548
+
"Haswell", &sandybridge_gtt_driver },
1549
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
1550
+
"Haswell", &sandybridge_gtt_driver },
1551
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
1552
+
"Haswell", &sandybridge_gtt_driver },
1553
+
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
1554
+
"Haswell", &sandybridge_gtt_driver },
1555
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
1556
+
"Haswell", &sandybridge_gtt_driver },
1557
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
1558
+
"Haswell", &sandybridge_gtt_driver },
1559
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
1560
+
"Haswell", &sandybridge_gtt_driver },
1561
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
1562
+
"Haswell", &sandybridge_gtt_driver },
1563
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
1564
+
"Haswell", &sandybridge_gtt_driver },
1565
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
1566
+
"Haswell", &sandybridge_gtt_driver },
1567
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
1568
+
"Haswell", &sandybridge_gtt_driver },
1569
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
1570
+
"Haswell", &sandybridge_gtt_driver },
1571
+
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
1514
1572
"Haswell", &sandybridge_gtt_driver },
1515
1573
{ 0, NULL, NULL }
1516
1574
};
+5
-3
drivers/gpu/drm/drm_edid_load.c
+5
-3
drivers/gpu/drm/drm_edid_load.c
···
119
119
{
120
120
const struct firmware *fw;
121
121
struct platform_device *pdev;
122
-
u8 *fwdata = NULL, *edid;
122
+
u8 *fwdata = NULL, *edid, *new_edid;
123
123
int fwsize, expected;
124
124
int builtin = 0, err = 0;
125
125
int i, valid_extensions = 0;
···
195
195
"\"%s\" for connector \"%s\"\n", valid_extensions,
196
196
edid[0x7e], name, connector_name);
197
197
edid[0x7e] = valid_extensions;
198
-
edid = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH,
198
+
new_edid = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH,
199
199
GFP_KERNEL);
200
-
if (edid == NULL) {
200
+
if (new_edid == NULL) {
201
201
err = -ENOMEM;
202
+
kfree(edid);
202
203
goto relfw_out;
203
204
}
205
+
edid = new_edid;
204
206
}
205
207
206
208
connector->display_info.raw_edid = edid;
+30
-1
drivers/gpu/drm/i915/i915_drv.c
+30
-1
drivers/gpu/drm/i915/i915_drv.c
···
346
346
INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
347
347
INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
348
348
INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
349
+
INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349
350
INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350
351
INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
352
+
INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
351
353
INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
352
354
INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
353
-
INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
355
+
INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
356
+
INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
357
+
INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
358
+
INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
359
+
INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
360
+
INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
361
+
INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
362
+
INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
363
+
INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
364
+
INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
365
+
INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
366
+
INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
367
+
INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
368
+
INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
369
+
INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
370
+
INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
371
+
INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
372
+
INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
373
+
INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
374
+
INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
375
+
INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
376
+
INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
377
+
INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
378
+
INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
379
+
INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
380
+
INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
381
+
INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
382
+
INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
354
383
INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
355
384
INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
356
385
INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
-1
drivers/gpu/drm/i915/i915_gem_context.c
-1
drivers/gpu/drm/i915/i915_gem_context.c
+10
-10
drivers/gpu/drm/i915/i915_gem_execbuffer.c
+10
-10
drivers/gpu/drm/i915/i915_gem_execbuffer.c
···
291
291
target_i915_obj = to_intel_bo(target_obj);
292
292
target_offset = target_i915_obj->gtt_offset;
293
293
294
+
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
295
+
* pipe_control writes because the gpu doesn't properly redirect them
296
+
* through the ppgtt for non_secure batchbuffers. */
297
+
if (unlikely(IS_GEN6(dev) &&
298
+
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
299
+
!target_i915_obj->has_global_gtt_mapping)) {
300
+
i915_gem_gtt_bind_object(target_i915_obj,
301
+
target_i915_obj->cache_level);
302
+
}
303
+
294
304
/* The target buffer should have appeared before us in the
295
305
* exec_object list, so it should have a GTT space bound by now.
296
306
*/
···
407
397
(reloc_page + (reloc->offset & ~PAGE_MASK));
408
398
iowrite32(reloc->delta, reloc_entry);
409
399
io_mapping_unmap_atomic(reloc_page);
410
-
}
411
-
412
-
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
413
-
* pipe_control writes because the gpu doesn't properly redirect them
414
-
* through the ppgtt for non_secure batchbuffers. */
415
-
if (unlikely(IS_GEN6(dev) &&
416
-
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
417
-
!target_i915_obj->has_global_gtt_mapping)) {
418
-
i915_gem_gtt_bind_object(target_i915_obj,
419
-
target_i915_obj->cache_level);
420
400
}
421
401
422
402
/* and update the user's relocation entry */
+2
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
+2
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
···
361
361
struct drm_device *dev = obj->base.dev;
362
362
struct drm_i915_private *dev_priv = dev->dev_private;
363
363
364
-
if (dev_priv->mm.gtt->needs_dmar)
364
+
/* don't map imported dma buf objects */
365
+
if (dev_priv->mm.gtt->needs_dmar && !obj->sg_table)
365
366
return intel_gtt_map_memory(obj->pages,
366
367
obj->base.size >> PAGE_SHIFT,
367
368
&obj->sg_list,
+12
drivers/gpu/drm/i915/i915_sysfs.c
+12
drivers/gpu/drm/i915/i915_sysfs.c
···
32
32
#include "intel_drv.h"
33
33
#include "i915_drv.h"
34
34
35
+
#ifdef CONFIG_PM
35
36
static u32 calc_residency(struct drm_device *dev, const u32 reg)
36
37
{
37
38
struct drm_i915_private *dev_priv = dev->dev_private;
···
225
224
device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
226
225
sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
227
226
}
227
+
#else
228
+
void i915_setup_sysfs(struct drm_device *dev)
229
+
{
230
+
return;
231
+
}
232
+
233
+
void i915_teardown_sysfs(struct drm_device *dev)
234
+
{
235
+
return;
236
+
}
237
+
#endif /* CONFIG_PM */
+1
drivers/gpu/drm/i915/intel_display.c
+1
drivers/gpu/drm/i915/intel_display.c
+10
-10
drivers/gpu/drm/i915/intel_drv.h
+10
-10
drivers/gpu/drm/i915/intel_drv.h
···
46
46
})
47
47
48
48
#define wait_for_atomic_us(COND, US) ({ \
49
-
int i, ret__ = -ETIMEDOUT; \
50
-
for (i = 0; i < (US); i++) { \
51
-
if ((COND)) { \
52
-
ret__ = 0; \
53
-
break; \
54
-
} \
55
-
udelay(1); \
56
-
} \
57
-
ret__; \
49
+
unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
50
+
int ret__ = 0; \
51
+
while (!(COND)) { \
52
+
if (time_after(jiffies, timeout__)) { \
53
+
ret__ = -ETIMEDOUT; \
54
+
break; \
55
+
} \
56
+
cpu_relax(); \
57
+
} \
58
+
ret__; \
58
59
})
59
60
60
61
#define wait_for(COND, MS) _wait_for(COND, MS, 1)
···
381
380
const struct drm_display_mode *mode,
382
381
struct drm_display_mode *adjusted_mode);
383
382
extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
384
-
extern u32 intel_panel_get_backlight(struct drm_device *dev);
385
383
extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
386
384
extern int intel_panel_setup_backlight(struct drm_device *dev);
387
385
extern void intel_panel_enable_backlight(struct drm_device *dev,
-3
drivers/gpu/drm/i915/intel_i2c.c
-3
drivers/gpu/drm/i915/intel_i2c.c
+1
-1
drivers/gpu/drm/i915/intel_panel.c
+1
-1
drivers/gpu/drm/i915/intel_panel.c
+4
-2
drivers/gpu/drm/i915/intel_pm.c
+4
-2
drivers/gpu/drm/i915/intel_pm.c
···
3963
3963
DRM_ERROR("Force wake wait timed out\n");
3964
3964
3965
3965
I915_WRITE_NOTRACE(FORCEWAKE, 1);
3966
+
POSTING_READ(FORCEWAKE);
3966
3967
3967
3968
if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3968
3969
DRM_ERROR("Force wake wait timed out\n");
···
3984
3983
DRM_ERROR("Force wake wait timed out\n");
3985
3984
3986
3985
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
3986
+
POSTING_READ(FORCEWAKE_MT);
3987
3987
3988
3988
if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3989
3989
DRM_ERROR("Force wake wait timed out\n");
···
4020
4018
static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4021
4019
{
4022
4020
I915_WRITE_NOTRACE(FORCEWAKE, 0);
4023
-
/* The below doubles as a POSTING_READ */
4021
+
POSTING_READ(FORCEWAKE);
4024
4022
gen6_gt_check_fifodbg(dev_priv);
4025
4023
}
4026
4024
4027
4025
static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4028
4026
{
4029
4027
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
4030
-
/* The below doubles as a POSTING_READ */
4028
+
POSTING_READ(FORCEWAKE_MT);
4031
4029
gen6_gt_check_fifodbg(dev_priv);
4032
4030
}
4033
4031
+5
-2
drivers/gpu/drm/i915/intel_ringbuffer.c
+5
-2
drivers/gpu/drm/i915/intel_ringbuffer.c
···
289
289
I915_WRITE_HEAD(ring, 0);
290
290
ring->write_tail(ring, 0);
291
291
292
-
/* Initialize the ring. */
293
-
I915_WRITE_START(ring, obj->gtt_offset);
294
292
head = I915_READ_HEAD(ring) & HEAD_ADDR;
295
293
296
294
/* G45 ring initialization fails to reset head to zero */
···
314
316
}
315
317
}
316
318
319
+
/* Initialize the ring. This must happen _after_ we've cleared the ring
320
+
* registers with the above sequence (the readback of the HEAD registers
321
+
* also enforces ordering), otherwise the hw might lose the new ring
322
+
* register values. */
323
+
I915_WRITE_START(ring, obj->gtt_offset);
317
324
I915_WRITE_CTL(ring,
318
325
((ring->size - PAGE_SIZE) & RING_NR_PAGES)
319
326
| RING_VALID);
+4
-1
drivers/gpu/drm/i915/intel_sdvo.c
+4
-1
drivers/gpu/drm/i915/intel_sdvo.c
···
444
444
struct i2c_msg *msgs;
445
445
int i, ret = true;
446
446
447
+
/* Would be simpler to allocate both in one go ? */
447
448
buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448
449
if (!buf)
449
450
return false;
450
451
451
452
msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
452
-
if (!msgs)
453
+
if (!msgs) {
454
+
kfree(buf);
453
455
return false;
456
+
}
454
457
455
458
intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
456
459
+7
-5
drivers/gpu/drm/mgag200/mgag200_mode.c
+7
-5
drivers/gpu/drm/mgag200/mgag200_mode.c
···
468
468
{
469
469
unsigned int vcomax, vcomin, pllreffreq;
470
470
unsigned int delta, tmpdelta;
471
-
unsigned int testr, testn, testm, testo;
471
+
int testr, testn, testm, testo;
472
472
unsigned int p, m, n;
473
-
unsigned int computed;
473
+
unsigned int computed, vco;
474
474
int tmp;
475
+
const unsigned int m_div_val[] = { 1, 2, 4, 8 };
475
476
476
477
m = n = p = 0;
477
478
vcomax = 1488000;
···
491
490
if (delta == 0)
492
491
break;
493
492
for (testo = 5; testo < 33; testo++) {
494
-
computed = pllreffreq * (testn + 1) /
493
+
vco = pllreffreq * (testn + 1) /
495
494
(testr + 1);
496
-
if (computed < vcomin)
495
+
if (vco < vcomin)
497
496
continue;
498
-
if (computed > vcomax)
497
+
if (vco > vcomax)
499
498
continue;
499
+
computed = vco / (m_div_val[testm] * (testo + 1));
500
500
if (computed > clock)
501
501
tmpdelta = computed - clock;
502
502
else
+16
-6
drivers/gpu/drm/radeon/atombios_crtc.c
+16
-6
drivers/gpu/drm/radeon/atombios_crtc.c
···
259
259
/* adjust pm to dpms changes BEFORE enabling crtcs */
260
260
radeon_pm_compute_clocks(rdev);
261
261
/* disable crtc pair power gating before programming */
262
-
if (ASIC_IS_DCE6(rdev))
262
+
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
263
263
atombios_powergate_crtc(crtc, ATOM_DISABLE);
264
264
atombios_enable_crtc(crtc, ATOM_ENABLE);
265
265
if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
···
279
279
atombios_enable_crtc(crtc, ATOM_DISABLE);
280
280
radeon_crtc->enabled = false;
281
281
/* power gating is per-pair */
282
-
if (ASIC_IS_DCE6(rdev)) {
282
+
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {
283
283
struct drm_crtc *other_crtc;
284
284
struct radeon_crtc *other_radeon_crtc;
285
285
list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
···
1531
1531
* crtc virtual pixel clock.
1532
1532
*/
1533
1533
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1534
-
if (ASIC_IS_DCE5(rdev))
1535
-
return ATOM_DCPLL;
1534
+
if (rdev->clock.dp_extclk)
1535
+
return ATOM_PPLL_INVALID;
1536
1536
else if (ASIC_IS_DCE6(rdev))
1537
1537
return ATOM_PPLL0;
1538
-
else if (rdev->clock.dp_extclk)
1539
-
return ATOM_PPLL_INVALID;
1538
+
else if (ASIC_IS_DCE5(rdev))
1539
+
return ATOM_DCPLL;
1540
1540
}
1541
1541
}
1542
1542
}
···
1635
1635
static void atombios_crtc_prepare(struct drm_crtc *crtc)
1636
1636
{
1637
1637
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1638
+
struct drm_device *dev = crtc->dev;
1639
+
struct radeon_device *rdev = dev->dev_private;
1638
1640
1641
+
radeon_crtc->in_mode_set = true;
1639
1642
/* pick pll */
1640
1643
radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1644
+
1645
+
/* disable crtc pair power gating before programming */
1646
+
if (ASIC_IS_DCE6(rdev))
1647
+
atombios_powergate_crtc(crtc, ATOM_DISABLE);
1641
1648
1642
1649
atombios_lock_crtc(crtc, ATOM_ENABLE);
1643
1650
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
···
1652
1645
1653
1646
static void atombios_crtc_commit(struct drm_crtc *crtc)
1654
1647
{
1648
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1649
+
1655
1650
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1656
1651
atombios_lock_crtc(crtc, ATOM_DISABLE);
1652
+
radeon_crtc->in_mode_set = false;
1657
1653
}
1658
1654
1659
1655
static void atombios_crtc_disable(struct drm_crtc *crtc)
+11
-60
drivers/gpu/drm/radeon/evergreen.c
+11
-60
drivers/gpu/drm/radeon/evergreen.c
···
1229
1229
1230
1230
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1231
1231
{
1232
-
save->vga_control[0] = RREG32(D1VGA_CONTROL);
1233
-
save->vga_control[1] = RREG32(D2VGA_CONTROL);
1234
1232
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1235
1233
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1236
-
save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1237
-
save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1238
-
if (rdev->num_crtc >= 4) {
1239
-
save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1240
-
save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1241
-
save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1242
-
save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1243
-
}
1244
-
if (rdev->num_crtc >= 6) {
1245
-
save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1246
-
save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1247
-
save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1248
-
save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1249
-
}
1250
1234
1251
1235
/* Stop all video */
1252
1236
WREG32(VGA_RENDER_CONTROL, 0);
···
1341
1357
/* Unlock host access */
1342
1358
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1343
1359
mdelay(1);
1344
-
/* Restore video state */
1345
-
WREG32(D1VGA_CONTROL, save->vga_control[0]);
1346
-
WREG32(D2VGA_CONTROL, save->vga_control[1]);
1347
-
if (rdev->num_crtc >= 4) {
1348
-
WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1349
-
WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1350
-
}
1351
-
if (rdev->num_crtc >= 6) {
1352
-
WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1353
-
WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1354
-
}
1355
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1356
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1357
-
if (rdev->num_crtc >= 4) {
1358
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1359
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1360
-
}
1361
-
if (rdev->num_crtc >= 6) {
1362
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1363
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1364
-
}
1365
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1366
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1367
-
if (rdev->num_crtc >= 4) {
1368
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1369
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1370
-
}
1371
-
if (rdev->num_crtc >= 6) {
1372
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1373
-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1374
-
}
1375
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1376
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1377
-
if (rdev->num_crtc >= 4) {
1378
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1379
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1380
-
}
1381
-
if (rdev->num_crtc >= 6) {
1382
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1383
-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1384
-
}
1385
1360
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1386
1361
}
1387
1362
···
1929
1986
if (rdev->flags & RADEON_IS_IGP)
1930
1987
rdev->config.evergreen.tile_config |= 1 << 4;
1931
1988
else {
1932
-
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1933
-
rdev->config.evergreen.tile_config |= 1 << 4;
1934
-
else
1989
+
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1990
+
case 0: /* four banks */
1935
1991
rdev->config.evergreen.tile_config |= 0 << 4;
1992
+
break;
1993
+
case 1: /* eight banks */
1994
+
rdev->config.evergreen.tile_config |= 1 << 4;
1995
+
break;
1996
+
case 2: /* sixteen banks */
1997
+
default:
1998
+
rdev->config.evergreen.tile_config |= 2 << 4;
1999
+
break;
2000
+
}
1936
2001
}
1937
2002
rdev->config.evergreen.tile_config |= 0 << 8;
1938
2003
rdev->config.evergreen.tile_config |=
+11
-2
drivers/gpu/drm/radeon/evergreen_cs.c
+11
-2
drivers/gpu/drm/radeon/evergreen_cs.c
···
788
788
case V_030000_SQ_TEX_DIM_1D_ARRAY:
789
789
case V_030000_SQ_TEX_DIM_2D_ARRAY:
790
790
depth = 1;
791
+
break;
792
+
case V_030000_SQ_TEX_DIM_2D_MSAA:
793
+
case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
794
+
surf.nsamples = 1 << llevel;
795
+
llevel = 0;
796
+
depth = 1;
797
+
break;
791
798
case V_030000_SQ_TEX_DIM_3D:
792
799
break;
793
800
default:
···
968
961
969
962
if (track->db_dirty) {
970
963
/* Check stencil buffer */
971
-
if (G_028800_STENCIL_ENABLE(track->db_depth_control)) {
964
+
if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
965
+
G_028800_STENCIL_ENABLE(track->db_depth_control)) {
972
966
r = evergreen_cs_track_validate_stencil(p);
973
967
if (r)
974
968
return r;
975
969
}
976
970
/* Check depth buffer */
977
-
if (G_028800_Z_ENABLE(track->db_depth_control)) {
971
+
if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
972
+
G_028800_Z_ENABLE(track->db_depth_control)) {
978
973
r = evergreen_cs_track_validate_depth(p);
979
974
if (r)
980
975
return r;
+2
drivers/gpu/drm/radeon/evergreend.h
+2
drivers/gpu/drm/radeon/evergreend.h
···
1277
1277
#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1278
1278
#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1279
1279
#define C_028044_FORMAT 0xFFFFFFFE
1280
+
#define V_028044_STENCIL_INVALID 0
1281
+
#define V_028044_STENCIL_8 1
1280
1282
#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1281
1283
#define DB_Z_READ_BASE 0x28048
1282
1284
#define DB_STENCIL_READ_BASE 0x2804c
+11
-3
drivers/gpu/drm/radeon/ni.c
+11
-3
drivers/gpu/drm/radeon/ni.c
···
574
574
if (rdev->flags & RADEON_IS_IGP)
575
575
rdev->config.cayman.tile_config |= 1 << 4;
576
576
else {
577
-
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
578
-
rdev->config.cayman.tile_config |= 1 << 4;
579
-
else
577
+
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578
+
case 0: /* four banks */
580
579
rdev->config.cayman.tile_config |= 0 << 4;
580
+
break;
581
+
case 1: /* eight banks */
582
+
rdev->config.cayman.tile_config |= 1 << 4;
583
+
break;
584
+
case 2: /* sixteen banks */
585
+
default:
586
+
rdev->config.cayman.tile_config |= 2 << 4;
587
+
break;
588
+
}
581
589
}
582
590
rdev->config.cayman.tile_config |=
583
591
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
+20
drivers/gpu/drm/radeon/r600.c
+20
drivers/gpu/drm/radeon/r600.c
···
3789
3789
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3790
3790
}
3791
3791
}
3792
+
3793
+
/**
3794
+
* r600_get_gpu_clock - return GPU clock counter snapshot
3795
+
*
3796
+
* @rdev: radeon_device pointer
3797
+
*
3798
+
* Fetches a GPU clock counter snapshot (R6xx-cayman).
3799
+
* Returns the 64 bit clock counter snapshot.
3800
+
*/
3801
+
uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
3802
+
{
3803
+
uint64_t clock;
3804
+
3805
+
mutex_lock(&rdev->gpu_clock_mutex);
3806
+
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3807
+
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3808
+
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3809
+
mutex_unlock(&rdev->gpu_clock_mutex);
3810
+
return clock;
3811
+
}
+36
-29
drivers/gpu/drm/radeon/r600_cs.c
+36
-29
drivers/gpu/drm/radeon/r600_cs.c
···
764
764
}
765
765
766
766
/* Check depth buffer */
767
-
if (track->db_dirty && (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
768
-
G_028800_Z_ENABLE(track->db_depth_control))) {
767
+
if (track->db_dirty &&
768
+
G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
769
+
(G_028800_STENCIL_ENABLE(track->db_depth_control) ||
770
+
G_028800_Z_ENABLE(track->db_depth_control))) {
769
771
r = r600_cs_track_validate_db(p);
770
772
if (r)
771
773
return r;
···
1559
1557
u32 tiling_flags)
1560
1558
{
1561
1559
struct r600_cs_track *track = p->track;
1562
-
u32 nfaces, llevel, blevel, w0, h0, d0;
1563
-
u32 word0, word1, l0_size, mipmap_size, word2, word3;
1560
+
u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1561
+
u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1564
1562
u32 height_align, pitch, pitch_align, depth_align;
1565
-
u32 array, barray, larray;
1563
+
u32 barray, larray;
1566
1564
u64 base_align;
1567
1565
struct array_mode_checker array_check;
1568
1566
u32 format;
1567
+
bool is_array;
1569
1568
1570
1569
/* on legacy kernel we don't perform advanced check */
1571
1570
if (p->rdev == NULL)
···
1584
1581
word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1585
1582
}
1586
1583
word1 = radeon_get_ib_value(p, idx + 1);
1584
+
word2 = radeon_get_ib_value(p, idx + 2) << 8;
1585
+
word3 = radeon_get_ib_value(p, idx + 3) << 8;
1586
+
word4 = radeon_get_ib_value(p, idx + 4);
1587
+
word5 = radeon_get_ib_value(p, idx + 5);
1588
+
dim = G_038000_DIM(word0);
1587
1589
w0 = G_038000_TEX_WIDTH(word0) + 1;
1590
+
pitch = (G_038000_PITCH(word0) + 1) * 8;
1588
1591
h0 = G_038004_TEX_HEIGHT(word1) + 1;
1589
1592
d0 = G_038004_TEX_DEPTH(word1);
1593
+
format = G_038004_DATA_FORMAT(word1);
1594
+
blevel = G_038010_BASE_LEVEL(word4);
1595
+
llevel = G_038014_LAST_LEVEL(word5);
1596
+
/* pitch in texels */
1597
+
array_check.array_mode = G_038000_TILE_MODE(word0);
1598
+
array_check.group_size = track->group_size;
1599
+
array_check.nbanks = track->nbanks;
1600
+
array_check.npipes = track->npipes;
1601
+
array_check.nsamples = 1;
1602
+
array_check.blocksize = r600_fmt_get_blocksize(format);
1590
1603
nfaces = 1;
1591
-
array = 0;
1592
-
switch (G_038000_DIM(word0)) {
1604
+
is_array = false;
1605
+
switch (dim) {
1593
1606
case V_038000_SQ_TEX_DIM_1D:
1594
1607
case V_038000_SQ_TEX_DIM_2D:
1595
1608
case V_038000_SQ_TEX_DIM_3D:
···
1618
1599
break;
1619
1600
case V_038000_SQ_TEX_DIM_1D_ARRAY:
1620
1601
case V_038000_SQ_TEX_DIM_2D_ARRAY:
1621
-
array = 1;
1602
+
is_array = true;
1622
1603
break;
1623
-
case V_038000_SQ_TEX_DIM_2D_MSAA:
1624
1604
case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1605
+
is_array = true;
1606
+
/* fall through */
1607
+
case V_038000_SQ_TEX_DIM_2D_MSAA:
1608
+
array_check.nsamples = 1 << llevel;
1609
+
llevel = 0;
1610
+
break;
1625
1611
default:
1626
1612
dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1627
1613
return -EINVAL;
1628
1614
}
1629
-
format = G_038004_DATA_FORMAT(word1);
1630
1615
if (!r600_fmt_is_valid_texture(format, p->family)) {
1631
1616
dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1632
1617
__func__, __LINE__, format);
1633
1618
return -EINVAL;
1634
1619
}
1635
1620
1636
-
/* pitch in texels */
1637
-
pitch = (G_038000_PITCH(word0) + 1) * 8;
1638
-
array_check.array_mode = G_038000_TILE_MODE(word0);
1639
-
array_check.group_size = track->group_size;
1640
-
array_check.nbanks = track->nbanks;
1641
-
array_check.npipes = track->npipes;
1642
-
array_check.nsamples = 1;
1643
-
array_check.blocksize = r600_fmt_get_blocksize(format);
1644
1621
if (r600_get_array_mode_alignment(&array_check,
1645
1622
&pitch_align, &height_align, &depth_align, &base_align)) {
1646
1623
dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
···
1662
1647
return -EINVAL;
1663
1648
}
1664
1649
1665
-
word2 = radeon_get_ib_value(p, idx + 2) << 8;
1666
-
word3 = radeon_get_ib_value(p, idx + 3) << 8;
1667
-
1668
-
word0 = radeon_get_ib_value(p, idx + 4);
1669
-
word1 = radeon_get_ib_value(p, idx + 5);
1670
-
blevel = G_038010_BASE_LEVEL(word0);
1671
-
llevel = G_038014_LAST_LEVEL(word1);
1672
1650
if (blevel > llevel) {
1673
1651
dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1674
1652
blevel, llevel);
1675
1653
}
1676
-
if (array == 1) {
1677
-
barray = G_038014_BASE_ARRAY(word1);
1678
-
larray = G_038014_LAST_ARRAY(word1);
1654
+
if (is_array) {
1655
+
barray = G_038014_BASE_ARRAY(word5);
1656
+
larray = G_038014_LAST_ARRAY(word5);
1679
1657
1680
1658
nfaces = larray - barray + 1;
1681
1659
}
···
1685
1677
return -EINVAL;
1686
1678
}
1687
1679
/* using get ib will give us the offset into the mipmap bo */
1688
-
word3 = radeon_get_ib_value(p, idx + 3) << 8;
1689
1680
if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1690
1681
/*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1691
1682
w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
+3
drivers/gpu/drm/radeon/r600d.h
+3
drivers/gpu/drm/radeon/r600d.h
···
602
602
#define RLC_HB_WPTR 0x3f1c
603
603
#define RLC_HB_WPTR_LSB_ADDR 0x3f14
604
604
#define RLC_HB_WPTR_MSB_ADDR 0x3f18
605
+
#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
606
+
#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
607
+
#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
605
608
#define RLC_MC_CNTL 0x3f44
606
609
#define RLC_UCODE_CNTL 0x3f48
607
610
#define RLC_UCODE_ADDR 0x3f2c
+7
-5
drivers/gpu/drm/radeon/radeon.h
+7
-5
drivers/gpu/drm/radeon/radeon.h
···
300
300
uint64_t soffset;
301
301
uint64_t eoffset;
302
302
uint32_t flags;
303
+
struct radeon_fence *fence;
303
304
bool valid;
304
305
};
305
306
···
1534
1533
unsigned debugfs_count;
1535
1534
/* virtual memory */
1536
1535
struct radeon_vm_manager vm_manager;
1536
+
struct mutex gpu_clock_mutex;
1537
1537
};
1538
1538
1539
1539
int radeon_device_init(struct radeon_device *rdev,
···
1735
1733
#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1736
1734
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1737
1735
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1738
-
#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1739
-
#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1740
-
#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1741
-
#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1742
-
#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1736
+
#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1737
+
#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1738
+
#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1739
+
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1740
+
#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1743
1741
1744
1742
/* Common functions */
1745
1743
/* AGP */
+4
-6
drivers/gpu/drm/radeon/radeon_asic.h
+4
-6
drivers/gpu/drm/radeon/radeon_asic.h
···
255
255
* rv515
256
256
*/
257
257
struct rv515_mc_save {
258
-
u32 d1vga_control;
259
-
u32 d2vga_control;
260
258
u32 vga_render_control;
261
259
u32 vga_hdp_control;
262
-
u32 d1crtc_control;
263
-
u32 d2crtc_control;
264
260
};
261
+
265
262
int rv515_init(struct radeon_device *rdev);
266
263
void rv515_fini(struct radeon_device *rdev);
267
264
uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
···
368
371
unsigned num_gpu_pages,
369
372
struct radeon_sa_bo *vb);
370
373
int r600_mc_wait_for_idle(struct radeon_device *rdev);
374
+
uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
371
375
372
376
/*
373
377
* rv770,rv730,rv710,rv740
···
387
389
* evergreen
388
390
*/
389
391
struct evergreen_mc_save {
390
-
u32 vga_control[6];
391
392
u32 vga_render_control;
392
393
u32 vga_hdp_control;
393
-
u32 crtc_control[6];
394
394
};
395
+
395
396
void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
396
397
int evergreen_init(struct radeon_device *rdev);
397
398
void evergreen_fini(struct radeon_device *rdev);
···
469
472
void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
470
473
void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
471
474
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
475
+
uint64_t si_get_gpu_clock(struct radeon_device *rdev);
472
476
473
477
#endif
+37
-12
drivers/gpu/drm/radeon/radeon_atombios.c
+37
-12
drivers/gpu/drm/radeon/radeon_atombios.c
···
1263
1263
union igp_info {
1264
1264
struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265
1265
struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266
+
struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1267
+
struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1266
1268
};
1267
1269
1268
1270
bool radeon_atombios_sideport_present(struct radeon_device *rdev)
···
1392
1390
struct radeon_mode_info *mode_info = &rdev->mode_info;
1393
1391
int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1394
1392
u16 data_offset, size;
1395
-
struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1393
+
union igp_info *igp_info;
1396
1394
u8 frev, crev;
1397
1395
u16 percentage = 0, rate = 0;
1398
1396
1399
1397
/* get any igp specific overrides */
1400
1398
if (atom_parse_data_header(mode_info->atom_context, index, &size,
1401
1399
&frev, &crev, &data_offset)) {
1402
-
igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1400
+
igp_info = (union igp_info *)
1403
1401
(mode_info->atom_context->bios + data_offset);
1404
-
switch (id) {
1405
-
case ASIC_INTERNAL_SS_ON_TMDS:
1406
-
percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1407
-
rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1402
+
switch (crev) {
1403
+
case 6:
1404
+
switch (id) {
1405
+
case ASIC_INTERNAL_SS_ON_TMDS:
1406
+
percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1407
+
rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1408
+
break;
1409
+
case ASIC_INTERNAL_SS_ON_HDMI:
1410
+
percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1411
+
rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1412
+
break;
1413
+
case ASIC_INTERNAL_SS_ON_LVDS:
1414
+
percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1415
+
rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1416
+
break;
1417
+
}
1408
1418
break;
1409
-
case ASIC_INTERNAL_SS_ON_HDMI:
1410
-
percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1411
-
rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1419
+
case 7:
1420
+
switch (id) {
1421
+
case ASIC_INTERNAL_SS_ON_TMDS:
1422
+
percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1423
+
rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1424
+
break;
1425
+
case ASIC_INTERNAL_SS_ON_HDMI:
1426
+
percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1427
+
rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1428
+
break;
1429
+
case ASIC_INTERNAL_SS_ON_LVDS:
1430
+
percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1431
+
rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1432
+
break;
1433
+
}
1412
1434
break;
1413
-
case ASIC_INTERNAL_SS_ON_LVDS:
1414
-
percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1415
-
rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1435
+
default:
1436
+
DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1416
1437
break;
1417
1438
}
1418
1439
if (percentage)
+36
-21
drivers/gpu/drm/radeon/radeon_combios.c
+36
-21
drivers/gpu/drm/radeon/radeon_combios.c
···
719
719
return i2c;
720
720
}
721
721
722
+
static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
723
+
{
724
+
struct drm_device *dev = rdev->ddev;
725
+
struct radeon_i2c_bus_rec i2c;
726
+
u16 offset;
727
+
u8 id, blocks, clk, data;
728
+
int i;
729
+
730
+
i2c.valid = false;
731
+
732
+
offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
733
+
if (offset) {
734
+
blocks = RBIOS8(offset + 2);
735
+
for (i = 0; i < blocks; i++) {
736
+
id = RBIOS8(offset + 3 + (i * 5) + 0);
737
+
if (id == 136) {
738
+
clk = RBIOS8(offset + 3 + (i * 5) + 3);
739
+
data = RBIOS8(offset + 3 + (i * 5) + 4);
740
+
/* gpiopad */
741
+
i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
742
+
(1 << clk), (1 << data));
743
+
break;
744
+
}
745
+
}
746
+
}
747
+
return i2c;
748
+
}
749
+
722
750
void radeon_combios_i2c_init(struct radeon_device *rdev)
723
751
{
724
752
struct drm_device *dev = rdev->ddev;
···
783
755
} else if (rdev->family == CHIP_RS300 ||
784
756
rdev->family == CHIP_RS400 ||
785
757
rdev->family == CHIP_RS480) {
786
-
u16 offset;
787
-
u8 id, blocks, clk, data;
788
-
int i;
789
-
790
758
/* 0x68 */
791
759
i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
792
760
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
793
761
794
-
offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
795
-
if (offset) {
796
-
blocks = RBIOS8(offset + 2);
797
-
for (i = 0; i < blocks; i++) {
798
-
id = RBIOS8(offset + 3 + (i * 5) + 0);
799
-
if (id == 136) {
800
-
clk = RBIOS8(offset + 3 + (i * 5) + 3);
801
-
data = RBIOS8(offset + 3 + (i * 5) + 4);
802
-
/* gpiopad */
803
-
i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
804
-
(1 << clk), (1 << data));
805
-
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
806
-
break;
807
-
}
808
-
}
809
-
}
762
+
/* gpiopad */
763
+
i2c = radeon_combios_get_i2c_info_from_table(rdev);
764
+
if (i2c.valid)
765
+
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
810
766
} else if ((rdev->family == CHIP_R200) ||
811
767
(rdev->family >= CHIP_R300)) {
812
768
/* 0x68 */
···
2333
2321
connector = (tmp >> 12) & 0xf;
2334
2322
2335
2323
ddc_type = (tmp >> 8) & 0xf;
2336
-
ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2324
+
if (ddc_type == 5)
2325
+
ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2326
+
else
2327
+
ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2337
2328
2338
2329
switch (connector) {
2339
2330
case CONNECTOR_PROPRIETARY_LEGACY:
+29
-3
drivers/gpu/drm/radeon/radeon_cs.c
+29
-3
drivers/gpu/drm/radeon/radeon_cs.c
···
278
278
return 0;
279
279
}
280
280
281
+
static void radeon_bo_vm_fence_va(struct radeon_cs_parser *parser,
282
+
struct radeon_fence *fence)
283
+
{
284
+
struct radeon_fpriv *fpriv = parser->filp->driver_priv;
285
+
struct radeon_vm *vm = &fpriv->vm;
286
+
struct radeon_bo_list *lobj;
287
+
288
+
if (parser->chunk_ib_idx == -1) {
289
+
return;
290
+
}
291
+
if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) {
292
+
return;
293
+
}
294
+
295
+
list_for_each_entry(lobj, &parser->validated, tv.head) {
296
+
struct radeon_bo_va *bo_va;
297
+
struct radeon_bo *rbo = lobj->bo;
298
+
299
+
bo_va = radeon_bo_va(rbo, vm);
300
+
radeon_fence_unref(&bo_va->fence);
301
+
bo_va->fence = radeon_fence_ref(fence);
302
+
}
303
+
}
304
+
281
305
/**
282
306
* cs_parser_fini() - clean parser states
283
307
* @parser: parser structure holding parsing context.
···
314
290
{
315
291
unsigned i;
316
292
317
-
if (!error)
293
+
if (!error) {
294
+
/* fence all bo va before ttm_eu_fence_buffer_objects so bo are still reserved */
295
+
radeon_bo_vm_fence_va(parser, parser->ib.fence);
318
296
ttm_eu_fence_buffer_objects(&parser->validated,
319
297
parser->ib.fence);
320
-
else
298
+
} else {
321
299
ttm_eu_backoff_reservation(&parser->validated);
300
+
}
322
301
323
302
if (parser->relocs != NULL) {
324
303
for (i = 0; i < parser->nrelocs; i++) {
···
415
388
416
389
if (parser->chunk_ib_idx == -1)
417
390
return 0;
418
-
419
391
if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
420
392
return 0;
421
393
+4
-2
drivers/gpu/drm/radeon/radeon_cursor.c
+4
-2
drivers/gpu/drm/radeon/radeon_cursor.c
···
67
67
68
68
if (ASIC_IS_DCE4(rdev)) {
69
69
WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
70
-
WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
70
+
WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
71
+
EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
71
72
} else if (ASIC_IS_AVIVO(rdev)) {
72
73
WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
73
74
WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
···
95
94
if (ASIC_IS_DCE4(rdev)) {
96
95
WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
97
96
WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
98
-
EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
97
+
EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
98
+
EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
99
99
} else if (ASIC_IS_AVIVO(rdev)) {
100
100
WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
101
101
WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
+1
drivers/gpu/drm/radeon/radeon_device.c
+1
drivers/gpu/drm/radeon/radeon_device.c
···
1009
1009
atomic_set(&rdev->ih.lock, 0);
1010
1010
mutex_init(&rdev->gem.mutex);
1011
1011
mutex_init(&rdev->pm.mutex);
1012
+
mutex_init(&rdev->gpu_clock_mutex);
1012
1013
init_rwsem(&rdev->pm.mclk_lock);
1013
1014
init_rwsem(&rdev->exclusive_lock);
1014
1015
init_waitqueue_head(&rdev->irq.vblank_queue);
+4
-1
drivers/gpu/drm/radeon/radeon_drv.c
+4
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
59
59
* 2.15.0 - add max_pipes query
60
60
* 2.16.0 - fix evergreen 2D tiled surface calculation
61
61
* 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
62
+
* 2.18.0 - r600-eg: allow "invalid" DB formats
63
+
* 2.19.0 - r600-eg: MSAA textures
64
+
* 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
62
65
*/
63
66
#define KMS_DRIVER_MAJOR 2
64
-
#define KMS_DRIVER_MINOR 17
67
+
#define KMS_DRIVER_MINOR 20
65
68
#define KMS_DRIVER_PATCHLEVEL 0
66
69
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
67
70
int radeon_driver_unload_kms(struct drm_device *dev);
+23
-3
drivers/gpu/drm/radeon/radeon_gart.c
+23
-3
drivers/gpu/drm/radeon/radeon_gart.c
···
814
814
return -EINVAL;
815
815
}
816
816
817
-
if (bo_va->valid)
817
+
if (bo_va->valid && mem)
818
818
return 0;
819
819
820
820
ngpu_pages = radeon_bo_ngpu_pages(bo);
···
859
859
struct radeon_bo *bo)
860
860
{
861
861
struct radeon_bo_va *bo_va;
862
+
int r;
862
863
863
864
bo_va = radeon_bo_va(bo, vm);
864
865
if (bo_va == NULL)
865
866
return 0;
867
+
868
+
/* wait for va use to end */
869
+
while (bo_va->fence) {
870
+
r = radeon_fence_wait(bo_va->fence, false);
871
+
if (r) {
872
+
DRM_ERROR("error while waiting for fence: %d\n", r);
873
+
}
874
+
if (r == -EDEADLK) {
875
+
r = radeon_gpu_reset(rdev);
876
+
if (!r)
877
+
continue;
878
+
}
879
+
break;
880
+
}
881
+
radeon_fence_unref(&bo_va->fence);
866
882
867
883
mutex_lock(&rdev->vm_manager.lock);
868
884
mutex_lock(&vm->mutex);
···
950
934
}
951
935
952
936
/**
953
-
* radeon_vm_init - tear down a vm instance
937
+
* radeon_vm_fini - tear down a vm instance
954
938
*
955
939
* @rdev: radeon_device pointer
956
940
* @vm: requested vm
···
968
952
radeon_vm_unbind_locked(rdev, vm);
969
953
mutex_unlock(&rdev->vm_manager.lock);
970
954
971
-
/* remove all bo */
955
+
/* remove all bo at this point non are busy any more because unbind
956
+
* waited for the last vm fence to signal
957
+
*/
972
958
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
973
959
if (!r) {
974
960
bo_va = radeon_bo_va(rdev->ring_tmp_bo.bo, vm);
975
961
list_del_init(&bo_va->bo_list);
976
962
list_del_init(&bo_va->vm_list);
963
+
radeon_fence_unref(&bo_va->fence);
977
964
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
978
965
kfree(bo_va);
979
966
}
···
988
969
r = radeon_bo_reserve(bo_va->bo, false);
989
970
if (!r) {
990
971
list_del_init(&bo_va->bo_list);
972
+
radeon_fence_unref(&bo_va->fence);
991
973
radeon_bo_unreserve(bo_va->bo);
992
974
kfree(bo_va);
993
975
}
+2
-11
drivers/gpu/drm/radeon/radeon_gem.c
+2
-11
drivers/gpu/drm/radeon/radeon_gem.c
···
134
134
struct radeon_device *rdev = rbo->rdev;
135
135
struct radeon_fpriv *fpriv = file_priv->driver_priv;
136
136
struct radeon_vm *vm = &fpriv->vm;
137
-
struct radeon_bo_va *bo_va, *tmp;
138
137
139
138
if (rdev->family < CHIP_CAYMAN) {
140
139
return;
141
140
}
142
141
143
142
if (radeon_bo_reserve(rbo, false)) {
143
+
dev_err(rdev->dev, "leaking bo va because we fail to reserve bo\n");
144
144
return;
145
145
}
146
-
list_for_each_entry_safe(bo_va, tmp, &rbo->va, bo_list) {
147
-
if (bo_va->vm == vm) {
148
-
/* remove from this vm address space */
149
-
mutex_lock(&vm->mutex);
150
-
list_del(&bo_va->vm_list);
151
-
mutex_unlock(&vm->mutex);
152
-
list_del(&bo_va->bo_list);
153
-
kfree(bo_va);
154
-
}
155
-
}
146
+
radeon_vm_bo_rmv(rdev, vm, rbo);
156
147
radeon_bo_unreserve(rbo);
157
148
}
158
149
+29
-6
drivers/gpu/drm/radeon/radeon_kms.c
+29
-6
drivers/gpu/drm/radeon/radeon_kms.c
···
29
29
#include "drm_sarea.h"
30
30
#include "radeon.h"
31
31
#include "radeon_drm.h"
32
+
#include "radeon_asic.h"
32
33
33
34
#include <linux/vga_switcheroo.h>
34
35
#include <linux/slab.h>
···
168
167
int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
169
168
{
170
169
struct radeon_device *rdev = dev->dev_private;
171
-
struct drm_radeon_info *info;
170
+
struct drm_radeon_info *info = data;
172
171
struct radeon_mode_info *minfo = &rdev->mode_info;
173
-
uint32_t *value_ptr;
174
-
uint32_t value;
172
+
uint32_t value, *value_ptr;
173
+
uint64_t value64, *value_ptr64;
175
174
struct drm_crtc *crtc;
176
175
int i, found;
177
176
178
-
info = data;
177
+
/* TIMESTAMP is a 64-bit value, needs special handling. */
178
+
if (info->request == RADEON_INFO_TIMESTAMP) {
179
+
if (rdev->family >= CHIP_R600) {
180
+
value_ptr64 = (uint64_t*)((unsigned long)info->value);
181
+
if (rdev->family >= CHIP_TAHITI) {
182
+
value64 = si_get_gpu_clock(rdev);
183
+
} else {
184
+
value64 = r600_get_gpu_clock(rdev);
185
+
}
186
+
187
+
if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
188
+
DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
189
+
return -EFAULT;
190
+
}
191
+
return 0;
192
+
} else {
193
+
DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
194
+
return -EINVAL;
195
+
}
196
+
}
197
+
179
198
value_ptr = (uint32_t *)((unsigned long)info->value);
180
-
if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
199
+
if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) {
200
+
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
181
201
return -EFAULT;
202
+
}
182
203
183
204
switch (info->request) {
184
205
case RADEON_INFO_DEVICE_ID:
···
360
337
return -EINVAL;
361
338
}
362
339
if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
363
-
DRM_ERROR("copy_to_user\n");
340
+
DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
364
341
return -EFAULT;
365
342
}
366
343
return 0;
+4
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+4
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
···
1025
1025
1026
1026
static void radeon_crtc_prepare(struct drm_crtc *crtc)
1027
1027
{
1028
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1028
1029
struct drm_device *dev = crtc->dev;
1029
1030
struct drm_crtc *crtci;
1030
1031
1032
+
radeon_crtc->in_mode_set = true;
1031
1033
/*
1032
1034
* The hardware wedges sometimes if you reconfigure one CRTC
1033
1035
* whilst another is running (see fdo bug #24611).
···
1040
1038
1041
1039
static void radeon_crtc_commit(struct drm_crtc *crtc)
1042
1040
{
1041
+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1043
1042
struct drm_device *dev = crtc->dev;
1044
1043
struct drm_crtc *crtci;
1045
1044
···
1051
1048
if (crtci->enabled)
1052
1049
radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1053
1050
}
1051
+
radeon_crtc->in_mode_set = false;
1054
1052
}
1055
1053
1056
1054
static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
+1
drivers/gpu/drm/radeon/radeon_mode.h
+1
drivers/gpu/drm/radeon/radeon_mode.h
+1
-5
drivers/gpu/drm/radeon/radeon_object.c
+1
-5
drivers/gpu/drm/radeon/radeon_object.c
···
52
52
53
53
list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54
54
/* remove from all vm address space */
55
-
mutex_lock(&bo_va->vm->mutex);
56
-
list_del(&bo_va->vm_list);
57
-
mutex_unlock(&bo_va->vm->mutex);
58
-
list_del(&bo_va->bo_list);
59
-
kfree(bo_va);
55
+
radeon_vm_bo_rmv(bo->rdev, bo_va->vm, bo);
60
56
}
61
57
}
62
58
-13
drivers/gpu/drm/radeon/rv515.c
-13
drivers/gpu/drm/radeon/rv515.c
···
281
281
282
282
void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
283
283
{
284
-
save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
285
-
save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
286
284
save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
287
285
save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
288
-
save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
289
-
save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
290
286
291
287
/* Stop all video */
292
288
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
···
307
311
/* Unlock host access */
308
312
WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
309
313
mdelay(1);
310
-
/* Restore video state */
311
-
WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
312
-
WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
313
-
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
314
-
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
315
-
WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
316
-
WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
317
-
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
318
-
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
319
314
WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
320
315
}
321
316
+31
-4
drivers/gpu/drm/radeon/si.c
+31
-4
drivers/gpu/drm/radeon/si.c
···
1639
1639
/* XXX what about 12? */
1640
1640
rdev->config.si.tile_config |= (3 << 0);
1641
1641
break;
1642
-
}
1643
-
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1644
-
rdev->config.si.tile_config |= 1 << 4;
1645
-
else
1642
+
}
1643
+
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1644
+
case 0: /* four banks */
1646
1645
rdev->config.si.tile_config |= 0 << 4;
1646
+
break;
1647
+
case 1: /* eight banks */
1648
+
rdev->config.si.tile_config |= 1 << 4;
1649
+
break;
1650
+
case 2: /* sixteen banks */
1651
+
default:
1652
+
rdev->config.si.tile_config |= 2 << 4;
1653
+
break;
1654
+
}
1647
1655
rdev->config.si.tile_config |=
1648
1656
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1649
1657
rdev->config.si.tile_config |=
···
3968
3960
rdev->bios = NULL;
3969
3961
}
3970
3962
3963
+
/**
3964
+
* si_get_gpu_clock - return GPU clock counter snapshot
3965
+
*
3966
+
* @rdev: radeon_device pointer
3967
+
*
3968
+
* Fetches a GPU clock counter snapshot (SI).
3969
+
* Returns the 64 bit clock counter snapshot.
3970
+
*/
3971
+
uint64_t si_get_gpu_clock(struct radeon_device *rdev)
3972
+
{
3973
+
uint64_t clock;
3974
+
3975
+
mutex_lock(&rdev->gpu_clock_mutex);
3976
+
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3977
+
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3978
+
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3979
+
mutex_unlock(&rdev->gpu_clock_mutex);
3980
+
return clock;
3981
+
}
+3
drivers/gpu/drm/radeon/sid.h
+3
drivers/gpu/drm/radeon/sid.h
···
698
698
#define RLC_UCODE_ADDR 0xC32C
699
699
#define RLC_UCODE_DATA 0xC330
700
700
701
+
#define RLC_GPU_CLOCK_COUNT_LSB 0xC338
702
+
#define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
703
+
#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
701
704
#define RLC_MC_CNTL 0xC344
702
705
#define RLC_UCODE_CNTL 0xC348
703
706
+1
-1
drivers/gpu/drm/udl/udl_gem.c
+1
-1
drivers/gpu/drm/udl/udl_gem.c
+3
include/drm/drm_pciids.h
+3
include/drm/drm_pciids.h
···
213
213
{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
214
214
{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
215
215
{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
216
+
{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
216
217
{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
217
218
{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
218
219
{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
220
+
{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
221
+
{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
219
222
{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
220
223
{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
221
224
{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+2
include/drm/radeon_drm.h
+2
include/drm/radeon_drm.h
···
964
964
#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
965
965
/* max pipes - needed for compute shaders */
966
966
#define RADEON_INFO_MAX_PIPES 0x10
967
+
/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
968
+
#define RADEON_INFO_TIMESTAMP 0x11
967
969
968
970
struct drm_radeon_info {
969
971
uint32_t request;