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clocksource/drivers/timer-rtl-otto: Simplify documentation

While the main SoC PLL is responsible for the lexra bus frequency
it has no implications on the the timer divisior. Update the
comments accordingly.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20250804080328.2609287-5-markus.stockhausen@gmx.de

authored by

Markus Stockhausen and committed by
Daniel Lezcano
931bd927 c445bffb

+4 -6
+4 -6
drivers/clocksource/timer-rtl-otto.c
··· 41 41 #define RTTM_MAX_DIVISOR GENMASK(15, 0) 42 42 43 43 /* 44 - * Timers are derived from the LXB clock frequency. Usually this is a fixed 45 - * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. 46 - * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its 47 - * base. The only meaningful frequencies we can achieve from that are 175.000 48 - * MHz and 153.125 MHz. The greatest common divisor of all explained possible 49 - * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. 44 + * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz 45 + * on RTL930x and 200 MHz on the other platforms. With 3.125 MHz choose a common 46 + * divisor to have enough range and detail. This provides comparability between 47 + * the different platforms. 50 48 */ 51 49 #define RTTM_TICKS_PER_SEC 3125000 52 50