Merge tag 'drm-fixes-2022-05-21' of git://anongit.freedesktop.org/drm/drm

+8

drivers/dma-buf/dma-buf.c

··· 407 407 408 408 static struct file *dma_buf_getfile(struct dma_buf *dmabuf, int flags) 409 409 { 410 + static atomic64_t dmabuf_inode = ATOMIC64_INIT(0); 410 411 struct file *file; 411 412 struct inode *inode = alloc_anon_inode(dma_buf_mnt->mnt_sb); 412 413 ··· 417 416 inode->i_size = dmabuf->size; 418 417 inode_set_bytes(inode, dmabuf->size); 419 418 419 + /* 420 + * The ->i_ino acquired from get_next_ino() is not unique thus 421 + * not suitable for using it as dentry name by dmabuf stats. 422 + * Override ->i_ino with the unique and dmabuffs specific 423 + * value. 424 + */ 425 + inode->i_ino = atomic64_add_return(1, &dmabuf_inode); 420 426 file = alloc_file_pseudo(inode, dma_buf_mnt, "dmabuf", 421 427 flags, &dma_buf_fops); 422 428 if (IS_ERR(file))

+2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1342 1342 1343 1343 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1344 1344 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1345 + bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1345 1346 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1346 1347 #else 1347 1348 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1349 + static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1348 1350 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1349 1351 #endif 1350 1352

+14

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

··· 1046 1046 } 1047 1047 1048 1048 /** 1049 + * amdgpu_acpi_should_gpu_reset 1050 + * 1051 + * @adev: amdgpu_device_pointer 1052 + * 1053 + * returns true if should reset GPU, false if not 1054 + */ 1055 + bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) 1056 + { 1057 + if (adev->flags & AMD_IS_APU) 1058 + return false; 1059 + return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; 1060 + } 1061 + 1062 + /** 1049 1063 * amdgpu_acpi_is_s0ix_active 1050 1064 * 1051 1065 * @adev: amdgpu_device_pointer

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 2336 2336 struct drm_device *drm_dev = dev_get_drvdata(dev); 2337 2337 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2338 2338 2339 - if (!adev->in_s0ix) 2339 + if (amdgpu_acpi_should_gpu_reset(adev)) 2340 2340 return amdgpu_asic_reset(adev); 2341 2341 2342 2342 return 0;

+1

drivers/gpu/drm/dp/drm_dp_mst_topology.c

··· 4852 4852 4853 4853 mst_edid = drm_dp_mst_get_edid(port->connector, mgr, port); 4854 4854 drm_edid_get_monitor_name(mst_edid, name, namelen); 4855 + kfree(mst_edid); 4855 4856 } 4856 4857 4857 4858 /**

+44

drivers/gpu/drm/i915/display/intel_dmc.c

··· 367 367 } 368 368 } 369 369 370 + static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 371 + const u32 *mmioaddr, u32 mmio_count, 372 + int header_ver, u8 dmc_id) 373 + { 374 + struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 375 + u32 start_range, end_range; 376 + int i; 377 + 378 + if (dmc_id >= DMC_FW_MAX) { 379 + drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id); 380 + return false; 381 + } 382 + 383 + if (header_ver == 1) { 384 + start_range = DMC_MMIO_START_RANGE; 385 + end_range = DMC_MMIO_END_RANGE; 386 + } else if (dmc_id == DMC_FW_MAIN) { 387 + start_range = TGL_MAIN_MMIO_START; 388 + end_range = TGL_MAIN_MMIO_END; 389 + } else if (DISPLAY_VER(i915) >= 13) { 390 + start_range = ADLP_PIPE_MMIO_START; 391 + end_range = ADLP_PIPE_MMIO_END; 392 + } else if (DISPLAY_VER(i915) >= 12) { 393 + start_range = TGL_PIPE_MMIO_START(dmc_id); 394 + end_range = TGL_PIPE_MMIO_END(dmc_id); 395 + } else { 396 + drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 397 + return false; 398 + } 399 + 400 + for (i = 0; i < mmio_count; i++) { 401 + if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 402 + return false; 403 + } 404 + 405 + return true; 406 + } 407 + 370 408 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 371 409 const struct intel_dmc_header_base *dmc_header, 372 410 size_t rem_size, u8 dmc_id) ··· 471 433 /* Cache the dmc header info. */ 472 434 if (mmio_count > mmio_count_max) { 473 435 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 436 + return 0; 437 + } 438 + 439 + if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 440 + dmc_header->header_ver, dmc_id)) { 441 + drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 474 442 return 0; 475 443 } 476 444

+2 -4

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

··· 1252 1252 * Only attempt to pin the batch buffer to ggtt if the current batch 1253 1253 * is not inside ggtt, or the batch buffer is not misplaced. 1254 1254 */ 1255 - if (!i915_is_ggtt(batch->vm)) { 1255 + if (!i915_is_ggtt(batch->vm) || 1256 + !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) { 1256 1257 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0, 1257 1258 PIN_MAPPABLE | 1258 1259 PIN_NONBLOCK /* NOWARN */ | 1259 1260 PIN_NOEVICT); 1260 - } else if (i915_vma_is_map_and_fenceable(batch)) { 1261 - __i915_vma_pin(batch); 1262 - vma = batch; 1263 1261 } 1264 1262 1265 1263 if (vma == ERR_PTR(-EDEADLK))

+1 -1

drivers/gpu/drm/i915/gt/intel_reset.c

··· 806 806 __intel_engine_reset(engine, stalled_mask & engine->mask); 807 807 local_bh_enable(); 808 808 809 - intel_uc_reset(&gt->uc, true); 809 + intel_uc_reset(&gt->uc, ALL_ENGINES); 810 810 811 811 intel_ggtt_restore_fences(gt->ggtt); 812 812

+1 -1

drivers/gpu/drm/i915/gt/uc/intel_guc.h

··· 438 438 void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq); 439 439 440 440 void intel_guc_submission_reset_prepare(struct intel_guc *guc); 441 - void intel_guc_submission_reset(struct intel_guc *guc, bool stalled); 441 + void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled); 442 442 void intel_guc_submission_reset_finish(struct intel_guc *guc); 443 443 void intel_guc_submission_cancel_requests(struct intel_guc *guc); 444 444

+8 -8

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

··· 1590 1590 spin_unlock_irqrestore(&sched_engine->lock, flags); 1591 1591 } 1592 1592 1593 - static void __guc_reset_context(struct intel_context *ce, bool stalled) 1593 + static void __guc_reset_context(struct intel_context *ce, intel_engine_mask_t stalled) 1594 1594 { 1595 - bool local_stalled; 1595 + bool guilty; 1596 1596 struct i915_request *rq; 1597 1597 unsigned long flags; 1598 1598 u32 head; ··· 1620 1620 if (!intel_context_is_pinned(ce)) 1621 1621 goto next_context; 1622 1622 1623 - local_stalled = false; 1623 + guilty = false; 1624 1624 rq = intel_context_find_active_request(ce); 1625 1625 if (!rq) { 1626 1626 head = ce->ring->tail; ··· 1628 1628 } 1629 1629 1630 1630 if (i915_request_started(rq)) 1631 - local_stalled = true; 1631 + guilty = stalled & ce->engine->mask; 1632 1632 1633 1633 GEM_BUG_ON(i915_active_is_idle(&ce->active)); 1634 1634 head = intel_ring_wrap(ce->ring, rq->head); 1635 1635 1636 - __i915_request_reset(rq, local_stalled && stalled); 1636 + __i915_request_reset(rq, guilty); 1637 1637 out_replay: 1638 - guc_reset_state(ce, head, local_stalled && stalled); 1638 + guc_reset_state(ce, head, guilty); 1639 1639 next_context: 1640 1640 if (i != number_children) 1641 1641 ce = list_next_entry(ce, parallel.child_link); ··· 1645 1645 intel_context_put(parent); 1646 1646 } 1647 1647 1648 - void intel_guc_submission_reset(struct intel_guc *guc, bool stalled) 1648 + void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled) 1649 1649 { 1650 1650 struct intel_context *ce; 1651 1651 unsigned long index; ··· 4013 4013 { 4014 4014 struct i915_sched_engine *sched_engine = ce->engine->sched_engine; 4015 4015 4016 - __guc_reset_context(ce, true); 4016 + __guc_reset_context(ce, ce->engine->mask); 4017 4017 tasklet_hi_schedule(&sched_engine->tasklet); 4018 4018 } 4019 4019

+1 -1

drivers/gpu/drm/i915/gt/uc/intel_uc.c

··· 593 593 __uc_sanitize(uc); 594 594 } 595 595 596 - void intel_uc_reset(struct intel_uc *uc, bool stalled) 596 + void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled) 597 597 { 598 598 struct intel_guc *guc = &uc->guc; 599 599

+1 -1

drivers/gpu/drm/i915/gt/uc/intel_uc.h

··· 42 42 void intel_uc_driver_remove(struct intel_uc *uc); 43 43 void intel_uc_init_mmio(struct intel_uc *uc); 44 44 void intel_uc_reset_prepare(struct intel_uc *uc); 45 - void intel_uc_reset(struct intel_uc *uc, bool stalled); 45 + void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled); 46 46 void intel_uc_reset_finish(struct intel_uc *uc); 47 47 void intel_uc_cancel_requests(struct intel_uc *uc); 48 48 void intel_uc_suspend(struct intel_uc *uc);

+16

drivers/gpu/drm/i915/i915_reg.h

··· 5501 5501 /* MMIO address range for DMC program (0x80000 - 0x82FFF) */ 5502 5502 #define DMC_MMIO_START_RANGE 0x80000 5503 5503 #define DMC_MMIO_END_RANGE 0x8FFFF 5504 + #define DMC_V1_MMIO_START_RANGE 0x80000 5505 + #define TGL_MAIN_MMIO_START 0x8F000 5506 + #define TGL_MAIN_MMIO_END 0x8FFFF 5507 + #define _TGL_PIPEA_MMIO_START 0x92000 5508 + #define _TGL_PIPEA_MMIO_END 0x93FFF 5509 + #define _TGL_PIPEB_MMIO_START 0x96000 5510 + #define _TGL_PIPEB_MMIO_END 0x97FFF 5511 + #define ADLP_PIPE_MMIO_START 0x5F000 5512 + #define ADLP_PIPE_MMIO_END 0x5FFFF 5513 + 5514 + #define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\ 5515 + _TGL_PIPEB_MMIO_START) 5516 + 5517 + #define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\ 5518 + _TGL_PIPEB_MMIO_END) 5519 + 5504 5520 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) 5505 5521 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) 5506 5522 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)

+2 -2

include/uapi/linux/dma-buf.h

··· 92 92 * between them in actual uapi, they're just different numbers. 93 93 */ 94 94 #define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *) 95 - #define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, u32) 96 - #define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, u64) 95 + #define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, __u32) 96 + #define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, __u64) 97 97 98 98 #endif

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