Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm: perf: Remove inlines from arm_pmuv3.c
These are all static and in one compilation unit so the inline has no
effect on the binary. Except if FTRACE is enabled, then 3 functions
which were already not inlined now get the nops added which allows them
to be traced.
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20231211161331.1277825-2-james.clark@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
authored by
James Clark
and committed by
Will Deacon
9343c790
5ca8ab55
+23
-23
+23
-23
drivers/perf/arm_pmuv3.c
+23
-23
drivers/perf/arm_pmuv3.c
···
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static int sysctl_perf_user_access __read_mostly;
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-
static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
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+
static bool armv8pmu_event_is_64bit(struct perf_event *event)
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{
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return event->attr.config1 & 0x1;
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}
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-
static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
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+
static bool armv8pmu_event_want_user_access(struct perf_event *event)
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{
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return event->attr.config1 & 0x2;
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}
···
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return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver));
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}
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-
static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
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+
static bool armv8pmu_event_has_user_read(struct perf_event *event)
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{
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return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
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}
···
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* except when we have allocated the 64bit cycle counter (for CPU
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* cycles event) or when user space counter access is enabled.
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*/
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-
static inline bool armv8pmu_event_is_chained(struct perf_event *event)
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+
static bool armv8pmu_event_is_chained(struct perf_event *event)
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{
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int idx = event->hw.idx;
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
···
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#define ARMV8_IDX_TO_COUNTER(x) \
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(((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
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-
static inline u64 armv8pmu_pmcr_read(void)
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+
static u64 armv8pmu_pmcr_read(void)
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{
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return read_pmcr();
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}
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-
static inline void armv8pmu_pmcr_write(u64 val)
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+
static void armv8pmu_pmcr_write(u64 val)
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{
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val &= ARMV8_PMU_PMCR_MASK;
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isb();
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write_pmcr(val);
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}
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-
static inline int armv8pmu_has_overflowed(u32 pmovsr)
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+
static int armv8pmu_has_overflowed(u32 pmovsr)
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{
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return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
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}
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-
static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
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+
static int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
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{
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return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
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}
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-
static inline u64 armv8pmu_read_evcntr(int idx)
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+
static u64 armv8pmu_read_evcntr(int idx)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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return read_pmevcntrn(counter);
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}
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-
static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
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+
static u64 armv8pmu_read_hw_counter(struct perf_event *event)
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{
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int idx = event->hw.idx;
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u64 val = armv8pmu_read_evcntr(idx);
···
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return armv8pmu_unbias_long_counter(event, value);
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}
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-
static inline void armv8pmu_write_evcntr(int idx, u64 value)
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+
static void armv8pmu_write_evcntr(int idx, u64 value)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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write_pmevcntrn(counter, value);
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}
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-
static inline void armv8pmu_write_hw_counter(struct perf_event *event,
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+
static void armv8pmu_write_hw_counter(struct perf_event *event,
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u64 value)
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{
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int idx = event->hw.idx;
···
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armv8pmu_write_hw_counter(event, value);
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}
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-
static inline void armv8pmu_write_evtype(int idx, u32 val)
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+
static void armv8pmu_write_evtype(int idx, u32 val)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(idx);
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···
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write_pmevtypern(counter, val);
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}
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-
static inline void armv8pmu_write_event_type(struct perf_event *event)
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+
static void armv8pmu_write_event_type(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
···
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return mask;
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}
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-
static inline void armv8pmu_enable_counter(u32 mask)
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+
static void armv8pmu_enable_counter(u32 mask)
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{
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/*
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* Make sure event configuration register writes are visible before we
···
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write_pmcntenset(mask);
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}
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-
static inline void armv8pmu_enable_event_counter(struct perf_event *event)
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+
static void armv8pmu_enable_event_counter(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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u32 mask = armv8pmu_event_cnten_mask(event);
···
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armv8pmu_enable_counter(mask);
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}
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623
-
static inline void armv8pmu_disable_counter(u32 mask)
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+
static void armv8pmu_disable_counter(u32 mask)
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{
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write_pmcntenclr(mask);
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/*
···
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isb();
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}
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-
static inline void armv8pmu_disable_event_counter(struct perf_event *event)
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+
static void armv8pmu_disable_event_counter(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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u32 mask = armv8pmu_event_cnten_mask(event);
···
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armv8pmu_disable_counter(mask);
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}
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-
static inline void armv8pmu_enable_intens(u32 mask)
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+
static void armv8pmu_enable_intens(u32 mask)
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{
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write_pmintenset(mask);
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}
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-
static inline void armv8pmu_enable_event_irq(struct perf_event *event)
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+
static void armv8pmu_enable_event_irq(struct perf_event *event)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
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armv8pmu_enable_intens(BIT(counter));
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}
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-
static inline void armv8pmu_disable_intens(u32 mask)
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+
static void armv8pmu_disable_intens(u32 mask)
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{
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write_pmintenclr(mask);
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isb();
···
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isb();
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}
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-
static inline void armv8pmu_disable_event_irq(struct perf_event *event)
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+
static void armv8pmu_disable_event_irq(struct perf_event *event)
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{
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u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
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armv8pmu_disable_intens(BIT(counter));
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}
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-
static inline u32 armv8pmu_getreset_flags(void)
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+
static u32 armv8pmu_getreset_flags(void)
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{
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u32 value;
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