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clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP

On the RZ/T2H SoC, a specific sequence is required when releasing a
module from the module stop state (i.e. when clearing the corresponding
bit in the MSTPCRm register to '0'). After writing to the MSTPCRm
register, a read-back of the same register must be performed, followed
by at least seven dummy reads of any register within the IP block that
is being released.

To avoid mapping device registers for this purpose, a short delay is
introduced after the read-back to ensure proper hardware stabilization
before the module becomes accessible.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251014105348.93705-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven 934dcccf 3b37979d

+13 -2
+13 -2
drivers/clk/renesas/renesas-cpg-mssr.c
··· 308 308 309 309 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); 310 310 311 - if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A || 312 - priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) 311 + if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 313 312 return 0; 313 + 314 + if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) { 315 + /* 316 + * For the RZ/T2H case, it is necessary to perform a read-back after 317 + * accessing the MSTPCRm register and to dummy-read any register of 318 + * the IP at least seven times. Instead of memory-mapping the IP 319 + * register, we simply add a delay after the read operation. 320 + */ 321 + cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]); 322 + udelay(10); 323 + return 0; 324 + } 314 325 315 326 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], 316 327 value, !(value & bitmask), 0, 10);