Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Much smaller batch of fixes this week.
Biggest one is a revert of an OMAP display change that removed some
non-DT pinmux code that was still needed for 3.13 to get DSI displays
to work.
There's also a fix that resolves some misdescribed GPIO controller
resources on shmobile. The rest are mostly smaller fixes, a couple of
MAINTAINERS updates, etc"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
Revert "ARM: OMAP2+: Remove legacy mux code for display.c"
MAINTAINERS: Add keystone clock drivers
MAINTAINERS: Add keystone git tree information
ARM: s3c64xx: dt: Fix boot failure due to double clock initialization
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
+61
-26
+2
MAINTAINERS
+2
MAINTAINERS
···
1008
1008
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1009
1009
S: Maintained
1010
1010
F: arch/arm/mach-keystone/
1011
+
F: drivers/clk/keystone/
1012
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
1011
1013
1012
1014
ARM/LOGICPD PXA270 MACHINE SUPPORT
1013
1015
M: Lennert Buytenhek <kernel@wantstofly.org>
+12
-12
arch/arm/boot/dts/r8a7790.dtsi
+12
-12
arch/arm/boot/dts/r8a7790.dtsi
···
87
87
interrupts = <1 9 0xf04>;
88
88
};
89
89
90
-
gpio0: gpio@ffc40000 {
90
+
gpio0: gpio@e6050000 {
91
91
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
92
-
reg = <0 0xffc40000 0 0x2c>;
92
+
reg = <0 0xe6050000 0 0x50>;
93
93
interrupt-parent = <&gic>;
94
94
interrupts = <0 4 0x4>;
95
95
#gpio-cells = <2>;
···
99
99
interrupt-controller;
100
100
};
101
101
102
-
gpio1: gpio@ffc41000 {
102
+
gpio1: gpio@e6051000 {
103
103
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
104
-
reg = <0 0xffc41000 0 0x2c>;
104
+
reg = <0 0xe6051000 0 0x50>;
105
105
interrupt-parent = <&gic>;
106
106
interrupts = <0 5 0x4>;
107
107
#gpio-cells = <2>;
···
111
111
interrupt-controller;
112
112
};
113
113
114
-
gpio2: gpio@ffc42000 {
114
+
gpio2: gpio@e6052000 {
115
115
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
116
-
reg = <0 0xffc42000 0 0x2c>;
116
+
reg = <0 0xe6052000 0 0x50>;
117
117
interrupt-parent = <&gic>;
118
118
interrupts = <0 6 0x4>;
119
119
#gpio-cells = <2>;
···
123
123
interrupt-controller;
124
124
};
125
125
126
-
gpio3: gpio@ffc43000 {
126
+
gpio3: gpio@e6053000 {
127
127
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
128
-
reg = <0 0xffc43000 0 0x2c>;
128
+
reg = <0 0xe6053000 0 0x50>;
129
129
interrupt-parent = <&gic>;
130
130
interrupts = <0 7 0x4>;
131
131
#gpio-cells = <2>;
···
135
135
interrupt-controller;
136
136
};
137
137
138
-
gpio4: gpio@ffc44000 {
138
+
gpio4: gpio@e6054000 {
139
139
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
140
-
reg = <0 0xffc44000 0 0x2c>;
140
+
reg = <0 0xe6054000 0 0x50>;
141
141
interrupt-parent = <&gic>;
142
142
interrupts = <0 8 0x4>;
143
143
#gpio-cells = <2>;
···
147
147
interrupt-controller;
148
148
};
149
149
150
-
gpio5: gpio@ffc45000 {
150
+
gpio5: gpio@e6055000 {
151
151
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
152
-
reg = <0 0xffc45000 0 0x2c>;
152
+
reg = <0 0xe6055000 0 0x50>;
153
153
interrupt-parent = <&gic>;
154
154
interrupts = <0 9 0x4>;
155
155
#gpio-cells = <2>;
+38
arch/arm/mach-omap2/display.c
+38
arch/arm/mach-omap2/display.c
···
101
101
{ "dss_hdmi", "omapdss_hdmi", -1 },
102
102
};
103
103
104
+
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
105
+
{
106
+
u32 enable_mask, enable_shift;
107
+
u32 pipd_mask, pipd_shift;
108
+
u32 reg;
109
+
110
+
if (dsi_id == 0) {
111
+
enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
112
+
enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
113
+
pipd_mask = OMAP4_DSI1_PIPD_MASK;
114
+
pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
115
+
} else if (dsi_id == 1) {
116
+
enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
117
+
enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
118
+
pipd_mask = OMAP4_DSI2_PIPD_MASK;
119
+
pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
120
+
} else {
121
+
return -ENODEV;
122
+
}
123
+
124
+
reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
125
+
126
+
reg &= ~enable_mask;
127
+
reg &= ~pipd_mask;
128
+
129
+
reg |= (lanes << enable_shift) & enable_mask;
130
+
reg |= (lanes << pipd_shift) & pipd_mask;
131
+
132
+
omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
133
+
134
+
return 0;
135
+
}
136
+
104
137
static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
105
138
{
139
+
if (cpu_is_omap44xx())
140
+
return omap4_dsi_mux_pads(dsi_id, lane_mask);
141
+
106
142
return 0;
107
143
}
108
144
109
145
static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
110
146
{
147
+
if (cpu_is_omap44xx())
148
+
omap4_dsi_mux_pads(dsi_id, 0);
111
149
}
112
150
113
151
static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
+1
-10
arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
+1
-10
arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
···
8
8
* published by the Free Software Foundation.
9
9
*/
10
10
11
-
#include <linux/clk-provider.h>
12
-
#include <linux/irqchip.h>
13
11
#include <linux/of_platform.h>
14
12
15
13
#include <asm/mach/arch.h>
···
46
48
panic("SoC is not S3C64xx!");
47
49
}
48
50
49
-
static void __init s3c64xx_dt_init_irq(void)
50
-
{
51
-
of_clk_init(NULL);
52
-
samsung_wdt_reset_of_init();
53
-
irqchip_init();
54
-
};
55
-
56
51
static void __init s3c64xx_dt_init_machine(void)
57
52
{
53
+
samsung_wdt_reset_of_init();
58
54
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
59
55
}
60
56
···
71
79
/* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
72
80
.dt_compat = s3c64xx_dt_compat,
73
81
.map_io = s3c64xx_dt_map_io,
74
-
.init_irq = s3c64xx_dt_init_irq,
75
82
.init_machine = s3c64xx_dt_init_machine,
76
83
.restart = s3c64xx_dt_restart,
77
84
MACHINE_END
+3
-1
arch/arm/mach-shmobile/board-lager.c
+3
-1
arch/arm/mach-shmobile/board-lager.c
···
245
245
{
246
246
lager_add_standard_devices();
247
247
248
-
phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
248
+
if (IS_ENABLED(CONFIG_PHYLIB))
249
+
phy_register_fixup_for_id("r8a7790-ether-ff:01",
250
+
lager_ksz8041_fixup);
249
251
}
250
252
251
253
static const char * const lager_boards_compat_dt[] __initconst = {
+5
-3
drivers/irqchip/irq-renesas-intc-irqpin.c
+5
-3
drivers/irqchip/irq-renesas-intc-irqpin.c
···
149
149
static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
150
150
int irq, int do_mask)
151
151
{
152
-
int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
153
-
int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
152
+
/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
153
+
int bitfield_width = 4;
154
+
int shift = 32 - (irq + 1) * bitfield_width;
154
155
155
156
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
156
157
shift, bitfield_width,
···
160
159
161
160
static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
162
161
{
162
+
/* The SENSE register is assumed to be 32-bit. */
163
163
int bitfield_width = p->config.sense_bitfield_width;
164
-
int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
164
+
int shift = 32 - (irq + 1) * bitfield_width;
165
165
166
166
dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
167
167