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platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P

Add support to read the low power mode requirements for Meteor Lake M and
Meteor Lake P.

Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20231129222132.2331261-19-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

authored by

Xi Pardee and committed by
Hans de Goede
935b8211 4d621c3f

+32 -7
+32 -7
drivers/platform/x86/intel/pmc/mtl.c
··· 11 11 #include <linux/pci.h> 12 12 #include "core.h" 13 13 14 + /* PMC SSRAM PMT Telemetry GUIDS */ 15 + #define SOCP_LPM_REQ_GUID 0x2625030 16 + #define IOEM_LPM_REQ_GUID 0x4357464 17 + #define IOEP_LPM_REQ_GUID 0x5077612 18 + 19 + static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; 20 + 14 21 /* 15 22 * Die Mapping to Product. 16 23 * Product SOCDie IOEDie PCHDie ··· 472 465 .lpm_sts = mtl_socm_lpm_maps, 473 466 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 474 467 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 468 + .lpm_reg_index = MTL_LPM_REG_INDEX, 475 469 }; 476 470 477 471 const struct pmc_bit_map mtl_ioep_pfear_map[] = { ··· 790 782 .ltr_show_sts = mtl_ioep_ltr_show_map, 791 783 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 792 784 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 785 + .lpm_num_maps = ADL_LPM_NUM_MAPS, 786 + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 787 + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 788 + .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 789 + .lpm_en_offset = MTL_LPM_EN_OFFSET, 790 + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 791 + .lpm_reg_index = MTL_LPM_REG_INDEX, 793 792 }; 794 793 795 794 const struct pmc_bit_map mtl_ioem_pfear_map[] = { ··· 937 922 .ltr_show_sts = mtl_ioep_ltr_show_map, 938 923 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 939 924 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 925 + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 926 + .lpm_num_maps = ADL_LPM_NUM_MAPS, 927 + .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 928 + .lpm_en_offset = MTL_LPM_EN_OFFSET, 929 + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 930 + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 931 + .lpm_reg_index = MTL_LPM_REG_INDEX, 940 932 }; 941 933 942 934 #define PMC_DEVID_SOCM 0x7e7f ··· 951 929 #define PMC_DEVID_IOEM 0x7ebf 952 930 static struct pmc_info mtl_pmc_info_list[] = { 953 931 { 954 - .devid = PMC_DEVID_SOCM, 955 - .map = &mtl_socm_reg_map, 932 + .guid = SOCP_LPM_REQ_GUID, 933 + .devid = PMC_DEVID_SOCM, 934 + .map = &mtl_socm_reg_map, 956 935 }, 957 936 { 958 - .devid = PMC_DEVID_IOEP, 959 - .map = &mtl_ioep_reg_map, 937 + .guid = IOEP_LPM_REQ_GUID, 938 + .devid = PMC_DEVID_IOEP, 939 + .map = &mtl_ioep_reg_map, 960 940 }, 961 941 { 962 - .devid = PMC_DEVID_IOEM, 963 - .map = &mtl_ioem_reg_map 942 + .guid = IOEM_LPM_REQ_GUID, 943 + .devid = PMC_DEVID_IOEM, 944 + .map = &mtl_ioem_reg_map 964 945 }, 965 946 {} 966 947 }; ··· 1039 1014 dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); 1040 1015 pmc_core_send_ltr_ignore(pmcdev, 3); 1041 1016 1042 - return 0; 1017 + return pmc_core_ssram_get_lpm_reqs(pmcdev); 1043 1018 }