Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 's390-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
Pull more s390 updates from Alexander Gordeev:
- Compile the decompressor with -Wno-pointer-sign flag to avoid a clang
warning
- Fix incomplete conversion to flag output macros in __xsch(), to avoid
always zero return value instead of the expected condition code
- Remove superfluous newlines from inline assemblies to improve
compiler inlining decisions
- Expose firmware provided UID Checking state in sysfs regardless of
the device presence or state
- CIO does not unregister subchannels when the attached device is
invalid or unavailable. Update the purge function to remove I/O
subchannels if the device number is found on cio_ignore list
- Consolidate PAI crypto allocation and cleanup paths
- The uv_get_secret_metadata() function has been removed some few
months ago, remove also the function mention it in a comment
* tag 's390-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
s390/uv: Fix comment of uv_find_secret() function
s390/pai_crypto: Consolidate PAI crypto allocation and cleanup paths
s390/cio: Update purge function to unregister the unused subchannels
s390/pci: Expose firmware provided UID Checking state in sysfs
s390: Remove superfluous newlines from inline assemblies
s390/cio/ioasm: Fix __xsch() condition code handling
s390: Add -Wno-pointer-sign to KBUILD_CFLAGS_DECOMPRESSOR
+223
-191
+1
arch/s390/Makefile
+1
arch/s390/Makefile
···
25
25
KBUILD_CFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -O2 -mpacked-stack -std=gnu11
26
26
KBUILD_CFLAGS_DECOMPRESSOR += -DDISABLE_BRANCH_PROFILING -D__NO_FORTIFY
27
27
KBUILD_CFLAGS_DECOMPRESSOR += -D__DECOMPRESSOR
28
+
KBUILD_CFLAGS_DECOMPRESSOR += -Wno-pointer-sign
28
29
KBUILD_CFLAGS_DECOMPRESSOR += -fno-delete-null-pointer-checks -msoft-float -mbackchain
29
30
KBUILD_CFLAGS_DECOMPRESSOR += -fno-asynchronous-unwind-tables
30
31
KBUILD_CFLAGS_DECOMPRESSOR += -ffreestanding
+1
-1
arch/s390/hypfs/hypfs_sprp.c
+1
-1
arch/s390/hypfs/hypfs_sprp.c
+9
-9
arch/s390/include/asm/ap.h
+9
-9
arch/s390/include/asm/ap.h
···
143
143
" lghi 2,0\n" /* 0 into gr2 */
144
144
" .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
145
145
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
146
-
" lgr %[reg2],2\n" /* gr2 into reg2 */
146
+
" lgr %[reg2],2" /* gr2 into reg2 */
147
147
: [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2)
148
148
: [qid] "d" (qid)
149
149
: "cc", "0", "1", "2");
···
186
186
asm volatile(
187
187
" lgr 0,%[reg0]\n" /* qid arg into gr0 */
188
188
" .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
189
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
189
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
190
190
: [reg1] "=&d" (reg1.value)
191
191
: [reg0] "d" (reg0)
192
192
: "cc", "0", "1");
···
211
211
asm volatile(
212
212
" lgr 0,%[reg0]\n" /* qid arg into gr0 */
213
213
" .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
214
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
214
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
215
215
: [reg1] "=&d" (reg1.value)
216
216
: [reg0] "d" (reg0)
217
217
: "cc", "0", "1");
···
315
315
" lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
316
316
" lgr 2,%[reg2]\n" /* ni addr into gr2 */
317
317
" .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
318
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
318
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
319
319
: [reg1] "+&d" (reg1.value)
320
320
: [reg0] "d" (reg0), [reg2] "d" (reg2)
321
321
: "cc", "memory", "0", "1", "2");
···
363
363
" lgr 1,%[reg1]\n" /* qact in info into gr1 */
364
364
" .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
365
365
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
366
-
" lgr %[reg2],2\n" /* qact out info into reg2 */
366
+
" lgr %[reg2],2" /* qact out info into reg2 */
367
367
: [reg1] "+&d" (reg1.value), [reg2] "=&d" (reg2)
368
368
: [reg0] "d" (reg0)
369
369
: "cc", "0", "1", "2");
···
388
388
asm volatile(
389
389
" lgr 0,%[reg0]\n" /* qid arg into gr0 */
390
390
" .insn rre,0xb2af0000,0,0\n" /* PQAP(BAPQ) */
391
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
391
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
392
392
: [reg1] "=&d" (reg1.value)
393
393
: [reg0] "d" (reg0)
394
394
: "cc", "0", "1");
···
416
416
" lgr 0,%[reg0]\n" /* qid arg into gr0 */
417
417
" lgr 2,%[reg2]\n" /* secret index into gr2 */
418
418
" .insn rre,0xb2af0000,0,0\n" /* PQAP(AAPQ) */
419
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
419
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
420
420
: [reg1] "=&d" (reg1.value)
421
421
: [reg0] "d" (reg0), [reg2] "d" (reg2)
422
422
: "cc", "0", "1", "2");
···
453
453
" lgr 0,%[reg0]\n" /* qid param in gr0 */
454
454
"0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n"
455
455
" brc 2,0b\n" /* handle partial completion */
456
-
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
456
+
" lgr %[reg1],1" /* gr1 (status) into reg1 */
457
457
: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
458
458
[nqap_r2] "+&d" (nqap_r2.pair)
459
459
: [nqap_r1] "d" (nqap_r1.pair)
···
518
518
" brc 6,0b\n" /* handle partial complete */
519
519
"2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */
520
520
" lgr %[reg1],1\n" /* gr1 (status) into reg1 */
521
-
" lgr %[reg2],2\n" /* gr2 (res length) into reg2 */
521
+
" lgr %[reg2],2" /* gr2 (res length) into reg2 */
522
522
: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
523
523
[reg2] "=&d" (reg2), [rp1] "+&d" (rp1.pair),
524
524
[rp2] "+&d" (rp2.pair)
+14
-14
arch/s390/include/asm/atomic_ops.h
+14
-14
arch/s390/include/asm/atomic_ops.h
···
17
17
int val;
18
18
19
19
asm volatile(
20
-
" l %[val],%[ptr]\n"
20
+
" l %[val],%[ptr]"
21
21
: [val] "=d" (val) : [ptr] "R" (*ptr));
22
22
return val;
23
23
}
···
26
26
{
27
27
if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) {
28
28
asm volatile(
29
-
" mvhi %[ptr],%[val]\n"
29
+
" mvhi %[ptr],%[val]"
30
30
: [ptr] "=Q" (*ptr) : [val] "K" (val));
31
31
} else {
32
32
asm volatile(
33
-
" st %[val],%[ptr]\n"
33
+
" st %[val],%[ptr]"
34
34
: [ptr] "=R" (*ptr) : [val] "d" (val));
35
35
}
36
36
}
···
40
40
long val;
41
41
42
42
asm volatile(
43
-
" lg %[val],%[ptr]\n"
43
+
" lg %[val],%[ptr]"
44
44
: [val] "=d" (val) : [ptr] "RT" (*ptr));
45
45
return val;
46
46
}
···
49
49
{
50
50
if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) {
51
51
asm volatile(
52
-
" mvghi %[ptr],%[val]\n"
52
+
" mvghi %[ptr],%[val]"
53
53
: [ptr] "=Q" (*ptr) : [val] "K" (val));
54
54
} else {
55
55
asm volatile(
56
-
" stg %[val],%[ptr]\n"
56
+
" stg %[val],%[ptr]"
57
57
: [ptr] "=RT" (*ptr) : [val] "d" (val));
58
58
}
59
59
}
···
66
66
op_type old; \
67
67
\
68
68
asm volatile( \
69
-
op_string " %[old],%[val],%[ptr]\n" \
69
+
op_string " %[old],%[val],%[ptr]" \
70
70
op_barrier \
71
71
: [old] "=d" (old), [ptr] "+QS" (*ptr) \
72
72
: [val] "d" (val) : "cc", "memory"); \
···
75
75
76
76
#define __ATOMIC_OPS(op_name, op_type, op_string) \
77
77
__ATOMIC_OP(op_name, op_type, op_string, "") \
78
-
__ATOMIC_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
78
+
__ATOMIC_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")
79
79
80
80
__ATOMIC_OPS(__atomic_add, int, "laa")
81
81
__ATOMIC_OPS(__atomic_and, int, "lan")
···
94
94
static __always_inline void op_name(op_type val, op_type *ptr) \
95
95
{ \
96
96
asm volatile( \
97
-
op_string " %[ptr],%[val]\n" \
97
+
op_string " %[ptr],%[val]" \
98
98
op_barrier \
99
99
: [ptr] "+QS" (*ptr) : [val] "i" (val) : "cc", "memory");\
100
100
}
101
101
102
102
#define __ATOMIC_CONST_OPS(op_name, op_type, op_string) \
103
103
__ATOMIC_CONST_OP(op_name, op_type, op_string, "") \
104
-
__ATOMIC_CONST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
104
+
__ATOMIC_CONST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")
105
105
106
106
__ATOMIC_CONST_OPS(__atomic_add_const, int, "asi")
107
107
__ATOMIC_CONST_OPS(__atomic64_add_const, long, "agsi")
···
179
179
int cc; \
180
180
\
181
181
asm volatile( \
182
-
op_string " %[tmp],%[val],%[ptr]\n" \
182
+
op_string " %[tmp],%[val],%[ptr]" \
183
183
op_barrier \
184
184
: "=@cc" (cc), [tmp] "=d" (tmp), [ptr] "+QS" (*ptr) \
185
185
: [val] "d" (val) \
···
189
189
190
190
#define __ATOMIC_TEST_OPS(op_name, op_type, op_string) \
191
191
__ATOMIC_TEST_OP(op_name, op_type, op_string, "") \
192
-
__ATOMIC_TEST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
192
+
__ATOMIC_TEST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")
193
193
194
194
__ATOMIC_TEST_OPS(__atomic_add_and_test, int, "laal")
195
195
__ATOMIC_TEST_OPS(__atomic64_add_and_test, long, "laalg")
···
203
203
int cc; \
204
204
\
205
205
asm volatile( \
206
-
op_string " %[ptr],%[val]\n" \
206
+
op_string " %[ptr],%[val]" \
207
207
op_barrier \
208
208
: "=@cc" (cc), [ptr] "+QS" (*ptr) \
209
209
: [val] "i" (val) \
···
213
213
214
214
#define __ATOMIC_CONST_TEST_OPS(op_name, op_type, op_string) \
215
215
__ATOMIC_CONST_TEST_OP(op_name, op_type, op_string, "") \
216
-
__ATOMIC_CONST_TEST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
216
+
__ATOMIC_CONST_TEST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")
217
217
218
218
__ATOMIC_CONST_TEST_OPS(__atomic_add_const_and_test, int, "alsi")
219
219
__ATOMIC_CONST_TEST_OPS(__atomic64_add_const_and_test, long, "algsi")
+4
-4
arch/s390/include/asm/barrier.h
+4
-4
arch/s390/include/asm/barrier.h
···
18
18
19
19
#ifdef MARCH_HAS_Z196_FEATURES
20
20
/* Fast-BCR without checkpoint synchronization */
21
-
#define __ASM_BCR_SERIALIZE "bcr 14,0\n"
21
+
#define __ASM_BCR_SERIALIZE "bcr 14,0"
22
22
#else
23
-
#define __ASM_BCR_SERIALIZE "bcr 15,0\n"
23
+
#define __ASM_BCR_SERIALIZE "bcr 15,0"
24
24
#endif
25
25
26
26
static __always_inline void bcr_serialize(void)
···
69
69
70
70
if (__builtin_constant_p(size) && size > 0) {
71
71
asm(" clgr %2,%1\n"
72
-
" slbgr %0,%0\n"
72
+
" slbgr %0,%0"
73
73
:"=d" (mask) : "d" (size-1), "d" (index) :"cc");
74
74
return mask;
75
75
}
76
76
asm(" clgr %1,%2\n"
77
-
" slbgr %0,%0\n"
77
+
" slbgr %0,%0"
78
78
:"=d" (mask) : "d" (size), "d" (index) :"cc");
79
79
return ~mask;
80
80
}
+1
-1
arch/s390/include/asm/bitops.h
+1
-1
arch/s390/include/asm/bitops.h
+1
-1
arch/s390/include/asm/checksum.h
+1
-1
arch/s390/include/asm/checksum.h
+6
-6
arch/s390/include/asm/cmpxchg.h
+6
-6
arch/s390/include/asm/cmpxchg.h
···
18
18
static __always_inline u32 __cs_asm(u64 ptr, u32 old, u32 new)
19
19
{
20
20
asm volatile(
21
-
" cs %[old],%[new],%[ptr]\n"
21
+
" cs %[old],%[new],%[ptr]"
22
22
: [old] "+d" (old), [ptr] "+Q" (*(u32 *)ptr)
23
23
: [new] "d" (new)
24
24
: "memory", "cc");
···
28
28
static __always_inline u64 __csg_asm(u64 ptr, u64 old, u64 new)
29
29
{
30
30
asm volatile(
31
-
" csg %[old],%[new],%[ptr]\n"
31
+
" csg %[old],%[new],%[ptr]"
32
32
: [old] "+d" (old), [ptr] "+QS" (*(u64 *)ptr)
33
33
: [new] "d" (new)
34
34
: "memory", "cc");
···
126
126
} \
127
127
case 4: { \
128
128
asm volatile( \
129
-
" cs %[__old],%[__new],%[__ptr]\n" \
129
+
" cs %[__old],%[__new],%[__ptr]" \
130
130
: [__old] "+d" (*__oldp), \
131
131
[__ptr] "+Q" (*(ptr)), \
132
132
"=@cc" (__cc) \
···
136
136
} \
137
137
case 8: { \
138
138
asm volatile( \
139
-
" csg %[__old],%[__new],%[__ptr]\n" \
139
+
" csg %[__old],%[__new],%[__ptr]" \
140
140
: [__old] "+d" (*__oldp), \
141
141
[__ptr] "+QS" (*(ptr)), \
142
142
"=@cc" (__cc) \
···
241
241
static __always_inline u128 arch_cmpxchg128(volatile u128 *ptr, u128 old, u128 new)
242
242
{
243
243
asm volatile(
244
-
" cdsg %[old],%[new],%[ptr]\n"
244
+
" cdsg %[old],%[new],%[ptr]"
245
245
: [old] "+d" (old), [ptr] "+QS" (*ptr)
246
246
: [new] "d" (new)
247
247
: "memory", "cc");
···
258
258
int cc;
259
259
260
260
asm volatile(
261
-
" cdsg %[old],%[new],%[ptr]\n"
261
+
" cdsg %[old],%[new],%[ptr]"
262
262
: [old] "+d" (*oldp), [ptr] "+QS" (*ptr), "=@cc" (cc)
263
263
: [new] "d" (new)
264
264
: "memory");
+12
-12
arch/s390/include/asm/cpacf.h
+12
-12
arch/s390/include/asm/cpacf.h
···
229
229
asm volatile(
230
230
" la %%r1,%[pb]\n"
231
231
" lghi %%r0,%[fc]\n"
232
-
" .insn rre,%[opc] << 16,%[r1],%[r2]\n"
232
+
" .insn rre,%[opc] << 16,%[r1],%[r2]"
233
233
: [pb] "=R" (*pb)
234
234
: [opc] "i" (opc), [fc] "i" (fc),
235
235
[r1] "i" (r1), [r2] "i" (r2)
···
242
242
asm volatile(
243
243
" la %%r1,%[pb]\n"
244
244
" lghi %%r0,%[fc]\n"
245
-
" .insn rrf,%[opc] << 16,%[r1],%[r2],%[r3],%[m4]\n"
245
+
" .insn rrf,%[opc] << 16,%[r1],%[r2],%[r3],%[m4]"
246
246
: [pb] "=R" (*pb)
247
247
: [opc] "i" (opc), [fc] "i" (fc), [r1] "i" (r1),
248
248
[r2] "i" (r2), [r3] "i" (r3), [m4] "i" (m4)
···
416
416
" lgr 0,%[fc]\n"
417
417
" lgr 1,%[pba]\n"
418
418
"0: .insn rre,%[opc] << 16,%[dst],%[src]\n"
419
-
" brc 1,0b\n" /* handle partial completion */
419
+
" brc 1,0b" /* handle partial completion */
420
420
: [src] "+&d" (s.pair), [dst] "+&d" (d.pair)
421
421
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
422
422
[opc] "i" (CPACF_KM)
···
448
448
" lgr 0,%[fc]\n"
449
449
" lgr 1,%[pba]\n"
450
450
"0: .insn rre,%[opc] << 16,%[dst],%[src]\n"
451
-
" brc 1,0b\n" /* handle partial completion */
451
+
" brc 1,0b" /* handle partial completion */
452
452
: [src] "+&d" (s.pair), [dst] "+&d" (d.pair)
453
453
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
454
454
[opc] "i" (CPACF_KMC)
···
476
476
" lgr 0,%[fc]\n"
477
477
" lgr 1,%[pba]\n"
478
478
"0: .insn rrf,%[opc] << 16,0,%[src],8,0\n"
479
-
" brc 1,0b\n" /* handle partial completion */
479
+
" brc 1,0b" /* handle partial completion */
480
480
: [src] "+&d" (s.pair)
481
481
: [fc] "d" (func), [pba] "d" ((unsigned long)(param)),
482
482
[opc] "i" (CPACF_KIMD)
···
501
501
" lgr 0,%[fc]\n"
502
502
" lgr 1,%[pba]\n"
503
503
"0: .insn rrf,%[opc] << 16,0,%[src],8,0\n"
504
-
" brc 1,0b\n" /* handle partial completion */
504
+
" brc 1,0b" /* handle partial completion */
505
505
: [src] "+&d" (s.pair)
506
506
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
507
507
[opc] "i" (CPACF_KLMD)
···
530
530
" lgr 1,%[pba]\n"
531
531
"0: .insn rre,%[opc] << 16,0,%[src]\n"
532
532
" brc 1,0b\n" /* handle partial completion */
533
-
" lgr %[r0],0\n"
533
+
" lgr %[r0],0"
534
534
: [r0] "+d" (*gr0), [src] "+&d" (s.pair)
535
535
: [pba] "d" ((unsigned long)param),
536
536
[opc] "i" (CPACF_KMAC)
···
580
580
" lgr 0,%[fc]\n"
581
581
" lgr 1,%[pba]\n"
582
582
"0: .insn rrf,%[opc] << 16,%[dst],%[src],%[ctr],0\n"
583
-
" brc 1,0b\n" /* handle partial completion */
583
+
" brc 1,0b" /* handle partial completion */
584
584
: [src] "+&d" (s.pair), [dst] "+&d" (d.pair),
585
585
[ctr] "+&d" (c.pair)
586
586
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
···
614
614
" lgr 0,%[fc]\n"
615
615
" lgr 1,%[pba]\n"
616
616
"0: .insn rre,%[opc] << 16,%[dst],%[seed]\n"
617
-
" brc 1,0b\n" /* handle partial completion */
617
+
" brc 1,0b" /* handle partial completion */
618
618
: [dst] "+&d" (d.pair)
619
619
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
620
620
[seed] "d" (s.pair), [opc] "i" (CPACF_PRNO)
···
640
640
asm volatile (
641
641
" lghi 0,%[fc]\n"
642
642
"0: .insn rre,%[opc] << 16,%[ucbuf],%[cbuf]\n"
643
-
" brc 1,0b\n" /* handle partial completion */
643
+
" brc 1,0b" /* handle partial completion */
644
644
: [ucbuf] "+&d" (u.pair), [cbuf] "+&d" (c.pair)
645
645
: [fc] "K" (CPACF_PRNO_TRNG), [opc] "i" (CPACF_PRNO)
646
646
: "cc", "memory", "0");
···
692
692
asm volatile(
693
693
" lgr 0,%[fc]\n"
694
694
" lgr 1,%[pba]\n"
695
-
" .insn rre,%[opc] << 16,0,0\n" /* PCKMO opcode */
695
+
" .insn rre,%[opc] << 16,0,0" /* PCKMO opcode */
696
696
:
697
697
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
698
698
[opc] "i" (CPACF_PCKMO)
···
725
725
" lgr 0,%[fc]\n"
726
726
" lgr 1,%[pba]\n"
727
727
"0: .insn rrf,%[opc] << 16,%[dst],%[src],%[aad],0\n"
728
-
" brc 1,0b\n" /* handle partial completion */
728
+
" brc 1,0b" /* handle partial completion */
729
729
: [dst] "+&d" (d.pair), [src] "+&d" (s.pair),
730
730
[aad] "+&d" (a.pair)
731
731
: [fc] "d" (func), [pba] "d" ((unsigned long)param),
+4
-4
arch/s390/include/asm/ctlreg.h
+4
-4
arch/s390/include/asm/ctlreg.h
···
100
100
BUILD_BUG_ON(sizeof(struct addrtype) != _esize); \
101
101
typecheck(struct ctlreg, array[0]); \
102
102
asm volatile( \
103
-
" lctlg %[_low],%[_high],%[_arr]\n" \
103
+
" lctlg %[_low],%[_high],%[_arr]" \
104
104
: \
105
105
: [_arr] "Q" (*(struct addrtype *)(&array)), \
106
106
[_low] "i" (low), [_high] "i" (high) \
···
119
119
BUILD_BUG_ON(sizeof(struct addrtype) != _esize); \
120
120
typecheck(struct ctlreg, array[0]); \
121
121
asm volatile( \
122
-
" stctg %[_low],%[_high],%[_arr]\n" \
122
+
" stctg %[_low],%[_high],%[_arr]" \
123
123
: [_arr] "=Q" (*(struct addrtype *)(&array)) \
124
124
: [_low] "i" (low), [_high] "i" (high)); \
125
125
} while (0)
···
127
127
static __always_inline void local_ctl_load(unsigned int cr, struct ctlreg *reg)
128
128
{
129
129
asm volatile(
130
-
" lctlg %[cr],%[cr],%[reg]\n"
130
+
" lctlg %[cr],%[cr],%[reg]"
131
131
:
132
132
: [reg] "Q" (*reg), [cr] "i" (cr)
133
133
: "memory");
···
136
136
static __always_inline void local_ctl_store(unsigned int cr, struct ctlreg *reg)
137
137
{
138
138
asm volatile(
139
-
" stctg %[cr],%[cr],%[reg]\n"
139
+
" stctg %[cr],%[cr],%[reg]"
140
140
: [reg] "=Q" (*reg)
141
141
: [cr] "i" (cr));
142
142
}
+18
-18
arch/s390/include/asm/fpu-insn.h
+18
-18
arch/s390/include/asm/fpu-insn.h
···
38
38
39
39
static __always_inline void fpu_cefbr(u8 f1, s32 val)
40
40
{
41
-
asm volatile("cefbr %[f1],%[val]\n"
41
+
asm volatile("cefbr %[f1],%[val]"
42
42
:
43
43
: [f1] "I" (f1), [val] "d" (val)
44
44
: "memory");
···
48
48
{
49
49
unsigned long val;
50
50
51
-
asm volatile("cgebr %[val],%[mode],%[f2]\n"
51
+
asm volatile("cgebr %[val],%[mode],%[f2]"
52
52
: [val] "=d" (val)
53
53
: [f2] "I" (f2), [mode] "I" (mode)
54
54
: "memory");
···
57
57
58
58
static __always_inline void fpu_debr(u8 f1, u8 f2)
59
59
{
60
-
asm volatile("debr %[f1],%[f2]\n"
60
+
asm volatile("debr %[f1],%[f2]"
61
61
:
62
62
: [f1] "I" (f1), [f2] "I" (f2)
63
63
: "memory");
···
66
66
static __always_inline void fpu_ld(unsigned short fpr, freg_t *reg)
67
67
{
68
68
instrument_read(reg, sizeof(*reg));
69
-
asm volatile("ld %[fpr],%[reg]\n"
69
+
asm volatile("ld %[fpr],%[reg]"
70
70
:
71
71
: [fpr] "I" (fpr), [reg] "Q" (reg->ui)
72
72
: "memory");
···
74
74
75
75
static __always_inline void fpu_ldgr(u8 f1, u32 val)
76
76
{
77
-
asm volatile("ldgr %[f1],%[val]\n"
77
+
asm volatile("ldgr %[f1],%[val]"
78
78
:
79
79
: [f1] "I" (f1), [val] "d" (val)
80
80
: "memory");
···
113
113
static __always_inline void fpu_std(unsigned short fpr, freg_t *reg)
114
114
{
115
115
instrument_write(reg, sizeof(*reg));
116
-
asm volatile("std %[fpr],%[reg]\n"
116
+
asm volatile("std %[fpr],%[reg]"
117
117
: [reg] "=Q" (reg->ui)
118
118
: [fpr] "I" (fpr)
119
119
: "memory");
···
181
181
static __always_inline void fpu_vl(u8 v1, const void *vxr)
182
182
{
183
183
instrument_read(vxr, sizeof(__vector128));
184
-
asm volatile("VL %[v1],%O[vxr],,%R[vxr]\n"
184
+
asm volatile("VL %[v1],%O[vxr],,%R[vxr]"
185
185
:
186
186
: [vxr] "Q" (*(__vector128 *)vxr),
187
187
[v1] "I" (v1)
···
195
195
instrument_read(vxr, sizeof(__vector128));
196
196
asm volatile(
197
197
" la 1,%[vxr]\n"
198
-
" VL %[v1],0,,1\n"
198
+
" VL %[v1],0,,1"
199
199
:
200
200
: [vxr] "R" (*(__vector128 *)vxr),
201
201
[v1] "I" (v1)
···
239
239
240
240
size = min(index + 1, sizeof(__vector128));
241
241
instrument_read(vxr, size);
242
-
asm volatile("VLL %[v1],%[index],%O[vxr],%R[vxr]\n"
242
+
asm volatile("VLL %[v1],%[index],%O[vxr],%R[vxr]"
243
243
:
244
244
: [vxr] "Q" (*(u8 *)vxr),
245
245
[index] "d" (index),
···
257
257
instrument_read(vxr, size);
258
258
asm volatile(
259
259
" la 1,%[vxr]\n"
260
-
" VLL %[v1],%[index],0,1\n"
260
+
" VLL %[v1],%[index],0,1"
261
261
:
262
262
: [vxr] "R" (*(u8 *)vxr),
263
263
[index] "d" (index),
···
277
277
} *_v = (void *)(_vxrs); \
278
278
\
279
279
instrument_read(_v, size); \
280
-
asm volatile("VLM %[v1],%[v3],%O[vxrs],%R[vxrs]\n" \
280
+
asm volatile("VLM %[v1],%[v3],%O[vxrs],%R[vxrs]" \
281
281
: \
282
282
: [vxrs] "Q" (*_v), \
283
283
[v1] "I" (_v1), [v3] "I" (_v3) \
···
297
297
instrument_read(_v, size); \
298
298
asm volatile( \
299
299
" la 1,%[vxrs]\n" \
300
-
" VLM %[v1],%[v3],0,1\n" \
300
+
" VLM %[v1],%[v3],0,1" \
301
301
: \
302
302
: [vxrs] "R" (*_v), \
303
303
[v1] "I" (_v1), [v3] "I" (_v3) \
···
360
360
static __always_inline void fpu_vst(u8 v1, const void *vxr)
361
361
{
362
362
instrument_write(vxr, sizeof(__vector128));
363
-
asm volatile("VST %[v1],%O[vxr],,%R[vxr]\n"
363
+
asm volatile("VST %[v1],%O[vxr],,%R[vxr]"
364
364
: [vxr] "=Q" (*(__vector128 *)vxr)
365
365
: [v1] "I" (v1)
366
366
: "memory");
···
373
373
instrument_write(vxr, sizeof(__vector128));
374
374
asm volatile(
375
375
" la 1,%[vxr]\n"
376
-
" VST %[v1],0,,1\n"
376
+
" VST %[v1],0,,1"
377
377
: [vxr] "=R" (*(__vector128 *)vxr)
378
378
: [v1] "I" (v1)
379
379
: "memory", "1");
···
389
389
390
390
size = min(index + 1, sizeof(__vector128));
391
391
instrument_write(vxr, size);
392
-
asm volatile("VSTL %[v1],%[index],%O[vxr],%R[vxr]\n"
392
+
asm volatile("VSTL %[v1],%[index],%O[vxr],%R[vxr]"
393
393
: [vxr] "=Q" (*(u8 *)vxr)
394
394
: [index] "d" (index), [v1] "I" (v1)
395
395
: "memory");
···
405
405
instrument_write(vxr, size);
406
406
asm volatile(
407
407
" la 1,%[vxr]\n"
408
-
" VSTL %[v1],%[index],0,1\n"
408
+
" VSTL %[v1],%[index],0,1"
409
409
: [vxr] "=R" (*(u8 *)vxr)
410
410
: [index] "d" (index), [v1] "I" (v1)
411
411
: "memory", "1");
···
423
423
} *_v = (void *)(_vxrs); \
424
424
\
425
425
instrument_write(_v, size); \
426
-
asm volatile("VSTM %[v1],%[v3],%O[vxrs],%R[vxrs]\n" \
426
+
asm volatile("VSTM %[v1],%[v3],%O[vxrs],%R[vxrs]" \
427
427
: [vxrs] "=Q" (*_v) \
428
428
: [v1] "I" (_v1), [v3] "I" (_v3) \
429
429
: "memory"); \
···
442
442
instrument_write(_v, size); \
443
443
asm volatile( \
444
444
" la 1,%[vxrs]\n" \
445
-
" VSTM %[v1],%[v3],0,1\n" \
445
+
" VSTM %[v1],%[v3],0,1" \
446
446
: [vxrs] "=R" (*_v) \
447
447
: [v1] "I" (_v1), [v3] "I" (_v3) \
448
448
: "memory", "1"); \
+1
-1
arch/s390/include/asm/kvm_para.h
+1
-1
arch/s390/include/asm/kvm_para.h
+10
arch/s390/include/asm/pci.h
+10
arch/s390/include/asm/pci.h
···
246
246
/* UID */
247
247
void update_uid_checking(bool new);
248
248
249
+
/* Firmware Sysfs */
250
+
int __init __zpci_fw_sysfs_init(void);
251
+
252
+
static inline int __init zpci_fw_sysfs_init(void)
253
+
{
254
+
if (IS_ENABLED(CONFIG_SYSFS))
255
+
return __zpci_fw_sysfs_init();
256
+
return 0;
257
+
}
258
+
249
259
/* IOMMU Interface */
250
260
int zpci_init_iommu(struct zpci_dev *zdev);
251
261
void zpci_destroy_iommu(struct zpci_dev *zdev);
+4
-4
arch/s390/include/asm/percpu.h
+4
-4
arch/s390/include/asm/percpu.h
···
73
73
if (__builtin_constant_p(val__) && \
74
74
((szcast)val__ > -129) && ((szcast)val__ < 128)) { \
75
75
asm volatile( \
76
-
op2 " %[ptr__],%[val__]\n" \
76
+
op2 " %[ptr__],%[val__]" \
77
77
: [ptr__] "+Q" (*ptr__) \
78
78
: [val__] "i" ((szcast)val__) \
79
79
: "cc"); \
80
80
} else { \
81
81
asm volatile( \
82
-
op1 " %[old__],%[val__],%[ptr__]\n" \
82
+
op1 " %[old__],%[val__],%[ptr__]" \
83
83
: [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \
84
84
: [val__] "d" (val__) \
85
85
: "cc"); \
···
98
98
preempt_disable_notrace(); \
99
99
ptr__ = raw_cpu_ptr(&(pcp)); \
100
100
asm volatile( \
101
-
op " %[old__],%[val__],%[ptr__]\n" \
101
+
op " %[old__],%[val__],%[ptr__]" \
102
102
: [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \
103
103
: [val__] "d" (val__) \
104
104
: "cc"); \
···
117
117
preempt_disable_notrace(); \
118
118
ptr__ = raw_cpu_ptr(&(pcp)); \
119
119
asm volatile( \
120
-
op " %[old__],%[val__],%[ptr__]\n" \
120
+
op " %[old__],%[val__],%[ptr__]" \
121
121
: [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \
122
122
: [val__] "d" (val__) \
123
123
: "cc"); \
+1
-1
arch/s390/include/asm/processor.h
+1
-1
arch/s390/include/asm/processor.h
+1
-1
arch/s390/include/asm/rwonce.h
+1
-1
arch/s390/include/asm/rwonce.h
+1
-1
arch/s390/include/asm/spinlock.h
+1
-1
arch/s390/include/asm/spinlock.h
+2
-2
arch/s390/include/asm/stacktrace.h
+2
-2
arch/s390/include/asm/stacktrace.h
···
199
199
" lg 15,%[_stack]\n" \
200
200
" stg %[_frame],%[_bc](15)\n" \
201
201
" brasl 14,%[_fn]\n" \
202
-
" lgr 15,%[_prev]\n" \
202
+
" lgr 15,%[_prev]" \
203
203
: [_prev] "=&d" (prev), CALL_FMT_##nr \
204
204
: [_stack] "R" (__stack), \
205
205
[_bc] "i" (offsetof(struct stack_frame, back_chain)), \
···
250
250
" lra 14,0(1)\n" \
251
251
" lpswe %[psw_enter]\n" \
252
252
"0: lpswe 0(7)\n" \
253
-
"1:\n" \
253
+
"1:" \
254
254
: CALL_FMT_##nr, [psw_leave] "=Q" (psw_leave) \
255
255
: [psw_enter] "Q" (psw_enter) \
256
256
: "7", CALL_CLOBBER_##nr); \
+1
-1
arch/s390/include/asm/string.h
+1
-1
arch/s390/include/asm/string.h
+1
-1
arch/s390/include/asm/syscall.h
+1
-1
arch/s390/include/asm/syscall.h
+1
-1
arch/s390/include/asm/timex.h
+1
-1
arch/s390/include/asm/timex.h
+1
-1
arch/s390/kernel/diag/diag310.c
+1
-1
arch/s390/kernel/diag/diag310.c
···
66
66
union register_pair rp = { .even = (unsigned long)addr, .odd = size };
67
67
68
68
diag_stat_inc(DIAG_STAT_X310);
69
-
asm volatile("diag %[rp],%[subcode],0x310\n"
69
+
asm volatile("diag %[rp],%[subcode],0x310"
70
70
: [rp] "+d" (rp.pair)
71
71
: [subcode] "d" (subcode)
72
72
: "memory");
+1
-1
arch/s390/kernel/diag/diag324.c
+1
-1
arch/s390/kernel/diag/diag324.c
···
101
101
union register_pair rp = { .even = (unsigned long)addr };
102
102
103
103
diag_stat_inc(DIAG_STAT_X324);
104
-
asm volatile("diag %[rp],%[subcode],0x324\n"
104
+
asm volatile("diag %[rp],%[subcode],0x324"
105
105
: [rp] "+d" (rp.pair)
106
106
: [subcode] "d" (subcode)
107
107
: "memory");
+44
-62
arch/s390/kernel/perf_pai_crypto.c
+44
-62
arch/s390/kernel/perf_pai_crypto.c
···
80
80
/* Release the PMU if event is the last perf event */
81
81
static DEFINE_MUTEX(pai_reserve_mutex);
82
82
83
+
/* Free all memory allocated for event counting/sampling setup */
84
+
static void paicrypt_free(struct paicrypt_mapptr *mp)
85
+
{
86
+
free_page((unsigned long)mp->mapptr->page);
87
+
kvfree(mp->mapptr->save);
88
+
kfree(mp->mapptr);
89
+
mp->mapptr = NULL;
90
+
}
91
+
83
92
/* Adjust usage counters and remove allocated memory when all users are
84
93
* gone.
85
94
*/
···
102
93
"refcnt %u\n", __func__, event->attr.config,
103
94
event->cpu, cpump->active_events,
104
95
refcount_read(&cpump->refcnt));
105
-
if (refcount_dec_and_test(&cpump->refcnt)) {
106
-
debug_sprintf_event(cfm_dbg, 4, "%s page %#lx save %p\n",
107
-
__func__, (unsigned long)cpump->page,
108
-
cpump->save);
109
-
free_page((unsigned long)cpump->page);
110
-
kvfree(cpump->save);
111
-
kfree(cpump);
112
-
mp->mapptr = NULL;
113
-
}
96
+
if (refcount_dec_and_test(&cpump->refcnt))
97
+
paicrypt_free(mp);
114
98
paicrypt_root_free();
115
99
mutex_unlock(&pai_reserve_mutex);
116
100
}
···
177
175
*
178
176
* Allocate the memory for the event.
179
177
*/
180
-
static struct paicrypt_map *paicrypt_busy(struct perf_event *event, int cpu)
178
+
static int paicrypt_alloc_cpu(struct perf_event *event, int cpu)
181
179
{
182
180
struct paicrypt_map *cpump = NULL;
183
181
struct paicrypt_mapptr *mp;
184
182
int rc;
185
183
186
184
mutex_lock(&pai_reserve_mutex);
187
-
188
185
/* Allocate root node */
189
186
rc = paicrypt_root_alloc();
190
187
if (rc)
···
193
192
mp = per_cpu_ptr(paicrypt_root.mapptr, cpu);
194
193
cpump = mp->mapptr;
195
194
if (!cpump) { /* Paicrypt_map allocated? */
195
+
rc = -ENOMEM;
196
196
cpump = kzalloc(sizeof(*cpump), GFP_KERNEL);
197
-
if (!cpump) {
198
-
rc = -ENOMEM;
199
-
goto free_root;
197
+
if (!cpump)
198
+
goto undo;
199
+
/* Allocate memory for counter page and counter extraction.
200
+
* Only the first counting event has to allocate a page.
201
+
*/
202
+
mp->mapptr = cpump;
203
+
cpump->page = (unsigned long *)get_zeroed_page(GFP_KERNEL);
204
+
cpump->save = kvmalloc_array(paicrypt_cnt + 1,
205
+
sizeof(struct pai_userdata),
206
+
GFP_KERNEL);
207
+
if (!cpump->page || !cpump->save) {
208
+
paicrypt_free(mp);
209
+
goto undo;
200
210
}
201
211
INIT_LIST_HEAD(&cpump->syswide_list);
202
-
}
203
-
204
-
/* Allocate memory for counter page and counter extraction.
205
-
* Only the first counting event has to allocate a page.
206
-
*/
207
-
if (cpump->page) {
212
+
refcount_set(&cpump->refcnt, 1);
213
+
rc = 0;
214
+
} else {
208
215
refcount_inc(&cpump->refcnt);
209
-
goto unlock;
210
216
}
211
217
212
-
rc = -ENOMEM;
213
-
cpump->page = (unsigned long *)get_zeroed_page(GFP_KERNEL);
214
-
if (!cpump->page)
215
-
goto free_paicrypt_map;
216
-
cpump->save = kvmalloc_array(paicrypt_cnt + 1,
217
-
sizeof(struct pai_userdata), GFP_KERNEL);
218
-
if (!cpump->save) {
219
-
free_page((unsigned long)cpump->page);
220
-
cpump->page = NULL;
221
-
goto free_paicrypt_map;
218
+
undo:
219
+
if (rc) {
220
+
/* Error in allocation of event, decrement anchor. Since
221
+
* the event in not created, its destroy() function is never
222
+
* invoked. Adjust the reference counter for the anchor.
223
+
*/
224
+
paicrypt_root_free();
222
225
}
223
-
224
-
/* Set mode and reference count */
225
-
rc = 0;
226
-
refcount_set(&cpump->refcnt, 1);
227
-
mp->mapptr = cpump;
228
-
debug_sprintf_event(cfm_dbg, 5, "%s users %d refcnt %u page %#lx "
229
-
"save %p rc %d\n", __func__, cpump->active_events,
230
-
refcount_read(&cpump->refcnt),
231
-
(unsigned long)cpump->page, cpump->save, rc);
232
-
goto unlock;
233
-
234
-
free_paicrypt_map:
235
-
/* Undo memory allocation */
236
-
kfree(cpump);
237
-
mp->mapptr = NULL;
238
-
free_root:
239
-
paicrypt_root_free();
240
226
unlock:
241
227
mutex_unlock(&pai_reserve_mutex);
242
-
return rc ? ERR_PTR(rc) : cpump;
228
+
return rc;
243
229
}
244
230
245
-
static int paicrypt_event_init_all(struct perf_event *event)
231
+
static int paicrypt_alloc(struct perf_event *event)
246
232
{
247
-
struct paicrypt_map *cpump;
248
233
struct cpumask *maskptr;
249
234
int cpu, rc = -ENOMEM;
250
235
···
239
252
goto out;
240
253
241
254
for_each_online_cpu(cpu) {
242
-
cpump = paicrypt_busy(event, cpu);
243
-
if (IS_ERR(cpump)) {
255
+
rc = paicrypt_alloc_cpu(event, cpu);
256
+
if (rc) {
244
257
for_each_cpu(cpu, maskptr)
245
258
paicrypt_event_destroy_cpu(event, cpu);
246
259
kfree(maskptr);
247
-
rc = PTR_ERR(cpump);
248
260
goto out;
249
261
}
250
262
cpumask_set_cpu(cpu, maskptr);
···
265
279
static int paicrypt_event_init(struct perf_event *event)
266
280
{
267
281
struct perf_event_attr *a = &event->attr;
268
-
struct paicrypt_map *cpump;
269
282
int rc = 0;
270
283
271
284
/* PAI crypto PMU registered as PERF_TYPE_RAW, check event type */
···
286
301
}
287
302
}
288
303
289
-
if (event->cpu >= 0) {
290
-
cpump = paicrypt_busy(event, event->cpu);
291
-
if (IS_ERR(cpump))
292
-
rc = PTR_ERR(cpump);
293
-
} else {
294
-
rc = paicrypt_event_init_all(event);
295
-
}
304
+
if (event->cpu >= 0)
305
+
rc = paicrypt_alloc_cpu(event, event->cpu);
306
+
else
307
+
rc = paicrypt_alloc(event);
296
308
if (rc) {
297
309
free_page(PAI_SAVE_AREA(event));
298
310
goto out;
+1
-1
arch/s390/kernel/setup.c
+1
-1
arch/s390/kernel/setup.c
+1
-1
arch/s390/kernel/skey.c
+1
-1
arch/s390/kernel/skey.c
+1
-1
arch/s390/kernel/smp.c
+1
-1
arch/s390/kernel/smp.c
···
340
340
"0: sigp 0,%0,%2 # sigp restart to target cpu\n"
341
341
" brc 2,0b # busy, try again\n"
342
342
"1: sigp 0,%1,%3 # sigp stop to current cpu\n"
343
-
" brc 2,1b # busy, try again\n"
343
+
" brc 2,1b # busy, try again"
344
344
: : "d" (pcpu->address), "d" (source_cpu),
345
345
"K" (SIGP_RESTART), "K" (SIGP_STOP)
346
346
: "0", "1", "cc");
+2
-2
arch/s390/kernel/uv.c
+2
-2
arch/s390/kernel/uv.c
···
866
866
return -ENOENT;
867
867
}
868
868
869
-
/*
870
-
* Do the actual search for `uv_get_secret_metadata`.
869
+
/**
870
+
* uv_find_secret() - search secret metadata for a given secret id.
871
871
* @secret_id: search pattern.
872
872
* @list: ephemeral buffer space
873
873
* @secret: output data, containing the secret's metadata.
+3
-3
arch/s390/kvm/kvm-s390.c
+3
-3
arch/s390/kvm/kvm-s390.c
···
356
356
{
357
357
asm volatile(
358
358
" lghi 0,0\n"
359
-
" .insn rsy,0xeb0000000016,0,0,%[query]\n"
359
+
" .insn rsy,0xeb0000000016,0,0,%[query]"
360
360
: [query] "=QS" (*query)
361
361
:
362
362
: "cc", "0");
···
368
368
" lghi 0,0\n"
369
369
" la 1,%[query]\n"
370
370
/* Parameter registers are ignored */
371
-
" .insn rre,0xb9380000,2,4\n"
371
+
" .insn rre,0xb9380000,2,4"
372
372
: [query] "=R" (*query)
373
373
:
374
374
: "cc", "0", "1");
···
380
380
" lghi 0,0\n"
381
381
" la 1,%[query]\n"
382
382
/* Parameter registers are ignored */
383
-
" .insn rrf,0xb9390000,2,4,6,0\n"
383
+
" .insn rrf,0xb9390000,2,4,6,0"
384
384
: [query] "=R" (*query)
385
385
:
386
386
: "cc", "0", "1");
+3
-3
arch/s390/lib/spinlock.c
+3
-3
arch/s390/lib/spinlock.c
···
96
96
97
97
asm_inline volatile(
98
98
ALTERNATIVE("nop", ".insn rre,0xb2fa0000,4,0", ALT_FACILITY(49)) /* NIAI 4 */
99
-
" l %[owner],%[lock]\n"
99
+
" l %[owner],%[lock]"
100
100
: [owner] "=d" (owner) : [lock] "R" (*lock) : "memory");
101
101
return owner;
102
102
}
···
109
109
110
110
asm_inline volatile(
111
111
ALTERNATIVE("nop", ".insn rre,0xb2fa0000,8,0", ALT_FACILITY(49)) /* NIAI 8 */
112
-
" cs %[old],%[new],%[lock]\n"
112
+
" cs %[old],%[new],%[lock]"
113
113
: [old] "+d" (old), [lock] "+Q" (*lock), "=@cc" (cc)
114
114
: [new] "d" (new)
115
115
: "memory");
···
124
124
125
125
asm_inline volatile(
126
126
ALTERNATIVE("nop", ".insn rre,0xb2fa0000,8,0", ALT_FACILITY(49)) /* NIAI 8 */
127
-
" cs %[old],%[new],%[lock]\n"
127
+
" cs %[old],%[new],%[lock]"
128
128
: [old] "+d" (old), [lock] "+Q" (*lock)
129
129
: [new] "d" (new)
130
130
: "cc", "memory");
+4
-4
arch/s390/lib/string.c
+4
-4
arch/s390/lib/string.c
···
27
27
asm volatile(
28
28
" lghi 0,0\n"
29
29
"0: srst %[e],%[s]\n"
30
-
" jo 0b\n"
30
+
" jo 0b"
31
31
: [e] "+&a" (e), [s] "+&a" (s)
32
32
:
33
33
: "cc", "memory", "0");
···
41
41
asm volatile(
42
42
" lghi 0,0\n"
43
43
"0: srst %[p],%[s]\n"
44
-
" jo 0b\n"
44
+
" jo 0b"
45
45
: [p] "+&d" (p), [s] "+&a" (s)
46
46
:
47
47
: "cc", "memory", "0");
···
95
95
"0: srst %[dummy],%[dest]\n"
96
96
" jo 0b\n"
97
97
"1: mvst %[dummy],%[src]\n"
98
-
" jo 1b\n"
98
+
" jo 1b"
99
99
: [dummy] "+&a" (dummy), [dest] "+&a" (dest), [src] "+&a" (src)
100
100
:
101
101
: "cc", "memory", "0");
···
291
291
asm volatile(
292
292
" lgr 0,%[c]\n"
293
293
"0: srst %[ret],%[s]\n"
294
-
" jo 0b\n"
294
+
" jo 0b"
295
295
: [ret] "+&a" (ret), [s] "+&a" (s)
296
296
: [c] "d" (c)
297
297
: "cc", "memory", "0");
+2
-2
arch/s390/lib/test_unwind.c
+2
-2
arch/s390/lib/test_unwind.c
···
150
150
regs.gprs[15] = current_stack_pointer;
151
151
152
152
asm volatile(
153
-
"basr %[psw_addr],0\n"
153
+
"basr %[psw_addr],0"
154
154
: [psw_addr] "=d" (regs.psw.addr));
155
155
return regs;
156
156
}
···
232
232
asm volatile(
233
233
" nopr %%r7\n"
234
234
"test_unwind_kprobed_insn:\n"
235
-
" nopr %%r7\n"
235
+
" nopr %%r7"
236
236
:);
237
237
}
238
238
+4
-4
arch/s390/lib/xor.c
+4
-4
arch/s390/lib/xor.c
···
27
27
"1: exrl %0,2f\n"
28
28
" j 3f\n"
29
29
"2: xc 0(1,%1),0(%2)\n"
30
-
"3:\n"
30
+
"3:"
31
31
: : "d" (bytes), "a" (p1), "a" (p2)
32
32
: "0", "cc", "memory");
33
33
}
···
53
53
" j 4f\n"
54
54
"2: xc 0(1,%1),0(%2)\n"
55
55
"3: xc 0(1,%1),0(%3)\n"
56
-
"4:\n"
56
+
"4:"
57
57
: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3)
58
58
: : "0", "cc", "memory");
59
59
}
···
84
84
"2: xc 0(1,%1),0(%2)\n"
85
85
"3: xc 0(1,%1),0(%3)\n"
86
86
"4: xc 0(1,%1),0(%4)\n"
87
-
"5:\n"
87
+
"5:"
88
88
: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4)
89
89
: : "0", "cc", "memory");
90
90
}
···
121
121
"3: xc 0(1,%1),0(%3)\n"
122
122
"4: xc 0(1,%1),0(%4)\n"
123
123
"5: xc 0(1,%1),0(%5)\n"
124
-
"6:\n"
124
+
"6:"
125
125
: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4),
126
126
"+a" (p5)
127
127
: : "0", "cc", "memory");
+1
-1
arch/s390/mm/maccess.c
+1
-1
arch/s390/mm/maccess.c
+1
-1
arch/s390/mm/pgalloc.c
+1
-1
arch/s390/mm/pgalloc.c
+4
arch/s390/pci/pci.c
+4
arch/s390/pci/pci.c
+2
-2
arch/s390/pci/pci_insn.c
+2
-2
arch/s390/pci/pci_insn.c
···
145
145
return -EIO;
146
146
147
147
asm volatile(
148
-
".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
148
+
".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]"
149
149
: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
150
150
151
151
return 0;
···
442
442
443
443
static inline void __pciwb_mio(void)
444
444
{
445
-
asm volatile (".insn rre,0xb9d50000,0,0\n");
445
+
asm volatile (".insn rre,0xb9d50000,0,0");
446
446
}
447
447
448
448
void zpci_barrier(void)
+25
arch/s390/pci/pci_sysfs.c
+25
arch/s390/pci/pci_sysfs.c
···
41
41
zpci_attr(segment2, "0x%02x\n", pfip[2]);
42
42
zpci_attr(segment3, "0x%02x\n", pfip[3]);
43
43
44
+
#define ZPCI_FW_ATTR_RO(_name) \
45
+
static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
46
+
44
47
static ssize_t mio_enabled_show(struct device *dev,
45
48
struct device_attribute *attr, char *buf)
46
49
{
···
167
164
}
168
165
static DEVICE_ATTR_RO(uid_is_unique);
169
166
167
+
static ssize_t uid_checking_show(struct kobject *kobj,
168
+
struct kobj_attribute *attr, char *buf)
169
+
{
170
+
return sysfs_emit(buf, "%d\n", zpci_unique_uid ? 1 : 0);
171
+
}
172
+
ZPCI_FW_ATTR_RO(uid_checking);
173
+
170
174
/* analogous to smbios index */
171
175
static ssize_t index_show(struct device *dev,
172
176
struct device_attribute *attr, char *buf)
···
243
233
.name = "pfip",
244
234
.attrs = pfip_attrs,
245
235
};
236
+
237
+
static struct attribute *clp_fw_attrs[] = {
238
+
&uid_checking_attr.attr,
239
+
NULL,
240
+
};
241
+
242
+
static struct attribute_group clp_fw_attr_group = {
243
+
.name = "clp",
244
+
.attrs = clp_fw_attrs,
245
+
};
246
+
247
+
int __init __zpci_fw_sysfs_init(void)
248
+
{
249
+
return sysfs_create_group(firmware_kobj, &clp_fw_attr_group);
250
+
}
+1
-1
drivers/s390/char/sclp_early_core.c
+1
-1
drivers/s390/char/sclp_early_core.c
+1
-1
drivers/s390/cio/cmf.c
+1
-1
drivers/s390/cio/cmf.c
+24
-13
drivers/s390/cio/device.c
+24
-13
drivers/s390/cio/device.c
···
1316
1316
spin_unlock_irqrestore(&recovery_lock, flags);
1317
1317
}
1318
1318
1319
-
static int purge_fn(struct device *dev, void *data)
1319
+
static int purge_fn(struct subchannel *sch, void *data)
1320
1320
{
1321
-
struct ccw_device *cdev = to_ccwdev(dev);
1322
-
struct ccw_dev_id *id = &cdev->private->dev_id;
1323
-
struct subchannel *sch = to_subchannel(cdev->dev.parent);
1321
+
struct ccw_device *cdev;
1324
1322
1325
-
spin_lock_irq(cdev->ccwlock);
1326
-
if (is_blacklisted(id->ssid, id->devno) &&
1327
-
(cdev->private->state == DEV_STATE_OFFLINE) &&
1328
-
(atomic_cmpxchg(&cdev->private->onoff, 0, 1) == 0)) {
1329
-
CIO_MSG_EVENT(3, "ccw: purging 0.%x.%04x\n", id->ssid,
1330
-
id->devno);
1323
+
spin_lock_irq(&sch->lock);
1324
+
if (sch->st != SUBCHANNEL_TYPE_IO || !sch->schib.pmcw.dnv)
1325
+
goto unlock;
1326
+
1327
+
if (!is_blacklisted(sch->schid.ssid, sch->schib.pmcw.dev))
1328
+
goto unlock;
1329
+
1330
+
cdev = sch_get_cdev(sch);
1331
+
if (cdev) {
1332
+
if (cdev->private->state != DEV_STATE_OFFLINE)
1333
+
goto unlock;
1334
+
1335
+
if (atomic_cmpxchg(&cdev->private->onoff, 0, 1) != 0)
1336
+
goto unlock;
1331
1337
ccw_device_sched_todo(cdev, CDEV_TODO_UNREG);
1332
-
css_sched_sch_todo(sch, SCH_TODO_UNREG);
1333
1338
atomic_set(&cdev->private->onoff, 0);
1334
1339
}
1335
-
spin_unlock_irq(cdev->ccwlock);
1340
+
1341
+
css_sched_sch_todo(sch, SCH_TODO_UNREG);
1342
+
CIO_MSG_EVENT(3, "ccw: purging 0.%x.%04x%s\n", sch->schid.ssid,
1343
+
sch->schib.pmcw.dev, cdev ? "" : " (no cdev)");
1344
+
1345
+
unlock:
1346
+
spin_unlock_irq(&sch->lock);
1336
1347
/* Abort loop in case of pending signal. */
1337
1348
if (signal_pending(current))
1338
1349
return -EINTR;
···
1359
1348
int ccw_purge_blacklisted(void)
1360
1349
{
1361
1350
CIO_MSG_EVENT(2, "ccw: purging blacklisted devices\n");
1362
-
bus_for_each_dev(&ccw_bus_type, NULL, NULL, purge_fn);
1351
+
for_each_subchannel_staged(purge_fn, NULL, NULL);
1363
1352
return 0;
1364
1353
}
1365
1354
+3
-4
drivers/s390/cio/ioasm.c
+3
-4
drivers/s390/cio/ioasm.c
···
253
253
asm volatile(
254
254
" lgr 1,%[r1]\n"
255
255
" xsch\n"
256
-
" ipm %[cc]\n"
257
-
" srl %[cc],28\n"
258
-
: [cc] "=&d" (ccode)
256
+
CC_IPM(cc)
257
+
: CC_OUT(cc, ccode)
259
258
: [r1] "d" (r1)
260
-
: "cc", "1");
259
+
: CC_CLOBBER_LIST("1"));
261
260
return CC_TRANSFORM(ccode);
262
261
}
263
262