Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:
"Two bugfixes, one v4.16 regression fix, and two documentation fixes"
* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: designware: Consider SCL GPIO optional
i2c: busses: i2c-sirf: Fix spelling: "formular" -> "formula".
i2c: bcm2835: Set up the rising/falling edge delays
i2c: i801: Add missing documentation entries for Braswell and Kaby Lake
i2c: designware: must wait for enable
+29
-5
+2
Documentation/i2c/busses/i2c-i801
+2
Documentation/i2c/busses/i2c-i801
···
28
28
* Intel Wildcat Point (PCH)
29
29
* Intel Wildcat Point-LP (PCH)
30
30
* Intel BayTrail (SOC)
31
+
* Intel Braswell (SOC)
31
32
* Intel Sunrise Point-H (PCH)
32
33
* Intel Sunrise Point-LP (PCH)
34
+
* Intel Kaby Lake-H (PCH)
33
35
* Intel DNV (SOC)
34
36
* Intel Broxton (SOC)
35
37
* Intel Lewisburg (PCH)
+2
drivers/i2c/busses/Kconfig
+2
drivers/i2c/busses/Kconfig
+20
-1
drivers/i2c/busses/i2c-bcm2835.c
+20
-1
drivers/i2c/busses/i2c-bcm2835.c
···
50
50
#define BCM2835_I2C_S_CLKT BIT(9)
51
51
#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
52
52
53
+
#define BCM2835_I2C_FEDL_SHIFT 16
54
+
#define BCM2835_I2C_REDL_SHIFT 0
55
+
53
56
#define BCM2835_I2C_CDIV_MIN 0x0002
54
57
#define BCM2835_I2C_CDIV_MAX 0xFFFE
55
58
···
84
81
85
82
static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
86
83
{
87
-
u32 divider;
84
+
u32 divider, redl, fedl;
88
85
89
86
divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
90
87
i2c_dev->bus_clk_rate);
···
103
100
104
101
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
105
102
103
+
/*
104
+
* Number of core clocks to wait after falling edge before
105
+
* outputting the next data bit. Note that both FEDL and REDL
106
+
* can't be greater than CDIV/2.
107
+
*/
108
+
fedl = max(divider / 16, 1u);
109
+
110
+
/*
111
+
* Number of core clocks to wait after rising edge before
112
+
* sampling the next incoming data bit.
113
+
*/
114
+
redl = max(divider / 4, 1u);
115
+
116
+
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
117
+
(fedl << BCM2835_I2C_FEDL_SHIFT) |
118
+
(redl << BCM2835_I2C_REDL_SHIFT));
106
119
return 0;
107
120
}
108
121
+2
-2
drivers/i2c/busses/i2c-designware-master.c
+2
-2
drivers/i2c/busses/i2c-designware-master.c
···
209
209
i2c_dw_disable_int(dev);
210
210
211
211
/* Enable the adapter */
212
-
__i2c_dw_enable(dev, true);
212
+
__i2c_dw_enable_and_wait(dev, true);
213
213
214
214
/* Clear and enable interrupts */
215
215
dw_readl(dev, DW_IC_CLR_INTR);
···
644
644
gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
645
645
if (IS_ERR(gpio)) {
646
646
r = PTR_ERR(gpio);
647
-
if (r == -ENOENT)
647
+
if (r == -ENOENT || r == -ENOSYS)
648
648
return 0;
649
649
return r;
650
650
}
+1
drivers/i2c/busses/i2c-i801.c
+1
drivers/i2c/busses/i2c-i801.c
···
58
58
* Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59
59
* Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60
60
* BayTrail (SOC) 0x0f12 32 hard yes yes yes
61
+
* Braswell (SOC) 0x2292 32 hard yes yes yes
61
62
* Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62
63
* Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63
64
* DNV (SOC) 0x19df 32 hard yes yes yes
+2
-2
drivers/i2c/busses/i2c-sirf.c
+2
-2
drivers/i2c/busses/i2c-sirf.c
···
341
341
platform_set_drvdata(pdev, adap);
342
342
init_completion(&siic->done);
343
343
344
-
/* Controller Initalisation */
344
+
/* Controller initialisation */
345
345
346
346
writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
347
347
while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
···
369
369
* but they start to affect the speed when clock is set to faster
370
370
* frequencies.
371
371
* Through the actual tests, use the different user_div value(which
372
-
* in the divider formular 'Fio / (Fi2c * user_div)') to adapt
372
+
* in the divider formula 'Fio / (Fi2c * user_div)') to adapt
373
373
* the different ranges of i2c bus clock frequency, to make the SCL
374
374
* more accurate.
375
375
*/