Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sc7280: convert to dynamic IDs
Stop using fixed and IDs and covert the platform to use dynamic IDs for
the interconnect. This gives more flexibility and also allows us to drop
the .num_links member, saving from possible errors related to it being
not set or set incorrectly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-rework-icc-v3-2-0575304c9624@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Georgi Djakov
93938e0c
fb6f1aae
+287
-496
+287
-342
drivers/interconnect/qcom/sc7280.c
+287
-342
drivers/interconnect/qcom/sc7280.c
···
15
15
16
16
#include "bcm-voter.h"
17
17
#include "icc-rpmh.h"
18
-
#include "sc7280.h"
18
+
19
+
static struct qcom_icc_node qhm_qspi;
20
+
static struct qcom_icc_node qhm_qup0;
21
+
static struct qcom_icc_node qhm_qup1;
22
+
static struct qcom_icc_node qnm_a1noc_cfg;
23
+
static struct qcom_icc_node xm_sdc1;
24
+
static struct qcom_icc_node xm_sdc2;
25
+
static struct qcom_icc_node xm_sdc4;
26
+
static struct qcom_icc_node xm_ufs_mem;
27
+
static struct qcom_icc_node xm_usb2;
28
+
static struct qcom_icc_node xm_usb3_0;
29
+
static struct qcom_icc_node qhm_qdss_bam;
30
+
static struct qcom_icc_node qnm_a2noc_cfg;
31
+
static struct qcom_icc_node qnm_cnoc_datapath;
32
+
static struct qcom_icc_node qxm_crypto;
33
+
static struct qcom_icc_node qxm_ipa;
34
+
static struct qcom_icc_node xm_pcie3_0;
35
+
static struct qcom_icc_node xm_pcie3_1;
36
+
static struct qcom_icc_node xm_qdss_etr;
37
+
static struct qcom_icc_node qup0_core_master;
38
+
static struct qcom_icc_node qup1_core_master;
39
+
static struct qcom_icc_node qnm_cnoc3_cnoc2;
40
+
static struct qcom_icc_node xm_qdss_dap;
41
+
static struct qcom_icc_node qnm_cnoc2_cnoc3;
42
+
static struct qcom_icc_node qnm_gemnoc_cnoc;
43
+
static struct qcom_icc_node qnm_gemnoc_pcie;
44
+
static struct qcom_icc_node qnm_cnoc_dc_noc;
45
+
static struct qcom_icc_node alm_gpu_tcu;
46
+
static struct qcom_icc_node alm_sys_tcu;
47
+
static struct qcom_icc_node chm_apps;
48
+
static struct qcom_icc_node qnm_cmpnoc;
49
+
static struct qcom_icc_node qnm_gemnoc_cfg;
50
+
static struct qcom_icc_node qnm_gpu;
51
+
static struct qcom_icc_node qnm_mnoc_hf;
52
+
static struct qcom_icc_node qnm_mnoc_sf;
53
+
static struct qcom_icc_node qnm_pcie;
54
+
static struct qcom_icc_node qnm_snoc_gc;
55
+
static struct qcom_icc_node qnm_snoc_sf;
56
+
static struct qcom_icc_node qhm_config_noc;
57
+
static struct qcom_icc_node llcc_mc;
58
+
static struct qcom_icc_node qnm_mnoc_cfg;
59
+
static struct qcom_icc_node qnm_video0;
60
+
static struct qcom_icc_node qnm_video_cpu;
61
+
static struct qcom_icc_node qxm_camnoc_hf;
62
+
static struct qcom_icc_node qxm_camnoc_icp;
63
+
static struct qcom_icc_node qxm_camnoc_sf;
64
+
static struct qcom_icc_node qxm_mdp0;
65
+
static struct qcom_icc_node qhm_nsp_noc_config;
66
+
static struct qcom_icc_node qxm_nsp;
67
+
static struct qcom_icc_node qnm_aggre1_noc;
68
+
static struct qcom_icc_node qnm_aggre2_noc;
69
+
static struct qcom_icc_node qnm_snoc_cfg;
70
+
static struct qcom_icc_node qxm_pimem;
71
+
static struct qcom_icc_node xm_gic;
72
+
static struct qcom_icc_node qns_a1noc_snoc;
73
+
static struct qcom_icc_node srvc_aggre1_noc;
74
+
static struct qcom_icc_node qns_a2noc_snoc;
75
+
static struct qcom_icc_node qns_pcie_mem_noc;
76
+
static struct qcom_icc_node srvc_aggre2_noc;
77
+
static struct qcom_icc_node qup0_core_slave;
78
+
static struct qcom_icc_node qup1_core_slave;
79
+
static struct qcom_icc_node qhs_ahb2phy0;
80
+
static struct qcom_icc_node qhs_ahb2phy1;
81
+
static struct qcom_icc_node qhs_camera_cfg;
82
+
static struct qcom_icc_node qhs_clk_ctl;
83
+
static struct qcom_icc_node qhs_compute_cfg;
84
+
static struct qcom_icc_node qhs_cpr_cx;
85
+
static struct qcom_icc_node qhs_cpr_mx;
86
+
static struct qcom_icc_node qhs_crypto0_cfg;
87
+
static struct qcom_icc_node qhs_cx_rdpm;
88
+
static struct qcom_icc_node qhs_dcc_cfg;
89
+
static struct qcom_icc_node qhs_display_cfg;
90
+
static struct qcom_icc_node qhs_gpuss_cfg;
91
+
static struct qcom_icc_node qhs_hwkm;
92
+
static struct qcom_icc_node qhs_imem_cfg;
93
+
static struct qcom_icc_node qhs_ipa;
94
+
static struct qcom_icc_node qhs_ipc_router;
95
+
static struct qcom_icc_node qhs_lpass_cfg;
96
+
static struct qcom_icc_node qhs_mss_cfg;
97
+
static struct qcom_icc_node qhs_mx_rdpm;
98
+
static struct qcom_icc_node qhs_pcie0_cfg;
99
+
static struct qcom_icc_node qhs_pcie1_cfg;
100
+
static struct qcom_icc_node qhs_pdm;
101
+
static struct qcom_icc_node qhs_pimem_cfg;
102
+
static struct qcom_icc_node qhs_pka_wrapper_cfg;
103
+
static struct qcom_icc_node qhs_pmu_wrapper_cfg;
104
+
static struct qcom_icc_node qhs_qdss_cfg;
105
+
static struct qcom_icc_node qhs_qspi;
106
+
static struct qcom_icc_node qhs_qup0;
107
+
static struct qcom_icc_node qhs_qup1;
108
+
static struct qcom_icc_node qhs_sdc1;
109
+
static struct qcom_icc_node qhs_sdc2;
110
+
static struct qcom_icc_node qhs_sdc4;
111
+
static struct qcom_icc_node qhs_security;
112
+
static struct qcom_icc_node qhs_tcsr;
113
+
static struct qcom_icc_node qhs_tlmm;
114
+
static struct qcom_icc_node qhs_ufs_mem_cfg;
115
+
static struct qcom_icc_node qhs_usb2;
116
+
static struct qcom_icc_node qhs_usb3_0;
117
+
static struct qcom_icc_node qhs_venus_cfg;
118
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg;
119
+
static struct qcom_icc_node qns_a1_noc_cfg;
120
+
static struct qcom_icc_node qns_a2_noc_cfg;
121
+
static struct qcom_icc_node qns_cnoc2_cnoc3;
122
+
static struct qcom_icc_node qns_mnoc_cfg;
123
+
static struct qcom_icc_node qns_snoc_cfg;
124
+
static struct qcom_icc_node qhs_aoss;
125
+
static struct qcom_icc_node qhs_apss;
126
+
static struct qcom_icc_node qns_cnoc3_cnoc2;
127
+
static struct qcom_icc_node qns_cnoc_a2noc;
128
+
static struct qcom_icc_node qns_ddrss_cfg;
129
+
static struct qcom_icc_node qxs_boot_imem;
130
+
static struct qcom_icc_node qxs_imem;
131
+
static struct qcom_icc_node qxs_pimem;
132
+
static struct qcom_icc_node xs_pcie_0;
133
+
static struct qcom_icc_node xs_pcie_1;
134
+
static struct qcom_icc_node xs_qdss_stm;
135
+
static struct qcom_icc_node xs_sys_tcu_cfg;
136
+
static struct qcom_icc_node qhs_llcc;
137
+
static struct qcom_icc_node qns_gemnoc;
138
+
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
139
+
static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
140
+
static struct qcom_icc_node qns_gem_noc_cnoc;
141
+
static struct qcom_icc_node qns_llcc;
142
+
static struct qcom_icc_node qns_pcie;
143
+
static struct qcom_icc_node srvc_even_gemnoc;
144
+
static struct qcom_icc_node srvc_odd_gemnoc;
145
+
static struct qcom_icc_node srvc_sys_gemnoc;
146
+
static struct qcom_icc_node qhs_lpass_core;
147
+
static struct qcom_icc_node qhs_lpass_lpi;
148
+
static struct qcom_icc_node qhs_lpass_mpu;
149
+
static struct qcom_icc_node qhs_lpass_top;
150
+
static struct qcom_icc_node srvc_niu_aml_noc;
151
+
static struct qcom_icc_node srvc_niu_lpass_agnoc;
152
+
static struct qcom_icc_node ebi;
153
+
static struct qcom_icc_node qns_mem_noc_hf;
154
+
static struct qcom_icc_node qns_mem_noc_sf;
155
+
static struct qcom_icc_node srvc_mnoc;
156
+
static struct qcom_icc_node qns_nsp_gemnoc;
157
+
static struct qcom_icc_node service_nsp_noc;
158
+
static struct qcom_icc_node qns_gemnoc_gc;
159
+
static struct qcom_icc_node qns_gemnoc_sf;
160
+
static struct qcom_icc_node srvc_snoc;
19
161
20
162
static struct qcom_icc_node qhm_qspi = {
21
163
.name = "qhm_qspi",
22
-
.id = SC7280_MASTER_QSPI_0,
23
164
.channels = 1,
24
165
.buswidth = 4,
25
166
.qosbox = &(const struct qcom_icc_qosbox) {
···
170
29
.urg_fwd = 0,
171
30
},
172
31
.num_links = 1,
173
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
32
+
.link_nodes = { &qns_a1noc_snoc },
174
33
};
175
34
176
35
static struct qcom_icc_node qhm_qup0 = {
177
36
.name = "qhm_qup0",
178
-
.id = SC7280_MASTER_QUP_0,
179
37
.channels = 1,
180
38
.buswidth = 4,
181
39
.qosbox = &(const struct qcom_icc_qosbox) {
···
184
44
.urg_fwd = 0,
185
45
},
186
46
.num_links = 1,
187
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
47
+
.link_nodes = { &qns_a1noc_snoc },
188
48
};
189
49
190
50
static struct qcom_icc_node qhm_qup1 = {
191
51
.name = "qhm_qup1",
192
-
.id = SC7280_MASTER_QUP_1,
193
52
.channels = 1,
194
53
.buswidth = 4,
195
54
.qosbox = &(const struct qcom_icc_qosbox) {
···
198
59
.urg_fwd = 0,
199
60
},
200
61
.num_links = 1,
201
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
62
+
.link_nodes = { &qns_a1noc_snoc },
202
63
};
203
64
204
65
static struct qcom_icc_node qnm_a1noc_cfg = {
205
66
.name = "qnm_a1noc_cfg",
206
-
.id = SC7280_MASTER_A1NOC_CFG,
207
67
.channels = 1,
208
68
.buswidth = 4,
209
69
.num_links = 1,
210
-
.links = { SC7280_SLAVE_SERVICE_A1NOC },
70
+
.link_nodes = { &srvc_aggre1_noc },
211
71
};
212
72
213
73
static struct qcom_icc_node xm_sdc1 = {
214
74
.name = "xm_sdc1",
215
-
.id = SC7280_MASTER_SDCC_1,
216
75
.channels = 1,
217
76
.buswidth = 8,
218
77
.qosbox = &(const struct qcom_icc_qosbox) {
···
220
83
.urg_fwd = 0,
221
84
},
222
85
.num_links = 1,
223
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
86
+
.link_nodes = { &qns_a1noc_snoc },
224
87
};
225
88
226
89
static struct qcom_icc_node xm_sdc2 = {
227
90
.name = "xm_sdc2",
228
-
.id = SC7280_MASTER_SDCC_2,
229
91
.channels = 1,
230
92
.buswidth = 8,
231
93
.qosbox = &(const struct qcom_icc_qosbox) {
···
234
98
.urg_fwd = 0,
235
99
},
236
100
.num_links = 1,
237
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
101
+
.link_nodes = { &qns_a1noc_snoc },
238
102
};
239
103
240
104
static struct qcom_icc_node xm_sdc4 = {
241
105
.name = "xm_sdc4",
242
-
.id = SC7280_MASTER_SDCC_4,
243
106
.channels = 1,
244
107
.buswidth = 8,
245
108
.qosbox = &(const struct qcom_icc_qosbox) {
···
248
113
.urg_fwd = 0,
249
114
},
250
115
.num_links = 1,
251
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
116
+
.link_nodes = { &qns_a1noc_snoc },
252
117
};
253
118
254
119
static struct qcom_icc_node xm_ufs_mem = {
255
120
.name = "xm_ufs_mem",
256
-
.id = SC7280_MASTER_UFS_MEM,
257
121
.channels = 1,
258
122
.buswidth = 8,
259
123
.qosbox = &(const struct qcom_icc_qosbox) {
···
262
128
.urg_fwd = 0,
263
129
},
264
130
.num_links = 1,
265
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
131
+
.link_nodes = { &qns_a1noc_snoc },
266
132
};
267
133
268
134
static struct qcom_icc_node xm_usb2 = {
269
135
.name = "xm_usb2",
270
-
.id = SC7280_MASTER_USB2,
271
136
.channels = 1,
272
137
.buswidth = 8,
273
138
.num_links = 1,
274
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
139
+
.link_nodes = { &qns_a1noc_snoc },
275
140
};
276
141
277
142
static struct qcom_icc_node xm_usb3_0 = {
278
143
.name = "xm_usb3_0",
279
-
.id = SC7280_MASTER_USB3_0,
280
144
.channels = 1,
281
145
.buswidth = 8,
282
146
.qosbox = &(const struct qcom_icc_qosbox) {
···
284
152
.urg_fwd = 0,
285
153
},
286
154
.num_links = 1,
287
-
.links = { SC7280_SLAVE_A1NOC_SNOC },
155
+
.link_nodes = { &qns_a1noc_snoc },
288
156
};
289
157
290
158
static struct qcom_icc_node qhm_qdss_bam = {
291
159
.name = "qhm_qdss_bam",
292
-
.id = SC7280_MASTER_QDSS_BAM,
293
160
.channels = 1,
294
161
.buswidth = 4,
295
162
.qosbox = &(const struct qcom_icc_qosbox) {
···
298
167
.urg_fwd = 0,
299
168
},
300
169
.num_links = 1,
301
-
.links = { SC7280_SLAVE_A2NOC_SNOC },
170
+
.link_nodes = { &qns_a2noc_snoc },
302
171
};
303
172
304
173
static struct qcom_icc_node qnm_a2noc_cfg = {
305
174
.name = "qnm_a2noc_cfg",
306
-
.id = SC7280_MASTER_A2NOC_CFG,
307
175
.channels = 1,
308
176
.buswidth = 4,
309
177
.num_links = 1,
310
-
.links = { SC7280_SLAVE_SERVICE_A2NOC },
178
+
.link_nodes = { &srvc_aggre2_noc },
311
179
};
312
180
313
181
static struct qcom_icc_node qnm_cnoc_datapath = {
314
182
.name = "qnm_cnoc_datapath",
315
-
.id = SC7280_MASTER_CNOC_A2NOC,
316
183
.channels = 1,
317
184
.buswidth = 8,
318
185
.qosbox = &(const struct qcom_icc_qosbox) {
···
320
191
.urg_fwd = 0,
321
192
},
322
193
.num_links = 1,
323
-
.links = { SC7280_SLAVE_A2NOC_SNOC },
194
+
.link_nodes = { &qns_a2noc_snoc },
324
195
};
325
196
326
197
static struct qcom_icc_node qxm_crypto = {
327
198
.name = "qxm_crypto",
328
-
.id = SC7280_MASTER_CRYPTO,
329
199
.channels = 1,
330
200
.buswidth = 8,
331
201
.qosbox = &(const struct qcom_icc_qosbox) {
···
334
206
.urg_fwd = 0,
335
207
},
336
208
.num_links = 1,
337
-
.links = { SC7280_SLAVE_A2NOC_SNOC },
209
+
.link_nodes = { &qns_a2noc_snoc },
338
210
};
339
211
340
212
static struct qcom_icc_node qxm_ipa = {
341
213
.name = "qxm_ipa",
342
-
.id = SC7280_MASTER_IPA,
343
214
.channels = 1,
344
215
.buswidth = 8,
345
216
.qosbox = &(const struct qcom_icc_qosbox) {
···
348
221
.urg_fwd = 0,
349
222
},
350
223
.num_links = 1,
351
-
.links = { SC7280_SLAVE_A2NOC_SNOC },
224
+
.link_nodes = { &qns_a2noc_snoc },
352
225
};
353
226
354
227
static struct qcom_icc_node xm_pcie3_0 = {
355
228
.name = "xm_pcie3_0",
356
-
.id = SC7280_MASTER_PCIE_0,
357
229
.channels = 1,
358
230
.buswidth = 8,
359
231
.num_links = 1,
360
-
.links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
232
+
.link_nodes = { &qns_pcie_mem_noc },
361
233
};
362
234
363
235
static struct qcom_icc_node xm_pcie3_1 = {
364
236
.name = "xm_pcie3_1",
365
-
.id = SC7280_MASTER_PCIE_1,
366
237
.channels = 1,
367
238
.buswidth = 8,
368
239
.num_links = 1,
369
-
.links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
240
+
.link_nodes = { &qns_pcie_mem_noc },
370
241
};
371
242
372
243
static struct qcom_icc_node xm_qdss_etr = {
373
244
.name = "xm_qdss_etr",
374
-
.id = SC7280_MASTER_QDSS_ETR,
375
245
.channels = 1,
376
246
.buswidth = 8,
377
247
.qosbox = &(const struct qcom_icc_qosbox) {
···
378
254
.urg_fwd = 0,
379
255
},
380
256
.num_links = 1,
381
-
.links = { SC7280_SLAVE_A2NOC_SNOC },
257
+
.link_nodes = { &qns_a2noc_snoc },
382
258
};
383
259
384
260
static struct qcom_icc_node qup0_core_master = {
385
261
.name = "qup0_core_master",
386
-
.id = SC7280_MASTER_QUP_CORE_0,
387
262
.channels = 1,
388
263
.buswidth = 4,
389
264
.num_links = 1,
390
-
.links = { SC7280_SLAVE_QUP_CORE_0 },
265
+
.link_nodes = { &qup0_core_slave },
391
266
};
392
267
393
268
static struct qcom_icc_node qup1_core_master = {
394
269
.name = "qup1_core_master",
395
-
.id = SC7280_MASTER_QUP_CORE_1,
396
270
.channels = 1,
397
271
.buswidth = 4,
398
272
.num_links = 1,
399
-
.links = { SC7280_SLAVE_QUP_CORE_1 },
273
+
.link_nodes = { &qup1_core_slave },
400
274
};
401
275
402
276
static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
403
277
.name = "qnm_cnoc3_cnoc2",
404
-
.id = SC7280_MASTER_CNOC3_CNOC2,
405
278
.channels = 1,
406
279
.buswidth = 8,
407
280
.num_links = 44,
408
-
.links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
409
-
SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
410
-
SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
411
-
SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
412
-
SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
413
-
SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
414
-
SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
415
-
SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
416
-
SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
417
-
SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
418
-
SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
419
-
SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
420
-
SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
421
-
SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
422
-
SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
423
-
SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
424
-
SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
425
-
SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
426
-
SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
427
-
SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
428
-
SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
429
-
SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
281
+
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
282
+
&qhs_camera_cfg, &qhs_clk_ctl,
283
+
&qhs_compute_cfg, &qhs_cpr_cx,
284
+
&qhs_cpr_mx, &qhs_crypto0_cfg,
285
+
&qhs_cx_rdpm, &qhs_dcc_cfg,
286
+
&qhs_display_cfg, &qhs_gpuss_cfg,
287
+
&qhs_hwkm, &qhs_imem_cfg,
288
+
&qhs_ipa, &qhs_ipc_router,
289
+
&qhs_lpass_cfg, &qhs_mss_cfg,
290
+
&qhs_mx_rdpm, &qhs_pcie0_cfg,
291
+
&qhs_pcie1_cfg, &qhs_pdm,
292
+
&qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
293
+
&qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
294
+
&qhs_qspi, &qhs_qup0,
295
+
&qhs_qup1, &qhs_sdc1,
296
+
&qhs_sdc2, &qhs_sdc4,
297
+
&qhs_security, &qhs_tcsr,
298
+
&qhs_tlmm, &qhs_ufs_mem_cfg,
299
+
&qhs_usb2, &qhs_usb3_0,
300
+
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
301
+
&qns_a1_noc_cfg, &qns_a2_noc_cfg,
302
+
&qns_mnoc_cfg, &qns_snoc_cfg },
430
303
};
431
304
432
305
static struct qcom_icc_node xm_qdss_dap = {
433
306
.name = "xm_qdss_dap",
434
-
.id = SC7280_MASTER_QDSS_DAP,
435
307
.channels = 1,
436
308
.buswidth = 8,
437
309
.num_links = 45,
438
-
.links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
439
-
SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
440
-
SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
441
-
SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
442
-
SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
443
-
SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
444
-
SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
445
-
SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
446
-
SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
447
-
SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
448
-
SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
449
-
SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
450
-
SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
451
-
SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
452
-
SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
453
-
SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
454
-
SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
455
-
SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
456
-
SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
457
-
SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
458
-
SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
459
-
SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
460
-
SC7280_SLAVE_SNOC_CFG },
310
+
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
311
+
&qhs_camera_cfg, &qhs_clk_ctl,
312
+
&qhs_compute_cfg, &qhs_cpr_cx,
313
+
&qhs_cpr_mx, &qhs_crypto0_cfg,
314
+
&qhs_cx_rdpm, &qhs_dcc_cfg,
315
+
&qhs_display_cfg, &qhs_gpuss_cfg,
316
+
&qhs_hwkm, &qhs_imem_cfg,
317
+
&qhs_ipa, &qhs_ipc_router,
318
+
&qhs_lpass_cfg, &qhs_mss_cfg,
319
+
&qhs_mx_rdpm, &qhs_pcie0_cfg,
320
+
&qhs_pcie1_cfg, &qhs_pdm,
321
+
&qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
322
+
&qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
323
+
&qhs_qspi, &qhs_qup0,
324
+
&qhs_qup1, &qhs_sdc1,
325
+
&qhs_sdc2, &qhs_sdc4,
326
+
&qhs_security, &qhs_tcsr,
327
+
&qhs_tlmm, &qhs_ufs_mem_cfg,
328
+
&qhs_usb2, &qhs_usb3_0,
329
+
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
330
+
&qns_a1_noc_cfg, &qns_a2_noc_cfg,
331
+
&qns_cnoc2_cnoc3, &qns_mnoc_cfg,
332
+
&qns_snoc_cfg },
461
333
};
462
334
463
335
static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
464
336
.name = "qnm_cnoc2_cnoc3",
465
-
.id = SC7280_MASTER_CNOC2_CNOC3,
466
337
.channels = 1,
467
338
.buswidth = 8,
468
339
.num_links = 9,
469
-
.links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
470
-
SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
471
-
SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
472
-
SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
473
-
SC7280_SLAVE_TCU },
340
+
.link_nodes = { &qhs_aoss, &qhs_apss,
341
+
&qns_cnoc_a2noc, &qns_ddrss_cfg,
342
+
&qxs_boot_imem, &qxs_imem,
343
+
&qxs_pimem, &xs_qdss_stm,
344
+
&xs_sys_tcu_cfg },
474
345
};
475
346
476
347
static struct qcom_icc_node qnm_gemnoc_cnoc = {
477
348
.name = "qnm_gemnoc_cnoc",
478
-
.id = SC7280_MASTER_GEM_NOC_CNOC,
479
349
.channels = 1,
480
350
.buswidth = 16,
481
351
.num_links = 9,
482
-
.links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
483
-
SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
484
-
SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
485
-
SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
486
-
SC7280_SLAVE_TCU },
352
+
.link_nodes = { &qhs_aoss, &qhs_apss,
353
+
&qns_cnoc3_cnoc2, &qns_ddrss_cfg,
354
+
&qxs_boot_imem, &qxs_imem,
355
+
&qxs_pimem, &xs_qdss_stm,
356
+
&xs_sys_tcu_cfg },
487
357
};
488
358
489
359
static struct qcom_icc_node qnm_gemnoc_pcie = {
490
360
.name = "qnm_gemnoc_pcie",
491
-
.id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
492
361
.channels = 1,
493
362
.buswidth = 8,
494
363
.num_links = 2,
495
-
.links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
364
+
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
496
365
};
497
366
498
367
static struct qcom_icc_node qnm_cnoc_dc_noc = {
499
368
.name = "qnm_cnoc_dc_noc",
500
-
.id = SC7280_MASTER_CNOC_DC_NOC,
501
369
.channels = 1,
502
370
.buswidth = 4,
503
371
.num_links = 2,
504
-
.links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
372
+
.link_nodes = { &qhs_llcc, &qns_gemnoc },
505
373
};
506
374
507
375
static struct qcom_icc_node alm_gpu_tcu = {
508
376
.name = "alm_gpu_tcu",
509
-
.id = SC7280_MASTER_GPU_TCU,
510
377
.channels = 1,
511
378
.buswidth = 8,
512
379
.qosbox = &(const struct qcom_icc_qosbox) {
···
507
392
.urg_fwd = 0,
508
393
},
509
394
.num_links = 2,
510
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
395
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
511
396
};
512
397
513
398
static struct qcom_icc_node alm_sys_tcu = {
514
399
.name = "alm_sys_tcu",
515
-
.id = SC7280_MASTER_SYS_TCU,
516
400
.channels = 1,
517
401
.buswidth = 8,
518
402
.qosbox = &(const struct qcom_icc_qosbox) {
···
521
407
.urg_fwd = 0,
522
408
},
523
409
.num_links = 2,
524
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
410
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
525
411
};
526
412
527
413
static struct qcom_icc_node chm_apps = {
528
414
.name = "chm_apps",
529
-
.id = SC7280_MASTER_APPSS_PROC,
530
415
.channels = 1,
531
416
.buswidth = 32,
532
417
.num_links = 3,
533
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
534
-
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
418
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
419
+
&qns_pcie },
535
420
};
536
421
537
422
static struct qcom_icc_node qnm_cmpnoc = {
538
423
.name = "qnm_cmpnoc",
539
-
.id = SC7280_MASTER_COMPUTE_NOC,
540
424
.channels = 2,
541
425
.buswidth = 32,
542
426
.qosbox = &(const struct qcom_icc_qosbox) {
···
544
432
.urg_fwd = 1,
545
433
},
546
434
.num_links = 2,
547
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
435
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
548
436
};
549
437
550
438
static struct qcom_icc_node qnm_gemnoc_cfg = {
551
439
.name = "qnm_gemnoc_cfg",
552
-
.id = SC7280_MASTER_GEM_NOC_CFG,
553
440
.channels = 1,
554
441
.buswidth = 4,
555
442
.num_links = 5,
556
-
.links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
557
-
SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
558
-
SC7280_SLAVE_SERVICE_GEM_NOC },
443
+
.link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg,
444
+
&srvc_even_gemnoc, &srvc_odd_gemnoc,
445
+
&srvc_sys_gemnoc },
559
446
};
560
447
561
448
static struct qcom_icc_node qnm_gpu = {
562
449
.name = "qnm_gpu",
563
-
.id = SC7280_MASTER_GFX3D,
564
450
.channels = 2,
565
451
.buswidth = 32,
566
452
.qosbox = &(const struct qcom_icc_qosbox) {
···
568
458
.urg_fwd = 0,
569
459
},
570
460
.num_links = 2,
571
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
461
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
572
462
};
573
463
574
464
static struct qcom_icc_node qnm_mnoc_hf = {
575
465
.name = "qnm_mnoc_hf",
576
-
.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
577
466
.channels = 2,
578
467
.buswidth = 32,
579
468
.qosbox = &(const struct qcom_icc_qosbox) {
···
582
473
.urg_fwd = 1,
583
474
},
584
475
.num_links = 1,
585
-
.links = { SC7280_SLAVE_LLCC },
476
+
.link_nodes = { &qns_llcc },
586
477
};
587
478
588
479
static struct qcom_icc_node qnm_mnoc_sf = {
589
480
.name = "qnm_mnoc_sf",
590
-
.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
591
481
.channels = 1,
592
482
.buswidth = 32,
593
483
.qosbox = &(const struct qcom_icc_qosbox) {
···
596
488
.urg_fwd = 1,
597
489
},
598
490
.num_links = 2,
599
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
491
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
600
492
};
601
493
602
494
static struct qcom_icc_node qnm_pcie = {
603
495
.name = "qnm_pcie",
604
-
.id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
605
496
.channels = 1,
606
497
.buswidth = 16,
607
498
.num_links = 2,
608
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
499
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
609
500
};
610
501
611
502
static struct qcom_icc_node qnm_snoc_gc = {
612
503
.name = "qnm_snoc_gc",
613
-
.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
614
504
.channels = 1,
615
505
.buswidth = 8,
616
506
.qosbox = &(const struct qcom_icc_qosbox) {
···
618
512
.urg_fwd = 1,
619
513
},
620
514
.num_links = 1,
621
-
.links = { SC7280_SLAVE_LLCC },
515
+
.link_nodes = { &qns_llcc },
622
516
};
623
517
624
518
static struct qcom_icc_node qnm_snoc_sf = {
625
519
.name = "qnm_snoc_sf",
626
-
.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
627
520
.channels = 1,
628
521
.buswidth = 16,
629
522
.qosbox = &(const struct qcom_icc_qosbox) {
···
632
527
.urg_fwd = 1,
633
528
},
634
529
.num_links = 3,
635
-
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
636
-
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
530
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
531
+
&qns_pcie },
637
532
};
638
533
639
534
static struct qcom_icc_node qhm_config_noc = {
640
535
.name = "qhm_config_noc",
641
-
.id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
642
536
.channels = 1,
643
537
.buswidth = 4,
644
538
.num_links = 6,
645
-
.links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
646
-
SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
647
-
SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
539
+
.link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
540
+
&qhs_lpass_mpu, &qhs_lpass_top,
541
+
&srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
648
542
};
649
543
650
544
static struct qcom_icc_node llcc_mc = {
651
545
.name = "llcc_mc",
652
-
.id = SC7280_MASTER_LLCC,
653
546
.channels = 2,
654
547
.buswidth = 4,
655
548
.num_links = 1,
656
-
.links = { SC7280_SLAVE_EBI1 },
549
+
.link_nodes = { &ebi },
657
550
};
658
551
659
552
static struct qcom_icc_node qnm_mnoc_cfg = {
660
553
.name = "qnm_mnoc_cfg",
661
-
.id = SC7280_MASTER_CNOC_MNOC_CFG,
662
554
.channels = 1,
663
555
.buswidth = 4,
664
556
.num_links = 1,
665
-
.links = { SC7280_SLAVE_SERVICE_MNOC },
557
+
.link_nodes = { &srvc_mnoc },
666
558
};
667
559
668
560
static struct qcom_icc_node qnm_video0 = {
669
561
.name = "qnm_video0",
670
-
.id = SC7280_MASTER_VIDEO_P0,
671
562
.channels = 1,
672
563
.buswidth = 32,
673
564
.qosbox = &(const struct qcom_icc_qosbox) {
···
673
572
.urg_fwd = 1,
674
573
},
675
574
.num_links = 1,
676
-
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
575
+
.link_nodes = { &qns_mem_noc_sf },
677
576
};
678
577
679
578
static struct qcom_icc_node qnm_video_cpu = {
680
579
.name = "qnm_video_cpu",
681
-
.id = SC7280_MASTER_VIDEO_PROC,
682
580
.channels = 1,
683
581
.buswidth = 8,
684
582
.qosbox = &(const struct qcom_icc_qosbox) {
···
687
587
.urg_fwd = 1,
688
588
},
689
589
.num_links = 1,
690
-
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
590
+
.link_nodes = { &qns_mem_noc_sf },
691
591
};
692
592
693
593
static struct qcom_icc_node qxm_camnoc_hf = {
694
594
.name = "qxm_camnoc_hf",
695
-
.id = SC7280_MASTER_CAMNOC_HF,
696
595
.channels = 2,
697
596
.buswidth = 32,
698
597
.qosbox = &(const struct qcom_icc_qosbox) {
···
701
602
.urg_fwd = 1,
702
603
},
703
604
.num_links = 1,
704
-
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
605
+
.link_nodes = { &qns_mem_noc_hf },
705
606
};
706
607
707
608
static struct qcom_icc_node qxm_camnoc_icp = {
708
609
.name = "qxm_camnoc_icp",
709
-
.id = SC7280_MASTER_CAMNOC_ICP,
710
610
.channels = 1,
711
611
.buswidth = 8,
712
612
.qosbox = &(const struct qcom_icc_qosbox) {
···
715
617
.urg_fwd = 1,
716
618
},
717
619
.num_links = 1,
718
-
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
620
+
.link_nodes = { &qns_mem_noc_sf },
719
621
};
720
622
721
623
static struct qcom_icc_node qxm_camnoc_sf = {
722
624
.name = "qxm_camnoc_sf",
723
-
.id = SC7280_MASTER_CAMNOC_SF,
724
625
.channels = 1,
725
626
.buswidth = 32,
726
627
.qosbox = &(const struct qcom_icc_qosbox) {
···
729
632
.urg_fwd = 1,
730
633
},
731
634
.num_links = 1,
732
-
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
635
+
.link_nodes = { &qns_mem_noc_sf },
733
636
};
734
637
735
638
static struct qcom_icc_node qxm_mdp0 = {
736
639
.name = "qxm_mdp0",
737
-
.id = SC7280_MASTER_MDP0,
738
640
.channels = 1,
739
641
.buswidth = 32,
740
642
.qosbox = &(const struct qcom_icc_qosbox) {
···
743
647
.urg_fwd = 1,
744
648
},
745
649
.num_links = 1,
746
-
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
650
+
.link_nodes = { &qns_mem_noc_hf },
747
651
};
748
652
749
653
static struct qcom_icc_node qhm_nsp_noc_config = {
750
654
.name = "qhm_nsp_noc_config",
751
-
.id = SC7280_MASTER_CDSP_NOC_CFG,
752
655
.channels = 1,
753
656
.buswidth = 4,
754
657
.num_links = 1,
755
-
.links = { SC7280_SLAVE_SERVICE_NSP_NOC },
658
+
.link_nodes = { &service_nsp_noc },
756
659
};
757
660
758
661
static struct qcom_icc_node qxm_nsp = {
759
662
.name = "qxm_nsp",
760
-
.id = SC7280_MASTER_CDSP_PROC,
761
663
.channels = 2,
762
664
.buswidth = 32,
763
665
.num_links = 1,
764
-
.links = { SC7280_SLAVE_CDSP_MEM_NOC },
666
+
.link_nodes = { &qns_nsp_gemnoc },
765
667
};
766
668
767
669
static struct qcom_icc_node qnm_aggre1_noc = {
768
670
.name = "qnm_aggre1_noc",
769
-
.id = SC7280_MASTER_A1NOC_SNOC,
770
671
.channels = 1,
771
672
.buswidth = 16,
772
673
.num_links = 1,
773
-
.links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
674
+
.link_nodes = { &qns_gemnoc_sf },
774
675
};
775
676
776
677
static struct qcom_icc_node qnm_aggre2_noc = {
777
678
.name = "qnm_aggre2_noc",
778
-
.id = SC7280_MASTER_A2NOC_SNOC,
779
679
.channels = 1,
780
680
.buswidth = 16,
781
681
.num_links = 1,
782
-
.links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
682
+
.link_nodes = { &qns_gemnoc_sf },
783
683
};
784
684
785
685
static struct qcom_icc_node qnm_snoc_cfg = {
786
686
.name = "qnm_snoc_cfg",
787
-
.id = SC7280_MASTER_SNOC_CFG,
788
687
.channels = 1,
789
688
.buswidth = 4,
790
689
.num_links = 1,
791
-
.links = { SC7280_SLAVE_SERVICE_SNOC },
690
+
.link_nodes = { &srvc_snoc },
792
691
};
793
692
794
693
static struct qcom_icc_node qxm_pimem = {
795
694
.name = "qxm_pimem",
796
-
.id = SC7280_MASTER_PIMEM,
797
695
.channels = 1,
798
696
.buswidth = 8,
799
697
.qosbox = &(const struct qcom_icc_qosbox) {
···
797
707
.urg_fwd = 0,
798
708
},
799
709
.num_links = 1,
800
-
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
710
+
.link_nodes = { &qns_gemnoc_gc },
801
711
};
802
712
803
713
static struct qcom_icc_node xm_gic = {
804
714
.name = "xm_gic",
805
-
.id = SC7280_MASTER_GIC,
806
715
.channels = 1,
807
716
.buswidth = 8,
808
717
.qosbox = &(const struct qcom_icc_qosbox) {
···
811
722
.urg_fwd = 0,
812
723
},
813
724
.num_links = 1,
814
-
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
725
+
.link_nodes = { &qns_gemnoc_gc },
815
726
};
816
727
817
728
static struct qcom_icc_node qns_a1noc_snoc = {
818
729
.name = "qns_a1noc_snoc",
819
-
.id = SC7280_SLAVE_A1NOC_SNOC,
820
730
.channels = 1,
821
731
.buswidth = 16,
822
732
.num_links = 1,
823
-
.links = { SC7280_MASTER_A1NOC_SNOC },
733
+
.link_nodes = { &qnm_aggre1_noc },
824
734
};
825
735
826
736
static struct qcom_icc_node srvc_aggre1_noc = {
827
737
.name = "srvc_aggre1_noc",
828
-
.id = SC7280_SLAVE_SERVICE_A1NOC,
829
738
.channels = 1,
830
739
.buswidth = 4,
831
-
.num_links = 0,
832
740
};
833
741
834
742
static struct qcom_icc_node qns_a2noc_snoc = {
835
743
.name = "qns_a2noc_snoc",
836
-
.id = SC7280_SLAVE_A2NOC_SNOC,
837
744
.channels = 1,
838
745
.buswidth = 16,
839
746
.num_links = 1,
840
-
.links = { SC7280_MASTER_A2NOC_SNOC },
747
+
.link_nodes = { &qnm_aggre2_noc },
841
748
};
842
749
843
750
static struct qcom_icc_node qns_pcie_mem_noc = {
844
751
.name = "qns_pcie_mem_noc",
845
-
.id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
846
752
.channels = 1,
847
753
.buswidth = 16,
848
754
.num_links = 1,
849
-
.links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
755
+
.link_nodes = { &qnm_pcie },
850
756
};
851
757
852
758
static struct qcom_icc_node srvc_aggre2_noc = {
853
759
.name = "srvc_aggre2_noc",
854
-
.id = SC7280_SLAVE_SERVICE_A2NOC,
855
760
.channels = 1,
856
761
.buswidth = 4,
857
-
.num_links = 0,
858
762
};
859
763
860
764
static struct qcom_icc_node qup0_core_slave = {
861
765
.name = "qup0_core_slave",
862
-
.id = SC7280_SLAVE_QUP_CORE_0,
863
766
.channels = 1,
864
767
.buswidth = 4,
865
-
.num_links = 0,
866
768
};
867
769
868
770
static struct qcom_icc_node qup1_core_slave = {
869
771
.name = "qup1_core_slave",
870
-
.id = SC7280_SLAVE_QUP_CORE_1,
871
772
.channels = 1,
872
773
.buswidth = 4,
873
-
.num_links = 0,
874
774
};
875
775
876
776
static struct qcom_icc_node qhs_ahb2phy0 = {
877
777
.name = "qhs_ahb2phy0",
878
-
.id = SC7280_SLAVE_AHB2PHY_SOUTH,
879
778
.channels = 1,
880
779
.buswidth = 4,
881
-
.num_links = 0,
882
780
};
883
781
884
782
static struct qcom_icc_node qhs_ahb2phy1 = {
885
783
.name = "qhs_ahb2phy1",
886
-
.id = SC7280_SLAVE_AHB2PHY_NORTH,
887
784
.channels = 1,
888
785
.buswidth = 4,
889
-
.num_links = 0,
890
786
};
891
787
892
788
static struct qcom_icc_node qhs_camera_cfg = {
893
789
.name = "qhs_camera_cfg",
894
-
.id = SC7280_SLAVE_CAMERA_CFG,
895
790
.channels = 1,
896
791
.buswidth = 4,
897
-
.num_links = 0,
898
792
};
899
793
900
794
static struct qcom_icc_node qhs_clk_ctl = {
901
795
.name = "qhs_clk_ctl",
902
-
.id = SC7280_SLAVE_CLK_CTL,
903
796
.channels = 1,
904
797
.buswidth = 4,
905
-
.num_links = 0,
906
798
};
907
799
908
800
static struct qcom_icc_node qhs_compute_cfg = {
909
801
.name = "qhs_compute_cfg",
910
-
.id = SC7280_SLAVE_CDSP_CFG,
911
802
.channels = 1,
912
803
.buswidth = 4,
913
804
.num_links = 1,
914
-
.links = { SC7280_MASTER_CDSP_NOC_CFG },
805
+
.link_nodes = { &qhm_nsp_noc_config },
915
806
};
916
807
917
808
static struct qcom_icc_node qhs_cpr_cx = {
918
809
.name = "qhs_cpr_cx",
919
-
.id = SC7280_SLAVE_RBCPR_CX_CFG,
920
810
.channels = 1,
921
811
.buswidth = 4,
922
-
.num_links = 0,
923
812
};
924
813
925
814
static struct qcom_icc_node qhs_cpr_mx = {
926
815
.name = "qhs_cpr_mx",
927
-
.id = SC7280_SLAVE_RBCPR_MX_CFG,
928
816
.channels = 1,
929
817
.buswidth = 4,
930
-
.num_links = 0,
931
818
};
932
819
933
820
static struct qcom_icc_node qhs_crypto0_cfg = {
934
821
.name = "qhs_crypto0_cfg",
935
-
.id = SC7280_SLAVE_CRYPTO_0_CFG,
936
822
.channels = 1,
937
823
.buswidth = 4,
938
-
.num_links = 0,
939
824
};
940
825
941
826
static struct qcom_icc_node qhs_cx_rdpm = {
942
827
.name = "qhs_cx_rdpm",
943
-
.id = SC7280_SLAVE_CX_RDPM,
944
828
.channels = 1,
945
829
.buswidth = 4,
946
-
.num_links = 0,
947
830
};
948
831
949
832
static struct qcom_icc_node qhs_dcc_cfg = {
950
833
.name = "qhs_dcc_cfg",
951
-
.id = SC7280_SLAVE_DCC_CFG,
952
834
.channels = 1,
953
835
.buswidth = 4,
954
-
.num_links = 0,
955
836
};
956
837
957
838
static struct qcom_icc_node qhs_display_cfg = {
958
839
.name = "qhs_display_cfg",
959
-
.id = SC7280_SLAVE_DISPLAY_CFG,
960
840
.channels = 1,
961
841
.buswidth = 4,
962
-
.num_links = 0,
963
842
};
964
843
965
844
static struct qcom_icc_node qhs_gpuss_cfg = {
966
845
.name = "qhs_gpuss_cfg",
967
-
.id = SC7280_SLAVE_GFX3D_CFG,
968
846
.channels = 1,
969
847
.buswidth = 8,
970
-
.num_links = 0,
971
848
};
972
849
973
850
static struct qcom_icc_node qhs_hwkm = {
974
851
.name = "qhs_hwkm",
975
-
.id = SC7280_SLAVE_HWKM,
976
852
.channels = 1,
977
853
.buswidth = 4,
978
-
.num_links = 0,
979
854
};
980
855
981
856
static struct qcom_icc_node qhs_imem_cfg = {
982
857
.name = "qhs_imem_cfg",
983
-
.id = SC7280_SLAVE_IMEM_CFG,
984
858
.channels = 1,
985
859
.buswidth = 4,
986
-
.num_links = 0,
987
860
};
988
861
989
862
static struct qcom_icc_node qhs_ipa = {
990
863
.name = "qhs_ipa",
991
-
.id = SC7280_SLAVE_IPA_CFG,
992
864
.channels = 1,
993
865
.buswidth = 4,
994
-
.num_links = 0,
995
866
};
996
867
997
868
static struct qcom_icc_node qhs_ipc_router = {
998
869
.name = "qhs_ipc_router",
999
-
.id = SC7280_SLAVE_IPC_ROUTER_CFG,
1000
870
.channels = 1,
1001
871
.buswidth = 4,
1002
-
.num_links = 0,
1003
872
};
1004
873
1005
874
static struct qcom_icc_node qhs_lpass_cfg = {
1006
875
.name = "qhs_lpass_cfg",
1007
-
.id = SC7280_SLAVE_LPASS,
1008
876
.channels = 1,
1009
877
.buswidth = 4,
1010
878
.num_links = 1,
1011
-
.links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
879
+
.link_nodes = { &qhm_config_noc },
1012
880
};
1013
881
1014
882
static struct qcom_icc_node qhs_mss_cfg = {
1015
883
.name = "qhs_mss_cfg",
1016
-
.id = SC7280_SLAVE_CNOC_MSS,
1017
884
.channels = 1,
1018
885
.buswidth = 4,
1019
-
.num_links = 0,
1020
886
};
1021
887
1022
888
static struct qcom_icc_node qhs_mx_rdpm = {
1023
889
.name = "qhs_mx_rdpm",
1024
-
.id = SC7280_SLAVE_MX_RDPM,
1025
890
.channels = 1,
1026
891
.buswidth = 4,
1027
-
.num_links = 0,
1028
892
};
1029
893
1030
894
static struct qcom_icc_node qhs_pcie0_cfg = {
1031
895
.name = "qhs_pcie0_cfg",
1032
-
.id = SC7280_SLAVE_PCIE_0_CFG,
1033
896
.channels = 1,
1034
897
.buswidth = 4,
1035
-
.num_links = 0,
1036
898
};
1037
899
1038
900
static struct qcom_icc_node qhs_pcie1_cfg = {
1039
901
.name = "qhs_pcie1_cfg",
1040
-
.id = SC7280_SLAVE_PCIE_1_CFG,
1041
902
.channels = 1,
1042
903
.buswidth = 4,
1043
-
.num_links = 0,
1044
904
};
1045
905
1046
906
static struct qcom_icc_node qhs_pdm = {
1047
907
.name = "qhs_pdm",
1048
-
.id = SC7280_SLAVE_PDM,
1049
908
.channels = 1,
1050
909
.buswidth = 4,
1051
-
.num_links = 0,
1052
910
};
1053
911
1054
912
static struct qcom_icc_node qhs_pimem_cfg = {
1055
913
.name = "qhs_pimem_cfg",
1056
-
.id = SC7280_SLAVE_PIMEM_CFG,
1057
914
.channels = 1,
1058
915
.buswidth = 4,
1059
-
.num_links = 0,
1060
916
};
1061
917
1062
918
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
1063
919
.name = "qhs_pka_wrapper_cfg",
1064
-
.id = SC7280_SLAVE_PKA_WRAPPER_CFG,
1065
920
.channels = 1,
1066
921
.buswidth = 4,
1067
-
.num_links = 0,
1068
922
};
1069
923
1070
924
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
1071
925
.name = "qhs_pmu_wrapper_cfg",
1072
-
.id = SC7280_SLAVE_PMU_WRAPPER_CFG,
1073
926
.channels = 1,
1074
927
.buswidth = 4,
1075
-
.num_links = 0,
1076
928
};
1077
929
1078
930
static struct qcom_icc_node qhs_qdss_cfg = {
1079
931
.name = "qhs_qdss_cfg",
1080
-
.id = SC7280_SLAVE_QDSS_CFG,
1081
932
.channels = 1,
1082
933
.buswidth = 4,
1083
-
.num_links = 0,
1084
934
};
1085
935
1086
936
static struct qcom_icc_node qhs_qspi = {
1087
937
.name = "qhs_qspi",
1088
-
.id = SC7280_SLAVE_QSPI_0,
1089
938
.channels = 1,
1090
939
.buswidth = 4,
1091
-
.num_links = 0,
1092
940
};
1093
941
1094
942
static struct qcom_icc_node qhs_qup0 = {
1095
943
.name = "qhs_qup0",
1096
-
.id = SC7280_SLAVE_QUP_0,
1097
944
.channels = 1,
1098
945
.buswidth = 4,
1099
-
.num_links = 0,
1100
946
};
1101
947
1102
948
static struct qcom_icc_node qhs_qup1 = {
1103
949
.name = "qhs_qup1",
1104
-
.id = SC7280_SLAVE_QUP_1,
1105
950
.channels = 1,
1106
951
.buswidth = 4,
1107
-
.num_links = 0,
1108
952
};
1109
953
1110
954
static struct qcom_icc_node qhs_sdc1 = {
1111
955
.name = "qhs_sdc1",
1112
-
.id = SC7280_SLAVE_SDCC_1,
1113
956
.channels = 1,
1114
957
.buswidth = 4,
1115
-
.num_links = 0,
1116
958
};
1117
959
1118
960
static struct qcom_icc_node qhs_sdc2 = {
1119
961
.name = "qhs_sdc2",
1120
-
.id = SC7280_SLAVE_SDCC_2,
1121
962
.channels = 1,
1122
963
.buswidth = 4,
1123
-
.num_links = 0,
1124
964
};
1125
965
1126
966
static struct qcom_icc_node qhs_sdc4 = {
1127
967
.name = "qhs_sdc4",
1128
-
.id = SC7280_SLAVE_SDCC_4,
1129
968
.channels = 1,
1130
969
.buswidth = 4,
1131
-
.num_links = 0,
1132
970
};
1133
971
1134
972
static struct qcom_icc_node qhs_security = {
1135
973
.name = "qhs_security",
1136
-
.id = SC7280_SLAVE_SECURITY,
1137
974
.channels = 1,
1138
975
.buswidth = 4,
1139
-
.num_links = 0,
1140
976
};
1141
977
1142
978
static struct qcom_icc_node qhs_tcsr = {
1143
979
.name = "qhs_tcsr",
1144
-
.id = SC7280_SLAVE_TCSR,
1145
980
.channels = 1,
1146
981
.buswidth = 4,
1147
-
.num_links = 0,
1148
982
};
1149
983
1150
984
static struct qcom_icc_node qhs_tlmm = {
1151
985
.name = "qhs_tlmm",
1152
-
.id = SC7280_SLAVE_TLMM,
1153
986
.channels = 1,
1154
987
.buswidth = 4,
1155
-
.num_links = 0,
1156
988
};
1157
989
1158
990
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1159
991
.name = "qhs_ufs_mem_cfg",
1160
-
.id = SC7280_SLAVE_UFS_MEM_CFG,
1161
992
.channels = 1,
1162
993
.buswidth = 4,
1163
-
.num_links = 0,
1164
994
};
1165
995
1166
996
static struct qcom_icc_node qhs_usb2 = {
1167
997
.name = "qhs_usb2",
1168
-
.id = SC7280_SLAVE_USB2,
1169
998
.channels = 1,
1170
999
.buswidth = 4,
1171
-
.num_links = 0,
1172
1000
};
1173
1001
1174
1002
static struct qcom_icc_node qhs_usb3_0 = {
1175
1003
.name = "qhs_usb3_0",
1176
-
.id = SC7280_SLAVE_USB3_0,
1177
1004
.channels = 1,
1178
1005
.buswidth = 4,
1179
-
.num_links = 0,
1180
1006
};
1181
1007
1182
1008
static struct qcom_icc_node qhs_venus_cfg = {
1183
1009
.name = "qhs_venus_cfg",
1184
-
.id = SC7280_SLAVE_VENUS_CFG,
1185
1010
.channels = 1,
1186
1011
.buswidth = 4,
1187
-
.num_links = 0,
1188
1012
};
1189
1013
1190
1014
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1191
1015
.name = "qhs_vsense_ctrl_cfg",
1192
-
.id = SC7280_SLAVE_VSENSE_CTRL_CFG,
1193
1016
.channels = 1,
1194
1017
.buswidth = 4,
1195
-
.num_links = 0,
1196
1018
};
1197
1019
1198
1020
static struct qcom_icc_node qns_a1_noc_cfg = {
1199
1021
.name = "qns_a1_noc_cfg",
1200
-
.id = SC7280_SLAVE_A1NOC_CFG,
1201
1022
.channels = 1,
1202
1023
.buswidth = 4,
1203
1024
.num_links = 1,
1204
-
.links = { SC7280_MASTER_A1NOC_CFG },
1025
+
.link_nodes = { &qnm_a1noc_cfg },
1205
1026
};
1206
1027
1207
1028
static struct qcom_icc_node qns_a2_noc_cfg = {
1208
1029
.name = "qns_a2_noc_cfg",
1209
-
.id = SC7280_SLAVE_A2NOC_CFG,
1210
1030
.channels = 1,
1211
1031
.buswidth = 4,
1212
1032
.num_links = 1,
1213
-
.links = { SC7280_MASTER_A2NOC_CFG },
1033
+
.link_nodes = { &qnm_a2noc_cfg },
1214
1034
};
1215
1035
1216
1036
static struct qcom_icc_node qns_cnoc2_cnoc3 = {
1217
1037
.name = "qns_cnoc2_cnoc3",
1218
-
.id = SC7280_SLAVE_CNOC2_CNOC3,
1219
1038
.channels = 1,
1220
1039
.buswidth = 8,
1221
1040
.num_links = 1,
1222
-
.links = { SC7280_MASTER_CNOC2_CNOC3 },
1041
+
.link_nodes = { &qnm_cnoc2_cnoc3 },
1223
1042
};
1224
1043
1225
1044
static struct qcom_icc_node qns_mnoc_cfg = {
1226
1045
.name = "qns_mnoc_cfg",
1227
-
.id = SC7280_SLAVE_CNOC_MNOC_CFG,
1228
1046
.channels = 1,
1229
1047
.buswidth = 4,
1230
1048
.num_links = 1,
1231
-
.links = { SC7280_MASTER_CNOC_MNOC_CFG },
1049
+
.link_nodes = { &qnm_mnoc_cfg },
1232
1050
};
1233
1051
1234
1052
static struct qcom_icc_node qns_snoc_cfg = {
1235
1053
.name = "qns_snoc_cfg",
1236
-
.id = SC7280_SLAVE_SNOC_CFG,
1237
1054
.channels = 1,
1238
1055
.buswidth = 4,
1239
1056
.num_links = 1,
1240
-
.links = { SC7280_MASTER_SNOC_CFG },
1057
+
.link_nodes = { &qnm_snoc_cfg },
1241
1058
};
1242
1059
1243
1060
static struct qcom_icc_node qhs_aoss = {
1244
1061
.name = "qhs_aoss",
1245
-
.id = SC7280_SLAVE_AOSS,
1246
1062
.channels = 1,
1247
1063
.buswidth = 4,
1248
-
.num_links = 0,
1249
1064
};
1250
1065
1251
1066
static struct qcom_icc_node qhs_apss = {
1252
1067
.name = "qhs_apss",
1253
-
.id = SC7280_SLAVE_APPSS,
1254
1068
.channels = 1,
1255
1069
.buswidth = 8,
1256
-
.num_links = 0,
1257
1070
};
1258
1071
1259
1072
static struct qcom_icc_node qns_cnoc3_cnoc2 = {
1260
1073
.name = "qns_cnoc3_cnoc2",
1261
-
.id = SC7280_SLAVE_CNOC3_CNOC2,
1262
1074
.channels = 1,
1263
1075
.buswidth = 8,
1264
1076
.num_links = 1,
1265
-
.links = { SC7280_MASTER_CNOC3_CNOC2 },
1077
+
.link_nodes = { &qnm_cnoc3_cnoc2 },
1266
1078
};
1267
1079
1268
1080
static struct qcom_icc_node qns_cnoc_a2noc = {
1269
1081
.name = "qns_cnoc_a2noc",
1270
-
.id = SC7280_SLAVE_CNOC_A2NOC,
1271
1082
.channels = 1,
1272
1083
.buswidth = 8,
1273
1084
.num_links = 1,
1274
-
.links = { SC7280_MASTER_CNOC_A2NOC },
1085
+
.link_nodes = { &qnm_cnoc_datapath },
1275
1086
};
1276
1087
1277
1088
static struct qcom_icc_node qns_ddrss_cfg = {
1278
1089
.name = "qns_ddrss_cfg",
1279
-
.id = SC7280_SLAVE_DDRSS_CFG,
1280
1090
.channels = 1,
1281
1091
.buswidth = 4,
1282
1092
.num_links = 1,
1283
-
.links = { SC7280_MASTER_CNOC_DC_NOC },
1093
+
.link_nodes = { &qnm_cnoc_dc_noc },
1284
1094
};
1285
1095
1286
1096
static struct qcom_icc_node qxs_boot_imem = {
1287
1097
.name = "qxs_boot_imem",
1288
-
.id = SC7280_SLAVE_BOOT_IMEM,
1289
1098
.channels = 1,
1290
1099
.buswidth = 8,
1291
-
.num_links = 0,
1292
1100
};
1293
1101
1294
1102
static struct qcom_icc_node qxs_imem = {
1295
1103
.name = "qxs_imem",
1296
-
.id = SC7280_SLAVE_IMEM,
1297
1104
.channels = 1,
1298
1105
.buswidth = 8,
1299
-
.num_links = 0,
1300
1106
};
1301
1107
1302
1108
static struct qcom_icc_node qxs_pimem = {
1303
1109
.name = "qxs_pimem",
1304
-
.id = SC7280_SLAVE_PIMEM,
1305
1110
.channels = 1,
1306
1111
.buswidth = 8,
1307
-
.num_links = 0,
1308
1112
};
1309
1113
1310
1114
static struct qcom_icc_node xs_pcie_0 = {
1311
1115
.name = "xs_pcie_0",
1312
-
.id = SC7280_SLAVE_PCIE_0,
1313
1116
.channels = 1,
1314
1117
.buswidth = 8,
1315
-
.num_links = 0,
1316
1118
};
1317
1119
1318
1120
static struct qcom_icc_node xs_pcie_1 = {
1319
1121
.name = "xs_pcie_1",
1320
-
.id = SC7280_SLAVE_PCIE_1,
1321
1122
.channels = 1,
1322
1123
.buswidth = 8,
1323
-
.num_links = 0,
1324
1124
};
1325
1125
1326
1126
static struct qcom_icc_node xs_qdss_stm = {
1327
1127
.name = "xs_qdss_stm",
1328
-
.id = SC7280_SLAVE_QDSS_STM,
1329
1128
.channels = 1,
1330
1129
.buswidth = 4,
1331
-
.num_links = 0,
1332
1130
};
1333
1131
1334
1132
static struct qcom_icc_node xs_sys_tcu_cfg = {
1335
1133
.name = "xs_sys_tcu_cfg",
1336
-
.id = SC7280_SLAVE_TCU,
1337
1134
.channels = 1,
1338
1135
.buswidth = 8,
1339
-
.num_links = 0,
1340
1136
};
1341
1137
1342
1138
static struct qcom_icc_node qhs_llcc = {
1343
1139
.name = "qhs_llcc",
1344
-
.id = SC7280_SLAVE_LLCC_CFG,
1345
1140
.channels = 1,
1346
1141
.buswidth = 4,
1347
-
.num_links = 0,
1348
1142
};
1349
1143
1350
1144
static struct qcom_icc_node qns_gemnoc = {
1351
1145
.name = "qns_gemnoc",
1352
-
.id = SC7280_SLAVE_GEM_NOC_CFG,
1353
1146
.channels = 1,
1354
1147
.buswidth = 4,
1355
1148
.num_links = 1,
1356
-
.links = { SC7280_MASTER_GEM_NOC_CFG },
1149
+
.link_nodes = { &qnm_gemnoc_cfg },
1357
1150
};
1358
1151
1359
1152
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1360
1153
.name = "qhs_mdsp_ms_mpu_cfg",
1361
-
.id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
1362
1154
.channels = 1,
1363
1155
.buswidth = 4,
1364
-
.num_links = 0,
1365
1156
};
1366
1157
1367
1158
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1368
1159
.name = "qhs_modem_ms_mpu_cfg",
1369
-
.id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
1370
1160
.channels = 1,
1371
1161
.buswidth = 4,
1372
-
.num_links = 0,
1373
1162
};
1374
1163
1375
1164
static struct qcom_icc_node qns_gem_noc_cnoc = {
1376
1165
.name = "qns_gem_noc_cnoc",
1377
-
.id = SC7280_SLAVE_GEM_NOC_CNOC,
1378
1166
.channels = 1,
1379
1167
.buswidth = 16,
1380
1168
.num_links = 1,
1381
-
.links = { SC7280_MASTER_GEM_NOC_CNOC },
1169
+
.link_nodes = { &qnm_gemnoc_cnoc },
1382
1170
};
1383
1171
1384
1172
static struct qcom_icc_node qns_llcc = {
1385
1173
.name = "qns_llcc",
1386
-
.id = SC7280_SLAVE_LLCC,
1387
1174
.channels = 2,
1388
1175
.buswidth = 16,
1389
1176
.num_links = 1,
1390
-
.links = { SC7280_MASTER_LLCC },
1177
+
.link_nodes = { &llcc_mc },
1391
1178
};
1392
1179
1393
1180
static struct qcom_icc_node qns_pcie = {
1394
1181
.name = "qns_pcie",
1395
-
.id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
1396
1182
.channels = 1,
1397
1183
.buswidth = 8,
1398
1184
.num_links = 1,
1399
-
.links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
1185
+
.link_nodes = { &qnm_gemnoc_pcie },
1400
1186
};
1401
1187
1402
1188
static struct qcom_icc_node srvc_even_gemnoc = {
1403
1189
.name = "srvc_even_gemnoc",
1404
-
.id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
1405
1190
.channels = 1,
1406
1191
.buswidth = 4,
1407
-
.num_links = 0,
1408
1192
};
1409
1193
1410
1194
static struct qcom_icc_node srvc_odd_gemnoc = {
1411
1195
.name = "srvc_odd_gemnoc",
1412
-
.id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
1413
1196
.channels = 1,
1414
1197
.buswidth = 4,
1415
-
.num_links = 0,
1416
1198
};
1417
1199
1418
1200
static struct qcom_icc_node srvc_sys_gemnoc = {
1419
1201
.name = "srvc_sys_gemnoc",
1420
-
.id = SC7280_SLAVE_SERVICE_GEM_NOC,
1421
1202
.channels = 1,
1422
1203
.buswidth = 4,
1423
-
.num_links = 0,
1424
1204
};
1425
1205
1426
1206
static struct qcom_icc_node qhs_lpass_core = {
1427
1207
.name = "qhs_lpass_core",
1428
-
.id = SC7280_SLAVE_LPASS_CORE_CFG,
1429
1208
.channels = 1,
1430
1209
.buswidth = 4,
1431
-
.num_links = 0,
1432
1210
};
1433
1211
1434
1212
static struct qcom_icc_node qhs_lpass_lpi = {
1435
1213
.name = "qhs_lpass_lpi",
1436
-
.id = SC7280_SLAVE_LPASS_LPI_CFG,
1437
1214
.channels = 1,
1438
1215
.buswidth = 4,
1439
-
.num_links = 0,
1440
1216
};
1441
1217
1442
1218
static struct qcom_icc_node qhs_lpass_mpu = {
1443
1219
.name = "qhs_lpass_mpu",
1444
-
.id = SC7280_SLAVE_LPASS_MPU_CFG,
1445
1220
.channels = 1,
1446
1221
.buswidth = 4,
1447
-
.num_links = 0,
1448
1222
};
1449
1223
1450
1224
static struct qcom_icc_node qhs_lpass_top = {
1451
1225
.name = "qhs_lpass_top",
1452
-
.id = SC7280_SLAVE_LPASS_TOP_CFG,
1453
1226
.channels = 1,
1454
1227
.buswidth = 4,
1455
-
.num_links = 0,
1456
1228
};
1457
1229
1458
1230
static struct qcom_icc_node srvc_niu_aml_noc = {
1459
1231
.name = "srvc_niu_aml_noc",
1460
-
.id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
1461
1232
.channels = 1,
1462
1233
.buswidth = 4,
1463
-
.num_links = 0,
1464
1234
};
1465
1235
1466
1236
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1467
1237
.name = "srvc_niu_lpass_agnoc",
1468
-
.id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
1469
1238
.channels = 1,
1470
1239
.buswidth = 4,
1471
-
.num_links = 0,
1472
1240
};
1473
1241
1474
1242
static struct qcom_icc_node ebi = {
1475
1243
.name = "ebi",
1476
-
.id = SC7280_SLAVE_EBI1,
1477
1244
.channels = 2,
1478
1245
.buswidth = 4,
1479
-
.num_links = 0,
1480
1246
};
1481
1247
1482
1248
static struct qcom_icc_node qns_mem_noc_hf = {
1483
1249
.name = "qns_mem_noc_hf",
1484
-
.id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
1485
1250
.channels = 2,
1486
1251
.buswidth = 32,
1487
1252
.num_links = 1,
1488
-
.links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
1253
+
.link_nodes = { &qnm_mnoc_hf },
1489
1254
};
1490
1255
1491
1256
static struct qcom_icc_node qns_mem_noc_sf = {
1492
1257
.name = "qns_mem_noc_sf",
1493
-
.id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
1494
1258
.channels = 1,
1495
1259
.buswidth = 32,
1496
1260
.num_links = 1,
1497
-
.links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
1261
+
.link_nodes = { &qnm_mnoc_sf },
1498
1262
};
1499
1263
1500
1264
static struct qcom_icc_node srvc_mnoc = {
1501
1265
.name = "srvc_mnoc",
1502
-
.id = SC7280_SLAVE_SERVICE_MNOC,
1503
1266
.channels = 1,
1504
1267
.buswidth = 4,
1505
-
.num_links = 0,
1506
1268
};
1507
1269
1508
1270
static struct qcom_icc_node qns_nsp_gemnoc = {
1509
1271
.name = "qns_nsp_gemnoc",
1510
-
.id = SC7280_SLAVE_CDSP_MEM_NOC,
1511
1272
.channels = 2,
1512
1273
.buswidth = 32,
1513
1274
.num_links = 1,
1514
-
.links = { SC7280_MASTER_COMPUTE_NOC },
1275
+
.link_nodes = { &qnm_cmpnoc },
1515
1276
};
1516
1277
1517
1278
static struct qcom_icc_node service_nsp_noc = {
1518
1279
.name = "service_nsp_noc",
1519
-
.id = SC7280_SLAVE_SERVICE_NSP_NOC,
1520
1280
.channels = 1,
1521
1281
.buswidth = 4,
1522
-
.num_links = 0,
1523
1282
};
1524
1283
1525
1284
static struct qcom_icc_node qns_gemnoc_gc = {
1526
1285
.name = "qns_gemnoc_gc",
1527
-
.id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
1528
1286
.channels = 1,
1529
1287
.buswidth = 8,
1530
1288
.num_links = 1,
1531
-
.links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
1289
+
.link_nodes = { &qnm_snoc_gc },
1532
1290
};
1533
1291
1534
1292
static struct qcom_icc_node qns_gemnoc_sf = {
1535
1293
.name = "qns_gemnoc_sf",
1536
-
.id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
1537
1294
.channels = 1,
1538
1295
.buswidth = 16,
1539
1296
.num_links = 1,
1540
-
.links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
1297
+
.link_nodes = { &qnm_snoc_sf },
1541
1298
};
1542
1299
1543
1300
static struct qcom_icc_node srvc_snoc = {
1544
1301
.name = "srvc_snoc",
1545
-
.id = SC7280_SLAVE_SERVICE_SNOC,
1546
1302
.channels = 1,
1547
1303
.buswidth = 4,
1548
-
.num_links = 0,
1549
1304
};
1550
1305
1551
1306
static struct qcom_icc_bcm bcm_acv = {
···
1620
1687
};
1621
1688
1622
1689
static const struct qcom_icc_desc sc7280_aggre1_noc = {
1690
+
.alloc_dyn_id = true,
1623
1691
.config = &sc7280_aggre1_noc_regmap_config,
1624
1692
.nodes = aggre1_noc_nodes,
1625
1693
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
···
1653
1719
};
1654
1720
1655
1721
static const struct qcom_icc_desc sc7280_aggre2_noc = {
1722
+
.alloc_dyn_id = true,
1656
1723
.config = &sc7280_aggre2_noc_regmap_config,
1657
1724
.nodes = aggre2_noc_nodes,
1658
1725
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
···
1675
1740
};
1676
1741
1677
1742
static const struct qcom_icc_desc sc7280_clk_virt = {
1743
+
.alloc_dyn_id = true,
1678
1744
.nodes = clk_virt_nodes,
1679
1745
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1680
1746
.bcms = clk_virt_bcms,
···
1746
1810
};
1747
1811
1748
1812
static const struct qcom_icc_desc sc7280_cnoc2 = {
1813
+
.alloc_dyn_id = true,
1749
1814
.config = &sc7280_cnoc2_regmap_config,
1750
1815
.nodes = cnoc2_nodes,
1751
1816
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
···
1788
1851
};
1789
1852
1790
1853
static const struct qcom_icc_desc sc7280_cnoc3 = {
1854
+
.alloc_dyn_id = true,
1791
1855
.config = &sc7280_cnoc3_regmap_config,
1792
1856
.nodes = cnoc3_nodes,
1793
1857
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
···
1814
1876
};
1815
1877
1816
1878
static const struct qcom_icc_desc sc7280_dc_noc = {
1879
+
.alloc_dyn_id = true,
1817
1880
.config = &sc7280_dc_noc_regmap_config,
1818
1881
.nodes = dc_noc_nodes,
1819
1882
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
···
1860
1921
};
1861
1922
1862
1923
static const struct qcom_icc_desc sc7280_gem_noc = {
1924
+
.alloc_dyn_id = true,
1863
1925
.config = &sc7280_gem_noc_regmap_config,
1864
1926
.nodes = gem_noc_nodes,
1865
1927
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
···
1890
1950
};
1891
1951
1892
1952
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1953
+
.alloc_dyn_id = true,
1893
1954
.config = &sc7280_lpass_ag_noc_regmap_config,
1894
1955
.nodes = lpass_ag_noc_nodes,
1895
1956
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
···
1917
1976
};
1918
1977
1919
1978
static const struct qcom_icc_desc sc7280_mc_virt = {
1979
+
.alloc_dyn_id = true,
1920
1980
.config = &sc7280_mc_virt_regmap_config,
1921
1981
.nodes = mc_virt_nodes,
1922
1982
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
···
1954
2012
};
1955
2013
1956
2014
static const struct qcom_icc_desc sc7280_mmss_noc = {
2015
+
.alloc_dyn_id = true,
1957
2016
.config = &sc7280_mmss_noc_regmap_config,
1958
2017
.nodes = mmss_noc_nodes,
1959
2018
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
···
1983
2040
};
1984
2041
1985
2042
static const struct qcom_icc_desc sc7280_nsp_noc = {
2043
+
.alloc_dyn_id = true,
1986
2044
.config = &sc7280_nsp_noc_regmap_config,
1987
2045
.nodes = nsp_noc_nodes,
1988
2046
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
···
2018
2074
};
2019
2075
2020
2076
static const struct qcom_icc_desc sc7280_system_noc = {
2077
+
.alloc_dyn_id = true,
2021
2078
.config = &sc7280_system_noc_regmap_config,
2022
2079
.nodes = system_noc_nodes,
2023
2080
.num_nodes = ARRAY_SIZE(system_noc_nodes),
-154
drivers/interconnect/qcom/sc7280.h
-154
drivers/interconnect/qcom/sc7280.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Qualcomm #define SC7280 interconnect IDs
4
-
*
5
-
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
6
-
*/
7
-
8
-
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H
9
-
#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H
10
-
11
-
#define SC7280_MASTER_GPU_TCU 0
12
-
#define SC7280_MASTER_SYS_TCU 1
13
-
#define SC7280_MASTER_APPSS_PROC 2
14
-
#define SC7280_MASTER_LLCC 3
15
-
#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4
16
-
#define SC7280_MASTER_CDSP_NOC_CFG 5
17
-
#define SC7280_MASTER_QDSS_BAM 6
18
-
#define SC7280_MASTER_QSPI_0 7
19
-
#define SC7280_MASTER_QUP_0 8
20
-
#define SC7280_MASTER_QUP_1 9
21
-
#define SC7280_MASTER_A1NOC_CFG 10
22
-
#define SC7280_MASTER_A2NOC_CFG 11
23
-
#define SC7280_MASTER_A1NOC_SNOC 12
24
-
#define SC7280_MASTER_A2NOC_SNOC 13
25
-
#define SC7280_MASTER_COMPUTE_NOC 14
26
-
#define SC7280_MASTER_CNOC2_CNOC3 15
27
-
#define SC7280_MASTER_CNOC3_CNOC2 16
28
-
#define SC7280_MASTER_CNOC_A2NOC 17
29
-
#define SC7280_MASTER_CNOC_DC_NOC 18
30
-
#define SC7280_MASTER_GEM_NOC_CFG 19
31
-
#define SC7280_MASTER_GEM_NOC_CNOC 20
32
-
#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21
33
-
#define SC7280_MASTER_GFX3D 22
34
-
#define SC7280_MASTER_CNOC_MNOC_CFG 23
35
-
#define SC7280_MASTER_MNOC_HF_MEM_NOC 24
36
-
#define SC7280_MASTER_MNOC_SF_MEM_NOC 25
37
-
#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26
38
-
#define SC7280_MASTER_SNOC_CFG 27
39
-
#define SC7280_MASTER_SNOC_GC_MEM_NOC 28
40
-
#define SC7280_MASTER_SNOC_SF_MEM_NOC 29
41
-
#define SC7280_MASTER_VIDEO_P0 30
42
-
#define SC7280_MASTER_VIDEO_PROC 31
43
-
#define SC7280_MASTER_QUP_CORE_0 32
44
-
#define SC7280_MASTER_QUP_CORE_1 33
45
-
#define SC7280_MASTER_CAMNOC_HF 34
46
-
#define SC7280_MASTER_CAMNOC_ICP 35
47
-
#define SC7280_MASTER_CAMNOC_SF 36
48
-
#define SC7280_MASTER_CRYPTO 37
49
-
#define SC7280_MASTER_IPA 38
50
-
#define SC7280_MASTER_MDP0 39
51
-
#define SC7280_MASTER_CDSP_PROC 40
52
-
#define SC7280_MASTER_PIMEM 41
53
-
#define SC7280_MASTER_GIC 42
54
-
#define SC7280_MASTER_PCIE_0 43
55
-
#define SC7280_MASTER_PCIE_1 44
56
-
#define SC7280_MASTER_QDSS_DAP 45
57
-
#define SC7280_MASTER_QDSS_ETR 46
58
-
#define SC7280_MASTER_SDCC_1 47
59
-
#define SC7280_MASTER_SDCC_2 48
60
-
#define SC7280_MASTER_SDCC_4 49
61
-
#define SC7280_MASTER_UFS_MEM 50
62
-
#define SC7280_MASTER_USB2 51
63
-
#define SC7280_MASTER_USB3_0 52
64
-
#define SC7280_SLAVE_EBI1 53
65
-
#define SC7280_SLAVE_AHB2PHY_SOUTH 54
66
-
#define SC7280_SLAVE_AHB2PHY_NORTH 55
67
-
#define SC7280_SLAVE_AOSS 56
68
-
#define SC7280_SLAVE_APPSS 57
69
-
#define SC7280_SLAVE_CAMERA_CFG 58
70
-
#define SC7280_SLAVE_CLK_CTL 59
71
-
#define SC7280_SLAVE_CDSP_CFG 60
72
-
#define SC7280_SLAVE_RBCPR_CX_CFG 61
73
-
#define SC7280_SLAVE_RBCPR_MX_CFG 62
74
-
#define SC7280_SLAVE_CRYPTO_0_CFG 63
75
-
#define SC7280_SLAVE_CX_RDPM 64
76
-
#define SC7280_SLAVE_DCC_CFG 65
77
-
#define SC7280_SLAVE_DISPLAY_CFG 66
78
-
#define SC7280_SLAVE_GFX3D_CFG 67
79
-
#define SC7280_SLAVE_HWKM 68
80
-
#define SC7280_SLAVE_IMEM_CFG 69
81
-
#define SC7280_SLAVE_IPA_CFG 70
82
-
#define SC7280_SLAVE_IPC_ROUTER_CFG 71
83
-
#define SC7280_SLAVE_LLCC_CFG 72
84
-
#define SC7280_SLAVE_LPASS 73
85
-
#define SC7280_SLAVE_LPASS_CORE_CFG 74
86
-
#define SC7280_SLAVE_LPASS_LPI_CFG 75
87
-
#define SC7280_SLAVE_LPASS_MPU_CFG 76
88
-
#define SC7280_SLAVE_LPASS_TOP_CFG 77
89
-
#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78
90
-
#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79
91
-
#define SC7280_SLAVE_CNOC_MSS 80
92
-
#define SC7280_SLAVE_MX_RDPM 81
93
-
#define SC7280_SLAVE_PCIE_0_CFG 82
94
-
#define SC7280_SLAVE_PCIE_1_CFG 83
95
-
#define SC7280_SLAVE_PDM 84
96
-
#define SC7280_SLAVE_PIMEM_CFG 85
97
-
#define SC7280_SLAVE_PKA_WRAPPER_CFG 86
98
-
#define SC7280_SLAVE_PMU_WRAPPER_CFG 87
99
-
#define SC7280_SLAVE_QDSS_CFG 88
100
-
#define SC7280_SLAVE_QSPI_0 89
101
-
#define SC7280_SLAVE_QUP_0 90
102
-
#define SC7280_SLAVE_QUP_1 91
103
-
#define SC7280_SLAVE_SDCC_1 92
104
-
#define SC7280_SLAVE_SDCC_2 93
105
-
#define SC7280_SLAVE_SDCC_4 94
106
-
#define SC7280_SLAVE_SECURITY 95
107
-
#define SC7280_SLAVE_TCSR 96
108
-
#define SC7280_SLAVE_TLMM 97
109
-
#define SC7280_SLAVE_UFS_MEM_CFG 98
110
-
#define SC7280_SLAVE_USB2 99
111
-
#define SC7280_SLAVE_USB3_0 100
112
-
#define SC7280_SLAVE_VENUS_CFG 101
113
-
#define SC7280_SLAVE_VSENSE_CTRL_CFG 102
114
-
#define SC7280_SLAVE_A1NOC_CFG 103
115
-
#define SC7280_SLAVE_A1NOC_SNOC 104
116
-
#define SC7280_SLAVE_A2NOC_CFG 105
117
-
#define SC7280_SLAVE_A2NOC_SNOC 106
118
-
#define SC7280_SLAVE_CNOC2_CNOC3 107
119
-
#define SC7280_SLAVE_CNOC3_CNOC2 108
120
-
#define SC7280_SLAVE_CNOC_A2NOC 109
121
-
#define SC7280_SLAVE_DDRSS_CFG 110
122
-
#define SC7280_SLAVE_GEM_NOC_CNOC 111
123
-
#define SC7280_SLAVE_GEM_NOC_CFG 112
124
-
#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113
125
-
#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114
126
-
#define SC7280_SLAVE_LLCC 115
127
-
#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116
128
-
#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117
129
-
#define SC7280_SLAVE_CNOC_MNOC_CFG 118
130
-
#define SC7280_SLAVE_CDSP_MEM_NOC 119
131
-
#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120
132
-
#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121
133
-
#define SC7280_SLAVE_SNOC_CFG 122
134
-
#define SC7280_SLAVE_QUP_CORE_0 123
135
-
#define SC7280_SLAVE_QUP_CORE_1 124
136
-
#define SC7280_SLAVE_BOOT_IMEM 125
137
-
#define SC7280_SLAVE_IMEM 126
138
-
#define SC7280_SLAVE_PIMEM 127
139
-
#define SC7280_SLAVE_SERVICE_NSP_NOC 128
140
-
#define SC7280_SLAVE_SERVICE_A1NOC 129
141
-
#define SC7280_SLAVE_SERVICE_A2NOC 130
142
-
#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131
143
-
#define SC7280_SLAVE_SERVICE_MNOC 132
144
-
#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133
145
-
#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134
146
-
#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135
147
-
#define SC7280_SLAVE_SERVICE_SNOC 136
148
-
#define SC7280_SLAVE_SERVICE_GEM_NOC 137
149
-
#define SC7280_SLAVE_PCIE_0 138
150
-
#define SC7280_SLAVE_PCIE_1 139
151
-
#define SC7280_SLAVE_QDSS_STM 140
152
-
#define SC7280_SLAVE_TCU 141
153
-
154
-
#endif