Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'r8152-add-helper-functions-for-pla-usb-phy-ocp-registers'
Chih Kai Hsu says:
====================
r8152: add helper functions for PLA/USB/PHY OCP registers
====================
Link: https://patch.msgid.link/20260326073925.32976-453-nic_swsd@realtek.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+629
-1161
+629
-1161
drivers/net/usb/r8152.c
+629
-1161
drivers/net/usb/r8152.c
···
1654
1654
r8152_mdio_write(tp, reg, val);
1655
1655
}
1656
1656
1657
+
static void
1658
+
ocp_dword_w0w1(struct r8152 *tp, u16 type, u16 index, u32 clear, u32 set)
1659
+
{
1660
+
u32 ocp_data;
1661
+
1662
+
ocp_data = ocp_read_dword(tp, type, index);
1663
+
ocp_data = (ocp_data & ~clear) | set;
1664
+
ocp_write_dword(tp, type, index, ocp_data);
1665
+
}
1666
+
1667
+
static void
1668
+
ocp_word_w0w1(struct r8152 *tp, u16 type, u16 index, u16 clear, u16 set)
1669
+
{
1670
+
u16 ocp_data;
1671
+
1672
+
ocp_data = ocp_read_word(tp, type, index);
1673
+
ocp_data = (ocp_data & ~clear) | set;
1674
+
ocp_write_word(tp, type, index, ocp_data);
1675
+
}
1676
+
1677
+
static void
1678
+
ocp_byte_w0w1(struct r8152 *tp, u16 type, u16 index, u8 clear, u8 set)
1679
+
{
1680
+
u8 ocp_data;
1681
+
1682
+
ocp_data = ocp_read_byte(tp, type, index);
1683
+
ocp_data = (ocp_data & ~clear) | set;
1684
+
ocp_write_byte(tp, type, index, ocp_data);
1685
+
}
1686
+
1687
+
static void ocp_dword_clr_bits(struct r8152 *tp, u16 type, u16 index, u32 clear)
1688
+
{
1689
+
ocp_dword_w0w1(tp, type, index, clear, 0);
1690
+
}
1691
+
1692
+
static void ocp_dword_set_bits(struct r8152 *tp, u16 type, u16 index, u32 set)
1693
+
{
1694
+
ocp_dword_w0w1(tp, type, index, 0, set);
1695
+
}
1696
+
1697
+
static void ocp_word_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 clear)
1698
+
{
1699
+
ocp_word_w0w1(tp, type, index, clear, 0);
1700
+
}
1701
+
1702
+
static void ocp_word_set_bits(struct r8152 *tp, u16 type, u16 index, u16 set)
1703
+
{
1704
+
ocp_word_w0w1(tp, type, index, 0, set);
1705
+
}
1706
+
1707
+
static int
1708
+
ocp_word_test_and_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 clear)
1709
+
{
1710
+
u16 ocp_data;
1711
+
1712
+
ocp_data = ocp_read_word(tp, type, index);
1713
+
if (ocp_data & clear)
1714
+
ocp_write_word(tp, type, index, ocp_data & ~clear);
1715
+
1716
+
return ocp_data & clear;
1717
+
}
1718
+
1719
+
static void ocp_byte_clr_bits(struct r8152 *tp, u16 type, u16 index, u8 clear)
1720
+
{
1721
+
ocp_byte_w0w1(tp, type, index, clear, 0);
1722
+
}
1723
+
1724
+
static void ocp_byte_set_bits(struct r8152 *tp, u16 type, u16 index, u8 set)
1725
+
{
1726
+
ocp_byte_w0w1(tp, type, index, 0, set);
1727
+
}
1728
+
1729
+
static void ocp_reg_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set)
1730
+
{
1731
+
u16 data;
1732
+
1733
+
data = ocp_reg_read(tp, addr);
1734
+
data = (data & ~clear) | set;
1735
+
ocp_reg_write(tp, addr, data);
1736
+
}
1737
+
1738
+
static void ocp_reg_clr_bits(struct r8152 *tp, u16 addr, u16 clear)
1739
+
{
1740
+
ocp_reg_w0w1(tp, addr, clear, 0);
1741
+
}
1742
+
1743
+
static void ocp_reg_set_bits(struct r8152 *tp, u16 addr, u16 set)
1744
+
{
1745
+
ocp_reg_w0w1(tp, addr, 0, set);
1746
+
}
1747
+
1748
+
static void sram_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set)
1749
+
{
1750
+
u16 data;
1751
+
1752
+
data = sram_read(tp, addr);
1753
+
data = (data & ~clear) | set;
1754
+
ocp_reg_write(tp, OCP_SRAM_DATA, data);
1755
+
}
1756
+
1757
+
static void sram_clr_bits(struct r8152 *tp, u16 addr, u16 clear)
1758
+
{
1759
+
sram_write_w0w1(tp, addr, clear, 0);
1760
+
}
1761
+
1762
+
static void sram_set_bits(struct r8152 *tp, u16 addr, u16 set)
1763
+
{
1764
+
sram_write_w0w1(tp, addr, 0, set);
1765
+
}
1766
+
1767
+
static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear)
1768
+
{
1769
+
int data;
1770
+
1771
+
data = r8152_mdio_read(tp, addr);
1772
+
r8152_mdio_write(tp, addr, data & ~clear);
1773
+
}
1774
+
1775
+
static void r8152_mdio_set_bit(struct r8152 *tp, u16 addr, u16 set)
1776
+
{
1777
+
int data;
1778
+
1779
+
data = r8152_mdio_read(tp, addr);
1780
+
r8152_mdio_write(tp, addr, data | set);
1781
+
}
1782
+
1783
+
static int r8152_mdio_test_and_clr_bit(struct r8152 *tp, u16 addr, u16 clear)
1784
+
{
1785
+
int data;
1786
+
1787
+
data = r8152_mdio_read(tp, addr);
1788
+
if (data & clear)
1789
+
r8152_mdio_write(tp, addr, data & ~clear);
1790
+
1791
+
return data & clear;
1792
+
}
1793
+
1657
1794
static int
1658
1795
r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1659
1796
···
3093
2956
3094
2957
static void r8152b_reset_packet_filter(struct r8152 *tp)
3095
2958
{
3096
-
u32 ocp_data;
3097
-
3098
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
3099
-
ocp_data &= ~FMC_FCR_MCU_EN;
3100
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
3101
-
ocp_data |= FMC_FCR_MCU_EN;
3102
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2959
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN);
2960
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN);
3103
2961
}
3104
2962
3105
2963
static void rtl8152_nic_reset(struct r8152 *tp)
3106
2964
{
3107
-
u32 ocp_data;
3108
2965
int i;
3109
2966
3110
2967
switch (tp->version) {
3111
2968
case RTL_TEST_01:
3112
2969
case RTL_VER_10:
3113
2970
case RTL_VER_11:
3114
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3115
-
ocp_data &= ~CR_TE;
3116
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2971
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_TE);
3117
2972
3118
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
3119
-
ocp_data &= ~BMU_RESET_EP_IN;
3120
-
ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2973
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET,
2974
+
BMU_RESET_EP_IN);
3121
2975
3122
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3123
-
ocp_data |= CDC_ECM_EN;
3124
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2976
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN);
3125
2977
3126
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3127
-
ocp_data &= ~CR_RE;
3128
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2978
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE);
3129
2979
3130
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
3131
-
ocp_data |= BMU_RESET_EP_IN;
3132
-
ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2980
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET,
2981
+
BMU_RESET_EP_IN);
3133
2982
3134
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3135
-
ocp_data &= ~CDC_ECM_EN;
3136
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2983
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN);
3137
2984
break;
3138
2985
3139
2986
default:
···
3146
3025
3147
3026
static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
3148
3027
{
3149
-
u32 ocp_data;
3150
-
3151
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
3152
3028
if (enable)
3153
-
ocp_data |= EEEP_CR_EEEP_TX;
3029
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR,
3030
+
EEEP_CR_EEEP_TX);
3154
3031
else
3155
-
ocp_data &= ~EEEP_CR_EEEP_TX;
3156
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
3032
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR,
3033
+
EEEP_CR_EEEP_TX);
3157
3034
}
3158
3035
3159
3036
static void rtl_set_eee_plus(struct r8152 *tp)
···
3164
3045
3165
3046
static void rxdy_gated_en(struct r8152 *tp, bool enable)
3166
3047
{
3167
-
u32 ocp_data;
3168
-
3169
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3170
3048
if (enable)
3171
-
ocp_data |= RXDY_GATED_EN;
3049
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN);
3172
3050
else
3173
-
ocp_data &= ~RXDY_GATED_EN;
3174
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
3051
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN);
3175
3052
}
3176
3053
3177
3054
static int rtl_start_rx(struct r8152 *tp)
···
3255
3140
3256
3141
static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3257
3142
{
3258
-
u32 ocp_data;
3259
-
3260
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3261
-
ocp_data &= ~IFG_MASK;
3262
3143
if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3263
-
ocp_data |= IFG_144NS;
3264
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3144
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_144NS);
3265
3145
3266
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3267
-
ocp_data &= ~TX10MIDLE_EN;
3268
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3146
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3147
+
TX10MIDLE_EN);
3269
3148
} else {
3270
-
ocp_data |= IFG_96NS;
3271
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3149
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_96NS);
3272
3150
3273
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3274
-
ocp_data |= TX10MIDLE_EN;
3275
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3151
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3152
+
TX10MIDLE_EN);
3276
3153
}
3277
3154
}
3278
3155
···
3276
3169
3277
3170
static int rtl_enable(struct r8152 *tp)
3278
3171
{
3279
-
u32 ocp_data;
3280
-
3281
3172
r8152b_reset_packet_filter(tp);
3282
3173
3283
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3284
-
ocp_data |= CR_RE | CR_TE;
3285
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3174
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE);
3286
3175
3287
3176
switch (tp->version) {
3288
3177
case RTL_VER_01:
···
3386
3283
3387
3284
static int rtl8153_enable(struct r8152 *tp)
3388
3285
{
3389
-
u32 ocp_data;
3390
-
3391
3286
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3392
3287
return -ENODEV;
3393
3288
···
3399
3298
switch (tp->version) {
3400
3299
case RTL_VER_09:
3401
3300
case RTL_VER_14:
3402
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3403
-
ocp_data &= ~FC_PATCH_TASK;
3404
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3301
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
3405
3302
usleep_range(1000, 2000);
3406
-
ocp_data |= FC_PATCH_TASK;
3407
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3303
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
3408
3304
break;
3409
3305
default:
3410
3306
break;
···
3420
3322
return;
3421
3323
}
3422
3324
3423
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3424
-
ocp_data &= ~RCR_ACPT_ALL;
3425
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3325
+
ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL);
3426
3326
3427
3327
rtl_drop_queued_tx(tp);
3428
3328
···
3453
3357
3454
3358
static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3455
3359
{
3456
-
u32 ocp_data;
3457
-
3458
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3459
3360
if (enable)
3460
-
ocp_data |= POWER_CUT;
3361
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT);
3461
3362
else
3462
-
ocp_data &= ~POWER_CUT;
3463
-
ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3363
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT);
3464
3364
3465
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3466
-
ocp_data &= ~RESUME_INDICATE;
3467
-
ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3365
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS,
3366
+
RESUME_INDICATE);
3468
3367
}
3469
3368
3470
3369
static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3471
3370
{
3472
-
u32 ocp_data;
3473
-
3474
3371
switch (tp->version) {
3475
3372
case RTL_VER_01:
3476
3373
case RTL_VER_02:
···
3475
3386
case RTL_VER_08:
3476
3387
case RTL_VER_09:
3477
3388
case RTL_VER_14:
3478
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3479
3389
if (enable)
3480
-
ocp_data |= CPCR_RX_VLAN;
3390
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR,
3391
+
CPCR_RX_VLAN);
3481
3392
else
3482
-
ocp_data &= ~CPCR_RX_VLAN;
3483
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3393
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CPCR,
3394
+
CPCR_RX_VLAN);
3484
3395
break;
3485
3396
3486
3397
case RTL_TEST_01:
···
3490
3401
case RTL_VER_13:
3491
3402
case RTL_VER_15:
3492
3403
default:
3493
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3494
3404
if (enable)
3495
-
ocp_data |= OUTER_VLAN | INNER_VLAN;
3405
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1,
3406
+
OUTER_VLAN | INNER_VLAN);
3496
3407
else
3497
-
ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3498
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3408
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1,
3409
+
OUTER_VLAN | INNER_VLAN);
3499
3410
break;
3500
3411
}
3501
3412
}
···
3556
3467
3557
3468
static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3558
3469
{
3559
-
u32 ocp_data;
3470
+
u16 ocp_data;
3560
3471
3561
3472
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3562
3473
3563
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3564
-
ocp_data &= ~LINK_ON_WAKE_EN;
3565
3474
if (wolopts & WAKE_PHY)
3566
-
ocp_data |= LINK_ON_WAKE_EN;
3567
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3475
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34,
3476
+
LINK_ON_WAKE_EN);
3477
+
else
3478
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34,
3479
+
LINK_ON_WAKE_EN);
3568
3480
3569
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3570
-
ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3481
+
ocp_data = 0;
3571
3482
if (wolopts & WAKE_UCAST)
3572
3483
ocp_data |= UWF_EN;
3573
3484
if (wolopts & WAKE_BCAST)
3574
3485
ocp_data |= BWF_EN;
3575
3486
if (wolopts & WAKE_MCAST)
3576
3487
ocp_data |= MWF_EN;
3577
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3488
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_CONFIG5, UWF_EN | BWF_EN | MWF_EN,
3489
+
ocp_data);
3578
3490
3579
3491
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3580
3492
3581
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3582
-
ocp_data &= ~MAGIC_EN;
3583
3493
if (wolopts & WAKE_MAGIC)
3584
-
ocp_data |= MAGIC_EN;
3585
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3494
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN);
3495
+
else
3496
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN);
3586
3497
3587
3498
if (wolopts & WAKE_ANY)
3588
3499
device_set_wakeup_enable(&tp->udev->dev, true);
···
3592
3503
3593
3504
static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3594
3505
{
3595
-
u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3596
-
3597
3506
/* MAC clock speed down */
3598
3507
if (enable)
3599
-
ocp_data |= MAC_CLK_SPDWN_EN;
3508
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3509
+
MAC_CLK_SPDWN_EN);
3600
3510
else
3601
-
ocp_data &= ~MAC_CLK_SPDWN_EN;
3602
-
3603
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3511
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3512
+
MAC_CLK_SPDWN_EN);
3604
3513
}
3605
3514
3606
3515
static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3607
3516
{
3608
-
u32 ocp_data;
3609
-
3610
3517
/* MAC clock speed down */
3611
3518
if (enable) {
3612
3519
/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3613
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3614
-
0x0403);
3520
+
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0x0403);
3615
3521
3616
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3617
-
ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3618
-
ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3619
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3522
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3523
+
EEE_SPDWN_RATIO_MASK, MAC_CLK_SPDWN_EN | 0x03);
3620
3524
} else {
3621
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3622
-
ocp_data &= ~MAC_CLK_SPDWN_EN;
3623
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3525
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3526
+
MAC_CLK_SPDWN_EN);
3624
3527
}
3625
3528
}
3626
3529
···
3630
3549
3631
3550
static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3632
3551
{
3633
-
u32 ocp_data;
3634
-
3635
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3636
3552
if (enable)
3637
-
ocp_data |= LPM_U1U2_EN;
3553
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG,
3554
+
LPM_U1U2_EN);
3638
3555
else
3639
-
ocp_data &= ~LPM_U1U2_EN;
3640
-
3641
-
ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3556
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG,
3557
+
LPM_U1U2_EN);
3642
3558
}
3643
3559
3644
3560
static void r8153_u2p3en(struct r8152 *tp, bool enable)
3645
3561
{
3646
-
u32 ocp_data;
3647
-
3648
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3649
3562
if (enable)
3650
-
ocp_data |= U2P3_ENABLE;
3563
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE);
3651
3564
else
3652
-
ocp_data &= ~U2P3_ENABLE;
3653
-
ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3565
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE);
3654
3566
}
3655
3567
3656
3568
static void r8153b_ups_flags(struct r8152 *tp)
···
3805
3731
3806
3732
static void rtl_green_en(struct r8152 *tp, bool enable)
3807
3733
{
3808
-
u16 data;
3809
-
3810
-
data = sram_read(tp, SRAM_GREEN_CFG);
3811
3734
if (enable)
3812
-
data |= GREEN_ETH_EN;
3735
+
sram_set_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN);
3813
3736
else
3814
-
data &= ~GREEN_ETH_EN;
3815
-
sram_write(tp, SRAM_GREEN_CFG, data);
3737
+
sram_clr_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN);
3816
3738
3817
3739
tp->ups_info.green = enable;
3818
3740
}
···
3854
3784
3855
3785
static void r8153b_ups_en(struct r8152 *tp, bool enable)
3856
3786
{
3857
-
u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3858
-
3859
3787
if (enable) {
3860
3788
r8153b_ups_flags(tp);
3861
3789
3862
-
ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3863
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3790
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3791
+
UPS_EN | USP_PREWAKE | PHASE2_EN);
3864
3792
3865
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3866
-
ocp_data |= UPS_FORCE_PWR_DOWN;
3867
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3793
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2,
3794
+
UPS_FORCE_PWR_DOWN);
3868
3795
} else {
3869
-
ocp_data &= ~(UPS_EN | USP_PREWAKE);
3870
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3796
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3797
+
UPS_EN | USP_PREWAKE);
3871
3798
3872
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3873
-
ocp_data &= ~UPS_FORCE_PWR_DOWN;
3874
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3799
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2,
3800
+
UPS_FORCE_PWR_DOWN);
3875
3801
3876
3802
if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3877
3803
int i;
···
3891
3825
3892
3826
static void r8153c_ups_en(struct r8152 *tp, bool enable)
3893
3827
{
3894
-
u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3895
-
3896
3828
if (enable) {
3897
3829
r8153b_ups_flags(tp);
3898
3830
3899
-
ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3900
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3831
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3832
+
UPS_EN | USP_PREWAKE | PHASE2_EN);
3901
3833
3902
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3903
-
ocp_data |= UPS_FORCE_PWR_DOWN;
3904
-
ocp_data &= ~BIT(7);
3905
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3834
+
ocp_byte_w0w1(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7),
3835
+
UPS_FORCE_PWR_DOWN);
3906
3836
} else {
3907
-
ocp_data &= ~(UPS_EN | USP_PREWAKE);
3908
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3837
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3838
+
UPS_EN | USP_PREWAKE);
3909
3839
3910
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3911
-
ocp_data &= ~UPS_FORCE_PWR_DOWN;
3912
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3840
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2,
3841
+
UPS_FORCE_PWR_DOWN);
3913
3842
3914
3843
if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3915
3844
int i;
···
3926
3865
3927
3866
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3928
3867
3929
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3930
-
ocp_data |= BIT(8);
3931
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3868
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8));
3932
3869
3933
3870
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3934
3871
}
···
3934
3875
3935
3876
static void r8156_ups_en(struct r8152 *tp, bool enable)
3936
3877
{
3937
-
u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3938
-
3939
3878
if (enable) {
3940
3879
r8156_ups_flags(tp);
3941
3880
3942
-
ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3943
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3881
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3882
+
UPS_EN | USP_PREWAKE | PHASE2_EN);
3944
3883
3945
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3946
-
ocp_data |= UPS_FORCE_PWR_DOWN;
3947
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3884
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2,
3885
+
UPS_FORCE_PWR_DOWN);
3948
3886
3949
3887
switch (tp->version) {
3950
3888
case RTL_VER_13:
3951
3889
case RTL_VER_15:
3952
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3953
-
ocp_data &= ~OOBS_POLLING;
3954
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3890
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPHY_XTAL,
3891
+
OOBS_POLLING);
3955
3892
break;
3956
3893
default:
3957
3894
break;
3958
3895
}
3959
3896
} else {
3960
-
ocp_data &= ~(UPS_EN | USP_PREWAKE);
3961
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3897
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3898
+
UPS_EN | USP_PREWAKE);
3962
3899
3963
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3964
-
ocp_data &= ~UPS_FORCE_PWR_DOWN;
3965
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3900
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2,
3901
+
UPS_FORCE_PWR_DOWN);
3966
3902
3967
3903
if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3968
3904
tp->rtl_ops.hw_phy_cfg(tp);
···
3970
3916
3971
3917
static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3972
3918
{
3973
-
u32 ocp_data;
3974
-
3975
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3976
3919
if (enable)
3977
-
ocp_data |= PWR_EN | PHASE2_EN;
3920
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3921
+
PWR_EN | PHASE2_EN);
3978
3922
else
3979
-
ocp_data &= ~(PWR_EN | PHASE2_EN);
3980
-
ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3923
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3924
+
PWR_EN | PHASE2_EN);
3981
3925
3982
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3983
-
ocp_data &= ~PCUT_STATUS;
3984
-
ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3926
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS);
3985
3927
}
3986
3928
3987
3929
static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3988
3930
{
3989
-
u32 ocp_data;
3990
-
3991
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3992
3931
if (enable)
3993
-
ocp_data |= PWR_EN | PHASE2_EN;
3932
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT,
3933
+
PWR_EN | PHASE2_EN);
3994
3934
else
3995
-
ocp_data &= ~PWR_EN;
3996
-
ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3935
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN);
3997
3936
3998
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3999
-
ocp_data &= ~PCUT_STATUS;
4000
-
ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3937
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS);
4001
3938
}
4002
3939
4003
3940
static void r8153_queue_wake(struct r8152 *tp, bool enable)
4004
3941
{
4005
-
u32 ocp_data;
4006
-
4007
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
4008
3942
if (enable)
4009
-
ocp_data |= UPCOMING_RUNTIME_D3;
3943
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG,
3944
+
UPCOMING_RUNTIME_D3);
4010
3945
else
4011
-
ocp_data &= ~UPCOMING_RUNTIME_D3;
4012
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3946
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG,
3947
+
UPCOMING_RUNTIME_D3);
4013
3948
4014
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
4015
-
ocp_data &= ~LINK_CHG_EVENT;
4016
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
4017
-
4018
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
4019
-
ocp_data &= ~LINK_CHANGE_FLAG;
4020
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3949
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, LINK_CHG_EVENT);
3950
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, LINK_CHANGE_FLAG);
4021
3951
}
4022
3952
4023
3953
static bool rtl_can_wakeup(struct r8152 *tp)
···
4014
3976
static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
4015
3977
{
4016
3978
if (enable) {
4017
-
u32 ocp_data;
4018
-
4019
3979
__rtl_set_wol(tp, WAKE_ANY);
4020
3980
4021
3981
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
4022
3982
4023
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
4024
-
ocp_data |= LINK_OFF_WAKE_EN;
4025
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3983
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34,
3984
+
LINK_OFF_WAKE_EN);
4026
3985
4027
3986
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4028
3987
} else {
4029
-
u32 ocp_data;
4030
-
4031
3988
__rtl_set_wol(tp, tp->saved_wolopts);
4032
3989
4033
3990
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
4034
3991
4035
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
4036
-
ocp_data &= ~LINK_OFF_WAKE_EN;
4037
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3992
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34,
3993
+
LINK_OFF_WAKE_EN);
4038
3994
4039
3995
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4040
3996
}
···
4109
4077
4110
4078
static void r8153_teredo_off(struct r8152 *tp)
4111
4079
{
4112
-
u32 ocp_data;
4113
-
4114
4080
switch (tp->version) {
4115
4081
case RTL_VER_01:
4116
4082
case RTL_VER_02:
···
4117
4087
case RTL_VER_05:
4118
4088
case RTL_VER_06:
4119
4089
case RTL_VER_07:
4120
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4121
-
ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4122
-
OOB_TEREDO_EN);
4123
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4090
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG,
4091
+
TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4092
+
OOB_TEREDO_EN);
4124
4093
break;
4125
4094
4126
4095
case RTL_VER_08:
···
4146
4117
4147
4118
static void rtl_reset_bmu(struct r8152 *tp)
4148
4119
{
4149
-
u32 ocp_data;
4150
-
4151
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4152
-
ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4153
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4154
-
ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4155
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
4120
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET,
4121
+
BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4122
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET,
4123
+
BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4156
4124
}
4157
4125
4158
4126
/* Clear the bp to stop the firmware before loading a new one */
···
4204
4178
4205
4179
static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4206
4180
{
4207
-
u16 data, check;
4181
+
u16 check;
4208
4182
int i;
4209
4183
4210
-
data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4211
4184
if (request) {
4212
-
data |= PATCH_REQUEST;
4185
+
ocp_reg_set_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST);
4213
4186
check = 0;
4214
4187
} else {
4215
-
data &= ~PATCH_REQUEST;
4188
+
ocp_reg_clr_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST);
4216
4189
check = PATCH_READY;
4217
4190
}
4218
-
ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4219
4191
4220
4192
for (i = 0; wait && i < 5000; i++) {
4221
4193
u32 ocp_data;
···
4243
4219
sram_write(tp, key_addr, patch_key);
4244
4220
sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4245
4221
} else if (key_addr) {
4246
-
u16 data;
4247
-
4248
4222
sram_write(tp, 0x0000, 0x0000);
4249
-
4250
-
data = ocp_reg_read(tp, OCP_PHY_LOCK);
4251
-
data &= ~PATCH_LOCK;
4252
-
ocp_reg_write(tp, OCP_PHY_LOCK, data);
4253
-
4223
+
ocp_reg_clr_bits(tp, OCP_PHY_LOCK, PATCH_LOCK);
4254
4224
sram_write(tp, key_addr, 0x0000);
4255
4225
} else {
4256
4226
WARN_ON_ONCE(1);
···
4962
4944
return;
4963
4945
4964
4946
while (len) {
4965
-
u32 ocp_data, size;
4947
+
u32 size;
4966
4948
int i;
4967
4949
4968
4950
if (len < 2048)
···
4970
4952
else
4971
4953
size = 2048;
4972
4954
4973
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4974
-
ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4975
-
ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4955
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_GPHY_CTRL,
4956
+
GPHY_PATCH_DONE | BACKUP_RESTRORE);
4976
4957
4977
4958
generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4978
4959
4979
4960
data += size;
4980
4961
len -= size;
4981
4962
4982
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4983
-
ocp_data |= POL_GPHY_PATCH;
4984
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4963
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL,
4964
+
POL_GPHY_PATCH);
4985
4965
4986
4966
for (i = 0; i < 1000; i++) {
4987
4967
if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
···
5352
5336
5353
5337
static void r8152_eee_en(struct r8152 *tp, bool enable)
5354
5338
{
5355
-
u16 config1, config2, config3;
5356
-
u32 ocp_data;
5357
-
5358
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5359
-
config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5360
-
config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5361
-
config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5362
-
5363
5339
if (enable) {
5364
-
ocp_data |= EEE_RX_EN | EEE_TX_EN;
5365
-
config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5366
-
config1 |= sd_rise_time(1);
5367
-
config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5368
-
config3 |= fast_snr(42);
5369
-
} else {
5370
-
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5371
-
config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5372
-
RX_QUIET_EN);
5373
-
config1 |= sd_rise_time(7);
5374
-
config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5375
-
config3 |= fast_snr(511);
5376
-
}
5340
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR,
5341
+
EEE_RX_EN | EEE_TX_EN);
5377
5342
5378
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5379
-
ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5380
-
ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5381
-
ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5343
+
ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask,
5344
+
EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5345
+
RX_QUIET_EN | sd_rise_time(1));
5346
+
5347
+
ocp_reg_set_bits(tp, OCP_EEE_CONFIG2,
5348
+
RG_DACQUIET_EN | RG_LDVQUIET_EN);
5349
+
5350
+
ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(42));
5351
+
} else {
5352
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR,
5353
+
EEE_RX_EN | EEE_TX_EN);
5354
+
5355
+
ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask |
5356
+
EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5357
+
RX_QUIET_EN, sd_rise_time(7));
5358
+
5359
+
ocp_reg_clr_bits(tp, OCP_EEE_CONFIG2,
5360
+
RG_DACQUIET_EN | RG_LDVQUIET_EN);
5361
+
5362
+
ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(511));
5363
+
}
5382
5364
}
5383
5365
5384
5366
static void r8153_eee_en(struct r8152 *tp, bool enable)
5385
5367
{
5386
-
u32 ocp_data;
5387
-
u16 config;
5388
-
5389
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5390
-
config = ocp_reg_read(tp, OCP_EEE_CFG);
5391
-
5392
5368
if (enable) {
5393
-
ocp_data |= EEE_RX_EN | EEE_TX_EN;
5394
-
config |= EEE10_EN;
5395
-
} else {
5396
-
ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5397
-
config &= ~EEE10_EN;
5398
-
}
5369
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR,
5370
+
EEE_RX_EN | EEE_TX_EN);
5399
5371
5400
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5401
-
ocp_reg_write(tp, OCP_EEE_CFG, config);
5372
+
ocp_reg_set_bits(tp, OCP_EEE_CFG, EEE10_EN);
5373
+
} else {
5374
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR,
5375
+
EEE_RX_EN | EEE_TX_EN);
5376
+
5377
+
ocp_reg_clr_bits(tp, OCP_EEE_CFG, EEE10_EN);
5378
+
}
5402
5379
5403
5380
tp->ups_info.eee = enable;
5404
5381
}
5405
5382
5406
5383
static void r8156_eee_en(struct r8152 *tp, bool enable)
5407
5384
{
5408
-
u16 config;
5409
-
5410
5385
r8153_eee_en(tp, enable);
5411
5386
5412
-
config = ocp_reg_read(tp, OCP_EEE_ADV2);
5413
-
5414
5387
if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT))
5415
-
config |= MDIO_EEE_2_5GT;
5388
+
ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT);
5416
5389
else
5417
-
config &= ~MDIO_EEE_2_5GT;
5418
-
5419
-
ocp_reg_write(tp, OCP_EEE_ADV2, config);
5390
+
ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT);
5420
5391
}
5421
5392
5422
5393
static void rtl_eee_enable(struct r8152 *tp, bool enable)
···
5456
5453
5457
5454
static void r8152b_enable_fc(struct r8152 *tp)
5458
5455
{
5459
-
u16 anar;
5460
-
5461
-
anar = r8152_mdio_read(tp, MII_ADVERTISE);
5462
-
anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5463
-
r8152_mdio_write(tp, MII_ADVERTISE, anar);
5456
+
r8152_mdio_set_bit(tp, MII_ADVERTISE,
5457
+
ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
5464
5458
5465
5459
tp->ups_info.flow_control = true;
5466
5460
}
···
5512
5512
5513
5513
static void r8152b_exit_oob(struct r8152 *tp)
5514
5514
{
5515
-
u32 ocp_data;
5516
-
5517
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5518
-
ocp_data &= ~RCR_ACPT_ALL;
5519
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5515
+
ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL);
5520
5516
5521
5517
rxdy_gated_en(tp, true);
5522
5518
r8153_teredo_off(tp);
5523
5519
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5524
5520
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5525
5521
5526
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5527
-
ocp_data &= ~NOW_IS_OOB;
5528
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5522
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
5529
5523
5530
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5531
-
ocp_data &= ~MCU_BORW_EN;
5532
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5524
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
5533
5525
5534
5526
wait_oob_link_list_ready(tp);
5535
5527
5536
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5537
-
ocp_data |= RE_INIT_LL;
5538
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5528
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL);
5539
5529
5540
5530
wait_oob_link_list_ready(tp);
5541
5531
···
5561
5571
5562
5572
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5563
5573
5564
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5565
-
ocp_data |= TCR0_AUTO_FIFO;
5566
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5574
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO);
5567
5575
}
5568
5576
5569
5577
static void r8152b_enter_oob(struct r8152 *tp)
5570
5578
{
5571
-
u32 ocp_data;
5572
-
5573
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5574
-
ocp_data &= ~NOW_IS_OOB;
5575
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5579
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
5576
5580
5577
5581
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5578
5582
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
···
5576
5592
5577
5593
wait_oob_link_list_ready(tp);
5578
5594
5579
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5580
-
ocp_data |= RE_INIT_LL;
5581
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5595
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL);
5582
5596
5583
5597
wait_oob_link_list_ready(tp);
5584
5598
···
5584
5602
5585
5603
rtl_rx_vlan_en(tp, true);
5586
5604
5587
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5588
-
ocp_data |= ALDPS_PROXY_MODE;
5589
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5605
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE);
5590
5606
5591
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5592
-
ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5593
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5607
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL,
5608
+
NOW_IS_OOB | DIS_MCU_CLROOB);
5594
5609
5595
5610
rxdy_gated_en(tp, false);
5596
5611
5597
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5598
-
ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5599
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5612
+
ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR,
5613
+
RCR_APM | RCR_AM | RCR_AB);
5600
5614
}
5601
5615
5602
5616
static int r8153_pre_firmware_1(struct r8152 *tp)
···
5627
5649
5628
5650
static int r8153_pre_firmware_2(struct r8152 *tp)
5629
5651
{
5630
-
u32 ocp_data;
5631
-
5632
5652
r8153_pre_firmware_1(tp);
5633
5653
5634
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5635
-
ocp_data &= ~FW_FIX_SUSPEND;
5636
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5654
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND);
5637
5655
5638
5656
return 0;
5639
5657
}
5640
5658
5641
5659
static int r8153_post_firmware_2(struct r8152 *tp)
5642
5660
{
5643
-
u32 ocp_data;
5644
-
5645
5661
/* enable bp0 if support USB_SPEED_SUPER only */
5646
-
if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5647
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5648
-
ocp_data |= BIT(0);
5649
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5650
-
}
5662
+
if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5663
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0));
5651
5664
5652
5665
/* reset UPHY timer to 36 ms */
5653
5666
ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
···
5646
5677
/* enable U3P3 check, set the counter to 4 */
5647
5678
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5648
5679
5649
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5650
-
ocp_data |= FW_FIX_SUSPEND;
5651
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5680
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND);
5652
5681
5653
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5654
-
ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5655
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5682
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY,
5683
+
USB2PHY_L1 | USB2PHY_SUSPEND);
5656
5684
5657
5685
return 0;
5658
5686
}
5659
5687
5660
5688
static int r8153_post_firmware_3(struct r8152 *tp)
5661
5689
{
5662
-
u32 ocp_data;
5690
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY,
5691
+
USB2PHY_L1 | USB2PHY_SUSPEND);
5663
5692
5664
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5665
-
ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5666
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5667
-
5668
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5669
-
ocp_data |= FW_IP_RESET_EN;
5670
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5693
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN);
5671
5694
5672
5695
return 0;
5673
5696
}
···
5679
5718
5680
5719
/* enable bp0 for RTL8153-BND */
5681
5720
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5682
-
if (ocp_data & BND_MASK) {
5683
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5684
-
ocp_data |= BIT(0);
5685
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5686
-
}
5721
+
if (ocp_data & BND_MASK)
5722
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0));
5687
5723
5688
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5689
-
ocp_data |= FLOW_CTRL_PATCH_OPT;
5690
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5724
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_OPT);
5691
5725
5692
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5693
-
ocp_data |= FC_PATCH_TASK;
5694
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5726
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
5695
5727
5696
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5697
-
ocp_data |= FW_IP_RESET_EN;
5698
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5728
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN);
5699
5729
5700
5730
return 0;
5701
5731
}
5702
5732
5703
5733
static int r8153c_post_firmware_1(struct r8152 *tp)
5704
5734
{
5705
-
u32 ocp_data;
5735
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_2);
5706
5736
5707
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5708
-
ocp_data |= FLOW_CTRL_PATCH_2;
5709
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5710
-
5711
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5712
-
ocp_data |= FC_PATCH_TASK;
5713
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5737
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
5714
5738
5715
5739
return 0;
5716
5740
}
5717
5741
5718
5742
static int r8156a_post_firmware_1(struct r8152 *tp)
5719
5743
{
5720
-
u32 ocp_data;
5721
-
5722
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5723
-
ocp_data |= FW_IP_RESET_EN;
5724
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5744
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN);
5725
5745
5726
5746
/* Modify U3PHY parameter for compatibility issue */
5727
5747
ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
···
5713
5771
5714
5772
static void r8153_aldps_en(struct r8152 *tp, bool enable)
5715
5773
{
5716
-
u16 data;
5717
-
5718
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
5719
5774
if (enable) {
5720
-
data |= EN_ALDPS;
5721
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
5775
+
ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_ALDPS);
5722
5776
} else {
5723
5777
int i;
5724
5778
5725
-
data &= ~EN_ALDPS;
5726
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
5779
+
ocp_reg_clr_bits(tp, OCP_POWER_CFG, EN_ALDPS);
5727
5780
for (i = 0; i < 20; i++) {
5728
5781
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5729
5782
return;
···
5733
5796
5734
5797
static void r8153_hw_phy_cfg(struct r8152 *tp)
5735
5798
{
5736
-
u32 ocp_data;
5737
-
u16 data;
5738
-
5739
5799
/* disable ALDPS before updating the PHY parameters */
5740
5800
r8153_aldps_en(tp, false);
5741
5801
···
5741
5807
5742
5808
rtl8152_apply_firmware(tp, false);
5743
5809
5744
-
if (tp->version == RTL_VER_03) {
5745
-
data = ocp_reg_read(tp, OCP_EEE_CFG);
5746
-
data &= ~CTAP_SHORT_EN;
5747
-
ocp_reg_write(tp, OCP_EEE_CFG, data);
5748
-
}
5810
+
if (tp->version == RTL_VER_03)
5811
+
ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN);
5749
5812
5750
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
5751
-
data |= EEE_CLKDIV_EN;
5752
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
5813
+
ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
5753
5814
5754
-
data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5755
-
data |= EN_10M_BGOFF;
5756
-
ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5757
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
5758
-
data |= EN_10M_PLLOFF;
5759
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
5815
+
ocp_reg_set_bits(tp, OCP_DOWN_SPEED, EN_10M_BGOFF);
5816
+
5817
+
ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF);
5818
+
5760
5819
sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5761
5820
5762
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5763
-
ocp_data |= PFM_PWM_SWITCH;
5764
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5821
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH);
5765
5822
5766
5823
/* Enable LPF corner auto tune */
5767
5824
sram_write(tp, SRAM_LPF_CFG, 0xf70f);
···
5798
5873
u32 ocp_data;
5799
5874
u16 data;
5800
5875
5801
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5802
-
if (ocp_data & PCUT_STATUS) {
5803
-
ocp_data &= ~PCUT_STATUS;
5804
-
ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5805
-
}
5876
+
ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS);
5806
5877
5807
5878
/* disable ALDPS before updating the PHY parameters */
5808
5879
r8153_aldps_en(tp, false);
···
5816
5895
case PHY_STAT_EXT_INIT:
5817
5896
rtl8152_apply_firmware(tp, true);
5818
5897
5819
-
data = r8152_mdio_read(tp, MII_BMCR);
5820
-
data &= ~BMCR_PDOWN;
5821
-
r8152_mdio_write(tp, MII_BMCR, data);
5898
+
r8152_mdio_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
5822
5899
break;
5823
5900
case PHY_STAT_LAN_ON:
5824
5901
default:
···
5826
5907
5827
5908
r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5828
5909
5829
-
data = sram_read(tp, SRAM_GREEN_CFG);
5830
-
data |= R_TUNE_EN;
5831
-
sram_write(tp, SRAM_GREEN_CFG, data);
5832
-
data = ocp_reg_read(tp, OCP_NCTL_CFG);
5833
-
data |= PGA_RETURN_EN;
5834
-
ocp_reg_write(tp, OCP_NCTL_CFG, data);
5910
+
sram_set_bits(tp, SRAM_GREEN_CFG, R_TUNE_EN);
5911
+
5912
+
ocp_reg_set_bits(tp, OCP_NCTL_CFG, PGA_RETURN_EN);
5835
5913
5836
5914
/* ADC Bias Calibration:
5837
5915
* read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
···
5850
5934
u32 swr_cnt_1ms_ini;
5851
5935
5852
5936
swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5853
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5854
-
ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5855
-
ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5937
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_UPS_CFG, SAW_CNT_1MS_MASK,
5938
+
swr_cnt_1ms_ini);
5856
5939
}
5857
5940
5858
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5859
-
ocp_data |= PFM_PWM_SWITCH;
5860
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5941
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH);
5861
5942
5862
5943
/* Advnace EEE */
5863
5944
if (!rtl_phy_patch_request(tp, true, true)) {
5864
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
5865
-
data |= EEE_CLKDIV_EN;
5866
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
5945
+
ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
5867
5946
tp->ups_info.eee_ckdiv = true;
5868
5947
5869
-
data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5870
-
data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5871
-
ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5948
+
ocp_reg_set_bits(tp, OCP_DOWN_SPEED,
5949
+
EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV);
5872
5950
tp->ups_info.eee_cmod_lv = true;
5873
5951
tp->ups_info._10m_ckdiv = true;
5874
5952
tp->ups_info.eee_plloff_giga = true;
···
5898
5988
5899
5989
static void r8153_first_init(struct r8152 *tp)
5900
5990
{
5901
-
u32 ocp_data;
5902
-
5903
5991
rxdy_gated_en(tp, true);
5904
5992
r8153_teredo_off(tp);
5905
5993
5906
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5907
-
ocp_data &= ~RCR_ACPT_ALL;
5908
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5994
+
ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL);
5909
5995
5910
5996
rtl8152_nic_reset(tp);
5911
5997
rtl_reset_bmu(tp);
5912
5998
5913
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5914
-
ocp_data &= ~NOW_IS_OOB;
5915
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5999
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
5916
6000
5917
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5918
-
ocp_data &= ~MCU_BORW_EN;
5919
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6001
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
5920
6002
5921
6003
wait_oob_link_list_ready(tp);
5922
6004
5923
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5924
-
ocp_data |= RE_INIT_LL;
5925
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6005
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL);
5926
6006
5927
6007
wait_oob_link_list_ready(tp);
5928
6008
···
5920
6020
5921
6021
rtl8153_change_mtu(tp);
5922
6022
5923
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5924
-
ocp_data |= TCR0_AUTO_FIFO;
5925
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
6023
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO);
5926
6024
5927
6025
rtl8152_nic_reset(tp);
5928
6026
···
5934
6036
5935
6037
static void r8153_enter_oob(struct r8152 *tp)
5936
6038
{
5937
-
u32 ocp_data;
5938
-
5939
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5940
-
ocp_data &= ~NOW_IS_OOB;
5941
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6039
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
5942
6040
5943
6041
/* RX FIFO settings for OOB */
5944
6042
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
···
5946
6052
5947
6053
wait_oob_link_list_ready(tp);
5948
6054
5949
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5950
-
ocp_data |= RE_INIT_LL;
5951
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6055
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL);
5952
6056
5953
6057
wait_oob_link_list_ready(tp);
5954
6058
···
5958
6066
case RTL_VER_04:
5959
6067
case RTL_VER_05:
5960
6068
case RTL_VER_06:
5961
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5962
-
ocp_data &= ~TEREDO_WAKE_MASK;
5963
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
6069
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG,
6070
+
TEREDO_WAKE_MASK);
5964
6071
break;
5965
6072
5966
6073
case RTL_VER_08:
···
5978
6087
5979
6088
rtl_rx_vlan_en(tp, true);
5980
6089
5981
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5982
-
ocp_data |= ALDPS_PROXY_MODE;
5983
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
6090
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE);
5984
6091
5985
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5986
-
ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5987
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6092
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL,
6093
+
NOW_IS_OOB | DIS_MCU_CLROOB);
5988
6094
5989
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5990
-
ocp_data |= MCU_BORW_EN;
5991
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6095
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
5992
6096
5993
6097
rxdy_gated_en(tp, false);
5994
6098
5995
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5996
-
ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5997
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6099
+
ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR,
6100
+
RCR_APM | RCR_AM | RCR_AB);
5998
6101
}
5999
6102
6000
6103
static void rtl8153_disable(struct r8152 *tp)
···
6020
6135
6021
6136
static int rtl8156_enable(struct r8152 *tp)
6022
6137
{
6023
-
u32 ocp_data;
6024
6138
u16 speed;
6025
6139
6026
6140
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
···
6034
6150
speed = rtl8152_get_speed(tp);
6035
6151
rtl_set_ifg(tp, speed);
6036
6152
6037
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6038
6153
if (speed & _2500bps)
6039
-
ocp_data &= ~IDLE_SPDWN_EN;
6154
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
6155
+
IDLE_SPDWN_EN);
6040
6156
else
6041
-
ocp_data |= IDLE_SPDWN_EN;
6042
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6157
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
6158
+
IDLE_SPDWN_EN);
6043
6159
6044
6160
if (speed & _1000bps)
6045
6161
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
···
6048
6164
6049
6165
if (tp->udev->speed == USB_SPEED_HIGH) {
6050
6166
/* USB 0xb45e[3:0] l1_nyet_hird */
6051
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6052
-
ocp_data &= ~0xf;
6053
6167
if (is_flow_control(speed))
6054
-
ocp_data |= 0xf;
6168
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf);
6055
6169
else
6056
-
ocp_data |= 0x1;
6057
-
ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6170
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1);
6058
6171
}
6059
6172
6060
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6061
-
ocp_data &= ~FC_PATCH_TASK;
6062
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6173
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
6063
6174
usleep_range(1000, 2000);
6064
-
ocp_data |= FC_PATCH_TASK;
6065
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6175
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
6066
6176
6067
6177
return rtl_enable(tp);
6068
6178
}
···
6071
6193
6072
6194
static int rtl8156b_enable(struct r8152 *tp)
6073
6195
{
6074
-
u32 ocp_data;
6075
6196
u16 speed;
6076
6197
6077
6198
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
···
6079
6202
set_tx_qlen(tp);
6080
6203
rtl_set_eee_plus(tp);
6081
6204
6082
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6083
-
ocp_data &= ~RX_AGGR_NUM_MASK;
6084
-
ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6205
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK);
6085
6206
6086
6207
r8153_set_rx_early_timeout(tp);
6087
6208
r8153_set_rx_early_size(tp);
···
6087
6212
speed = rtl8152_get_speed(tp);
6088
6213
rtl_set_ifg(tp, speed);
6089
6214
6090
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6091
6215
if (speed & _2500bps)
6092
-
ocp_data &= ~IDLE_SPDWN_EN;
6216
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
6217
+
IDLE_SPDWN_EN);
6093
6218
else
6094
-
ocp_data |= IDLE_SPDWN_EN;
6095
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6219
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
6220
+
IDLE_SPDWN_EN);
6096
6221
6097
6222
if (tp->udev->speed == USB_SPEED_HIGH) {
6098
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6099
-
ocp_data &= ~0xf;
6100
6223
if (is_flow_control(speed))
6101
-
ocp_data |= 0xf;
6224
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf);
6102
6225
else
6103
-
ocp_data |= 0x1;
6104
-
ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6226
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1);
6105
6227
}
6106
6228
6107
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6108
-
ocp_data &= ~FC_PATCH_TASK;
6109
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6229
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
6110
6230
usleep_range(1000, 2000);
6111
-
ocp_data |= FC_PATCH_TASK;
6112
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6231
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
6113
6232
6114
6233
return rtl_enable(tp);
6115
6234
}
···
6274
6405
6275
6406
static void rtl8153_up(struct r8152 *tp)
6276
6407
{
6277
-
u32 ocp_data;
6278
-
6279
6408
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6280
6409
return;
6281
6410
···
6282
6415
r8153_aldps_en(tp, false);
6283
6416
r8153_first_init(tp);
6284
6417
6285
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6286
-
ocp_data |= LANWAKE_CLR_EN;
6287
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6418
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN);
6288
6419
6289
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6290
-
ocp_data &= ~LANWAKE_PIN;
6291
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6420
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN);
6292
6421
6293
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6294
-
ocp_data &= ~DELAY_PHY_PWR_CHG;
6295
-
ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6422
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SSPHYLINK1, DELAY_PHY_PWR_CHG);
6296
6423
6297
6424
r8153_aldps_en(tp, true);
6298
6425
···
6306
6445
6307
6446
static void rtl8153_down(struct r8152 *tp)
6308
6447
{
6309
-
u32 ocp_data;
6310
-
6311
6448
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6312
6449
rtl_drop_queued_tx(tp);
6313
6450
return;
6314
6451
}
6315
6452
6316
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6317
-
ocp_data &= ~LANWAKE_CLR_EN;
6318
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6453
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN);
6319
6454
6320
6455
r8153_u1u2en(tp, false);
6321
6456
r8153_u2p3en(tp, false);
···
6323
6466
6324
6467
static void rtl8153b_up(struct r8152 *tp)
6325
6468
{
6326
-
u32 ocp_data;
6327
-
6328
6469
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6329
6470
return;
6330
6471
···
6333
6478
r8153_first_init(tp);
6334
6479
ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6335
6480
6336
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6337
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
6338
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6481
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
6482
+
PLA_MCU_SPDWN_EN);
6339
6483
6340
6484
r8153_aldps_en(tp, true);
6341
6485
···
6344
6490
6345
6491
static void rtl8153b_down(struct r8152 *tp)
6346
6492
{
6347
-
u32 ocp_data;
6348
-
6349
6493
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6350
6494
rtl_drop_queued_tx(tp);
6351
6495
return;
6352
6496
}
6353
6497
6354
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6355
-
ocp_data |= PLA_MCU_SPDWN_EN;
6356
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6498
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
6499
+
PLA_MCU_SPDWN_EN);
6357
6500
6358
6501
r8153b_u1u2en(tp, false);
6359
6502
r8153_u2p3en(tp, false);
···
6378
6527
6379
6528
static void rtl8153c_up(struct r8152 *tp)
6380
6529
{
6381
-
u32 ocp_data;
6382
-
6383
6530
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6384
6531
return;
6385
6532
···
6388
6539
rxdy_gated_en(tp, true);
6389
6540
r8153_teredo_off(tp);
6390
6541
6391
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6392
-
ocp_data &= ~RCR_ACPT_ALL;
6393
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6542
+
ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL);
6394
6543
6395
6544
rtl8152_nic_reset(tp);
6396
6545
rtl_reset_bmu(tp);
6397
6546
6398
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6399
-
ocp_data &= ~NOW_IS_OOB;
6400
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6547
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
6401
6548
6402
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6403
-
ocp_data &= ~MCU_BORW_EN;
6404
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6549
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
6405
6550
6406
6551
wait_oob_link_list_ready(tp);
6407
6552
6408
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6409
-
ocp_data |= RE_INIT_LL;
6410
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6553
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL);
6411
6554
6412
6555
wait_oob_link_list_ready(tp);
6413
6556
···
6419
6578
6420
6579
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6421
6580
6422
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6423
-
ocp_data |= BIT(8);
6424
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6581
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8));
6425
6582
6426
6583
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6427
6584
6428
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6429
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
6430
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6585
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
6586
+
PLA_MCU_SPDWN_EN);
6431
6587
6432
6588
r8153_aldps_en(tp, true);
6433
6589
r8153b_u1u2en(tp, true);
···
6446
6608
6447
6609
static void rtl8156_up(struct r8152 *tp)
6448
6610
{
6449
-
u32 ocp_data;
6450
-
6451
6611
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6452
6612
return;
6453
6613
···
6456
6620
rxdy_gated_en(tp, true);
6457
6621
r8153_teredo_off(tp);
6458
6622
6459
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6460
-
ocp_data &= ~RCR_ACPT_ALL;
6461
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6623
+
ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL);
6462
6624
6463
6625
rtl8152_nic_reset(tp);
6464
6626
rtl_reset_bmu(tp);
6465
6627
6466
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6467
-
ocp_data &= ~NOW_IS_OOB;
6468
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6628
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
6469
6629
6470
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6471
-
ocp_data &= ~MCU_BORW_EN;
6472
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6630
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
6473
6631
6474
6632
rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6475
6633
···
6473
6643
case RTL_TEST_01:
6474
6644
case RTL_VER_10:
6475
6645
case RTL_VER_11:
6476
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6477
-
ocp_data |= ACT_ODMA;
6478
-
ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6646
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA);
6479
6647
break;
6480
6648
default:
6481
6649
break;
6482
6650
}
6483
6651
6484
6652
/* share FIFO settings */
6485
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6486
-
ocp_data &= ~RXFIFO_FULL_MASK;
6487
-
ocp_data |= 0x08;
6488
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6653
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK,
6654
+
0x08);
6489
6655
6490
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6491
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
6492
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6656
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
6657
+
PLA_MCU_SPDWN_EN);
6493
6658
6494
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6495
-
ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6496
-
ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6659
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION,
6660
+
RG_PWRDN_EN | ALL_SPEED_OFF);
6497
6661
6498
6662
ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6499
6663
···
6505
6681
6506
6682
static void rtl8156_down(struct r8152 *tp)
6507
6683
{
6508
-
u32 ocp_data;
6509
-
6510
6684
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6511
6685
rtl_drop_queued_tx(tp);
6512
6686
return;
6513
6687
}
6514
6688
6515
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6516
-
ocp_data |= PLA_MCU_SPDWN_EN;
6517
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6689
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
6690
+
PLA_MCU_SPDWN_EN);
6518
6691
6519
6692
r8153b_u1u2en(tp, false);
6520
6693
r8153_u2p3en(tp, false);
6521
6694
r8153b_power_cut_en(tp, false);
6522
6695
r8153_aldps_en(tp, false);
6523
6696
6524
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6525
-
ocp_data &= ~NOW_IS_OOB;
6526
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6697
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
6527
6698
6528
6699
/* RX FIFO settings for OOB */
6529
6700
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
···
6537
6718
*/
6538
6719
ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6539
6720
6540
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6541
-
ocp_data |= NOW_IS_OOB;
6542
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6721
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB);
6543
6722
6544
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6545
-
ocp_data |= MCU_BORW_EN;
6546
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6723
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN);
6547
6724
6548
6725
rtl_rx_vlan_en(tp, true);
6549
6726
rxdy_gated_en(tp, false);
6550
6727
6551
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6552
-
ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6553
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6728
+
ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR,
6729
+
RCR_APM | RCR_AM | RCR_AB);
6554
6730
6555
6731
r8153_aldps_en(tp, true);
6556
6732
}
···
6822
7008
6823
7009
static void rtl_tally_reset(struct r8152 *tp)
6824
7010
{
6825
-
u32 ocp_data;
6826
-
6827
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6828
-
ocp_data |= TALLY_RESET;
6829
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
7011
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RSTTALLY, TALLY_RESET);
6830
7012
}
6831
7013
6832
7014
static void r8152b_init(struct r8152 *tp)
6833
7015
{
6834
7016
u32 ocp_data;
6835
-
u16 data;
6836
7017
6837
7018
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6838
7019
return;
6839
7020
6840
-
data = r8152_mdio_read(tp, MII_BMCR);
6841
-
if (data & BMCR_PDOWN) {
6842
-
data &= ~BMCR_PDOWN;
6843
-
r8152_mdio_write(tp, MII_BMCR, data);
6844
-
}
7021
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
6845
7022
6846
7023
r8152_aldps_en(tp, false);
6847
7024
6848
-
if (tp->version == RTL_VER_01) {
6849
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6850
-
ocp_data &= ~LED_MODE_MASK;
6851
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6852
-
}
7025
+
if (tp->version == RTL_VER_01)
7026
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE,
7027
+
LED_MODE_MASK);
6853
7028
6854
7029
r8152_power_cut_en(tp, false);
6855
7030
6856
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6857
-
ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6858
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6859
-
ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6860
-
ocp_data &= ~MCU_CLK_RATIO_MASK;
6861
-
ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6862
-
ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
7031
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR,
7032
+
TX_10M_IDLE_EN | PFM_PWM_SWITCH);
7033
+
7034
+
ocp_dword_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, MCU_CLK_RATIO_MASK,
7035
+
MCU_CLK_RATIO | D3_CLK_GATED_EN);
7036
+
6863
7037
ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6864
7038
SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6865
7039
ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
···
6855
7053
rtl_tally_reset(tp);
6856
7054
6857
7055
/* enable rx aggregation */
6858
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6859
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6860
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7056
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
7057
+
RX_AGG_DISABLE | RX_ZERO_EN);
6861
7058
}
6862
7059
6863
7060
static void r8153_init(struct r8152 *tp)
6864
7061
{
6865
7062
u32 ocp_data;
6866
-
u16 data;
6867
7063
int i;
6868
7064
6869
7065
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
···
6879
7079
break;
6880
7080
}
6881
7081
6882
-
data = r8153_phy_status(tp, 0);
7082
+
r8153_phy_status(tp, 0);
6883
7083
6884
7084
if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6885
7085
tp->version == RTL_VER_05)
6886
7086
ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6887
7087
6888
-
data = r8152_mdio_read(tp, MII_BMCR);
6889
-
if (data & BMCR_PDOWN) {
6890
-
data &= ~BMCR_PDOWN;
6891
-
r8152_mdio_write(tp, MII_BMCR, data);
6892
-
}
7088
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
6893
7089
6894
-
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7090
+
r8153_phy_status(tp, PHY_STAT_LAN_ON);
6895
7091
6896
7092
r8153_u2p3en(tp, false);
6897
7093
6898
7094
if (tp->version == RTL_VER_04) {
6899
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6900
-
ocp_data &= ~pwd_dn_scale_mask;
6901
-
ocp_data |= pwd_dn_scale(96);
6902
-
ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
7095
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_SSPHYLINK2,
7096
+
pwd_dn_scale_mask, pwd_dn_scale(96));
6903
7097
6904
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6905
-
ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6906
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
7098
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY,
7099
+
USB2PHY_L1 | USB2PHY_SUSPEND);
6907
7100
} else if (tp->version == RTL_VER_05) {
6908
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6909
-
ocp_data &= ~ECM_ALDPS;
6910
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
7101
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ECM_ALDPS);
6911
7102
6912
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6913
7103
if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6914
-
ocp_data &= ~DYNAMIC_BURST;
7104
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1,
7105
+
DYNAMIC_BURST);
6915
7106
else
6916
-
ocp_data |= DYNAMIC_BURST;
6917
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7107
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1,
7108
+
DYNAMIC_BURST);
6918
7109
} else if (tp->version == RTL_VER_06) {
6919
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6920
7110
if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6921
-
ocp_data &= ~DYNAMIC_BURST;
7111
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1,
7112
+
DYNAMIC_BURST);
6922
7113
else
6923
-
ocp_data |= DYNAMIC_BURST;
6924
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
7114
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1,
7115
+
DYNAMIC_BURST);
6925
7116
6926
7117
r8153_queue_wake(tp, false);
6927
7118
6928
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6929
7119
if (rtl8152_get_speed(tp) & LINK_STATUS)
6930
-
ocp_data |= CUR_LINK_OK;
7120
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
7121
+
CUR_LINK_OK | POLL_LINK_CHG);
6931
7122
else
6932
-
ocp_data &= ~CUR_LINK_OK;
6933
-
ocp_data |= POLL_LINK_CHG;
6934
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7123
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
7124
+
CUR_LINK_OK, POLL_LINK_CHG);
6935
7125
}
6936
7126
6937
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6938
-
ocp_data |= EP4_FULL_FC;
6939
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
7127
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, EP4_FULL_FC);
6940
7128
6941
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6942
-
ocp_data &= ~TIMER11_EN;
6943
-
ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7129
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_WDT11_CTRL, TIMER11_EN);
6944
7130
6945
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6946
-
ocp_data &= ~LED_MODE_MASK;
6947
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7131
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, LED_MODE_MASK);
6948
7132
6949
7133
ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
6950
7134
if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
···
6937
7153
ocp_data |= LPM_TIMER_500US;
6938
7154
ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
6939
7155
6940
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
6941
-
ocp_data &= ~SEN_VAL_MASK;
6942
-
ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
6943
-
ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7156
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_AFE_CTRL2, SEN_VAL_MASK,
7157
+
SEN_VAL_NORMAL | SEL_RXIDLE);
6944
7158
6945
7159
ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
6946
7160
···
6948
7166
r8153_u1u2en(tp, true);
6949
7167
usb_enable_lpm(tp->udev);
6950
7168
6951
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6952
-
ocp_data |= LANWAKE_CLR_EN;
6953
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7169
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN);
6954
7170
6955
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6956
-
ocp_data &= ~LANWAKE_PIN;
6957
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7171
+
ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN);
6958
7172
6959
7173
/* rx aggregation */
6960
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6961
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6962
7174
if (tp->dell_tb_rx_agg_bug)
6963
-
ocp_data |= RX_AGG_DISABLE;
6964
-
6965
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7175
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_ZERO_EN,
7176
+
RX_AGG_DISABLE);
7177
+
else
7178
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
7179
+
RX_AGG_DISABLE | RX_ZERO_EN);
6966
7180
6967
7181
rtl_tally_reset(tp);
6968
7182
···
6978
7200
6979
7201
static void r8153b_init(struct r8152 *tp)
6980
7202
{
6981
-
u32 ocp_data;
6982
-
u16 data;
6983
7203
int i;
6984
7204
6985
7205
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
···
6995
7219
break;
6996
7220
}
6997
7221
6998
-
data = r8153_phy_status(tp, 0);
7222
+
r8153_phy_status(tp, 0);
6999
7223
7000
-
data = r8152_mdio_read(tp, MII_BMCR);
7001
-
if (data & BMCR_PDOWN) {
7002
-
data &= ~BMCR_PDOWN;
7003
-
r8152_mdio_write(tp, MII_BMCR, data);
7004
-
}
7224
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
7005
7225
7006
-
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7226
+
r8153_phy_status(tp, PHY_STAT_LAN_ON);
7007
7227
7008
7228
r8153_u2p3en(tp, false);
7009
7229
···
7011
7239
r8153_queue_wake(tp, false);
7012
7240
rtl_runtime_suspend_enable(tp, false);
7013
7241
7014
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7015
7242
if (rtl8152_get_speed(tp) & LINK_STATUS)
7016
-
ocp_data |= CUR_LINK_OK;
7243
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
7244
+
CUR_LINK_OK | POLL_LINK_CHG);
7017
7245
else
7018
-
ocp_data &= ~CUR_LINK_OK;
7019
-
ocp_data |= POLL_LINK_CHG;
7020
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7246
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK,
7247
+
POLL_LINK_CHG);
7021
7248
7022
7249
if (tp->udev->speed >= USB_SPEED_SUPER)
7023
7250
r8153b_u1u2en(tp, true);
···
7026
7255
/* MAC clock speed down */
7027
7256
r8153_mac_clk_speed_down(tp, true);
7028
7257
7029
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7030
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
7031
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7258
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
7259
+
PLA_MCU_SPDWN_EN);
7032
7260
7033
-
if (tp->version == RTL_VER_09) {
7261
+
if (tp->version == RTL_VER_09)
7034
7262
/* Disable Test IO for 32QFN */
7035
-
if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7036
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7037
-
ocp_data |= TEST_IO_OFF;
7038
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7039
-
}
7040
-
}
7263
+
if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5))
7264
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR,
7265
+
TEST_IO_OFF);
7041
7266
7042
7267
set_bit(GREEN_ETHERNET, &tp->flags);
7043
7268
7044
7269
/* rx aggregation */
7045
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7046
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7047
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7270
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
7271
+
RX_AGG_DISABLE | RX_ZERO_EN);
7048
7272
7049
7273
rtl_tally_reset(tp);
7050
7274
···
7048
7282
7049
7283
static void r8153c_init(struct r8152 *tp)
7050
7284
{
7051
-
u32 ocp_data;
7052
-
u16 data;
7053
7285
int i;
7054
7286
7055
7287
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
···
7057
7293
7058
7294
/* Disable spi_en */
7059
7295
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7060
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7061
-
ocp_data &= ~BIT(3);
7062
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7063
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7064
-
ocp_data |= BIT(1);
7065
-
ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7296
+
7297
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG5, BIT(3));
7298
+
7299
+
ocp_word_set_bits(tp, MCU_TYPE_USB, 0xcbf0, BIT(1));
7066
7300
7067
7301
for (i = 0; i < 500; i++) {
7068
7302
if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
···
7072
7310
return;
7073
7311
}
7074
7312
7075
-
data = r8153_phy_status(tp, 0);
7313
+
r8153_phy_status(tp, 0);
7076
7314
7077
-
data = r8152_mdio_read(tp, MII_BMCR);
7078
-
if (data & BMCR_PDOWN) {
7079
-
data &= ~BMCR_PDOWN;
7080
-
r8152_mdio_write(tp, MII_BMCR, data);
7081
-
}
7315
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
7082
7316
7083
-
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7317
+
r8153_phy_status(tp, PHY_STAT_LAN_ON);
7084
7318
7085
7319
r8153_u2p3en(tp, false);
7086
7320
···
7088
7330
r8153_queue_wake(tp, false);
7089
7331
rtl_runtime_suspend_enable(tp, false);
7090
7332
7091
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7092
7333
if (rtl8152_get_speed(tp) & LINK_STATUS)
7093
-
ocp_data |= CUR_LINK_OK;
7334
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
7335
+
CUR_LINK_OK | POLL_LINK_CHG);
7094
7336
else
7095
-
ocp_data &= ~CUR_LINK_OK;
7096
-
7097
-
ocp_data |= POLL_LINK_CHG;
7098
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7337
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK,
7338
+
POLL_LINK_CHG);
7099
7339
7100
7340
r8153b_u1u2en(tp, true);
7101
7341
···
7102
7346
/* MAC clock speed down */
7103
7347
r8153_mac_clk_speed_down(tp, true);
7104
7348
7105
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7106
-
ocp_data &= ~BIT(7);
7107
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7349
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7));
7108
7350
7109
7351
set_bit(GREEN_ETHERNET, &tp->flags);
7110
7352
7111
7353
/* rx aggregation */
7112
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7113
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7114
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7354
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
7355
+
RX_AGG_DISABLE | RX_ZERO_EN);
7115
7356
7116
7357
rtl_tally_reset(tp);
7117
7358
···
7117
7364
7118
7365
static void r8156_hw_phy_cfg(struct r8152 *tp)
7119
7366
{
7120
-
u32 ocp_data;
7121
7367
u16 data;
7122
7368
7123
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7124
-
if (ocp_data & PCUT_STATUS) {
7125
-
ocp_data &= ~PCUT_STATUS;
7126
-
ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7127
-
}
7369
+
ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS);
7128
7370
7129
7371
data = r8153_phy_status(tp, 0);
7130
7372
switch (data) {
7131
7373
case PHY_STAT_EXT_INIT:
7132
7374
rtl8152_apply_firmware(tp, true);
7133
7375
7134
-
data = ocp_reg_read(tp, 0xa468);
7135
-
data &= ~(BIT(3) | BIT(1));
7136
-
ocp_reg_write(tp, 0xa468, data);
7376
+
ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1));
7137
7377
break;
7138
7378
case PHY_STAT_LAN_ON:
7139
7379
case PHY_STAT_PWRDN:
···
7144
7398
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7145
7399
WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7146
7400
7147
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7148
-
ocp_data |= PFM_PWM_SWITCH;
7149
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7401
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH);
7150
7402
7151
7403
switch (tp->version) {
7152
7404
case RTL_VER_10:
7153
-
data = ocp_reg_read(tp, 0xad40);
7154
-
data &= ~0x3ff;
7155
-
data |= BIT(7) | BIT(2);
7156
-
ocp_reg_write(tp, 0xad40, data);
7405
+
ocp_reg_w0w1(tp, 0xad40, 0x3ff, BIT(7) | BIT(2));
7157
7406
7158
-
data = ocp_reg_read(tp, 0xad4e);
7159
-
data |= BIT(4);
7160
-
ocp_reg_write(tp, 0xad4e, data);
7161
-
data = ocp_reg_read(tp, 0xad16);
7162
-
data &= ~0x3ff;
7163
-
data |= 0x6;
7164
-
ocp_reg_write(tp, 0xad16, data);
7165
-
data = ocp_reg_read(tp, 0xad32);
7166
-
data &= ~0x3f;
7167
-
data |= 6;
7168
-
ocp_reg_write(tp, 0xad32, data);
7169
-
data = ocp_reg_read(tp, 0xac08);
7170
-
data &= ~(BIT(12) | BIT(8));
7171
-
ocp_reg_write(tp, 0xac08, data);
7172
-
data = ocp_reg_read(tp, 0xac8a);
7173
-
data |= BIT(12) | BIT(13) | BIT(14);
7174
-
data &= ~BIT(15);
7175
-
ocp_reg_write(tp, 0xac8a, data);
7176
-
data = ocp_reg_read(tp, 0xad18);
7177
-
data |= BIT(10);
7178
-
ocp_reg_write(tp, 0xad18, data);
7179
-
data = ocp_reg_read(tp, 0xad1a);
7180
-
data |= 0x3ff;
7181
-
ocp_reg_write(tp, 0xad1a, data);
7182
-
data = ocp_reg_read(tp, 0xad1c);
7183
-
data |= 0x3ff;
7184
-
ocp_reg_write(tp, 0xad1c, data);
7407
+
ocp_reg_set_bits(tp, 0xad4e, BIT(4));
7408
+
ocp_reg_w0w1(tp, 0xad16, 0x3ff, 0x6);
7409
+
ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6);
7410
+
ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8));
7411
+
ocp_reg_w0w1(tp, 0xac8a, BIT(15), BIT(12) | BIT(13) | BIT(14));
7412
+
ocp_reg_set_bits(tp, 0xad18, BIT(10));
7413
+
ocp_reg_set_bits(tp, 0xad1a, 0x3ff);
7414
+
ocp_reg_set_bits(tp, 0xad1c, 0x3ff);
7185
7415
7186
-
data = sram_read(tp, 0x80ea);
7187
-
data &= ~0xff00;
7188
-
data |= 0xc400;
7189
-
sram_write(tp, 0x80ea, data);
7190
-
data = sram_read(tp, 0x80eb);
7191
-
data &= ~0x0700;
7192
-
data |= 0x0300;
7193
-
sram_write(tp, 0x80eb, data);
7194
-
data = sram_read(tp, 0x80f8);
7195
-
data &= ~0xff00;
7196
-
data |= 0x1c00;
7197
-
sram_write(tp, 0x80f8, data);
7198
-
data = sram_read(tp, 0x80f1);
7199
-
data &= ~0xff00;
7200
-
data |= 0x3000;
7201
-
sram_write(tp, 0x80f1, data);
7416
+
sram_write_w0w1(tp, 0x80ea, 0xff00, 0xc400);
7417
+
sram_write_w0w1(tp, 0x80eb, 0x0700, 0x0300);
7418
+
sram_write_w0w1(tp, 0x80f8, 0xff00, 0x1c00);
7419
+
sram_write_w0w1(tp, 0x80f1, 0xff00, 0x3000);
7202
7420
7203
-
data = sram_read(tp, 0x80fe);
7204
-
data &= ~0xff00;
7205
-
data |= 0xa500;
7206
-
sram_write(tp, 0x80fe, data);
7207
-
data = sram_read(tp, 0x8102);
7208
-
data &= ~0xff00;
7209
-
data |= 0x5000;
7210
-
sram_write(tp, 0x8102, data);
7211
-
data = sram_read(tp, 0x8015);
7212
-
data &= ~0xff00;
7213
-
data |= 0x3300;
7214
-
sram_write(tp, 0x8015, data);
7215
-
data = sram_read(tp, 0x8100);
7216
-
data &= ~0xff00;
7217
-
data |= 0x7000;
7218
-
sram_write(tp, 0x8100, data);
7219
-
data = sram_read(tp, 0x8014);
7220
-
data &= ~0xff00;
7221
-
data |= 0xf000;
7222
-
sram_write(tp, 0x8014, data);
7223
-
data = sram_read(tp, 0x8016);
7224
-
data &= ~0xff00;
7225
-
data |= 0x6500;
7226
-
sram_write(tp, 0x8016, data);
7227
-
data = sram_read(tp, 0x80dc);
7228
-
data &= ~0xff00;
7229
-
data |= 0xed00;
7230
-
sram_write(tp, 0x80dc, data);
7231
-
data = sram_read(tp, 0x80df);
7232
-
data |= BIT(8);
7233
-
sram_write(tp, 0x80df, data);
7234
-
data = sram_read(tp, 0x80e1);
7235
-
data &= ~BIT(8);
7236
-
sram_write(tp, 0x80e1, data);
7421
+
sram_write_w0w1(tp, 0x80fe, 0xff00, 0xa500);
7422
+
sram_write_w0w1(tp, 0x8102, 0xff00, 0x5000);
7423
+
sram_write_w0w1(tp, 0x8015, 0xff00, 0x3300);
7424
+
sram_write_w0w1(tp, 0x8100, 0xff00, 0x7000);
7425
+
sram_write_w0w1(tp, 0x8014, 0xff00, 0xf000);
7426
+
sram_write_w0w1(tp, 0x8016, 0xff00, 0x6500);
7427
+
sram_write_w0w1(tp, 0x80dc, 0xff00, 0xed00);
7428
+
sram_set_bits(tp, 0x80df, BIT(8));
7429
+
sram_clr_bits(tp, 0x80e1, BIT(8));
7237
7430
7238
-
data = ocp_reg_read(tp, 0xbf06);
7239
-
data &= ~0x003f;
7240
-
data |= 0x0038;
7241
-
ocp_reg_write(tp, 0xbf06, data);
7431
+
ocp_reg_w0w1(tp, 0xbf06, 0x003f, 0x0038);
7242
7432
7243
7433
sram_write(tp, 0x819f, 0xddb6);
7244
7434
7245
7435
ocp_reg_write(tp, 0xbc34, 0x5555);
7246
-
data = ocp_reg_read(tp, 0xbf0a);
7247
-
data &= ~0x0e00;
7248
-
data |= 0x0a00;
7249
-
ocp_reg_write(tp, 0xbf0a, data);
7436
+
ocp_reg_w0w1(tp, 0xbf0a, 0x0e00, 0x0a00);
7250
7437
7251
-
data = ocp_reg_read(tp, 0xbd2c);
7252
-
data &= ~BIT(13);
7253
-
ocp_reg_write(tp, 0xbd2c, data);
7438
+
ocp_reg_clr_bits(tp, 0xbd2c, BIT(13));
7254
7439
break;
7255
7440
case RTL_VER_11:
7256
-
data = ocp_reg_read(tp, 0xad16);
7257
-
data |= 0x3ff;
7258
-
ocp_reg_write(tp, 0xad16, data);
7259
-
data = ocp_reg_read(tp, 0xad32);
7260
-
data &= ~0x3f;
7261
-
data |= 6;
7262
-
ocp_reg_write(tp, 0xad32, data);
7263
-
data = ocp_reg_read(tp, 0xac08);
7264
-
data &= ~(BIT(12) | BIT(8));
7265
-
ocp_reg_write(tp, 0xac08, data);
7266
-
data = ocp_reg_read(tp, 0xacc0);
7267
-
data &= ~0x3;
7268
-
data |= BIT(1);
7269
-
ocp_reg_write(tp, 0xacc0, data);
7270
-
data = ocp_reg_read(tp, 0xad40);
7271
-
data &= ~0xe7;
7272
-
data |= BIT(6) | BIT(2);
7273
-
ocp_reg_write(tp, 0xad40, data);
7274
-
data = ocp_reg_read(tp, 0xac14);
7275
-
data &= ~BIT(7);
7276
-
ocp_reg_write(tp, 0xac14, data);
7277
-
data = ocp_reg_read(tp, 0xac80);
7278
-
data &= ~(BIT(8) | BIT(9));
7279
-
ocp_reg_write(tp, 0xac80, data);
7280
-
data = ocp_reg_read(tp, 0xac5e);
7281
-
data &= ~0x7;
7282
-
data |= BIT(1);
7283
-
ocp_reg_write(tp, 0xac5e, data);
7441
+
ocp_reg_set_bits(tp, 0xad16, 0x3ff);
7442
+
ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6);
7443
+
ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8));
7444
+
ocp_reg_w0w1(tp, 0xacc0, 0x3, BIT(1));
7445
+
ocp_reg_w0w1(tp, 0xad40, 0xe7, BIT(6) | BIT(2));
7446
+
ocp_reg_clr_bits(tp, 0xac14, BIT(7));
7447
+
ocp_reg_clr_bits(tp, 0xac80, BIT(8) | BIT(9));
7448
+
ocp_reg_w0w1(tp, 0xac5e, 0x7, BIT(1));
7284
7449
ocp_reg_write(tp, 0xad4c, 0x00a8);
7285
7450
ocp_reg_write(tp, 0xac5c, 0x01ff);
7286
-
data = ocp_reg_read(tp, 0xac8a);
7287
-
data &= ~0xf0;
7288
-
data |= BIT(4) | BIT(5);
7289
-
ocp_reg_write(tp, 0xac8a, data);
7451
+
ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5));
7290
7452
ocp_reg_write(tp, 0xb87c, 0x8157);
7291
-
data = ocp_reg_read(tp, 0xb87e);
7292
-
data &= ~0xff00;
7293
-
data |= 0x0500;
7294
-
ocp_reg_write(tp, 0xb87e, data);
7453
+
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500);
7295
7454
ocp_reg_write(tp, 0xb87c, 0x8159);
7296
-
data = ocp_reg_read(tp, 0xb87e);
7297
-
data &= ~0xff00;
7298
-
data |= 0x0700;
7299
-
ocp_reg_write(tp, 0xb87e, data);
7455
+
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700);
7300
7456
7301
7457
/* AAGC */
7302
7458
ocp_reg_write(tp, 0xb87c, 0x80a2);
···
7209
7561
/* EEE parameter */
7210
7562
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7211
7563
7212
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7213
-
ocp_data |= EN_XG_LIP | EN_G_LIP;
7214
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7564
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG,
7565
+
EN_XG_LIP | EN_G_LIP);
7215
7566
7216
7567
sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7217
7568
sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
···
7219
7572
return;
7220
7573
7221
7574
/* Advance EEE */
7222
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7223
-
ocp_data |= EEE_SPDWN_EN;
7224
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7575
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
7576
+
EEE_SPDWN_EN);
7225
7577
7226
-
data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7227
-
data &= ~(EN_EEE_100 | EN_EEE_1000);
7228
-
data |= EN_10M_CLKDIV;
7229
-
ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7578
+
ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000,
7579
+
EN_10M_CLKDIV);
7230
7580
tp->ups_info._10m_ckdiv = true;
7231
7581
tp->ups_info.eee_plloff_100 = false;
7232
7582
tp->ups_info.eee_plloff_giga = false;
7233
7583
7234
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
7235
-
data &= ~EEE_CLKDIV_EN;
7236
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
7584
+
ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
7237
7585
tp->ups_info.eee_ckdiv = false;
7238
7586
7239
7587
ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
···
7238
7596
rtl_phy_patch_request(tp, false, true);
7239
7597
7240
7598
/* enable ADC Ibias Cal */
7241
-
data = ocp_reg_read(tp, 0xd068);
7242
-
data |= BIT(13);
7243
-
ocp_reg_write(tp, 0xd068, data);
7599
+
ocp_reg_set_bits(tp, 0xd068, BIT(13));
7244
7600
7245
7601
/* enable Thermal Sensor */
7246
-
data = sram_read(tp, 0x81a2);
7247
-
data &= ~BIT(8);
7248
-
sram_write(tp, 0x81a2, data);
7249
-
data = ocp_reg_read(tp, 0xb54c);
7250
-
data &= ~0xff00;
7251
-
data |= 0xdb00;
7252
-
ocp_reg_write(tp, 0xb54c, data);
7602
+
sram_clr_bits(tp, 0x81a2, BIT(8));
7603
+
ocp_reg_w0w1(tp, 0xb54c, 0xff00, 0xdb00);
7253
7604
7254
7605
/* Nway 2.5G Lite */
7255
-
data = ocp_reg_read(tp, 0xa454);
7256
-
data &= ~BIT(0);
7257
-
ocp_reg_write(tp, 0xa454, data);
7606
+
ocp_reg_clr_bits(tp, 0xa454, BIT(0));
7258
7607
7259
7608
/* CS DSP solution */
7260
-
data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7261
-
data |= RTL_ADV2_5G_F_R;
7262
-
ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7263
-
data = ocp_reg_read(tp, 0xad4e);
7264
-
data &= ~BIT(4);
7265
-
ocp_reg_write(tp, 0xad4e, data);
7266
-
data = ocp_reg_read(tp, 0xa86a);
7267
-
data &= ~BIT(0);
7268
-
ocp_reg_write(tp, 0xa86a, data);
7609
+
ocp_reg_set_bits(tp, OCP_10GBT_CTRL, RTL_ADV2_5G_F_R);
7610
+
ocp_reg_clr_bits(tp, 0xad4e, BIT(4));
7611
+
ocp_reg_clr_bits(tp, 0xa86a, BIT(0));
7269
7612
7270
7613
/* MDI SWAP */
7271
7614
if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
···
7311
7684
}
7312
7685
7313
7686
/* Notify the MAC when the speed is changed to force mode. */
7314
-
data = ocp_reg_read(tp, OCP_INTR_EN);
7315
-
data |= INTR_SPEED_FORCE;
7316
-
ocp_reg_write(tp, OCP_INTR_EN, data);
7687
+
ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE);
7317
7688
break;
7318
7689
default:
7319
7690
break;
···
7319
7694
7320
7695
rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7321
7696
7322
-
data = ocp_reg_read(tp, 0xa428);
7323
-
data &= ~BIT(9);
7324
-
ocp_reg_write(tp, 0xa428, data);
7325
-
data = ocp_reg_read(tp, 0xa5ea);
7326
-
data &= ~BIT(0);
7327
-
ocp_reg_write(tp, 0xa5ea, data);
7697
+
ocp_reg_clr_bits(tp, 0xa428, BIT(9));
7698
+
ocp_reg_clr_bits(tp, 0xa5ea, BIT(0));
7328
7699
tp->ups_info.lite_mode = 0;
7329
7700
7330
7701
if (tp->eee_en)
···
7335
7714
7336
7715
static void r8156b_hw_phy_cfg(struct r8152 *tp)
7337
7716
{
7338
-
u32 ocp_data;
7339
7717
u16 data;
7340
7718
7341
7719
switch (tp->version) {
7342
7720
case RTL_VER_12:
7343
7721
ocp_reg_write(tp, 0xbf86, 0x9000);
7344
-
data = ocp_reg_read(tp, 0xc402);
7345
-
data |= BIT(10);
7346
-
ocp_reg_write(tp, 0xc402, data);
7347
-
data &= ~BIT(10);
7348
-
ocp_reg_write(tp, 0xc402, data);
7722
+
ocp_reg_set_bits(tp, 0xc402, BIT(10));
7723
+
ocp_reg_clr_bits(tp, 0xc402, BIT(10));
7349
7724
ocp_reg_write(tp, 0xbd86, 0x1010);
7350
7725
ocp_reg_write(tp, 0xbd88, 0x1010);
7351
-
data = ocp_reg_read(tp, 0xbd4e);
7352
-
data &= ~(BIT(10) | BIT(11));
7353
-
data |= BIT(11);
7354
-
ocp_reg_write(tp, 0xbd4e, data);
7355
-
data = ocp_reg_read(tp, 0xbf46);
7356
-
data &= ~0xf00;
7357
-
data |= 0x700;
7358
-
ocp_reg_write(tp, 0xbf46, data);
7726
+
ocp_reg_w0w1(tp, 0xbd4e, BIT(10) | BIT(11), BIT(11));
7727
+
ocp_reg_w0w1(tp, 0xbf46, 0xf00, 0x700);
7359
7728
break;
7360
7729
case RTL_VER_13:
7361
7730
case RTL_VER_15:
···
7355
7744
break;
7356
7745
}
7357
7746
7358
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7359
-
if (ocp_data & PCUT_STATUS) {
7360
-
ocp_data &= ~PCUT_STATUS;
7361
-
ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7362
-
}
7747
+
ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS);
7363
7748
7364
7749
data = r8153_phy_status(tp, 0);
7365
7750
switch (data) {
7366
7751
case PHY_STAT_EXT_INIT:
7367
7752
rtl8152_apply_firmware(tp, true);
7368
7753
7369
-
data = ocp_reg_read(tp, 0xa466);
7370
-
data &= ~BIT(0);
7371
-
ocp_reg_write(tp, 0xa466, data);
7372
-
7373
-
data = ocp_reg_read(tp, 0xa468);
7374
-
data &= ~(BIT(3) | BIT(1));
7375
-
ocp_reg_write(tp, 0xa468, data);
7754
+
ocp_reg_clr_bits(tp, 0xa466, BIT(0));
7755
+
ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1));
7376
7756
break;
7377
7757
case PHY_STAT_LAN_ON:
7378
7758
case PHY_STAT_PWRDN:
···
7372
7770
break;
7373
7771
}
7374
7772
7375
-
data = r8152_mdio_read(tp, MII_BMCR);
7376
-
if (data & BMCR_PDOWN) {
7377
-
data &= ~BMCR_PDOWN;
7378
-
r8152_mdio_write(tp, MII_BMCR, data);
7379
-
}
7773
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
7380
7774
7381
7775
/* disable ALDPS before updating the PHY parameters */
7382
7776
r8153_aldps_en(tp, false);
···
7383
7785
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7384
7786
WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7385
7787
7386
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7387
-
ocp_data |= PFM_PWM_SWITCH;
7388
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7788
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH);
7389
7789
7390
7790
switch (tp->version) {
7391
7791
case RTL_VER_12:
7392
-
data = ocp_reg_read(tp, 0xbc08);
7393
-
data |= BIT(3) | BIT(2);
7394
-
ocp_reg_write(tp, 0xbc08, data);
7792
+
ocp_reg_set_bits(tp, 0xbc08, BIT(3) | BIT(2));
7395
7793
7396
-
data = sram_read(tp, 0x8fff);
7397
-
data &= ~0xff00;
7398
-
data |= 0x0400;
7399
-
sram_write(tp, 0x8fff, data);
7794
+
sram_write_w0w1(tp, 0x8fff, 0xff00, 0x0400);
7400
7795
7401
-
data = ocp_reg_read(tp, 0xacda);
7402
-
data |= 0xff00;
7403
-
ocp_reg_write(tp, 0xacda, data);
7404
-
data = ocp_reg_read(tp, 0xacde);
7405
-
data |= 0xf000;
7406
-
ocp_reg_write(tp, 0xacde, data);
7796
+
ocp_reg_set_bits(tp, 0xacda, 0xff00);
7797
+
ocp_reg_set_bits(tp, 0xacde, 0xf000);
7407
7798
ocp_reg_write(tp, 0xac8c, 0x0ffc);
7408
7799
ocp_reg_write(tp, 0xac46, 0xb7b4);
7409
7800
ocp_reg_write(tp, 0xac50, 0x0fbc);
···
7461
7874
ocp_reg_write(tp, 0xb87c, 0x8fd8);
7462
7875
ocp_reg_write(tp, 0xb87e, 0xf600);
7463
7876
7464
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7465
-
ocp_data |= EN_XG_LIP | EN_G_LIP;
7466
-
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7877
+
ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG,
7878
+
EN_XG_LIP | EN_G_LIP);
7879
+
7467
7880
ocp_reg_write(tp, 0xb87c, 0x813d);
7468
7881
ocp_reg_write(tp, 0xb87e, 0x390e);
7469
7882
ocp_reg_write(tp, 0xb87c, 0x814f);
7470
7883
ocp_reg_write(tp, 0xb87e, 0x790e);
7471
7884
ocp_reg_write(tp, 0xb87c, 0x80b0);
7472
7885
ocp_reg_write(tp, 0xb87e, 0x0f31);
7473
-
data = ocp_reg_read(tp, 0xbf4c);
7474
-
data |= BIT(1);
7475
-
ocp_reg_write(tp, 0xbf4c, data);
7476
-
data = ocp_reg_read(tp, 0xbcca);
7477
-
data |= BIT(9) | BIT(8);
7478
-
ocp_reg_write(tp, 0xbcca, data);
7886
+
ocp_reg_set_bits(tp, 0xbf4c, BIT(1));
7887
+
ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8));
7479
7888
ocp_reg_write(tp, 0xb87c, 0x8141);
7480
7889
ocp_reg_write(tp, 0xb87e, 0x320e);
7481
7890
ocp_reg_write(tp, 0xb87c, 0x8153);
7482
7891
ocp_reg_write(tp, 0xb87e, 0x720e);
7483
7892
ocp_reg_write(tp, 0xb87c, 0x8529);
7484
7893
ocp_reg_write(tp, 0xb87e, 0x050e);
7485
-
data = ocp_reg_read(tp, OCP_EEE_CFG);
7486
-
data &= ~CTAP_SHORT_EN;
7487
-
ocp_reg_write(tp, OCP_EEE_CFG, data);
7894
+
ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN);
7488
7895
7489
7896
sram_write(tp, 0x816c, 0xc4a0);
7490
7897
sram_write(tp, 0x8170, 0xc4a0);
···
7511
7930
ocp_reg_write(tp, 0xb87c, 0x817b);
7512
7931
ocp_reg_write(tp, 0xb87e, 0x1d0a);
7513
7932
7514
-
data = sram_read(tp, 0x8217);
7515
-
data &= ~0xff00;
7516
-
data |= 0x5000;
7517
-
sram_write(tp, 0x8217, data);
7518
-
data = sram_read(tp, 0x821a);
7519
-
data &= ~0xff00;
7520
-
data |= 0x5000;
7521
-
sram_write(tp, 0x821a, data);
7933
+
sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000);
7934
+
sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000);
7522
7935
sram_write(tp, 0x80da, 0x0403);
7523
-
data = sram_read(tp, 0x80dc);
7524
-
data &= ~0xff00;
7525
-
data |= 0x1000;
7526
-
sram_write(tp, 0x80dc, data);
7936
+
sram_write_w0w1(tp, 0x80dc, 0xff00, 0x1000);
7527
7937
sram_write(tp, 0x80b3, 0x0384);
7528
7938
sram_write(tp, 0x80b7, 0x2007);
7529
-
data = sram_read(tp, 0x80ba);
7530
-
data &= ~0xff00;
7531
-
data |= 0x6c00;
7532
-
sram_write(tp, 0x80ba, data);
7939
+
sram_write_w0w1(tp, 0x80ba, 0xff00, 0x6c00);
7533
7940
sram_write(tp, 0x80b5, 0xf009);
7534
-
data = sram_read(tp, 0x80bd);
7535
-
data &= ~0xff00;
7536
-
data |= 0x9f00;
7537
-
sram_write(tp, 0x80bd, data);
7941
+
sram_write_w0w1(tp, 0x80bd, 0xff00, 0x9f00);
7538
7942
sram_write(tp, 0x80c7, 0xf083);
7539
7943
sram_write(tp, 0x80dd, 0x03f0);
7540
-
data = sram_read(tp, 0x80df);
7541
-
data &= ~0xff00;
7542
-
data |= 0x1000;
7543
-
sram_write(tp, 0x80df, data);
7944
+
sram_write_w0w1(tp, 0x80df, 0xff00, 0x1000);
7544
7945
sram_write(tp, 0x80cb, 0x2007);
7545
-
data = sram_read(tp, 0x80ce);
7546
-
data &= ~0xff00;
7547
-
data |= 0x6c00;
7548
-
sram_write(tp, 0x80ce, data);
7946
+
sram_write_w0w1(tp, 0x80ce, 0xff00, 0x6c00);
7549
7947
sram_write(tp, 0x80c9, 0x8009);
7550
-
data = sram_read(tp, 0x80d1);
7551
-
data &= ~0xff00;
7552
-
data |= 0x8000;
7553
-
sram_write(tp, 0x80d1, data);
7948
+
sram_write_w0w1(tp, 0x80d1, 0xff00, 0x8000);
7554
7949
sram_write(tp, 0x80a3, 0x200a);
7555
7950
sram_write(tp, 0x80a5, 0xf0ad);
7556
7951
sram_write(tp, 0x809f, 0x6073);
7557
7952
sram_write(tp, 0x80a1, 0x000b);
7558
-
data = sram_read(tp, 0x80a9);
7559
-
data &= ~0xff00;
7560
-
data |= 0xc000;
7561
-
sram_write(tp, 0x80a9, data);
7953
+
sram_write_w0w1(tp, 0x80a9, 0xff00, 0xc000);
7562
7954
7563
7955
if (rtl_phy_patch_request(tp, true, true))
7564
7956
return;
7565
7957
7566
-
data = ocp_reg_read(tp, 0xb896);
7567
-
data &= ~BIT(0);
7568
-
ocp_reg_write(tp, 0xb896, data);
7569
-
data = ocp_reg_read(tp, 0xb892);
7570
-
data &= ~0xff00;
7571
-
ocp_reg_write(tp, 0xb892, data);
7958
+
ocp_reg_clr_bits(tp, 0xb896, BIT(0));
7959
+
ocp_reg_clr_bits(tp, 0xb892, 0xff00);
7572
7960
ocp_reg_write(tp, 0xb88e, 0xc23e);
7573
7961
ocp_reg_write(tp, 0xb890, 0x0000);
7574
7962
ocp_reg_write(tp, 0xb88e, 0xc240);
···
7552
8002
ocp_reg_write(tp, 0xb890, 0x1012);
7553
8003
ocp_reg_write(tp, 0xb88e, 0xc24a);
7554
8004
ocp_reg_write(tp, 0xb890, 0x1416);
7555
-
data = ocp_reg_read(tp, 0xb896);
7556
-
data |= BIT(0);
7557
-
ocp_reg_write(tp, 0xb896, data);
8005
+
ocp_reg_set_bits(tp, 0xb896, BIT(0));
7558
8006
7559
8007
rtl_phy_patch_request(tp, false, true);
7560
8008
7561
-
data = ocp_reg_read(tp, 0xa86a);
7562
-
data |= BIT(0);
7563
-
ocp_reg_write(tp, 0xa86a, data);
7564
-
data = ocp_reg_read(tp, 0xa6f0);
7565
-
data |= BIT(0);
7566
-
ocp_reg_write(tp, 0xa6f0, data);
8009
+
ocp_reg_set_bits(tp, 0xa86a, BIT(0));
8010
+
ocp_reg_set_bits(tp, 0xa6f0, BIT(0));
7567
8011
7568
8012
ocp_reg_write(tp, 0xbfa0, 0xd70d);
7569
8013
ocp_reg_write(tp, 0xbfa2, 0x4100);
7570
8014
ocp_reg_write(tp, 0xbfa4, 0xe868);
7571
8015
ocp_reg_write(tp, 0xbfa6, 0xdc59);
7572
8016
ocp_reg_write(tp, 0xb54c, 0x3c18);
7573
-
data = ocp_reg_read(tp, 0xbfa4);
7574
-
data &= ~BIT(5);
7575
-
ocp_reg_write(tp, 0xbfa4, data);
7576
-
data = sram_read(tp, 0x817d);
7577
-
data |= BIT(12);
7578
-
sram_write(tp, 0x817d, data);
8017
+
ocp_reg_clr_bits(tp, 0xbfa4, BIT(5));
8018
+
sram_set_bits(tp, 0x817d, BIT(12));
7579
8019
break;
7580
8020
case RTL_VER_13:
7581
8021
/* 2.5G INRX */
7582
-
data = ocp_reg_read(tp, 0xac46);
7583
-
data &= ~0x00f0;
7584
-
data |= 0x0090;
7585
-
ocp_reg_write(tp, 0xac46, data);
7586
-
data = ocp_reg_read(tp, 0xad30);
7587
-
data &= ~0x0003;
7588
-
data |= 0x0001;
7589
-
ocp_reg_write(tp, 0xad30, data);
8022
+
ocp_reg_w0w1(tp, 0xac46, 0x00f0, 0x0090);
8023
+
ocp_reg_w0w1(tp, 0xad30, 0x0003, 0x0001);
7590
8024
fallthrough;
7591
8025
case RTL_VER_15:
7592
8026
/* EEE parameter */
···
7579
8045
ocp_reg_write(tp, 0xb87c, 0x8107);
7580
8046
ocp_reg_write(tp, 0xb87e, 0x360e);
7581
8047
ocp_reg_write(tp, 0xb87c, 0x8551);
7582
-
data = ocp_reg_read(tp, 0xb87e);
7583
-
data &= ~0xff00;
7584
-
data |= 0x0800;
7585
-
ocp_reg_write(tp, 0xb87e, data);
8048
+
ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800);
7586
8049
7587
8050
/* ADC_PGA parameter */
7588
-
data = ocp_reg_read(tp, 0xbf00);
7589
-
data &= ~0xe000;
7590
-
data |= 0xa000;
7591
-
ocp_reg_write(tp, 0xbf00, data);
7592
-
data = ocp_reg_read(tp, 0xbf46);
7593
-
data &= ~0x0f00;
7594
-
data |= 0x0300;
7595
-
ocp_reg_write(tp, 0xbf46, data);
8051
+
ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000);
8052
+
ocp_reg_w0w1(tp, 0xbf46, 0x0f00, 0x0300);
7596
8053
7597
8054
/* Green Table-PGA, 1G full viterbi */
7598
8055
sram_write(tp, 0x8044, 0x2417);
···
7598
8073
sram_write(tp, 0x807a, 0x2417);
7599
8074
7600
8075
/* XG PLL */
7601
-
data = ocp_reg_read(tp, 0xbf84);
7602
-
data &= ~0xe000;
7603
-
data |= 0xa000;
7604
-
ocp_reg_write(tp, 0xbf84, data);
8076
+
ocp_reg_w0w1(tp, 0xbf84, 0xe000, 0xa000);
7605
8077
break;
7606
8078
default:
7607
8079
break;
7608
8080
}
7609
8081
7610
8082
/* Notify the MAC when the speed is changed to force mode. */
7611
-
data = ocp_reg_read(tp, OCP_INTR_EN);
7612
-
data |= INTR_SPEED_FORCE;
7613
-
ocp_reg_write(tp, OCP_INTR_EN, data);
8083
+
ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE);
7614
8084
7615
8085
if (rtl_phy_patch_request(tp, true, true))
7616
8086
return;
7617
8087
7618
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7619
-
ocp_data |= EEE_SPDWN_EN;
7620
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
8088
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN);
7621
8089
7622
-
data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7623
-
data &= ~(EN_EEE_100 | EN_EEE_1000);
7624
-
data |= EN_10M_CLKDIV;
7625
-
ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8090
+
ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000,
8091
+
EN_10M_CLKDIV);
7626
8092
tp->ups_info._10m_ckdiv = true;
7627
8093
tp->ups_info.eee_plloff_100 = false;
7628
8094
tp->ups_info.eee_plloff_giga = false;
7629
8095
7630
-
data = ocp_reg_read(tp, OCP_POWER_CFG);
7631
-
data &= ~EEE_CLKDIV_EN;
7632
-
ocp_reg_write(tp, OCP_POWER_CFG, data);
8096
+
ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN);
7633
8097
tp->ups_info.eee_ckdiv = false;
7634
8098
7635
8099
rtl_phy_patch_request(tp, false, true);
7636
8100
7637
8101
rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7638
8102
7639
-
data = ocp_reg_read(tp, 0xa428);
7640
-
data &= ~BIT(9);
7641
-
ocp_reg_write(tp, 0xa428, data);
7642
-
data = ocp_reg_read(tp, 0xa5ea);
7643
-
data &= ~BIT(0);
7644
-
ocp_reg_write(tp, 0xa5ea, data);
8103
+
ocp_reg_clr_bits(tp, 0xa428, BIT(9));
8104
+
ocp_reg_clr_bits(tp, 0xa5ea, BIT(0));
7645
8105
tp->ups_info.lite_mode = 0;
7646
8106
7647
8107
if (tp->eee_en)
···
7641
8131
7642
8132
static void r8156_init(struct r8152 *tp)
7643
8133
{
7644
-
u32 ocp_data;
7645
8134
u16 data;
7646
8135
int i;
7647
8136
7648
8137
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7649
8138
return;
7650
8139
7651
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7652
-
ocp_data &= ~EN_ALL_SPEED;
7653
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8140
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED);
7654
8141
7655
8142
ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7656
8143
7657
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7658
-
ocp_data |= BYPASS_MAC_RESET;
7659
-
ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8144
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET);
7660
8145
7661
8146
r8153b_u1u2en(tp, false);
7662
8147
···
7666
8161
}
7667
8162
7668
8163
data = r8153_phy_status(tp, 0);
7669
-
if (data == PHY_STAT_EXT_INIT) {
7670
-
data = ocp_reg_read(tp, 0xa468);
7671
-
data &= ~(BIT(3) | BIT(1));
7672
-
ocp_reg_write(tp, 0xa468, data);
7673
-
}
8164
+
if (data == PHY_STAT_EXT_INIT)
8165
+
ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1));
7674
8166
7675
-
data = r8152_mdio_read(tp, MII_BMCR);
7676
-
if (data & BMCR_PDOWN) {
7677
-
data &= ~BMCR_PDOWN;
7678
-
r8152_mdio_write(tp, MII_BMCR, data);
7679
-
}
8167
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
7680
8168
7681
8169
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7682
8170
WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
···
7694
8196
7695
8197
r8156_mac_clk_spd(tp, true);
7696
8198
7697
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7698
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
7699
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8199
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
8200
+
PLA_MCU_SPDWN_EN);
7700
8201
7701
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7702
8202
if (rtl8152_get_speed(tp) & LINK_STATUS)
7703
-
ocp_data |= CUR_LINK_OK;
8203
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
8204
+
CUR_LINK_OK | POLL_LINK_CHG);
7704
8205
else
7705
-
ocp_data &= ~CUR_LINK_OK;
7706
-
ocp_data |= POLL_LINK_CHG;
7707
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8206
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK,
8207
+
POLL_LINK_CHG);
7708
8208
7709
8209
set_bit(GREEN_ETHERNET, &tp->flags);
7710
8210
7711
8211
/* rx aggregation */
7712
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7713
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7714
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8212
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
8213
+
RX_AGG_DISABLE | RX_ZERO_EN);
7715
8214
7716
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
7717
-
ocp_data |= ACT_ODMA;
7718
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8215
+
ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA);
7719
8216
7720
8217
r8156_mdio_force_mode(tp);
7721
8218
rtl_tally_reset(tp);
···
7720
8227
7721
8228
static void r8156b_init(struct r8152 *tp)
7722
8229
{
7723
-
u32 ocp_data;
7724
8230
u16 data;
7725
8231
int i;
7726
8232
7727
8233
if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7728
8234
return;
7729
8235
7730
-
ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7731
-
ocp_data &= ~EN_ALL_SPEED;
7732
-
ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8236
+
ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED);
7733
8237
7734
8238
ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7735
8239
7736
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7737
-
ocp_data |= BYPASS_MAC_RESET;
7738
-
ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8240
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET);
7739
8241
7740
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
7741
-
ocp_data |= RX_DETECT8;
7742
-
ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8242
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8);
7743
8243
7744
8244
r8153b_u1u2en(tp, false);
7745
8245
···
7757
8271
7758
8272
data = r8153_phy_status(tp, 0);
7759
8273
if (data == PHY_STAT_EXT_INIT) {
7760
-
data = ocp_reg_read(tp, 0xa468);
7761
-
data &= ~(BIT(3) | BIT(1));
7762
-
ocp_reg_write(tp, 0xa468, data);
7763
-
7764
-
data = ocp_reg_read(tp, 0xa466);
7765
-
data &= ~BIT(0);
7766
-
ocp_reg_write(tp, 0xa466, data);
8274
+
ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1));
8275
+
ocp_reg_clr_bits(tp, 0xa466, BIT(0));
7767
8276
}
7768
8277
7769
-
data = r8152_mdio_read(tp, MII_BMCR);
7770
-
if (data & BMCR_PDOWN) {
7771
-
data &= ~BMCR_PDOWN;
7772
-
r8152_mdio_write(tp, MII_BMCR, data);
7773
-
}
8278
+
r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN);
7774
8279
7775
8280
data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7776
8281
···
7783
8306
7784
8307
usb_enable_lpm(tp->udev);
7785
8308
7786
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
7787
-
ocp_data &= ~SLOT_EN;
7788
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8309
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN);
7789
8310
7790
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
7791
-
ocp_data |= FLOW_CTRL_EN;
7792
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8311
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN);
7793
8312
7794
8313
/* enable fc timer and set timer to 600 ms. */
7795
8314
ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
7796
8315
CTRL_TIMER_EN | (600 / 8));
7797
8316
7798
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
7799
8317
if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
7800
-
ocp_data |= FLOW_CTRL_PATCH_2;
7801
-
ocp_data &= ~AUTO_SPEEDUP;
7802
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8318
+
ocp_word_w0w1(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP,
8319
+
FLOW_CTRL_PATCH_2);
8320
+
else
8321
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP);
7803
8322
7804
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
7805
-
ocp_data |= FC_PATCH_TASK;
7806
-
ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8323
+
ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK);
7807
8324
7808
8325
r8156_mac_clk_spd(tp, true);
7809
8326
7810
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7811
-
ocp_data &= ~PLA_MCU_SPDWN_EN;
7812
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8327
+
ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
8328
+
PLA_MCU_SPDWN_EN);
7813
8329
7814
-
ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7815
8330
if (rtl8152_get_speed(tp) & LINK_STATUS)
7816
-
ocp_data |= CUR_LINK_OK;
8331
+
ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS,
8332
+
CUR_LINK_OK | POLL_LINK_CHG);
7817
8333
else
7818
-
ocp_data &= ~CUR_LINK_OK;
7819
-
ocp_data |= POLL_LINK_CHG;
7820
-
ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8334
+
ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK,
8335
+
POLL_LINK_CHG);
7821
8336
7822
8337
set_bit(GREEN_ETHERNET, &tp->flags);
7823
8338
7824
8339
/* rx aggregation */
7825
-
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7826
-
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7827
-
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8340
+
ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL,
8341
+
RX_AGG_DISABLE | RX_ZERO_EN);
7828
8342
7829
8343
r8156_mdio_force_mode(tp);
7830
8344
rtl_tally_reset(tp);