tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"Some pin control fixes for the v6.3 series.

The most notable and urgent one is probably the AMD fix which affects
AMD laptops, found by the Chromium people.

Summary:

- Fix up the Kconfig options for MediaTek MT7981

- Fix the irq domain name in the AT91-PIO4 driver

- Fix some alternative muxing modes in the Ocelot driver

- Allocate the GPIO numbers dynamically in the STM32 driver

- Disable and mask interrupts on resume in the AMD driver

- Fix a typo in the Qualcomm SM8550 pin control device tree bindings"

* tag 'pinctrl-v6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
dt-bindings: pinctrl: qcom,sm8550-lpass-lpi: allow input-enabled and bias-bus-hold
pinctrl: amd: Disable and mask interrupts on resume
pinctrl: stm32: use dynamic allocation of GPIO base
pinctrl: ocelot: Fix alt mode for ocelot
pinctrl: at91-pio4: fix domain name assignment
pinctrl: mediatek: fix naming inconsistency
pinctrl: mediatek: add missing options to PINCTRL_MT7981

Linus Torvalds 93e2b017 ce0c2375

+47 -40
+2
Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
··· 96 96 2: Lower Slew rate (slower edges) 97 97 3: Reserved (No adjustments) 98 98 99 + bias-bus-hold: true 99 100 bias-pull-down: true 100 101 bias-pull-up: true 101 102 bias-disable: true 103 + input-enable: true 102 104 output-high: true 103 105 output-low: true 104 106
+23 -21
drivers/pinctrl/mediatek/Kconfig
··· 45 45 46 46 # For ARMv7 SoCs 47 47 config PINCTRL_MT2701 48 - bool "Mediatek MT2701 pin control" 48 + bool "MediaTek MT2701 pin control" 49 49 depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST 50 50 depends on OF 51 51 default MACH_MT2701 52 52 select PINCTRL_MTK 53 53 54 54 config PINCTRL_MT7623 55 - bool "Mediatek MT7623 pin control with generic binding" 55 + bool "MediaTek MT7623 pin control with generic binding" 56 56 depends on MACH_MT7623 || COMPILE_TEST 57 57 depends on OF 58 58 default MACH_MT7623 59 59 select PINCTRL_MTK_MOORE 60 60 61 61 config PINCTRL_MT7629 62 - bool "Mediatek MT7629 pin control" 62 + bool "MediaTek MT7629 pin control" 63 63 depends on MACH_MT7629 || COMPILE_TEST 64 64 depends on OF 65 65 default MACH_MT7629 66 66 select PINCTRL_MTK_MOORE 67 67 68 68 config PINCTRL_MT8135 69 - bool "Mediatek MT8135 pin control" 69 + bool "MediaTek MT8135 pin control" 70 70 depends on MACH_MT8135 || COMPILE_TEST 71 71 depends on OF 72 72 default MACH_MT8135 73 73 select PINCTRL_MTK 74 74 75 75 config PINCTRL_MT8127 76 - bool "Mediatek MT8127 pin control" 76 + bool "MediaTek MT8127 pin control" 77 77 depends on MACH_MT8127 || COMPILE_TEST 78 78 depends on OF 79 79 default MACH_MT8127 ··· 88 88 select PINCTRL_MTK 89 89 90 90 config PINCTRL_MT6765 91 - tristate "Mediatek MT6765 pin control" 91 + tristate "MediaTek MT6765 pin control" 92 92 depends on OF 93 93 depends on ARM64 || COMPILE_TEST 94 94 default ARM64 && ARCH_MEDIATEK 95 95 select PINCTRL_MTK_PARIS 96 96 97 97 config PINCTRL_MT6779 98 - tristate "Mediatek MT6779 pin control" 98 + tristate "MediaTek MT6779 pin control" 99 99 depends on OF 100 100 depends on ARM64 || COMPILE_TEST 101 101 default ARM64 && ARCH_MEDIATEK 102 102 select PINCTRL_MTK_PARIS 103 103 help 104 104 Say yes here to support pin controller and gpio driver 105 - on Mediatek MT6779 SoC. 105 + on MediaTek MT6779 SoC. 106 106 In MTK platform, we support virtual gpio and use it to 107 107 map specific eint which doesn't have real gpio pin. 108 108 109 109 config PINCTRL_MT6795 110 - bool "Mediatek MT6795 pin control" 110 + bool "MediaTek MT6795 pin control" 111 111 depends on OF 112 112 depends on ARM64 || COMPILE_TEST 113 113 default ARM64 && ARCH_MEDIATEK 114 114 select PINCTRL_MTK_PARIS 115 115 116 116 config PINCTRL_MT6797 117 - bool "Mediatek MT6797 pin control" 117 + bool "MediaTek MT6797 pin control" 118 118 depends on OF 119 119 depends on ARM64 || COMPILE_TEST 120 120 default ARM64 && ARCH_MEDIATEK ··· 128 128 select PINCTRL_MTK_MOORE 129 129 130 130 config PINCTRL_MT7981 131 - bool "Mediatek MT7981 pin control" 131 + bool "MediaTek MT7981 pin control" 132 132 depends on OF 133 + depends on ARM64 || COMPILE_TEST 134 + default ARM64 && ARCH_MEDIATEK 133 135 select PINCTRL_MTK_MOORE 134 136 135 137 config PINCTRL_MT7986 136 - bool "Mediatek MT7986 pin control" 138 + bool "MediaTek MT7986 pin control" 137 139 depends on OF 138 140 depends on ARM64 || COMPILE_TEST 139 141 default ARM64 && ARCH_MEDIATEK 140 142 select PINCTRL_MTK_MOORE 141 143 142 144 config PINCTRL_MT8167 143 - bool "Mediatek MT8167 pin control" 145 + bool "MediaTek MT8167 pin control" 144 146 depends on OF 145 147 depends on ARM64 || COMPILE_TEST 146 148 default ARM64 && ARCH_MEDIATEK 147 149 select PINCTRL_MTK 148 150 149 151 config PINCTRL_MT8173 150 - bool "Mediatek MT8173 pin control" 152 + bool "MediaTek MT8173 pin control" 151 153 depends on OF 152 154 depends on ARM64 || COMPILE_TEST 153 155 default ARM64 && ARCH_MEDIATEK 154 156 select PINCTRL_MTK 155 157 156 158 config PINCTRL_MT8183 157 - bool "Mediatek MT8183 pin control" 159 + bool "MediaTek MT8183 pin control" 158 160 depends on OF 159 161 depends on ARM64 || COMPILE_TEST 160 162 default ARM64 && ARCH_MEDIATEK 161 163 select PINCTRL_MTK_PARIS 162 164 163 165 config PINCTRL_MT8186 164 - bool "Mediatek MT8186 pin control" 166 + bool "MediaTek MT8186 pin control" 165 167 depends on OF 166 168 depends on ARM64 || COMPILE_TEST 167 169 default ARM64 && ARCH_MEDIATEK ··· 182 180 map specific eint which doesn't have real gpio pin. 183 181 184 182 config PINCTRL_MT8192 185 - bool "Mediatek MT8192 pin control" 183 + bool "MediaTek MT8192 pin control" 186 184 depends on OF 187 185 depends on ARM64 || COMPILE_TEST 188 186 default ARM64 && ARCH_MEDIATEK 189 187 select PINCTRL_MTK_PARIS 190 188 191 189 config PINCTRL_MT8195 192 - bool "Mediatek MT8195 pin control" 190 + bool "MediaTek MT8195 pin control" 193 191 depends on OF 194 192 depends on ARM64 || COMPILE_TEST 195 193 default ARM64 && ARCH_MEDIATEK 196 194 select PINCTRL_MTK_PARIS 197 195 198 196 config PINCTRL_MT8365 199 - bool "Mediatek MT8365 pin control" 197 + bool "MediaTek MT8365 pin control" 200 198 depends on OF 201 199 depends on ARM64 || COMPILE_TEST 202 200 default ARM64 && ARCH_MEDIATEK 203 201 select PINCTRL_MTK 204 202 205 203 config PINCTRL_MT8516 206 - bool "Mediatek MT8516 pin control" 204 + bool "MediaTek MT8516 pin control" 207 205 depends on OF 208 206 depends on ARM64 || COMPILE_TEST 209 207 default ARM64 && ARCH_MEDIATEK ··· 211 209 212 210 # For PMIC 213 211 config PINCTRL_MT6397 214 - bool "Mediatek MT6397 pin control" 212 + bool "MediaTek MT6397 pin control" 215 213 depends on MFD_MT6397 || COMPILE_TEST 216 214 depends on OF 217 215 default MFD_MT6397
+20 -16
drivers/pinctrl/pinctrl-amd.c
··· 872 872 .pin_config_group_set = amd_pinconf_group_set, 873 873 }; 874 874 875 - static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 875 + static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) 876 876 { 877 - struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 877 + const struct pin_desc *pd; 878 878 unsigned long flags; 879 879 u32 pin_reg, mask; 880 - int i; 881 880 882 881 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 883 882 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 884 883 BIT(WAKE_CNTRL_OFF_S4); 885 884 886 - for (i = 0; i < desc->npins; i++) { 887 - int pin = desc->pins[i].number; 888 - const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 885 + pd = pin_desc_get(gpio_dev->pctrl, pin); 886 + if (!pd) 887 + return; 889 888 890 - if (!pd) 891 - continue; 889 + raw_spin_lock_irqsave(&gpio_dev->lock, flags); 890 + pin_reg = readl(gpio_dev->base + pin * 4); 891 + pin_reg &= ~mask; 892 + writel(pin_reg, gpio_dev->base + pin * 4); 893 + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 894 + } 892 895 893 - raw_spin_lock_irqsave(&gpio_dev->lock, flags); 896 + static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 897 + { 898 + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 899 + int i; 894 900 895 - pin_reg = readl(gpio_dev->base + i * 4); 896 - pin_reg &= ~mask; 897 - writel(pin_reg, gpio_dev->base + i * 4); 898 - 899 - raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 900 - } 901 + for (i = 0; i < desc->npins; i++) 902 + amd_gpio_irq_init_pin(gpio_dev, i); 901 903 } 902 904 903 905 #ifdef CONFIG_PM_SLEEP ··· 952 950 for (i = 0; i < desc->npins; i++) { 953 951 int pin = desc->pins[i].number; 954 952 955 - if (!amd_gpio_should_save(gpio_dev, pin)) 953 + if (!amd_gpio_should_save(gpio_dev, pin)) { 954 + amd_gpio_irq_init_pin(gpio_dev, pin); 956 955 continue; 956 + } 957 957 958 958 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 959 959 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
-1
drivers/pinctrl/pinctrl-at91-pio4.c
··· 1206 1206 dev_err(dev, "can't add the irq domain\n"); 1207 1207 return -ENODEV; 1208 1208 } 1209 - atmel_pioctrl->irq_domain->name = "atmel gpio"; 1210 1209 1211 1210 for (i = 0; i < atmel_pioctrl->npins; i++) { 1212 1211 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
+1 -1
drivers/pinctrl/pinctrl-ocelot.c
··· 1204 1204 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin), 1205 1205 BIT(p), f << p); 1206 1206 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin), 1207 - BIT(p), f << (p - 1)); 1207 + BIT(p), (f >> 1) << p); 1208 1208 1209 1209 return 0; 1210 1210 }
+1 -1
drivers/pinctrl/stm32/pinctrl-stm32.c
··· 1330 1330 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr)) 1331 1331 bank_ioport_nr = bank_nr; 1332 1332 1333 - bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; 1333 + bank->gpio_chip.base = -1; 1334 1334 1335 1335 bank->gpio_chip.ngpio = npins; 1336 1336 bank->gpio_chip.fwnode = fwnode;