tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/xe: Mark ROW_CHICKEN5 as a masked register

ROW_CHICKEN5 is a masked register (i.e., to adjust the value of any of
the lower 16 bits, the corresponding bit in the upper 16 bits must also
be set). Add the XE_REG_OPTION_MASKED to its definition; failure to do
so will cause workaround updates of this register to not apply properly.

Bspec: 56853
Fixes: 835cd6cbb0d0 ("drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10")
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-3-e206a62ee38f@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit cd84bfbba7feb4c1e72356f14de026dfda1a9e2a)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

authored by

Matt Roper and committed by
Rodrigo Vivi 94079362 2299d735

+1 -1
+1 -1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
··· 583 583 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 584 584 #define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32) 585 585 586 - #define ROW_CHICKEN5 XE_REG_MCR(0xe7f0) 586 + #define ROW_CHICKEN5 XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED) 587 587 #define CPSS_AWARE_DIS REG_BIT(3) 588 588 589 589 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)