Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Here is a late set of pin control fixes for v5.10, most concern some
minor and major issues found in the Intel drivers. Some are so hairy
that I have no idea what is going on there, but luckily the maintainer
knows what's up.
We also have an interesting fix for AMD, which makes AMD-based laptops
more stable IIUC.
Summary:
- Fix up some SPI group and a register offset on Intel Jasperlake
- Set default bias on Intel Merrifield
- Preserve debouncing on Intel Baytrail
- Stop .set_type() irqchip callback in the AMD driver from fiddling
with the debounce filter
- Fix access to GPIO banks that are pass-thru on the Aspeed
- Fix a fix for the Intel pin control driver to disable Rx/Tx when
requesting a UART line as GPIO"
* tag 'pinctrl-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: intel: Actually disable Tx and Rx buffers on GPIO request
pinctrl: aspeed: Fix GPIO requests on pass-through banks
pinctrl: amd: remove debounce filter setting in IRQ type setting
pinctrl: baytrail: Avoid clearing debounce value when turning it off
pinctrl: merrifield: Set default bias in case no particular value given
pinctrl: jasperlake: Fix HOSTSW_OWN offset
pinctrl: jasperlake: Unhide SPI group of pins
+320
-240
+68
-6
drivers/pinctrl/aspeed/pinctrl-aspeed.c
+68
-6
drivers/pinctrl/aspeed/pinctrl-aspeed.c
···
286
286
static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
287
287
{
288
288
/*
289
-
* The signal type is GPIO if the signal name has "GPI" as a prefix.
290
-
* strncmp (rather than strcmp) is used to implement the prefix
291
-
* requirement.
289
+
* We need to differentiate between GPIO and non-GPIO signals to
290
+
* implement the gpio_request_enable() interface. For better or worse
291
+
* the ASPEED pinctrl driver uses the expression names to determine
292
+
* whether an expression will mux a pin for GPIO.
292
293
*
293
-
* expr->signal might look like "GPIOB1" in the GPIO case.
294
-
* expr->signal might look like "GPIT0" in the GPI case.
294
+
* Generally we have the following - A GPIO such as B1 has:
295
+
*
296
+
* - expr->signal set to "GPIOB1"
297
+
* - expr->function set to "GPIOB1"
298
+
*
299
+
* Using this fact we can determine whether the provided expression is
300
+
* a GPIO expression by testing the signal name for the string prefix
301
+
* "GPIO".
302
+
*
303
+
* However, some GPIOs are input-only, and the ASPEED datasheets name
304
+
* them differently. An input-only GPIO such as T0 has:
305
+
*
306
+
* - expr->signal set to "GPIT0"
307
+
* - expr->function set to "GPIT0"
308
+
*
309
+
* It's tempting to generalise the prefix test from "GPIO" to "GPI" to
310
+
* account for both GPIOs and GPIs, but in doing so we run aground on
311
+
* another feature:
312
+
*
313
+
* Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
314
+
* function where the input state of one pin is replicated as the
315
+
* output state of another (as if they were shorted together - a mux
316
+
* configuration that is typically enabled by hardware strapping).
317
+
* This feature allows the BMC to pass e.g. power button state through
318
+
* to the host while the BMC is yet to boot, but take control of the
319
+
* button state once the BMC has booted by muxing each pin as a
320
+
* separate, pin-specific GPIO.
321
+
*
322
+
* Conceptually this pass-through mode is a form of GPIO and is named
323
+
* as such in the datasheets, e.g. "GPID0". This naming similarity
324
+
* trips us up with the simple GPI-prefixed-signal-name scheme
325
+
* discussed above, as the pass-through configuration is not what we
326
+
* want when muxing a pin as GPIO for the GPIO subsystem.
327
+
*
328
+
* On e.g. the AST2400, a pass-through function "GPID0" is grouped on
329
+
* balls A18 and D16, where we have:
330
+
*
331
+
* For ball A18:
332
+
* - expr->signal set to "GPID0IN"
333
+
* - expr->function set to "GPID0"
334
+
*
335
+
* For ball D16:
336
+
* - expr->signal set to "GPID0OUT"
337
+
* - expr->function set to "GPID0"
338
+
*
339
+
* By contrast, the pin-specific GPIO expressions for the same pins are
340
+
* as follows:
341
+
*
342
+
* For ball A18:
343
+
* - expr->signal looks like "GPIOD0"
344
+
* - expr->function looks like "GPIOD0"
345
+
*
346
+
* For ball D16:
347
+
* - expr->signal looks like "GPIOD1"
348
+
* - expr->function looks like "GPIOD1"
349
+
*
350
+
* Testing both the signal _and_ function names gives us the means
351
+
* differentiate the pass-through GPIO pinmux configuration from the
352
+
* pin-specific configuration that the GPIO subsystem is after: An
353
+
* expression is a pin-specific (non-pass-through) GPIO configuration
354
+
* if the signal prefix is "GPI" and the signal name matches the
355
+
* function name.
295
356
*/
296
-
return strncmp(expr->signal, "GPI", 3) == 0;
357
+
return !strncmp(expr->signal, "GPI", 3) &&
358
+
!strcmp(expr->signal, expr->function);
297
359
}
298
360
299
361
static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
+4
-3
drivers/pinctrl/aspeed/pinmux-aspeed.h
+4
-3
drivers/pinctrl/aspeed/pinmux-aspeed.h
···
452
452
* evaluation of the descriptors.
453
453
*
454
454
* @signal: The signal name for the priority level on the pin. If the signal
455
-
* type is GPIO, then the signal name must begin with the string
456
-
* "GPIO", e.g. GPIOA0, GPIOT4 etc.
455
+
* type is GPIO, then the signal name must begin with the
456
+
* prefix "GPI", e.g. GPIOA0, GPIT0 etc.
457
457
* @function: The name of the function the signal participates in for the
458
-
* associated expression
458
+
* associated expression. For pin-specific GPIO, the function
459
+
* name must match the signal name.
459
460
* @ndescs: The number of signal descriptors in the expression
460
461
* @descs: Pointer to an array of signal descriptors that comprise the
461
462
* function expression
+7
-1
drivers/pinctrl/intel/pinctrl-baytrail.c
+7
-1
drivers/pinctrl/intel/pinctrl-baytrail.c
···
1049
1049
break;
1050
1050
case PIN_CONFIG_INPUT_DEBOUNCE:
1051
1051
debounce = readl(db_reg);
1052
-
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1053
1052
1054
1053
if (arg)
1055
1054
conf |= BYT_DEBOUNCE_EN;
···
1057
1058
1058
1059
switch (arg) {
1059
1060
case 375:
1061
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1060
1062
debounce |= BYT_DEBOUNCE_PULSE_375US;
1061
1063
break;
1062
1064
case 750:
1065
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1063
1066
debounce |= BYT_DEBOUNCE_PULSE_750US;
1064
1067
break;
1065
1068
case 1500:
1069
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1066
1070
debounce |= BYT_DEBOUNCE_PULSE_1500US;
1067
1071
break;
1068
1072
case 3000:
1073
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1069
1074
debounce |= BYT_DEBOUNCE_PULSE_3MS;
1070
1075
break;
1071
1076
case 6000:
1077
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1072
1078
debounce |= BYT_DEBOUNCE_PULSE_6MS;
1073
1079
break;
1074
1080
case 12000:
1081
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1075
1082
debounce |= BYT_DEBOUNCE_PULSE_12MS;
1076
1083
break;
1077
1084
case 24000:
1085
+
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1078
1086
debounce |= BYT_DEBOUNCE_PULSE_24MS;
1079
1087
break;
1080
1088
default:
+2
-2
drivers/pinctrl/intel/pinctrl-intel.c
+2
-2
drivers/pinctrl/intel/pinctrl-intel.c
···
442
442
value |= PADCFG0_PMODE_GPIO;
443
443
444
444
/* Disable input and output buffers */
445
-
value &= ~PADCFG0_GPIORXDIS;
446
-
value &= ~PADCFG0_GPIOTXDIS;
445
+
value |= PADCFG0_GPIORXDIS;
446
+
value |= PADCFG0_GPIOTXDIS;
447
447
448
448
/* Disable SCI/SMI/NMI generation */
449
449
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
+231
-221
drivers/pinctrl/intel/pinctrl-jasperlake.c
+231
-221
drivers/pinctrl/intel/pinctrl-jasperlake.c
···
16
16
17
17
#define JSL_PAD_OWN 0x020
18
18
#define JSL_PADCFGLOCK 0x080
19
-
#define JSL_HOSTSW_OWN 0x0b0
19
+
#define JSL_HOSTSW_OWN 0x0c0
20
20
#define JSL_GPI_IS 0x100
21
21
#define JSL_GPI_IE 0x120
22
22
···
65
65
PINCTRL_PIN(17, "EMMC_CLK"),
66
66
PINCTRL_PIN(18, "EMMC_RESETB"),
67
67
PINCTRL_PIN(19, "A4WP_PRESENT"),
68
+
/* SPI */
69
+
PINCTRL_PIN(20, "SPI0_IO_2"),
70
+
PINCTRL_PIN(21, "SPI0_IO_3"),
71
+
PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
72
+
PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
73
+
PINCTRL_PIN(24, "SPI0_TPM_CSB"),
74
+
PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
75
+
PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
76
+
PINCTRL_PIN(27, "SPI0_CLK"),
77
+
PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
68
78
/* GPP_B */
69
-
PINCTRL_PIN(20, "CORE_VID_0"),
70
-
PINCTRL_PIN(21, "CORE_VID_1"),
71
-
PINCTRL_PIN(22, "VRALERTB"),
72
-
PINCTRL_PIN(23, "CPU_GP_2"),
73
-
PINCTRL_PIN(24, "CPU_GP_3"),
74
-
PINCTRL_PIN(25, "SRCCLKREQB_0"),
75
-
PINCTRL_PIN(26, "SRCCLKREQB_1"),
76
-
PINCTRL_PIN(27, "SRCCLKREQB_2"),
77
-
PINCTRL_PIN(28, "SRCCLKREQB_3"),
78
-
PINCTRL_PIN(29, "SRCCLKREQB_4"),
79
-
PINCTRL_PIN(30, "SRCCLKREQB_5"),
80
-
PINCTRL_PIN(31, "PMCALERTB"),
81
-
PINCTRL_PIN(32, "SLP_S0B"),
82
-
PINCTRL_PIN(33, "PLTRSTB"),
83
-
PINCTRL_PIN(34, "SPKR"),
84
-
PINCTRL_PIN(35, "GSPI0_CS0B"),
85
-
PINCTRL_PIN(36, "GSPI0_CLK"),
86
-
PINCTRL_PIN(37, "GSPI0_MISO"),
87
-
PINCTRL_PIN(38, "GSPI0_MOSI"),
88
-
PINCTRL_PIN(39, "GSPI1_CS0B"),
89
-
PINCTRL_PIN(40, "GSPI1_CLK"),
90
-
PINCTRL_PIN(41, "GSPI1_MISO"),
91
-
PINCTRL_PIN(42, "GSPI1_MOSI"),
92
-
PINCTRL_PIN(43, "DDSP_HPD_A"),
93
-
PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"),
94
-
PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"),
79
+
PINCTRL_PIN(29, "CORE_VID_0"),
80
+
PINCTRL_PIN(30, "CORE_VID_1"),
81
+
PINCTRL_PIN(31, "VRALERTB"),
82
+
PINCTRL_PIN(32, "CPU_GP_2"),
83
+
PINCTRL_PIN(33, "CPU_GP_3"),
84
+
PINCTRL_PIN(34, "SRCCLKREQB_0"),
85
+
PINCTRL_PIN(35, "SRCCLKREQB_1"),
86
+
PINCTRL_PIN(36, "SRCCLKREQB_2"),
87
+
PINCTRL_PIN(37, "SRCCLKREQB_3"),
88
+
PINCTRL_PIN(38, "SRCCLKREQB_4"),
89
+
PINCTRL_PIN(39, "SRCCLKREQB_5"),
90
+
PINCTRL_PIN(40, "PMCALERTB"),
91
+
PINCTRL_PIN(41, "SLP_S0B"),
92
+
PINCTRL_PIN(42, "PLTRSTB"),
93
+
PINCTRL_PIN(43, "SPKR"),
94
+
PINCTRL_PIN(44, "GSPI0_CS0B"),
95
+
PINCTRL_PIN(45, "GSPI0_CLK"),
96
+
PINCTRL_PIN(46, "GSPI0_MISO"),
97
+
PINCTRL_PIN(47, "GSPI0_MOSI"),
98
+
PINCTRL_PIN(48, "GSPI1_CS0B"),
99
+
PINCTRL_PIN(49, "GSPI1_CLK"),
100
+
PINCTRL_PIN(50, "GSPI1_MISO"),
101
+
PINCTRL_PIN(51, "GSPI1_MOSI"),
102
+
PINCTRL_PIN(52, "DDSP_HPD_A"),
103
+
PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
104
+
PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
95
105
/* GPP_A */
96
-
PINCTRL_PIN(46, "ESPI_IO_0"),
97
-
PINCTRL_PIN(47, "ESPI_IO_1"),
98
-
PINCTRL_PIN(48, "ESPI_IO_2"),
99
-
PINCTRL_PIN(49, "ESPI_IO_3"),
100
-
PINCTRL_PIN(50, "ESPI_CSB"),
101
-
PINCTRL_PIN(51, "ESPI_CLK"),
102
-
PINCTRL_PIN(52, "ESPI_RESETB"),
103
-
PINCTRL_PIN(53, "SMBCLK"),
104
-
PINCTRL_PIN(54, "SMBDATA"),
105
-
PINCTRL_PIN(55, "SMBALERTB"),
106
-
PINCTRL_PIN(56, "CPU_GP_0"),
107
-
PINCTRL_PIN(57, "CPU_GP_1"),
108
-
PINCTRL_PIN(58, "USB2_OCB_1"),
109
-
PINCTRL_PIN(59, "USB2_OCB_2"),
110
-
PINCTRL_PIN(60, "USB2_OCB_3"),
111
-
PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"),
112
-
PINCTRL_PIN(62, "DDSP_HPD_B"),
113
-
PINCTRL_PIN(63, "DDSP_HPD_C"),
114
-
PINCTRL_PIN(64, "USB2_OCB_0"),
115
-
PINCTRL_PIN(65, "PCHHOTB"),
116
-
PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
106
+
PINCTRL_PIN(55, "ESPI_IO_0"),
107
+
PINCTRL_PIN(56, "ESPI_IO_1"),
108
+
PINCTRL_PIN(57, "ESPI_IO_2"),
109
+
PINCTRL_PIN(58, "ESPI_IO_3"),
110
+
PINCTRL_PIN(59, "ESPI_CSB"),
111
+
PINCTRL_PIN(60, "ESPI_CLK"),
112
+
PINCTRL_PIN(61, "ESPI_RESETB"),
113
+
PINCTRL_PIN(62, "SMBCLK"),
114
+
PINCTRL_PIN(63, "SMBDATA"),
115
+
PINCTRL_PIN(64, "SMBALERTB"),
116
+
PINCTRL_PIN(65, "CPU_GP_0"),
117
+
PINCTRL_PIN(66, "CPU_GP_1"),
118
+
PINCTRL_PIN(67, "USB2_OCB_1"),
119
+
PINCTRL_PIN(68, "USB2_OCB_2"),
120
+
PINCTRL_PIN(69, "USB2_OCB_3"),
121
+
PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"),
122
+
PINCTRL_PIN(71, "DDSP_HPD_B"),
123
+
PINCTRL_PIN(72, "DDSP_HPD_C"),
124
+
PINCTRL_PIN(73, "USB2_OCB_0"),
125
+
PINCTRL_PIN(74, "PCHHOTB"),
126
+
PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"),
117
127
/* GPP_S */
118
-
PINCTRL_PIN(67, "SNDW1_CLK"),
119
-
PINCTRL_PIN(68, "SNDW1_DATA"),
120
-
PINCTRL_PIN(69, "SNDW2_CLK"),
121
-
PINCTRL_PIN(70, "SNDW2_DATA"),
122
-
PINCTRL_PIN(71, "SNDW1_CLK"),
123
-
PINCTRL_PIN(72, "SNDW1_DATA"),
124
-
PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"),
125
-
PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"),
128
+
PINCTRL_PIN(76, "SNDW1_CLK"),
129
+
PINCTRL_PIN(77, "SNDW1_DATA"),
130
+
PINCTRL_PIN(78, "SNDW2_CLK"),
131
+
PINCTRL_PIN(79, "SNDW2_DATA"),
132
+
PINCTRL_PIN(80, "SNDW1_CLK"),
133
+
PINCTRL_PIN(81, "SNDW1_DATA"),
134
+
PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"),
135
+
PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"),
126
136
/* GPP_R */
127
-
PINCTRL_PIN(75, "HDA_BCLK"),
128
-
PINCTRL_PIN(76, "HDA_SYNC"),
129
-
PINCTRL_PIN(77, "HDA_SDO"),
130
-
PINCTRL_PIN(78, "HDA_SDI_0"),
131
-
PINCTRL_PIN(79, "HDA_RSTB"),
132
-
PINCTRL_PIN(80, "HDA_SDI_1"),
133
-
PINCTRL_PIN(81, "I2S1_SFRM"),
134
-
PINCTRL_PIN(82, "I2S1_TXD"),
137
+
PINCTRL_PIN(84, "HDA_BCLK"),
138
+
PINCTRL_PIN(85, "HDA_SYNC"),
139
+
PINCTRL_PIN(86, "HDA_SDO"),
140
+
PINCTRL_PIN(87, "HDA_SDI_0"),
141
+
PINCTRL_PIN(88, "HDA_RSTB"),
142
+
PINCTRL_PIN(89, "HDA_SDI_1"),
143
+
PINCTRL_PIN(90, "I2S1_SFRM"),
144
+
PINCTRL_PIN(91, "I2S1_TXD"),
135
145
/* GPP_H */
136
-
PINCTRL_PIN(83, "GPPC_H_0"),
137
-
PINCTRL_PIN(84, "SD_PWR_EN_B"),
138
-
PINCTRL_PIN(85, "MODEM_CLKREQ"),
139
-
PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"),
140
-
PINCTRL_PIN(87, "I2C2_SDA"),
141
-
PINCTRL_PIN(88, "I2C2_SCL"),
142
-
PINCTRL_PIN(89, "I2C3_SDA"),
143
-
PINCTRL_PIN(90, "I2C3_SCL"),
144
-
PINCTRL_PIN(91, "I2C4_SDA"),
145
-
PINCTRL_PIN(92, "I2C4_SCL"),
146
-
PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"),
147
-
PINCTRL_PIN(94, "I2S2_SCLK"),
148
-
PINCTRL_PIN(95, "I2S2_SFRM"),
149
-
PINCTRL_PIN(96, "I2S2_TXD"),
150
-
PINCTRL_PIN(97, "I2S2_RXD"),
151
-
PINCTRL_PIN(98, "I2S1_SCLK"),
152
-
PINCTRL_PIN(99, "GPPC_H_16"),
153
-
PINCTRL_PIN(100, "GPPC_H_17"),
154
-
PINCTRL_PIN(101, "GPPC_H_18"),
155
-
PINCTRL_PIN(102, "GPPC_H_19"),
156
-
PINCTRL_PIN(103, "GPPC_H_20"),
157
-
PINCTRL_PIN(104, "GPPC_H_21"),
158
-
PINCTRL_PIN(105, "GPPC_H_22"),
159
-
PINCTRL_PIN(106, "GPPC_H_23"),
146
+
PINCTRL_PIN(92, "GPPC_H_0"),
147
+
PINCTRL_PIN(93, "SD_PWR_EN_B"),
148
+
PINCTRL_PIN(94, "MODEM_CLKREQ"),
149
+
PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"),
150
+
PINCTRL_PIN(96, "I2C2_SDA"),
151
+
PINCTRL_PIN(97, "I2C2_SCL"),
152
+
PINCTRL_PIN(98, "I2C3_SDA"),
153
+
PINCTRL_PIN(99, "I2C3_SCL"),
154
+
PINCTRL_PIN(100, "I2C4_SDA"),
155
+
PINCTRL_PIN(101, "I2C4_SCL"),
156
+
PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"),
157
+
PINCTRL_PIN(103, "I2S2_SCLK"),
158
+
PINCTRL_PIN(104, "I2S2_SFRM"),
159
+
PINCTRL_PIN(105, "I2S2_TXD"),
160
+
PINCTRL_PIN(106, "I2S2_RXD"),
161
+
PINCTRL_PIN(107, "I2S1_SCLK"),
162
+
PINCTRL_PIN(108, "GPPC_H_16"),
163
+
PINCTRL_PIN(109, "GPPC_H_17"),
164
+
PINCTRL_PIN(110, "GPPC_H_18"),
165
+
PINCTRL_PIN(111, "GPPC_H_19"),
166
+
PINCTRL_PIN(112, "GPPC_H_20"),
167
+
PINCTRL_PIN(113, "GPPC_H_21"),
168
+
PINCTRL_PIN(114, "GPPC_H_22"),
169
+
PINCTRL_PIN(115, "GPPC_H_23"),
160
170
/* GPP_D */
161
-
PINCTRL_PIN(107, "SPI1_CSB"),
162
-
PINCTRL_PIN(108, "SPI1_CLK"),
163
-
PINCTRL_PIN(109, "SPI1_MISO_IO_1"),
164
-
PINCTRL_PIN(110, "SPI1_MOSI_IO_0"),
165
-
PINCTRL_PIN(111, "ISH_I2C0_SDA"),
166
-
PINCTRL_PIN(112, "ISH_I2C0_SCL"),
167
-
PINCTRL_PIN(113, "ISH_I2C1_SDA"),
168
-
PINCTRL_PIN(114, "ISH_I2C1_SCL"),
169
-
PINCTRL_PIN(115, "ISH_SPI_CSB"),
170
-
PINCTRL_PIN(116, "ISH_SPI_CLK"),
171
-
PINCTRL_PIN(117, "ISH_SPI_MISO"),
172
-
PINCTRL_PIN(118, "ISH_SPI_MOSI"),
173
-
PINCTRL_PIN(119, "ISH_UART0_RXD"),
174
-
PINCTRL_PIN(120, "ISH_UART0_TXD"),
175
-
PINCTRL_PIN(121, "ISH_UART0_RTSB"),
176
-
PINCTRL_PIN(122, "ISH_UART0_CTSB"),
177
-
PINCTRL_PIN(123, "SPI1_IO_2"),
178
-
PINCTRL_PIN(124, "SPI1_IO_3"),
179
-
PINCTRL_PIN(125, "I2S_MCLK"),
180
-
PINCTRL_PIN(126, "CNV_MFUART2_RXD"),
181
-
PINCTRL_PIN(127, "CNV_MFUART2_TXD"),
182
-
PINCTRL_PIN(128, "CNV_PA_BLANKING"),
183
-
PINCTRL_PIN(129, "I2C5_SDA"),
184
-
PINCTRL_PIN(130, "I2C5_SCL"),
185
-
PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"),
186
-
PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"),
171
+
PINCTRL_PIN(116, "SPI1_CSB"),
172
+
PINCTRL_PIN(117, "SPI1_CLK"),
173
+
PINCTRL_PIN(118, "SPI1_MISO_IO_1"),
174
+
PINCTRL_PIN(119, "SPI1_MOSI_IO_0"),
175
+
PINCTRL_PIN(120, "ISH_I2C0_SDA"),
176
+
PINCTRL_PIN(121, "ISH_I2C0_SCL"),
177
+
PINCTRL_PIN(122, "ISH_I2C1_SDA"),
178
+
PINCTRL_PIN(123, "ISH_I2C1_SCL"),
179
+
PINCTRL_PIN(124, "ISH_SPI_CSB"),
180
+
PINCTRL_PIN(125, "ISH_SPI_CLK"),
181
+
PINCTRL_PIN(126, "ISH_SPI_MISO"),
182
+
PINCTRL_PIN(127, "ISH_SPI_MOSI"),
183
+
PINCTRL_PIN(128, "ISH_UART0_RXD"),
184
+
PINCTRL_PIN(129, "ISH_UART0_TXD"),
185
+
PINCTRL_PIN(130, "ISH_UART0_RTSB"),
186
+
PINCTRL_PIN(131, "ISH_UART0_CTSB"),
187
+
PINCTRL_PIN(132, "SPI1_IO_2"),
188
+
PINCTRL_PIN(133, "SPI1_IO_3"),
189
+
PINCTRL_PIN(134, "I2S_MCLK"),
190
+
PINCTRL_PIN(135, "CNV_MFUART2_RXD"),
191
+
PINCTRL_PIN(136, "CNV_MFUART2_TXD"),
192
+
PINCTRL_PIN(137, "CNV_PA_BLANKING"),
193
+
PINCTRL_PIN(138, "I2C5_SDA"),
194
+
PINCTRL_PIN(139, "I2C5_SCL"),
195
+
PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"),
196
+
PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"),
187
197
/* vGPIO */
188
-
PINCTRL_PIN(133, "CNV_BTEN"),
189
-
PINCTRL_PIN(134, "CNV_WCEN"),
190
-
PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"),
191
-
PINCTRL_PIN(136, "CNV_BT_IF_SELECT"),
192
-
PINCTRL_PIN(137, "vCNV_BT_UART_TXD"),
193
-
PINCTRL_PIN(138, "vCNV_BT_UART_RXD"),
194
-
PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"),
195
-
PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"),
196
-
PINCTRL_PIN(141, "vCNV_MFUART1_TXD"),
197
-
PINCTRL_PIN(142, "vCNV_MFUART1_RXD"),
198
-
PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"),
199
-
PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"),
200
-
PINCTRL_PIN(145, "vUART0_TXD"),
201
-
PINCTRL_PIN(146, "vUART0_RXD"),
202
-
PINCTRL_PIN(147, "vUART0_CTS_B"),
203
-
PINCTRL_PIN(148, "vUART0_RTS_B"),
204
-
PINCTRL_PIN(149, "vISH_UART0_TXD"),
205
-
PINCTRL_PIN(150, "vISH_UART0_RXD"),
206
-
PINCTRL_PIN(151, "vISH_UART0_CTS_B"),
207
-
PINCTRL_PIN(152, "vISH_UART0_RTS_B"),
208
-
PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"),
209
-
PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"),
210
-
PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"),
211
-
PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"),
212
-
PINCTRL_PIN(157, "vI2S2_SCLK"),
213
-
PINCTRL_PIN(158, "vI2S2_SFRM"),
214
-
PINCTRL_PIN(159, "vI2S2_TXD"),
215
-
PINCTRL_PIN(160, "vI2S2_RXD"),
216
-
PINCTRL_PIN(161, "vSD3_CD_B"),
198
+
PINCTRL_PIN(142, "CNV_BTEN"),
199
+
PINCTRL_PIN(143, "CNV_WCEN"),
200
+
PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"),
201
+
PINCTRL_PIN(145, "CNV_BT_IF_SELECT"),
202
+
PINCTRL_PIN(146, "vCNV_BT_UART_TXD"),
203
+
PINCTRL_PIN(147, "vCNV_BT_UART_RXD"),
204
+
PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"),
205
+
PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"),
206
+
PINCTRL_PIN(150, "vCNV_MFUART1_TXD"),
207
+
PINCTRL_PIN(151, "vCNV_MFUART1_RXD"),
208
+
PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"),
209
+
PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"),
210
+
PINCTRL_PIN(154, "vUART0_TXD"),
211
+
PINCTRL_PIN(155, "vUART0_RXD"),
212
+
PINCTRL_PIN(156, "vUART0_CTS_B"),
213
+
PINCTRL_PIN(157, "vUART0_RTS_B"),
214
+
PINCTRL_PIN(158, "vISH_UART0_TXD"),
215
+
PINCTRL_PIN(159, "vISH_UART0_RXD"),
216
+
PINCTRL_PIN(160, "vISH_UART0_CTS_B"),
217
+
PINCTRL_PIN(161, "vISH_UART0_RTS_B"),
218
+
PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"),
219
+
PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"),
220
+
PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"),
221
+
PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"),
222
+
PINCTRL_PIN(166, "vI2S2_SCLK"),
223
+
PINCTRL_PIN(167, "vI2S2_SFRM"),
224
+
PINCTRL_PIN(168, "vI2S2_TXD"),
225
+
PINCTRL_PIN(169, "vI2S2_RXD"),
226
+
PINCTRL_PIN(170, "vSD3_CD_B"),
217
227
/* GPP_C */
218
-
PINCTRL_PIN(162, "GPPC_C_0"),
219
-
PINCTRL_PIN(163, "GPPC_C_1"),
220
-
PINCTRL_PIN(164, "GPPC_C_2"),
221
-
PINCTRL_PIN(165, "GPPC_C_3"),
222
-
PINCTRL_PIN(166, "GPPC_C_4"),
223
-
PINCTRL_PIN(167, "GPPC_C_5"),
224
-
PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"),
225
-
PINCTRL_PIN(169, "SUSACKB"),
226
-
PINCTRL_PIN(170, "UART0_RXD"),
227
-
PINCTRL_PIN(171, "UART0_TXD"),
228
-
PINCTRL_PIN(172, "UART0_RTSB"),
229
-
PINCTRL_PIN(173, "UART0_CTSB"),
230
-
PINCTRL_PIN(174, "UART1_RXD"),
231
-
PINCTRL_PIN(175, "UART1_TXD"),
232
-
PINCTRL_PIN(176, "UART1_RTSB"),
233
-
PINCTRL_PIN(177, "UART1_CTSB"),
234
-
PINCTRL_PIN(178, "I2C0_SDA"),
235
-
PINCTRL_PIN(179, "I2C0_SCL"),
236
-
PINCTRL_PIN(180, "I2C1_SDA"),
237
-
PINCTRL_PIN(181, "I2C1_SCL"),
238
-
PINCTRL_PIN(182, "UART2_RXD"),
239
-
PINCTRL_PIN(183, "UART2_TXD"),
240
-
PINCTRL_PIN(184, "UART2_RTSB"),
241
-
PINCTRL_PIN(185, "UART2_CTSB"),
228
+
PINCTRL_PIN(171, "GPPC_C_0"),
229
+
PINCTRL_PIN(172, "GPPC_C_1"),
230
+
PINCTRL_PIN(173, "GPPC_C_2"),
231
+
PINCTRL_PIN(174, "GPPC_C_3"),
232
+
PINCTRL_PIN(175, "GPPC_C_4"),
233
+
PINCTRL_PIN(176, "GPPC_C_5"),
234
+
PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"),
235
+
PINCTRL_PIN(178, "SUSACKB"),
236
+
PINCTRL_PIN(179, "UART0_RXD"),
237
+
PINCTRL_PIN(180, "UART0_TXD"),
238
+
PINCTRL_PIN(181, "UART0_RTSB"),
239
+
PINCTRL_PIN(182, "UART0_CTSB"),
240
+
PINCTRL_PIN(183, "UART1_RXD"),
241
+
PINCTRL_PIN(184, "UART1_TXD"),
242
+
PINCTRL_PIN(185, "UART1_RTSB"),
243
+
PINCTRL_PIN(186, "UART1_CTSB"),
244
+
PINCTRL_PIN(187, "I2C0_SDA"),
245
+
PINCTRL_PIN(188, "I2C0_SCL"),
246
+
PINCTRL_PIN(189, "I2C1_SDA"),
247
+
PINCTRL_PIN(190, "I2C1_SCL"),
248
+
PINCTRL_PIN(191, "UART2_RXD"),
249
+
PINCTRL_PIN(192, "UART2_TXD"),
250
+
PINCTRL_PIN(193, "UART2_RTSB"),
251
+
PINCTRL_PIN(194, "UART2_CTSB"),
242
252
/* HVCMOS */
243
-
PINCTRL_PIN(186, "L_BKLTEN"),
244
-
PINCTRL_PIN(187, "L_BKLTCTL"),
245
-
PINCTRL_PIN(188, "L_VDDEN"),
246
-
PINCTRL_PIN(189, "SYS_PWROK"),
247
-
PINCTRL_PIN(190, "SYS_RESETB"),
248
-
PINCTRL_PIN(191, "MLK_RSTB"),
253
+
PINCTRL_PIN(195, "L_BKLTEN"),
254
+
PINCTRL_PIN(196, "L_BKLTCTL"),
255
+
PINCTRL_PIN(197, "L_VDDEN"),
256
+
PINCTRL_PIN(198, "SYS_PWROK"),
257
+
PINCTRL_PIN(199, "SYS_RESETB"),
258
+
PINCTRL_PIN(200, "MLK_RSTB"),
249
259
/* GPP_E */
250
-
PINCTRL_PIN(192, "ISH_GP_0"),
251
-
PINCTRL_PIN(193, "ISH_GP_1"),
252
-
PINCTRL_PIN(194, "IMGCLKOUT_1"),
253
-
PINCTRL_PIN(195, "ISH_GP_2"),
254
-
PINCTRL_PIN(196, "IMGCLKOUT_2"),
255
-
PINCTRL_PIN(197, "SATA_LEDB"),
256
-
PINCTRL_PIN(198, "IMGCLKOUT_3"),
257
-
PINCTRL_PIN(199, "ISH_GP_3"),
258
-
PINCTRL_PIN(200, "ISH_GP_4"),
259
-
PINCTRL_PIN(201, "ISH_GP_5"),
260
-
PINCTRL_PIN(202, "ISH_GP_6"),
261
-
PINCTRL_PIN(203, "ISH_GP_7"),
262
-
PINCTRL_PIN(204, "IMGCLKOUT_4"),
263
-
PINCTRL_PIN(205, "DDPA_CTRLCLK"),
264
-
PINCTRL_PIN(206, "DDPA_CTRLDATA"),
265
-
PINCTRL_PIN(207, "DDPB_CTRLCLK"),
266
-
PINCTRL_PIN(208, "DDPB_CTRLDATA"),
267
-
PINCTRL_PIN(209, "DDPC_CTRLCLK"),
268
-
PINCTRL_PIN(210, "DDPC_CTRLDATA"),
269
-
PINCTRL_PIN(211, "IMGCLKOUT_5"),
270
-
PINCTRL_PIN(212, "CNV_BRI_DT"),
271
-
PINCTRL_PIN(213, "CNV_BRI_RSP"),
272
-
PINCTRL_PIN(214, "CNV_RGI_DT"),
273
-
PINCTRL_PIN(215, "CNV_RGI_RSP"),
260
+
PINCTRL_PIN(201, "ISH_GP_0"),
261
+
PINCTRL_PIN(202, "ISH_GP_1"),
262
+
PINCTRL_PIN(203, "IMGCLKOUT_1"),
263
+
PINCTRL_PIN(204, "ISH_GP_2"),
264
+
PINCTRL_PIN(205, "IMGCLKOUT_2"),
265
+
PINCTRL_PIN(206, "SATA_LEDB"),
266
+
PINCTRL_PIN(207, "IMGCLKOUT_3"),
267
+
PINCTRL_PIN(208, "ISH_GP_3"),
268
+
PINCTRL_PIN(209, "ISH_GP_4"),
269
+
PINCTRL_PIN(210, "ISH_GP_5"),
270
+
PINCTRL_PIN(211, "ISH_GP_6"),
271
+
PINCTRL_PIN(212, "ISH_GP_7"),
272
+
PINCTRL_PIN(213, "IMGCLKOUT_4"),
273
+
PINCTRL_PIN(214, "DDPA_CTRLCLK"),
274
+
PINCTRL_PIN(215, "DDPA_CTRLDATA"),
275
+
PINCTRL_PIN(216, "DDPB_CTRLCLK"),
276
+
PINCTRL_PIN(217, "DDPB_CTRLDATA"),
277
+
PINCTRL_PIN(218, "DDPC_CTRLCLK"),
278
+
PINCTRL_PIN(219, "DDPC_CTRLDATA"),
279
+
PINCTRL_PIN(220, "IMGCLKOUT_5"),
280
+
PINCTRL_PIN(221, "CNV_BRI_DT"),
281
+
PINCTRL_PIN(222, "CNV_BRI_RSP"),
282
+
PINCTRL_PIN(223, "CNV_RGI_DT"),
283
+
PINCTRL_PIN(224, "CNV_RGI_RSP"),
274
284
/* GPP_G */
275
-
PINCTRL_PIN(216, "SD3_CMD"),
276
-
PINCTRL_PIN(217, "SD3_D0"),
277
-
PINCTRL_PIN(218, "SD3_D1"),
278
-
PINCTRL_PIN(219, "SD3_D2"),
279
-
PINCTRL_PIN(220, "SD3_D3"),
280
-
PINCTRL_PIN(221, "SD3_CDB"),
281
-
PINCTRL_PIN(222, "SD3_CLK"),
282
-
PINCTRL_PIN(223, "SD3_WP"),
285
+
PINCTRL_PIN(225, "SD3_CMD"),
286
+
PINCTRL_PIN(226, "SD3_D0"),
287
+
PINCTRL_PIN(227, "SD3_D1"),
288
+
PINCTRL_PIN(228, "SD3_D2"),
289
+
PINCTRL_PIN(229, "SD3_D3"),
290
+
PINCTRL_PIN(230, "SD3_CDB"),
291
+
PINCTRL_PIN(231, "SD3_CLK"),
292
+
PINCTRL_PIN(232, "SD3_WP"),
283
293
};
284
294
285
295
static const struct intel_padgroup jsl_community0_gpps[] = {
286
296
JSL_GPP(0, 0, 19, 320), /* GPP_F */
287
-
JSL_GPP(1, 20, 45, 32), /* GPP_B */
288
-
JSL_GPP(2, 46, 66, 64), /* GPP_A */
289
-
JSL_GPP(3, 67, 74, 96), /* GPP_S */
290
-
JSL_GPP(4, 75, 82, 128), /* GPP_R */
297
+
JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */
298
+
JSL_GPP(2, 29, 54, 32), /* GPP_B */
299
+
JSL_GPP(3, 55, 75, 64), /* GPP_A */
300
+
JSL_GPP(4, 76, 83, 96), /* GPP_S */
301
+
JSL_GPP(5, 84, 91, 128), /* GPP_R */
291
302
};
292
303
293
304
static const struct intel_padgroup jsl_community1_gpps[] = {
294
-
JSL_GPP(0, 83, 106, 160), /* GPP_H */
295
-
JSL_GPP(1, 107, 132, 192), /* GPP_D */
296
-
JSL_GPP(2, 133, 161, 224), /* vGPIO */
297
-
JSL_GPP(3, 162, 185, 256), /* GPP_C */
305
+
JSL_GPP(0, 92, 115, 160), /* GPP_H */
306
+
JSL_GPP(1, 116, 141, 192), /* GPP_D */
307
+
JSL_GPP(2, 142, 170, 224), /* vGPIO */
308
+
JSL_GPP(3, 171, 194, 256), /* GPP_C */
298
309
};
299
310
300
311
static const struct intel_padgroup jsl_community4_gpps[] = {
301
-
JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
302
-
JSL_GPP(1, 192, 215, 288), /* GPP_E */
312
+
JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
313
+
JSL_GPP(1, 201, 224, 288), /* GPP_E */
303
314
};
304
315
305
316
static const struct intel_padgroup jsl_community5_gpps[] = {
306
-
JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */
317
+
JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */
307
318
};
308
319
309
320
static const struct intel_community jsl_communities[] = {
310
-
JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps),
311
-
JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps),
312
-
JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps),
313
-
JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps),
321
+
JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps),
322
+
JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps),
323
+
JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps),
324
+
JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps),
314
325
};
315
326
316
327
static const struct intel_pinctrl_soc_data jsl_soc_data = {
···
347
336
.pm = &jsl_pinctrl_pm_ops,
348
337
},
349
338
};
350
-
351
339
module_platform_driver(jsl_pinctrl_driver);
352
340
353
341
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+8
drivers/pinctrl/intel/pinctrl-merrifield.c
+8
drivers/pinctrl/intel/pinctrl-merrifield.c
···
745
745
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
746
746
bits |= BUFCFG_PU_EN;
747
747
748
+
/* Set default strength value in case none is given */
749
+
if (arg == 1)
750
+
arg = 20000;
751
+
748
752
switch (arg) {
749
753
case 50000:
750
754
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
···
768
764
case PIN_CONFIG_BIAS_PULL_DOWN:
769
765
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
770
766
bits |= BUFCFG_PD_EN;
767
+
768
+
/* Set default strength value in case none is given */
769
+
if (arg == 1)
770
+
arg = 20000;
771
771
772
772
switch (arg) {
773
773
case 50000:
-7
drivers/pinctrl/pinctrl-amd.c
-7
drivers/pinctrl/pinctrl-amd.c
···
429
429
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
430
430
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
431
431
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
432
-
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
433
432
irq_set_handler_locked(d, handle_edge_irq);
434
433
break;
435
434
···
436
437
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
437
438
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
438
439
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
439
-
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
440
440
irq_set_handler_locked(d, handle_edge_irq);
441
441
break;
442
442
···
443
445
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
444
446
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
445
447
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
446
-
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
447
448
irq_set_handler_locked(d, handle_edge_irq);
448
449
break;
449
450
···
450
453
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
451
454
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
452
455
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
453
-
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
454
-
pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
455
456
irq_set_handler_locked(d, handle_level_irq);
456
457
break;
457
458
···
457
462
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
458
463
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
459
464
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
460
-
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
461
-
pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
462
465
irq_set_handler_locked(d, handle_level_irq);
463
466
break;
464
467