tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv-for-linus-6.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

- A fix to avoid dropping some of the internal pseudo-extensions, which
breaks *envcfg dependency parsing

- The kernel entry address is now aligned in purgatory, which avoids a
misaligned load that can lead to crash on systems that don't support
misaligned accesses early in boot

- The FW_SFENCE_VMA_RECEIVED perf event was duplicated in a handful of
perf JSON configurations, one of them been updated to
FW_SFENCE_VMA_ASID_SENT

- The starfive cache driver is now restricted to 64-bit systems, as it
isn't 32-bit clean

- A fix for to avoid aliasing legacy-mode perf counters with software
perf counters

- VM_FAULT_SIGSEGV is now handled in the page fault code

- A fix for stalls during CPU hotplug due to IPIs being disabled

- A fix for memblock bounds checking. This manifests as a crash on
systems with discontinuous memory maps that have regions that don't
fit in the linear map

* tag 'riscv-for-linus-6.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fix linear mapping checks for non-contiguous memory regions
RISC-V: Enable the IPI before workqueue_online_cpu()
riscv/mm: Add handling for VM_FAULT_SIGSEGV in mm_fault_error()
perf: riscv: Fix selecting counters in legacy mode
cache: StarFive: Require a 64-bit system
perf arch events: Fix duplicate RISC-V SBI firmware event name
riscv/purgatory: align riscv_kernel_entry
riscv: cpufeature: Do not drop Linux-internal extensions

Linus Torvalds 948752d2 66242ef2

+37 -27
+6 -8
arch/riscv/kernel/cpufeature.c
··· 432 432 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX); 433 433 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) { 434 434 ext = riscv_get_isa_ext_data(bit); 435 - if (!ext) 436 - continue; 437 435 438 - if (ext->validate) { 436 + if (ext && ext->validate) { 439 437 ret = ext->validate(ext, resolved_isa); 440 438 if (ret == -EPROBE_DEFER) { 441 439 loop = true; 442 440 continue; 443 441 } else if (ret) { 444 442 /* Disable the extension entirely */ 445 - clear_bit(ext->id, source_isa); 443 + clear_bit(bit, source_isa); 446 444 continue; 447 445 } 448 446 } 449 447 450 - set_bit(ext->id, resolved_isa); 448 + set_bit(bit, resolved_isa); 451 449 /* No need to keep it in source isa now that it is enabled */ 452 - clear_bit(ext->id, source_isa); 450 + clear_bit(bit, source_isa); 453 451 454 452 /* Single letter extensions get set in hwcap */ 455 - if (ext->id < RISCV_ISA_EXT_BASE) 456 - *this_hwcap |= isa2hwcap[ext->id]; 453 + if (bit < RISCV_ISA_EXT_BASE) 454 + *this_hwcap |= isa2hwcap[bit]; 457 455 } 458 456 } while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa))); 459 457 }
+1 -1
arch/riscv/kernel/sbi-ipi.c
··· 71 71 * the masking/unmasking of virtual IPIs is done 72 72 * via generic IPI-Mux 73 73 */ 74 - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 74 + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING, 75 75 "irqchip/sbi-ipi:starting", 76 76 sbi_ipi_starting_cpu, NULL); 77 77
+9 -8
arch/riscv/mm/fault.c
··· 61 61 62 62 static inline void mm_fault_error(struct pt_regs *regs, unsigned long addr, vm_fault_t fault) 63 63 { 64 + if (!user_mode(regs)) { 65 + no_context(regs, addr); 66 + return; 67 + } 68 + 64 69 if (fault & VM_FAULT_OOM) { 65 70 /* 66 71 * We ran out of memory, call the OOM killer, and return the userspace 67 72 * (which will retry the fault, or kill us if we got oom-killed). 68 73 */ 69 - if (!user_mode(regs)) { 70 - no_context(regs, addr); 71 - return; 72 - } 73 74 pagefault_out_of_memory(); 74 75 return; 75 76 } else if (fault & (VM_FAULT_SIGBUS | VM_FAULT_HWPOISON | VM_FAULT_HWPOISON_LARGE)) { 76 77 /* Kernel mode? Handle exceptions or die */ 77 - if (!user_mode(regs)) { 78 - no_context(regs, addr); 79 - return; 80 - } 81 78 do_trap(regs, SIGBUS, BUS_ADRERR, addr); 82 79 return; 80 + } else if (fault & VM_FAULT_SIGSEGV) { 81 + do_trap(regs, SIGSEGV, SEGV_MAPERR, addr); 82 + return; 83 83 } 84 + 84 85 BUG(); 85 86 } 86 87
+11 -4
arch/riscv/mm/init.c
··· 234 234 */ 235 235 memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start); 236 236 237 - phys_ram_end = memblock_end_of_DRAM(); 238 - 239 237 /* 240 238 * Make sure we align the start of the memory on a PMD boundary so that 241 239 * at worst, we map the linear mapping with PMD mappings. ··· 247 249 */ 248 250 if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) 249 251 kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base; 252 + 253 + /* 254 + * The size of the linear page mapping may restrict the amount of 255 + * usable RAM. 256 + */ 257 + if (IS_ENABLED(CONFIG_64BIT)) { 258 + max_mapped_addr = __pa(PAGE_OFFSET) + KERN_VIRT_SIZE; 259 + memblock_cap_memory_range(phys_ram_base, 260 + max_mapped_addr - phys_ram_base); 261 + } 250 262 251 263 /* 252 264 * Reserve physical address space that would be mapped to virtual ··· 274 266 memblock_reserve(max_mapped_addr, (phys_addr_t)-max_mapped_addr); 275 267 } 276 268 269 + phys_ram_end = memblock_end_of_DRAM(); 277 270 min_low_pfn = PFN_UP(phys_ram_base); 278 271 max_low_pfn = max_pfn = PFN_DOWN(phys_ram_end); 279 272 high_memory = (void *)(__va(PFN_PHYS(max_low_pfn))); ··· 1293 1284 if (start <= __pa(PAGE_OFFSET) && 1294 1285 __pa(PAGE_OFFSET) < end) 1295 1286 start = __pa(PAGE_OFFSET); 1296 - if (end >= __pa(PAGE_OFFSET) + memory_limit) 1297 - end = __pa(PAGE_OFFSET) + memory_limit; 1298 1287 1299 1288 create_linear_mapping_range(start, end, 0, NULL); 1300 1289 }
+2
arch/riscv/purgatory/entry.S
··· 7 7 * Author: Li Zhengyu (lizhengyu3@huawei.com) 8 8 * 9 9 */ 10 + #include <asm/asm.h> 10 11 #include <linux/linkage.h> 11 12 12 13 .text ··· 35 34 36 35 .data 37 36 37 + .align LGREG 38 38 SYM_DATA(riscv_kernel_entry, .quad 0) 39 39 40 40 .end
+1
drivers/cache/Kconfig
··· 18 18 bool "StarFive StarLink Cache controller" 19 19 depends on RISCV 20 20 depends on ARCH_STARFIVE 21 + depends on 64BIT 21 22 select RISCV_DMA_NONCOHERENT 22 23 select RISCV_NONSTANDARD_CACHE_OPS 23 24 help
+1 -1
drivers/perf/riscv_pmu_sbi.c
··· 416 416 * but not in the user access mode as we want to use the other counters 417 417 * that support sampling/filtering. 418 418 */ 419 - if (hwc->flags & PERF_EVENT_FLAG_LEGACY) { 419 + if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) { 420 420 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) { 421 421 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; 422 422 cmask = 1;
+1
include/linux/cpuhotplug.h
··· 147 147 CPUHP_AP_IRQ_LOONGARCH_STARTING, 148 148 CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 149 149 CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, 150 + CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING, 150 151 CPUHP_AP_ARM_MVEBU_COHERENCY, 151 152 CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, 152 153 CPUHP_AP_PERF_X86_STARTING,
+1 -1
tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
··· 36 36 "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 37 37 }, 38 38 { 39 - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 39 + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" 40 40 }, 41 41 { 42 42 "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+1 -1
tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
··· 74 74 { 75 75 "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", 76 76 "ConfigCode": "0x800000000000000c", 77 - "EventName": "FW_SFENCE_VMA_RECEIVED", 77 + "EventName": "FW_SFENCE_VMA_ASID_SENT", 78 78 "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" 79 79 }, 80 80 {
+1 -1
tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
··· 36 36 "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 37 37 }, 38 38 { 39 - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 39 + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" 40 40 }, 41 41 { 42 42 "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+1 -1
tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json
··· 36 36 "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 37 37 }, 38 38 { 39 - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 39 + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" 40 40 }, 41 41 { 42 42 "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+1 -1
tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
··· 36 36 "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 37 37 }, 38 38 { 39 - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" 39 + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" 40 40 }, 41 41 { 42 42 "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"