Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: smd-rpm: Add clocks for MSM8909
MSM8909 has mostly the same as clocks in RPM as MSM8916,
but additionally the QPIC clock for the NAND flash controller.
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-7-stephan.gerhold@kernkonzept.com
authored by
Stephan Gerhold
and committed by
Bjorn Andersson
94a70c87
1727a402
+36
-1
+36
-1
drivers/clk/qcom/clk-smd-rpm.c
+36
-1
drivers/clk/qcom/clk-smd-rpm.c
···
417
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DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
418
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DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
419
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DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
420
+
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
420
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DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
421
422
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
422
423
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
···
427
426
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
429
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
429
+
430
+
static struct clk_smd_rpm *msm8909_clks[] = {
431
+
[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
432
+
[RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
433
+
[RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
434
+
[RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
435
+
[RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
436
+
[RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
437
+
[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
438
+
[RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
439
+
[RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
440
+
[RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
441
+
[RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
442
+
[RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
443
+
[RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
444
+
[RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
445
+
[RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
446
+
[RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
447
+
[RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
448
+
[RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
449
+
[RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
450
+
[RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
451
+
[RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
452
+
[RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
453
+
[RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
454
+
[RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
455
+
[RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
456
+
[RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
457
+
};
458
+
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+
static const struct rpm_smd_clk_desc rpm_clk_msm8909 = {
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+
.clks = msm8909_clks,
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+
.num_clks = ARRAY_SIZE(msm8909_clks),
462
+
};
430
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431
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static struct clk_smd_rpm *msm8916_clks[] = {
432
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[RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
···
822
787
};
823
788
824
789
DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
825
-
DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
826
790
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
827
791
828
792
static struct clk_smd_rpm *qcs404_clks[] = {
···
1180
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static const struct of_device_id rpm_smd_clk_match_table[] = {
1181
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{ .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1182
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{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1149
+
{ .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
1183
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{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1184
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{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1185
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{ .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },