Merge tag 'wireless-next-2025-09-25' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next

+1 -2

drivers/net/wireless/ath/ath10k/leds.c

··· 27 27 goto out; 28 28 29 29 ar->leds.gpio_state_pin = (brightness != LED_OFF) ^ led->active_low; 30 - ath10k_wmi_gpio_output(ar, led->gpio, ar->leds.gpio_state_pin); 30 + ath10k_wmi_gpio_output(ar, ar->hw_params.led_pin, ar->leds.gpio_state_pin); 31 31 32 32 out: 33 33 mutex_unlock(&ar->conf_mutex); ··· 64 64 snprintf(ar->leds.label, sizeof(ar->leds.label), "ath10k-%s", 65 65 wiphy_name(ar->hw->wiphy)); 66 66 ar->leds.wifi_led.active_low = 1; 67 - ar->leds.wifi_led.gpio = ar->hw_params.led_pin; 68 67 ar->leds.wifi_led.name = ar->leds.label; 69 68 ar->leds.wifi_led.default_state = LEDS_GPIO_DEFSTATE_KEEP; 70 69

+10 -2

drivers/net/wireless/ath/ath10k/mac.c

··· 16 16 #include <linux/acpi.h> 17 17 #include <linux/of.h> 18 18 #include <linux/bitfield.h> 19 + #include <linux/random.h> 19 20 20 21 #include "hif.h" 21 22 #include "core.h" ··· 291 290 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 292 291 293 292 if (cmd == DISABLE_KEY) { 294 - arg.key_cipher = ar->wmi_key_cipher[WMI_CIPHER_NONE]; 295 - arg.key_data = NULL; 293 + if (flags & WMI_KEY_GROUP) { 294 + /* Not all hardware handles group-key deletion operation 295 + * correctly. Replace the key with a junk value to invalidate it. 296 + */ 297 + get_random_bytes(key->key, key->keylen); 298 + } else { 299 + arg.key_cipher = ar->wmi_key_cipher[WMI_CIPHER_NONE]; 300 + arg.key_data = NULL; 301 + } 296 302 } 297 303 298 304 return ath10k_wmi_vdev_install_key(arvif->ar, &arg);

+3 -11

drivers/net/wireless/ath/ath10k/snoc.c

··· 13 13 #include <linux/property.h> 14 14 #include <linux/regulator/consumer.h> 15 15 #include <linux/remoteproc/qcom_rproc.h> 16 - #include <linux/of_address.h> 16 + #include <linux/of_reserved_mem.h> 17 17 #include <linux/iommu.h> 18 18 19 19 #include "ce.h" ··· 1559 1559 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size) 1560 1560 { 1561 1561 struct device *dev = ar->dev; 1562 - struct device_node *node; 1563 1562 struct resource r; 1564 1563 int ret; 1565 1564 1566 - node = of_parse_phandle(dev->of_node, "memory-region", 0); 1567 - if (node) { 1568 - ret = of_address_to_resource(node, 0, &r); 1569 - of_node_put(node); 1570 - if (ret) { 1571 - dev_err(dev, "failed to resolve msa fixed region\n"); 1572 - return ret; 1573 - } 1574 - 1565 + ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &r); 1566 + if (!ret) { 1575 1567 ar->msa.paddr = r.start; 1576 1568 ar->msa.mem_size = resource_size(&r); 1577 1569 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr,

+19 -20

drivers/net/wireless/ath/ath10k/wmi.c

··· 1764 1764 1765 1765 int ath10k_wmi_wait_for_service_ready(struct ath10k *ar) 1766 1766 { 1767 + unsigned long timeout = jiffies + WMI_SERVICE_READY_TIMEOUT_HZ; 1767 1768 unsigned long time_left, i; 1768 1769 1769 - time_left = wait_for_completion_timeout(&ar->wmi.service_ready, 1770 - WMI_SERVICE_READY_TIMEOUT_HZ); 1771 - if (!time_left) { 1772 - /* Sometimes the PCI HIF doesn't receive interrupt 1773 - * for the service ready message even if the buffer 1774 - * was completed. PCIe sniffer shows that it's 1775 - * because the corresponding CE ring doesn't fires 1776 - * it. Workaround here by polling CE rings once. 1777 - */ 1778 - ath10k_warn(ar, "failed to receive service ready completion, polling..\n"); 1779 - 1770 + /* Sometimes the PCI HIF doesn't receive interrupt 1771 + * for the service ready message even if the buffer 1772 + * was completed. PCIe sniffer shows that it's 1773 + * because the corresponding CE ring doesn't fires 1774 + * it. Workaround here by polling CE rings. Since 1775 + * the message could arrive at any time, continue 1776 + * polling until timeout. 1777 + */ 1778 + do { 1780 1779 for (i = 0; i < CE_COUNT; i++) 1781 1780 ath10k_hif_send_complete_check(ar, i, 1); 1782 1781 1782 + /* The 100 ms granularity is a tradeoff considering scheduler 1783 + * overhead and response latency 1784 + */ 1783 1785 time_left = wait_for_completion_timeout(&ar->wmi.service_ready, 1784 - WMI_SERVICE_READY_TIMEOUT_HZ); 1785 - if (!time_left) { 1786 - ath10k_warn(ar, "polling timed out\n"); 1787 - return -ETIMEDOUT; 1788 - } 1786 + msecs_to_jiffies(100)); 1787 + if (time_left) 1788 + return 0; 1789 + } while (time_before(jiffies, timeout)); 1789 1790 1790 - ath10k_warn(ar, "service ready completion received, continuing normally\n"); 1791 - } 1792 - 1793 - return 0; 1791 + ath10k_warn(ar, "failed to receive service ready completion\n"); 1792 + return -ETIMEDOUT; 1794 1793 } 1795 1794 1796 1795 int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar)

+3 -14

drivers/net/wireless/ath/ath11k/ahb.c

··· 9 9 #include <linux/property.h> 10 10 #include <linux/of_device.h> 11 11 #include <linux/of.h> 12 + #include <linux/of_reserved_mem.h> 12 13 #include <linux/dma-mapping.h> 13 - #include <linux/of_address.h> 14 14 #include <linux/iommu.h> 15 15 #include "ahb.h" 16 16 #include "debug.h" ··· 919 919 { 920 920 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 921 921 struct device *dev = ab->dev; 922 - struct device_node *node; 923 922 struct resource r; 924 923 int ret; 925 924 926 - node = of_parse_phandle(dev->of_node, "memory-region", 0); 927 - if (!node) 928 - return -ENOENT; 929 - 930 - ret = of_address_to_resource(node, 0, &r); 931 - of_node_put(node); 925 + ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &r); 932 926 if (ret) { 933 927 dev_err(dev, "failed to resolve msa fixed region\n"); 934 928 return ret; ··· 931 937 ab_ahb->fw.msa_paddr = r.start; 932 938 ab_ahb->fw.msa_size = resource_size(&r); 933 939 934 - node = of_parse_phandle(dev->of_node, "memory-region", 1); 935 - if (!node) 936 - return -ENOENT; 937 - 938 - ret = of_address_to_resource(node, 0, &r); 939 - of_node_put(node); 940 + ret = of_reserved_mem_region_to_resource(dev->of_node, 1, &r); 940 941 if (ret) { 941 942 dev_err(dev, "failed to resolve ce fixed region\n"); 942 943 return ret;

+2 -1

drivers/net/wireless/ath/ath11k/ce.c

··· 354 354 ret = ath11k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr); 355 355 356 356 if (ret) { 357 - ath11k_warn(ab, "failed to enqueue rx buf: %d\n", ret); 357 + ath11k_dbg(ab, ATH11K_DBG_CE, "failed to enqueue rx buf: %d\n", 358 + ret); 358 359 dma_unmap_single(ab->dev, paddr, 359 360 skb->len + skb_tailroom(skb), 360 361 DMA_FROM_DEVICE);

+1 -5

drivers/net/wireless/ath/ath11k/core.c

··· 2215 2215 mutex_unlock(&ab->core_lock); 2216 2216 2217 2217 ath11k_dp_free(ab); 2218 - ath11k_hal_srng_deinit(ab); 2218 + ath11k_hal_srng_clear(ab); 2219 2219 2220 2220 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 2221 - 2222 - ret = ath11k_hal_srng_init(ab); 2223 - if (ret) 2224 - return ret; 2225 2221 2226 2222 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 2227 2223

-1

drivers/net/wireless/ath/ath11k/dp_rx.c

··· 4615 4615 msdu_details[i].buf_addr_info.info0) == 0) { 4616 4616 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4617 4617 msdu_desc_info->info0 |= last; 4618 - ; 4619 4618 break; 4620 4619 } 4621 4620 msdu_desc_info = &msdu_details[i].rx_msdu_info;

+16

drivers/net/wireless/ath/ath11k/hal.c

··· 1386 1386 } 1387 1387 EXPORT_SYMBOL(ath11k_hal_srng_deinit); 1388 1388 1389 + void ath11k_hal_srng_clear(struct ath11k_base *ab) 1390 + { 1391 + /* No need to memset rdp and wrp memory since each individual 1392 + * segment would get cleared in ath11k_hal_srng_src_hw_init() 1393 + * and ath11k_hal_srng_dst_hw_init(). 1394 + */ 1395 + memset(ab->hal.srng_list, 0, 1396 + sizeof(ab->hal.srng_list)); 1397 + memset(ab->hal.shadow_reg_addr, 0, 1398 + sizeof(ab->hal.shadow_reg_addr)); 1399 + ab->hal.avail_blk_resource = 0; 1400 + ab->hal.current_blk_index = 0; 1401 + ab->hal.num_shadow_reg_configured = 0; 1402 + } 1403 + EXPORT_SYMBOL(ath11k_hal_srng_clear); 1404 + 1389 1405 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab) 1390 1406 { 1391 1407 struct hal_srng *srng;

+1

drivers/net/wireless/ath/ath11k/hal.h

··· 965 965 struct hal_srng_params *params); 966 966 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 967 967 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 968 + void ath11k_hal_srng_clear(struct ath11k_base *ab); 968 969 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 969 970 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 970 971 u32 **cfg, u32 *len);

+5 -14

drivers/net/wireless/ath/ath11k/qmi.c

··· 13 13 #include "debug.h" 14 14 #include "hif.h" 15 15 #include <linux/of.h> 16 - #include <linux/of_address.h> 16 + #include <linux/of_reserved_mem.h> 17 17 #include <linux/ioport.h> 18 18 #include <linux/firmware.h> 19 19 #include <linux/of_irq.h> ··· 2040 2040 static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab) 2041 2041 { 2042 2042 struct device *dev = ab->dev; 2043 - struct device_node *hremote_node = NULL; 2044 - struct resource res; 2043 + struct resource res = {}; 2045 2044 u32 host_ddr_sz; 2046 2045 int i, idx, ret; 2047 2046 2048 2047 for (i = 0, idx = 0; i < ab->qmi.mem_seg_count; i++) { 2049 2048 switch (ab->qmi.target_mem[i].type) { 2050 2049 case HOST_DDR_REGION_TYPE: 2051 - hremote_node = of_parse_phandle(dev->of_node, "memory-region", 0); 2052 - if (!hremote_node) { 2053 - ath11k_dbg(ab, ATH11K_DBG_QMI, 2054 - "fail to get hremote_node\n"); 2055 - return -ENODEV; 2056 - } 2057 - 2058 - ret = of_address_to_resource(hremote_node, 0, &res); 2059 - of_node_put(hremote_node); 2050 + ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 2060 2051 if (ret) { 2061 2052 ath11k_dbg(ab, ATH11K_DBG_QMI, 2062 2053 "fail to get reg from hremote\n"); ··· 2086 2095 } 2087 2096 2088 2097 if (ath11k_core_coldboot_cal_support(ab)) { 2089 - if (hremote_node) { 2098 + if (resource_size(&res)) { 2090 2099 ab->qmi.target_mem[idx].paddr = 2091 2100 res.start + host_ddr_sz; 2092 2101 ab->qmi.target_mem[idx].iaddr = ··· 2548 2557 GFP_KERNEL); 2549 2558 if (!m3_mem->vaddr) { 2550 2559 ath11k_err(ab, "failed to allocate memory for M3 with size %zu\n", 2551 - fw->size); 2560 + m3_len); 2552 2561 ret = -ENOMEM; 2553 2562 goto out; 2554 2563 }

+3 -2

drivers/net/wireless/ath/ath12k/ce.c

··· 392 392 393 393 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr); 394 394 if (ret) { 395 - ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret); 395 + ath12k_dbg(ab, ATH12K_DBG_CE, "failed to enqueue rx buf: %d\n", 396 + ret); 396 397 dma_unmap_single(ab->dev, paddr, 397 398 skb->len + skb_tailroom(skb), 398 399 DMA_FROM_DEVICE); ··· 479 478 } 480 479 481 480 while ((skb = __skb_dequeue(&list))) { 482 - ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n", 481 + ath12k_dbg(ab, ATH12K_DBG_CE, "rx ce pipe %d len %d\n", 483 482 pipe->pipe_num, skb->len); 484 483 pipe->recv_cb(ab, skb); 485 484 }

+6 -1

drivers/net/wireless/ath/ath12k/core.h

··· 1 1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 2 /* 3 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 - * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 5 */ 6 6 7 7 #ifndef ATH12K_CORE_H ··· 71 71 72 72 #define ATH12K_MAX_MLO_PEERS 256 73 73 #define ATH12K_MLO_PEER_ID_INVALID 0xFFFF 74 + 75 + #define ATH12K_INVALID_RSSI_FULL -1 76 + #define ATH12K_INVALID_RSSI_EMPTY -128 74 77 75 78 enum ath12k_bdf_search { 76 79 ATH12K_BDF_SEARCH_DEFAULT, ··· 563 560 u32 bw_prev; 564 561 u32 peer_nss; 565 562 s8 rssi_beacon; 563 + s8 chain_signal[IEEE80211_MAX_CHAINS]; 566 564 567 565 /* For now the assoc link will be considered primary */ 568 566 bool is_assoc_link; ··· 734 730 u32 txpower_scale; 735 731 u32 power_scale; 736 732 u32 chan_tx_pwr; 733 + u32 rts_threshold; 737 734 u32 num_stations; 738 735 u32 max_num_stations; 739 736

+1

drivers/net/wireless/ath/ath12k/debug.h

··· 26 26 ATH12K_DBG_DP_TX = 0x00002000, 27 27 ATH12K_DBG_DP_RX = 0x00004000, 28 28 ATH12K_DBG_WOW = 0x00008000, 29 + ATH12K_DBG_CE = 0x00010000, 29 30 ATH12K_DBG_ANY = 0xffffffff, 30 31 }; 31 32

+2

drivers/net/wireless/ath/ath12k/dp.c

··· 1745 1745 1746 1746 INIT_LIST_HEAD(&dp->reo_cmd_list); 1747 1747 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 1748 + INIT_LIST_HEAD(&dp->reo_cmd_update_rx_queue_list); 1748 1749 spin_lock_init(&dp->reo_cmd_lock); 1750 + spin_lock_init(&dp->reo_rxq_flush_lock); 1749 1751 1750 1752 dp->reo_cmd_cache_flush_count = 0; 1751 1753 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab);

+8 -4

drivers/net/wireless/ath/ath12k/dp.h

··· 184 184 #define DP_REO_REINJECT_RING_SIZE 32 185 185 #define DP_RX_RELEASE_RING_SIZE 1024 186 186 #define DP_REO_EXCEPTION_RING_SIZE 128 187 - #define DP_REO_CMD_RING_SIZE 128 187 + #define DP_REO_CMD_RING_SIZE 256 188 188 #define DP_REO_STATUS_RING_SIZE 2048 189 189 #define DP_RXDMA_BUF_RING_SIZE 4096 190 190 #define DP_RX_MAC_BUF_RING_SIZE 2048 ··· 389 389 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 390 390 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 391 391 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 392 - struct list_head reo_cmd_list; 392 + struct list_head reo_cmd_update_rx_queue_list; 393 393 struct list_head reo_cmd_cache_flush_list; 394 394 u32 reo_cmd_cache_flush_count; 395 - 396 395 /* protects access to below fields, 397 - * - reo_cmd_list 396 + * - reo_cmd_update_rx_queue_list 398 397 * - reo_cmd_cache_flush_list 399 398 * - reo_cmd_cache_flush_count 399 + */ 400 + spinlock_t reo_rxq_flush_lock; 401 + struct list_head reo_cmd_list; 402 + /* protects access to below fields, 403 + * - reo_cmd_list 400 404 */ 401 405 spinlock_t reo_cmd_lock; 402 406 struct ath12k_hp_update_timer reo_cmd_timer;

+42 -14

drivers/net/wireless/ath/ath12k/dp_mon.c

··· 1441 1441 } 1442 1442 1443 1443 static void 1444 + ath12k_parse_cmn_usr_info(const struct hal_phyrx_common_user_info *cmn_usr_info, 1445 + struct hal_rx_mon_ppdu_info *ppdu_info) 1446 + { 1447 + struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht; 1448 + u32 known, data, cp_setting, ltf_size; 1449 + 1450 + known = __le32_to_cpu(eht->known); 1451 + known |= IEEE80211_RADIOTAP_EHT_KNOWN_GI | 1452 + IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF; 1453 + eht->known = cpu_to_le32(known); 1454 + 1455 + cp_setting = le32_get_bits(cmn_usr_info->info0, 1456 + HAL_RX_CMN_USR_INFO0_CP_SETTING); 1457 + ltf_size = le32_get_bits(cmn_usr_info->info0, 1458 + HAL_RX_CMN_USR_INFO0_LTF_SIZE); 1459 + 1460 + data = __le32_to_cpu(eht->data[0]); 1461 + data |= u32_encode_bits(cp_setting, IEEE80211_RADIOTAP_EHT_DATA0_GI); 1462 + data |= u32_encode_bits(ltf_size, IEEE80211_RADIOTAP_EHT_DATA0_LTF); 1463 + eht->data[0] = cpu_to_le32(data); 1464 + 1465 + if (!ppdu_info->ltf_size) 1466 + ppdu_info->ltf_size = ltf_size; 1467 + if (!ppdu_info->gi) 1468 + ppdu_info->gi = cp_setting; 1469 + } 1470 + 1471 + static void 1444 1472 ath12k_dp_mon_parse_status_msdu_end(struct ath12k_mon_data *pmon, 1445 1473 const struct hal_rx_msdu_end *msdu_end) 1446 1474 { ··· 1655 1627 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data; 1656 1628 1657 1629 info[0] = __le32_to_cpu(rssi->info0); 1658 - info[1] = __le32_to_cpu(rssi->info1); 1630 + info[2] = __le32_to_cpu(rssi->info2); 1659 1631 1660 1632 /* TODO: Please note that the combined rssi will not be accurate 1661 1633 * in MU case. Rssi in MU needs to be retrieved from 1662 1634 * PHYRX_OTHER_RECEIVE_INFO TLV. 1663 1635 */ 1664 1636 ppdu_info->rssi_comb = 1665 - u32_get_bits(info[1], 1666 - HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB); 1637 + u32_get_bits(info[2], 1638 + HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU); 1667 1639 1668 1640 ppdu_info->bw = u32_get_bits(info[0], 1669 - HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW); 1641 + HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW); 1670 1642 break; 1671 1643 } 1672 - case HAL_PHYRX_OTHER_RECEIVE_INFO: { 1673 - const struct hal_phyrx_common_user_info *cmn_usr_info = tlv_data; 1674 - 1675 - ppdu_info->gi = le32_get_bits(cmn_usr_info->info0, 1676 - HAL_RX_PHY_CMN_USER_INFO0_GI); 1644 + case HAL_PHYRX_COMMON_USER_INFO: { 1645 + ath12k_parse_cmn_usr_info(tlv_data, ppdu_info); 1677 1646 break; 1678 1647 } 1679 1648 case HAL_RX_PPDU_START_USER_INFO: ··· 2179 2154 spin_unlock_bh(&ar->data_lock); 2180 2155 2181 2156 rxs->flag |= RX_FLAG_MACTIME_START; 2182 - rxs->signal = ppduinfo->rssi_comb + noise_floor; 2183 2157 rxs->nss = ppduinfo->nss + 1; 2158 + if (test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 2159 + ar->ab->wmi_ab.svc_map)) 2160 + rxs->signal = ppduinfo->rssi_comb; 2161 + else 2162 + rxs->signal = ppduinfo->rssi_comb + noise_floor; 2184 2163 2185 2164 if (ppduinfo->userstats[ppduinfo->userid].ampdu_present) { 2186 2165 rxs->flag |= RX_FLAG_AMPDU_DETAILS; ··· 2273 2244 2274 2245 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2275 2246 struct sk_buff *msdu, 2247 + const struct hal_rx_mon_ppdu_info *ppduinfo, 2276 2248 struct ieee80211_rx_status *status, 2277 2249 u8 decap) 2278 2250 { ··· 2287 2257 struct ieee80211_sta *pubsta = NULL; 2288 2258 struct ath12k_peer *peer; 2289 2259 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2290 - struct ath12k_dp_rx_info rx_info; 2291 2260 bool is_mcbc = rxcb->is_mcbc; 2292 2261 bool is_eapol_tkip = rxcb->is_eapol; 2293 2262 ··· 2300 2271 } 2301 2272 2302 2273 spin_lock_bh(&ar->ab->base_lock); 2303 - rx_info.addr2_present = false; 2304 - peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu, &rx_info); 2274 + peer = ath12k_peer_find_by_id(ar->ab, ppduinfo->peer_id); 2305 2275 if (peer && peer->sta) { 2306 2276 pubsta = peer->sta; 2307 2277 if (pubsta->valid_links) { ··· 2393 2365 decap = mon_mpdu->decap_format; 2394 2366 2395 2367 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs); 2396 - ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs, decap); 2368 + ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, ppduinfo, rxs, decap); 2397 2369 mon_skb = skb_next; 2398 2370 } while (mon_skb); 2399 2371 rxs->flag = 0;

+235 -117

drivers/net/wireless/ath/ath12k/dp_rx.c

··· 21 21 22 22 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 23 23 24 + static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 25 + struct ath12k_dp_rx_tid_rxq *rx_tid); 26 + 24 27 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 25 28 struct hal_rx_desc *desc) 26 29 { ··· 584 581 return 0; 585 582 } 586 583 584 + static void ath12k_dp_init_rx_tid_rxq(struct ath12k_dp_rx_tid_rxq *rx_tid_rxq, 585 + struct ath12k_dp_rx_tid *rx_tid) 586 + { 587 + rx_tid_rxq->tid = rx_tid->tid; 588 + rx_tid_rxq->active = rx_tid->active; 589 + rx_tid_rxq->qbuf = rx_tid->qbuf; 590 + } 591 + 592 + static void ath12k_dp_rx_tid_cleanup(struct ath12k_base *ab, 593 + struct ath12k_reoq_buf *tid_qbuf) 594 + { 595 + if (tid_qbuf->vaddr) { 596 + dma_unmap_single(ab->dev, tid_qbuf->paddr_aligned, 597 + tid_qbuf->size, DMA_BIDIRECTIONAL); 598 + kfree(tid_qbuf->vaddr); 599 + tid_qbuf->vaddr = NULL; 600 + } 601 + } 602 + 587 603 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 588 604 { 589 605 struct ath12k_dp *dp = &ab->dp; 590 606 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 591 607 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 608 + struct dp_reo_update_rx_queue_elem *cmd_queue, *tmp_queue; 592 609 593 - spin_lock_bh(&dp->reo_cmd_lock); 594 - list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 595 - list_del(&cmd->list); 596 - dma_unmap_single(ab->dev, cmd->data.qbuf.paddr_aligned, 597 - cmd->data.qbuf.size, DMA_BIDIRECTIONAL); 598 - kfree(cmd->data.qbuf.vaddr); 599 - kfree(cmd); 610 + spin_lock_bh(&dp->reo_rxq_flush_lock); 611 + list_for_each_entry_safe(cmd_queue, tmp_queue, &dp->reo_cmd_update_rx_queue_list, 612 + list) { 613 + list_del(&cmd_queue->list); 614 + ath12k_dp_rx_tid_cleanup(ab, &cmd_queue->rx_tid.qbuf); 615 + kfree(cmd_queue); 600 616 } 601 - 602 617 list_for_each_entry_safe(cmd_cache, tmp_cache, 603 618 &dp->reo_cmd_cache_flush_list, list) { 604 619 list_del(&cmd_cache->list); 605 620 dp->reo_cmd_cache_flush_count--; 606 - dma_unmap_single(ab->dev, cmd_cache->data.qbuf.paddr_aligned, 607 - cmd_cache->data.qbuf.size, DMA_BIDIRECTIONAL); 608 - kfree(cmd_cache->data.qbuf.vaddr); 621 + ath12k_dp_rx_tid_cleanup(ab, &cmd_cache->data.qbuf); 609 622 kfree(cmd_cache); 623 + } 624 + spin_unlock_bh(&dp->reo_rxq_flush_lock); 625 + 626 + spin_lock_bh(&dp->reo_cmd_lock); 627 + list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 628 + list_del(&cmd->list); 629 + ath12k_dp_rx_tid_cleanup(ab, &cmd->data.qbuf); 630 + kfree(cmd); 610 631 } 611 632 spin_unlock_bh(&dp->reo_cmd_lock); 612 633 } ··· 638 611 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 639 612 enum hal_reo_cmd_status status) 640 613 { 641 - struct ath12k_dp_rx_tid *rx_tid = ctx; 614 + struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 642 615 643 616 if (status != HAL_REO_CMD_SUCCESS) 644 617 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 645 618 rx_tid->tid, status); 646 619 647 - dma_unmap_single(dp->ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 648 - DMA_BIDIRECTIONAL); 649 - kfree(rx_tid->qbuf.vaddr); 650 - rx_tid->qbuf.vaddr = NULL; 620 + ath12k_dp_rx_tid_cleanup(dp->ab, &rx_tid->qbuf); 651 621 } 652 622 653 - static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 623 + static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, 624 + struct ath12k_dp_rx_tid_rxq *rx_tid, 654 625 enum hal_reo_cmd_type type, 655 626 struct ath12k_hal_reo_cmd *cmd, 656 627 void (*cb)(struct ath12k_dp *dp, void *ctx, ··· 693 668 return 0; 694 669 } 695 670 696 - static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 697 - struct ath12k_dp_rx_tid *rx_tid) 671 + static int ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 672 + struct ath12k_dp_rx_tid_rxq *rx_tid) 698 673 { 699 674 struct ath12k_hal_reo_cmd cmd = {}; 700 - unsigned long tot_desc_sz, desc_sz; 701 675 int ret; 702 676 703 - tot_desc_sz = rx_tid->qbuf.size; 704 - desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 705 - 706 - while (tot_desc_sz > desc_sz) { 707 - tot_desc_sz -= desc_sz; 708 - cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned + tot_desc_sz); 709 - cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 710 - ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 711 - HAL_REO_CMD_FLUSH_CACHE, &cmd, 712 - NULL); 713 - if (ret) 714 - ath12k_warn(ab, 715 - "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 716 - rx_tid->tid, ret); 717 - } 718 - 719 - memset(&cmd, 0, sizeof(cmd)); 720 677 cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 721 678 cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 722 - cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 679 + /* HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS - all pending MPDUs 680 + *in the bitmap will be forwarded/flushed to REO output rings 681 + */ 682 + cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS | 683 + HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS; 684 + 685 + /* For all QoS TIDs (except NON_QOS), the driver allocates a maximum 686 + * window size of 1024. In such cases, the driver can issue a single 687 + * 1KB descriptor flush command instead of sending multiple 128-byte 688 + * flush commands for each QoS TID, improving efficiency. 689 + */ 690 + 691 + if (rx_tid->tid != HAL_DESC_REO_NON_QOS_TID) 692 + cmd.flag |= HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC; 693 + 723 694 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 724 695 HAL_REO_CMD_FLUSH_CACHE, 725 696 &cmd, ath12k_dp_reo_cmd_free); 726 - if (ret) { 727 - ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 728 - rx_tid->tid, ret); 729 - dma_unmap_single(ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 730 - DMA_BIDIRECTIONAL); 731 - kfree(rx_tid->qbuf.vaddr); 732 - rx_tid->qbuf.vaddr = NULL; 697 + return ret; 698 + } 699 + 700 + static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 701 + { 702 + struct ath12k_reo_queue_ref *qref; 703 + struct ath12k_dp *dp = &ab->dp; 704 + bool ml_peer = false; 705 + 706 + if (!ab->hw_params->reoq_lut_support) 707 + return; 708 + 709 + if (peer_id & ATH12K_PEER_ML_ID_VALID) { 710 + peer_id &= ~ATH12K_PEER_ML_ID_VALID; 711 + ml_peer = true; 733 712 } 713 + 714 + if (ml_peer) 715 + qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 716 + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 717 + else 718 + qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 719 + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 720 + 721 + qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 722 + qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 723 + u32_encode_bits(tid, DP_REO_QREF_NUM); 724 + } 725 + 726 + static void ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(struct ath12k_dp *dp) 727 + { 728 + struct ath12k_base *ab = dp->ab; 729 + struct dp_reo_update_rx_queue_elem *elem, *tmp; 730 + 731 + spin_lock_bh(&dp->reo_rxq_flush_lock); 732 + 733 + list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_update_rx_queue_list, list) { 734 + if (elem->rx_tid.active) 735 + continue; 736 + 737 + if (ath12k_dp_rx_tid_delete_handler(ab, &elem->rx_tid)) 738 + break; 739 + 740 + ath12k_peer_rx_tid_qref_reset(ab, 741 + elem->is_ml_peer ? elem->ml_peer_id : 742 + elem->peer_id, 743 + elem->rx_tid.tid); 744 + 745 + if (ab->hw_params->reoq_lut_support) 746 + ath12k_hal_reo_shared_qaddr_cache_clear(ab); 747 + 748 + list_del(&elem->list); 749 + kfree(elem); 750 + } 751 + 752 + spin_unlock_bh(&dp->reo_rxq_flush_lock); 734 753 } 735 754 736 755 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 737 756 enum hal_reo_cmd_status status) 738 757 { 739 758 struct ath12k_base *ab = dp->ab; 740 - struct ath12k_dp_rx_tid *rx_tid = ctx; 759 + struct ath12k_dp_rx_tid_rxq *rx_tid = ctx; 741 760 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 742 761 743 762 if (status == HAL_REO_CMD_DRAIN) { ··· 793 724 return; 794 725 } 795 726 727 + /* Retry the HAL_REO_CMD_UPDATE_RX_QUEUE command for entries 728 + * in the pending queue list marked TID as inactive 729 + */ 730 + spin_lock_bh(&dp->ab->base_lock); 731 + ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 732 + spin_unlock_bh(&dp->ab->base_lock); 733 + 796 734 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 797 735 if (!elem) 798 736 goto free_desc; ··· 807 731 elem->ts = jiffies; 808 732 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 809 733 810 - spin_lock_bh(&dp->reo_cmd_lock); 734 + spin_lock_bh(&dp->reo_rxq_flush_lock); 811 735 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 812 736 dp->reo_cmd_cache_flush_count++; 813 737 ··· 817 741 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 818 742 time_after(jiffies, elem->ts + 819 743 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 744 + /* The reo_cmd_cache_flush_list is used in only two contexts, 745 + * one is in this function called from napi and the 746 + * other in ath12k_dp_free during core destroy. 747 + * If cache command sent is success, delete the element in 748 + * the cache list. ath12k_dp_rx_reo_cmd_list_cleanup 749 + * will be called during core destroy. 750 + */ 751 + 752 + if (ath12k_dp_reo_cache_flush(ab, &elem->data)) 753 + break; 754 + 820 755 list_del(&elem->list); 821 756 dp->reo_cmd_cache_flush_count--; 822 - 823 - /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 824 - * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 825 - * is used in only two contexts, one is in this function called 826 - * from napi and the other in ath12k_dp_free during core destroy. 827 - * Before dp_free, the irqs would be disabled and would wait to 828 - * synchronize. Hence there wouldn’t be any race against add or 829 - * delete to this list. Hence unlock-lock is safe here. 830 - */ 831 - spin_unlock_bh(&dp->reo_cmd_lock); 832 - 833 - ath12k_dp_reo_cache_flush(ab, &elem->data); 834 757 kfree(elem); 835 - spin_lock_bh(&dp->reo_cmd_lock); 836 758 } 837 759 } 838 - spin_unlock_bh(&dp->reo_cmd_lock); 760 + spin_unlock_bh(&dp->reo_rxq_flush_lock); 839 761 840 762 return; 841 763 free_desc: 842 - dma_unmap_single(ab->dev, rx_tid->qbuf.paddr_aligned, rx_tid->qbuf.size, 843 - DMA_BIDIRECTIONAL); 844 - kfree(rx_tid->qbuf.vaddr); 845 - rx_tid->qbuf.vaddr = NULL; 764 + ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 765 + } 766 + 767 + static int ath12k_dp_rx_tid_delete_handler(struct ath12k_base *ab, 768 + struct ath12k_dp_rx_tid_rxq *rx_tid) 769 + { 770 + struct ath12k_hal_reo_cmd cmd = {}; 771 + 772 + cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 773 + cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 774 + cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 775 + cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 776 + /* Observed flush cache failure, to avoid that set vld bit during delete */ 777 + cmd.upd1 |= HAL_REO_CMD_UPD1_VLD; 778 + 779 + return ath12k_dp_reo_cmd_send(ab, rx_tid, 780 + HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 781 + ath12k_dp_rx_tid_del_func); 846 782 } 847 783 848 784 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, ··· 887 799 ath12k_hal_reo_shared_qaddr_cache_clear(ab); 888 800 } 889 801 890 - static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 802 + static void ath12k_dp_mark_tid_as_inactive(struct ath12k_dp *dp, int peer_id, u8 tid) 891 803 { 892 - struct ath12k_reo_queue_ref *qref; 893 - struct ath12k_dp *dp = &ab->dp; 894 - bool ml_peer = false; 804 + struct dp_reo_update_rx_queue_elem *elem; 805 + struct ath12k_dp_rx_tid_rxq *rx_tid; 895 806 896 - if (!ab->hw_params->reoq_lut_support) 897 - return; 898 - 899 - if (peer_id & ATH12K_PEER_ML_ID_VALID) { 900 - peer_id &= ~ATH12K_PEER_ML_ID_VALID; 901 - ml_peer = true; 807 + spin_lock_bh(&dp->reo_rxq_flush_lock); 808 + list_for_each_entry(elem, &dp->reo_cmd_update_rx_queue_list, list) { 809 + if (elem->peer_id == peer_id) { 810 + rx_tid = &elem->rx_tid; 811 + if (rx_tid->tid == tid) { 812 + rx_tid->active = false; 813 + break; 814 + } 815 + } 902 816 } 903 - 904 - if (ml_peer) 905 - qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + 906 - (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 907 - else 908 - qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 909 - (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 910 - 911 - qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 912 - qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 913 - u32_encode_bits(tid, DP_REO_QREF_NUM); 817 + spin_unlock_bh(&dp->reo_rxq_flush_lock); 914 818 } 915 819 916 820 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 917 821 struct ath12k_peer *peer, u8 tid) 918 822 { 919 - struct ath12k_hal_reo_cmd cmd = {}; 920 823 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 921 - int ret; 824 + struct ath12k_base *ab = ar->ab; 825 + struct ath12k_dp *dp = &ab->dp; 922 826 923 827 if (!rx_tid->active) 924 828 return; 925 829 926 - cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 927 - cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 928 - cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 929 - cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 930 - ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 931 - HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 932 - ath12k_dp_rx_tid_del_func); 933 - if (ret) { 934 - ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 935 - tid, ret); 936 - dma_unmap_single(ar->ab->dev, rx_tid->qbuf.paddr_aligned, 937 - rx_tid->qbuf.size, DMA_BIDIRECTIONAL); 938 - kfree(rx_tid->qbuf.vaddr); 939 - rx_tid->qbuf.vaddr = NULL; 940 - } 941 - 942 - if (peer->mlo) 943 - ath12k_peer_rx_tid_qref_reset(ar->ab, peer->ml_id, tid); 944 - else 945 - ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 946 - 947 830 rx_tid->active = false; 831 + 832 + ath12k_dp_mark_tid_as_inactive(dp, peer->peer_id, tid); 833 + ath12k_dp_rx_process_reo_cmd_update_rx_queue_list(dp); 948 834 } 949 835 950 836 int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, ··· 1003 941 { 1004 942 struct ath12k_hal_reo_cmd cmd = {}; 1005 943 int ret; 944 + struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 1006 945 1007 - cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 1008 - cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 946 + ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid); 947 + 948 + cmd.addr_lo = lower_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 949 + cmd.addr_hi = upper_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1009 950 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1010 951 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 1011 952 cmd.ba_window_size = ba_win_sz; ··· 1018 953 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 1019 954 } 1020 955 1021 - ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 956 + ret = ath12k_dp_reo_cmd_send(ar->ab, &rx_tid_rxq, 1022 957 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 1023 958 NULL); 1024 959 if (ret) { 1025 960 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 1026 - rx_tid->tid, ret); 961 + rx_tid_rxq.tid, ret); 1027 962 return ret; 1028 963 } 1029 964 ··· 1079 1014 1080 1015 rx_tid->qbuf = *buf; 1081 1016 rx_tid->active = true; 1017 + 1018 + return 0; 1019 + } 1020 + 1021 + static int ath12k_dp_prepare_reo_update_elem(struct ath12k_dp *dp, 1022 + struct ath12k_peer *peer, 1023 + struct ath12k_dp_rx_tid *rx_tid) 1024 + { 1025 + struct dp_reo_update_rx_queue_elem *elem; 1026 + 1027 + elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 1028 + if (!elem) 1029 + return -ENOMEM; 1030 + 1031 + elem->peer_id = peer->peer_id; 1032 + elem->is_ml_peer = peer->mlo; 1033 + elem->ml_peer_id = peer->ml_id; 1034 + 1035 + ath12k_dp_init_rx_tid_rxq(&elem->rx_tid, rx_tid); 1036 + 1037 + spin_lock_bh(&dp->reo_rxq_flush_lock); 1038 + list_add_tail(&elem->list, &dp->reo_cmd_update_rx_queue_list); 1039 + spin_unlock_bh(&dp->reo_rxq_flush_lock); 1082 1040 1083 1041 return 0; 1084 1042 } ··· 1183 1095 if (ret) { 1184 1096 spin_unlock_bh(&ab->base_lock); 1185 1097 ath12k_warn(ab, "failed to assign reoq buf for rx tid %u\n", tid); 1098 + return ret; 1099 + } 1100 + 1101 + /* Pre-allocate the update_rxq_list for the corresponding tid 1102 + * This will be used during the tid delete. The reason we are not 1103 + * allocating during tid delete is that, if any alloc fail in update_rxq_list 1104 + * we may not be able to delete the tid vaddr/paddr and may lead to leak 1105 + */ 1106 + ret = ath12k_dp_prepare_reo_update_elem(dp, peer, rx_tid); 1107 + if (ret) { 1108 + ath12k_warn(ab, "failed to alloc update_rxq_list for rx tid %u\n", tid); 1109 + ath12k_dp_rx_tid_cleanup(ab, &rx_tid->qbuf); 1110 + spin_unlock_bh(&ab->base_lock); 1186 1111 return ret; 1187 1112 } 1188 1113 ··· 1308 1207 struct ath12k_hal_reo_cmd cmd = {}; 1309 1208 struct ath12k_peer *peer; 1310 1209 struct ath12k_dp_rx_tid *rx_tid; 1210 + struct ath12k_dp_rx_tid_rxq rx_tid_rxq; 1311 1211 u8 tid; 1312 1212 int ret = 0; 1313 1213 ··· 1355 1253 rx_tid = &peer->rx_tid[tid]; 1356 1254 if (!rx_tid->active) 1357 1255 continue; 1358 - cmd.addr_lo = lower_32_bits(rx_tid->qbuf.paddr_aligned); 1359 - cmd.addr_hi = upper_32_bits(rx_tid->qbuf.paddr_aligned); 1360 - ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1256 + 1257 + ath12k_dp_init_rx_tid_rxq(&rx_tid_rxq, rx_tid); 1258 + cmd.addr_lo = lower_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1259 + cmd.addr_hi = upper_32_bits(rx_tid_rxq.qbuf.paddr_aligned); 1260 + ret = ath12k_dp_reo_cmd_send(ab, &rx_tid_rxq, 1361 1261 HAL_REO_CMD_UPDATE_RX_QUEUE, 1362 1262 &cmd, NULL); 1363 1263 if (ret) { ··· 2637 2533 channel_num = meta_data; 2638 2534 center_freq = meta_data >> 16; 2639 2535 2536 + rx_status->band = NUM_NL80211_BANDS; 2537 + 2640 2538 if (center_freq >= ATH12K_MIN_6GHZ_FREQ && 2641 2539 center_freq <= ATH12K_MAX_6GHZ_FREQ) { 2642 2540 rx_status->band = NL80211_BAND_6GHZ; ··· 2647 2541 rx_status->band = NL80211_BAND_2GHZ; 2648 2542 } else if (channel_num >= 36 && channel_num <= 173) { 2649 2543 rx_status->band = NL80211_BAND_5GHZ; 2650 - } else { 2544 + } 2545 + 2546 + if (unlikely(rx_status->band == NUM_NL80211_BANDS || 2547 + !ath12k_ar_to_hw(ar)->wiphy->bands[rx_status->band])) { 2548 + ath12k_warn(ar->ab, "sband is NULL for status band %d channel_num %d center_freq %d pdev_id %d\n", 2549 + rx_status->band, channel_num, center_freq, ar->pdev_idx); 2550 + 2651 2551 spin_lock_bh(&ar->data_lock); 2652 2552 channel = ar->rx_channel; 2653 2553 if (channel) { 2654 2554 rx_status->band = channel->band; 2655 2555 channel_num = 2656 2556 ieee80211_frequency_to_channel(channel->center_freq); 2557 + rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2558 + rx_status->band); 2559 + } else { 2560 + ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); 2657 2561 } 2658 2562 spin_unlock_bh(&ar->data_lock); 2563 + goto h_rate; 2659 2564 } 2660 2565 2661 2566 if (rx_status->band != NL80211_BAND_6GHZ) 2662 2567 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2663 2568 rx_status->band); 2664 2569 2570 + h_rate: 2665 2571 ath12k_dp_rx_h_rate(ar, rx_info); 2666 2572 } 2667 2573

+16 -2

drivers/net/wireless/ath/ath12k/dp_rx.h

··· 31 31 struct ath12k_base *ab; 32 32 }; 33 33 34 + struct ath12k_dp_rx_tid_rxq { 35 + u8 tid; 36 + bool active; 37 + struct ath12k_reoq_buf qbuf; 38 + }; 39 + 34 40 struct ath12k_dp_rx_reo_cache_flush_elem { 35 41 struct list_head list; 36 - struct ath12k_dp_rx_tid data; 42 + struct ath12k_dp_rx_tid_rxq data; 37 43 unsigned long ts; 44 + }; 45 + 46 + struct dp_reo_update_rx_queue_elem { 47 + struct list_head list; 48 + struct ath12k_dp_rx_tid_rxq rx_tid; 49 + int peer_id; 50 + bool is_ml_peer; 51 + u16 ml_peer_id; 38 52 }; 39 53 40 54 struct ath12k_dp_rx_reo_cmd { 41 55 struct list_head list; 42 - struct ath12k_dp_rx_tid data; 56 + struct ath12k_dp_rx_tid_rxq data; 43 57 int cmd_num; 44 58 void (*handler)(struct ath12k_dp *dp, void *ctx, 45 59 enum hal_reo_cmd_status status);

+1

drivers/net/wireless/ath/ath12k/hal.h

··· 832 832 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 833 833 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 834 834 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 835 + #define HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC BIT(9) 835 836 836 837 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ 837 838 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)

+1

drivers/net/wireless/ath/ath12k/hal_desc.h

··· 1225 1225 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 1226 1226 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 1227 1227 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 1228 + #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC BIT(15) 1228 1229 1229 1230 struct hal_reo_flush_cache { 1230 1231 struct hal_reo_cmd_hdr cmd;

+3

drivers/net/wireless/ath/ath12k/hal_rx.c

··· 89 89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 90 90 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL); 91 91 92 + if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC) 93 + desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC); 94 + 92 95 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 93 96 } 94 97

+7 -5

drivers/net/wireless/ath/ath12k/hal_rx.h

··· 483 483 HAL_RECEPTION_TYPE_FRAMELESS 484 484 }; 485 485 486 - #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0) 487 - #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5) 488 - #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8) 486 + #define HAL_RX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0) 487 + #define HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5) 488 + #define HAL_RX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8) 489 + #define HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU GENMASK(7, 0) 489 490 490 491 struct hal_rx_phyrx_rssi_legacy_info { 491 492 __le32 info0; 492 493 __le32 rsvd0[39]; 493 494 __le32 info1; 494 - __le32 rsvd1; 495 + __le32 info2; 495 496 } __packed; 496 497 497 498 #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) ··· 696 695 #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) 697 696 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) 698 697 699 - #define HAL_RX_PHY_CMN_USER_INFO0_GI GENMASK(17, 16) 698 + #define HAL_RX_CMN_USR_INFO0_CP_SETTING GENMASK(17, 16) 699 + #define HAL_RX_CMN_USR_INFO0_LTF_SIZE GENMASK(19, 18) 700 700 701 701 struct hal_phyrx_common_user_info { 702 702 __le32 rsvd[2];

+85 -32

drivers/net/wireless/ath/ath12k/mac.c

··· 1 1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 2 /* 3 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 - * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 5 */ 6 6 7 7 #include <net/mac80211.h> ··· 1822 1822 skb); 1823 1823 } 1824 1824 1825 - static void ath12k_mac_handle_beacon_miss_iter(void *data, u8 *mac, 1826 - struct ieee80211_vif *vif) 1825 + void ath12k_mac_handle_beacon_miss(struct ath12k *ar, 1826 + struct ath12k_link_vif *arvif) 1827 1827 { 1828 - u32 *vdev_id = data; 1829 - struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); 1830 - struct ath12k_link_vif *arvif = &ahvif->deflink; 1831 - struct ieee80211_hw *hw; 1828 + struct ieee80211_hw *hw = ath12k_ar_to_hw(ar); 1829 + struct ieee80211_vif *vif = ath12k_ahvif_to_vif(arvif->ahvif); 1832 1830 1833 - if (!arvif->is_created || arvif->vdev_id != *vdev_id) 1834 - return; 1835 - 1836 - if (!arvif->is_up) 1831 + if (!(arvif->is_created && arvif->is_up)) 1837 1832 return; 1838 1833 1839 1834 ieee80211_beacon_loss(vif); 1840 - hw = ath12k_ar_to_hw(arvif->ar); 1841 1835 1842 1836 /* Firmware doesn't report beacon loss events repeatedly. If AP probe 1843 1837 * (done by mac80211) succeeds but beacons do not resume then it ··· 1840 1846 */ 1841 1847 ieee80211_queue_delayed_work(hw, &arvif->connection_loss_work, 1842 1848 ATH12K_CONNECTION_LOSS_HZ); 1843 - } 1844 - 1845 - void ath12k_mac_handle_beacon_miss(struct ath12k *ar, u32 vdev_id) 1846 - { 1847 - ieee80211_iterate_active_interfaces_atomic(ath12k_ar_to_hw(ar), 1848 - IEEE80211_IFACE_ITER_NORMAL, 1849 - ath12k_mac_handle_beacon_miss_iter, 1850 - &vdev_id); 1851 1849 } 1852 1850 1853 1851 static void ath12k_mac_vif_sta_connection_loss_work(struct work_struct *work) ··· 9846 9860 9847 9861 param_id = WMI_VDEV_PARAM_RTS_THRESHOLD; 9848 9862 param_value = hw->wiphy->rts_threshold; 9863 + ar->rts_threshold = param_value; 9849 9864 ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, 9850 9865 param_id, param_value); 9851 9866 if (ret) { ··· 11227 11240 struct ieee80211_channel *chan, *temp_chan; 11228 11241 u8 pwr_lvl_idx, num_pwr_levels, pwr_reduction; 11229 11242 bool is_psd_power = false, is_tpe_present = false; 11230 - s8 max_tx_power[ATH12K_NUM_PWR_LEVELS], 11231 - psd_power, tx_power, eirp_power; 11243 + s8 max_tx_power[ATH12K_NUM_PWR_LEVELS], psd_power, tx_power; 11244 + s8 eirp_power = 0; 11232 11245 struct ath12k_vif *ahvif = arvif->ahvif; 11233 11246 u16 start_freq, center_freq; 11234 11247 u8 reg_6ghz_power_mode; ··· 11434 11447 11435 11448 tpc_info->num_pwr_levels = max(local_psd->count, 11436 11449 reg_psd->count); 11437 - if (tpc_info->num_pwr_levels > ATH12K_NUM_PWR_LEVELS) 11438 - tpc_info->num_pwr_levels = ATH12K_NUM_PWR_LEVELS; 11450 + tpc_info->num_pwr_levels = 11451 + min3(tpc_info->num_pwr_levels, 11452 + IEEE80211_TPE_PSD_ENTRIES_320MHZ, 11453 + ATH12K_NUM_PWR_LEVELS); 11439 11454 11440 11455 for (i = 0; i < tpc_info->num_pwr_levels; i++) { 11441 11456 tpc_info->tpe[i] = min(local_psd->power[i], ··· 11452 11463 11453 11464 tpc_info->num_pwr_levels = max(local_non_psd->count, 11454 11465 reg_non_psd->count); 11455 - if (tpc_info->num_pwr_levels > ATH12K_NUM_PWR_LEVELS) 11456 - tpc_info->num_pwr_levels = ATH12K_NUM_PWR_LEVELS; 11466 + tpc_info->num_pwr_levels = 11467 + min3(tpc_info->num_pwr_levels, 11468 + IEEE80211_TPE_EIRP_ENTRIES_320MHZ, 11469 + ATH12K_NUM_PWR_LEVELS); 11457 11470 11458 11471 for (i = 0; i < tpc_info->num_pwr_levels; i++) { 11459 11472 tpc_info->tpe[i] = min(local_non_psd->power[i], ··· 11678 11687 int radio_idx, u32 value) 11679 11688 { 11680 11689 struct ath12k_hw *ah = ath12k_hw_to_ah(hw); 11690 + struct wiphy *wiphy = hw->wiphy; 11681 11691 struct ath12k *ar; 11682 - int param_id = WMI_VDEV_PARAM_RTS_THRESHOLD, ret = 0, i; 11692 + int param_id = WMI_VDEV_PARAM_RTS_THRESHOLD; 11693 + int ret = 0, ret_err, i; 11683 11694 11684 11695 lockdep_assert_wiphy(hw->wiphy); 11685 11696 11686 - /* Currently we set the rts threshold value to all the vifs across 11687 - * all radios of the single wiphy. 11688 - * TODO Once support for vif specific RTS threshold in mac80211 is 11689 - * available, ath12k can make use of it. 11690 - */ 11697 + if (radio_idx >= wiphy->n_radio || radio_idx < -1) 11698 + return -EINVAL; 11699 + 11700 + if (radio_idx != -1) { 11701 + /* Update RTS threshold in specified radio */ 11702 + ar = ath12k_ah_to_ar(ah, radio_idx); 11703 + ret = ath12k_set_vdev_param_to_all_vifs(ar, param_id, value); 11704 + if (ret) { 11705 + ath12k_warn(ar->ab, 11706 + "failed to set RTS config for all vdevs of pdev %d", 11707 + ar->pdev->pdev_id); 11708 + return ret; 11709 + } 11710 + 11711 + ar->rts_threshold = value; 11712 + return 0; 11713 + } 11714 + 11715 + /* Radio_index passed is -1, so set RTS threshold for all radios. */ 11691 11716 for_each_ar(ah, ar, i) { 11692 11717 ret = ath12k_set_vdev_param_to_all_vifs(ar, param_id, value); 11693 11718 if (ret) { ··· 11711 11704 ar->pdev->pdev_id); 11712 11705 break; 11713 11706 } 11707 + } 11708 + if (!ret) { 11709 + /* Setting new RTS threshold for vdevs of all radios passed, so update 11710 + * the RTS threshold value for all radios 11711 + */ 11712 + for_each_ar(ah, ar, i) 11713 + ar->rts_threshold = value; 11714 + return 0; 11715 + } 11716 + 11717 + /* RTS threshold config failed, revert to the previous RTS threshold */ 11718 + for (i = i - 1; i >= 0; i--) { 11719 + ar = ath12k_ah_to_ar(ah, i); 11720 + ret_err = ath12k_set_vdev_param_to_all_vifs(ar, param_id, 11721 + ar->rts_threshold); 11722 + if (ret_err) 11723 + ath12k_warn(ar->ab, 11724 + "failed to restore RTS threshold for all vdevs of pdev %d", 11725 + ar->pdev->pdev_id); 11714 11726 } 11715 11727 11716 11728 return ret; ··· 12636 12610 return 0; 12637 12611 } 12638 12612 12613 + static void ath12k_mac_put_chain_rssi(struct station_info *sinfo, 12614 + struct ath12k_link_sta *arsta) 12615 + { 12616 + s8 rssi; 12617 + int i; 12618 + 12619 + for (i = 0; i < ARRAY_SIZE(sinfo->chain_signal); i++) { 12620 + sinfo->chains &= ~BIT(i); 12621 + rssi = arsta->chain_signal[i]; 12622 + 12623 + if (rssi != ATH12K_DEFAULT_NOISE_FLOOR && 12624 + rssi != ATH12K_INVALID_RSSI_FULL && 12625 + rssi != ATH12K_INVALID_RSSI_EMPTY && 12626 + rssi != 0) { 12627 + sinfo->chain_signal[i] = rssi; 12628 + sinfo->chains |= BIT(i); 12629 + sinfo->filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL); 12630 + } 12631 + } 12632 + } 12633 + 12639 12634 static void ath12k_mac_op_sta_statistics(struct ieee80211_hw *hw, 12640 12635 struct ieee80211_vif *vif, 12641 12636 struct ieee80211_sta *sta, ··· 12713 12666 ahsta->ahvif->vdev_type == WMI_VDEV_TYPE_STA && 12714 12667 !(ath12k_mac_get_fw_stats(ar, &params))) 12715 12668 signal = arsta->rssi_beacon; 12669 + 12670 + params.stats_id = WMI_REQUEST_RSSI_PER_CHAIN_STAT; 12671 + if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) && 12672 + ahsta->ahvif->vdev_type == WMI_VDEV_TYPE_STA && 12673 + !(ath12k_mac_get_fw_stats(ar, &params))) 12674 + ath12k_mac_put_chain_rssi(sinfo, arsta); 12716 12675 12717 12676 spin_lock_bh(&ar->data_lock); 12718 12677 noise_floor = ath12k_pdev_get_noise_floor(ar);

+2 -1

drivers/net/wireless/ath/ath12k/mac.h

··· 168 168 int ath12k_mac_rfkill_config(struct ath12k *ar); 169 169 int ath12k_mac_wait_tx_complete(struct ath12k *ar); 170 170 void ath12k_mac_handle_beacon(struct ath12k *ar, struct sk_buff *skb); 171 - void ath12k_mac_handle_beacon_miss(struct ath12k *ar, u32 vdev_id); 171 + void ath12k_mac_handle_beacon_miss(struct ath12k *ar, 172 + struct ath12k_link_vif *arvif); 172 173 int ath12k_mac_vif_set_keepalive(struct ath12k_link_vif *arvif, 173 174 enum wmi_sta_keepalive_method method, 174 175 u32 interval);

+16 -8

drivers/net/wireless/ath/ath12k/qmi.c

··· 3307 3307 /* This is number of CE configs */ 3308 3308 req->tgt_cfg_len = ab->qmi.ce_cfg.tgt_ce_len; 3309 3309 for (pipe_num = 0; pipe_num < req->tgt_cfg_len ; pipe_num++) { 3310 - req->tgt_cfg[pipe_num].pipe_num = ce_cfg[pipe_num].pipenum; 3311 - req->tgt_cfg[pipe_num].pipe_dir = ce_cfg[pipe_num].pipedir; 3312 - req->tgt_cfg[pipe_num].nentries = ce_cfg[pipe_num].nentries; 3313 - req->tgt_cfg[pipe_num].nbytes_max = ce_cfg[pipe_num].nbytes_max; 3314 - req->tgt_cfg[pipe_num].flags = ce_cfg[pipe_num].flags; 3310 + req->tgt_cfg[pipe_num].pipe_num = 3311 + __le32_to_cpu(ce_cfg[pipe_num].pipenum); 3312 + req->tgt_cfg[pipe_num].pipe_dir = 3313 + __le32_to_cpu(ce_cfg[pipe_num].pipedir); 3314 + req->tgt_cfg[pipe_num].nentries = 3315 + __le32_to_cpu(ce_cfg[pipe_num].nentries); 3316 + req->tgt_cfg[pipe_num].nbytes_max = 3317 + __le32_to_cpu(ce_cfg[pipe_num].nbytes_max); 3318 + req->tgt_cfg[pipe_num].flags = 3319 + __le32_to_cpu(ce_cfg[pipe_num].flags); 3315 3320 } 3316 3321 3317 3322 req->svc_cfg_valid = 1; 3318 3323 /* This is number of Service/CE configs */ 3319 3324 req->svc_cfg_len = ab->qmi.ce_cfg.svc_to_ce_map_len; 3320 3325 for (pipe_num = 0; pipe_num < req->svc_cfg_len; pipe_num++) { 3321 - req->svc_cfg[pipe_num].service_id = svc_cfg[pipe_num].service_id; 3322 - req->svc_cfg[pipe_num].pipe_dir = svc_cfg[pipe_num].pipedir; 3323 - req->svc_cfg[pipe_num].pipe_num = svc_cfg[pipe_num].pipenum; 3326 + req->svc_cfg[pipe_num].service_id = 3327 + __le32_to_cpu(svc_cfg[pipe_num].service_id); 3328 + req->svc_cfg[pipe_num].pipe_dir = 3329 + __le32_to_cpu(svc_cfg[pipe_num].pipedir); 3330 + req->svc_cfg[pipe_num].pipe_num = 3331 + __le32_to_cpu(svc_cfg[pipe_num].pipenum); 3324 3332 } 3325 3333 3326 3334 /* set shadow v3 configuration */

+8 -8

drivers/net/wireless/ath/ath12k/qmi.h

··· 392 392 }; 393 393 394 394 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 395 - __le32 pipe_num; 396 - __le32 pipe_dir; 397 - __le32 nentries; 398 - __le32 nbytes_max; 399 - __le32 flags; 395 + u32 pipe_num; 396 + u32 pipe_dir; 397 + u32 nentries; 398 + u32 nbytes_max; 399 + u32 flags; 400 400 }; 401 401 402 402 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 403 - __le32 service_id; 404 - __le32 pipe_dir; 405 - __le32 pipe_num; 403 + u32 service_id; 404 + u32 pipe_dir; 405 + u32 pipe_num; 406 406 }; 407 407 408 408 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {

+142 -16

drivers/net/wireless/ath/ath12k/wmi.c

··· 30 30 struct wmi_tlv_fw_stats_parse { 31 31 const struct wmi_stats_event *ev; 32 32 struct ath12k_fw_stats *stats; 33 + const struct wmi_per_chain_rssi_stat_params *rssi; 34 + int rssi_num; 35 + bool chain_rssi_done; 33 36 }; 34 37 35 38 struct ath12k_wmi_dma_ring_caps_parse { ··· 188 185 .min_len = sizeof(struct wmi_p2p_noa_event) }, 189 186 [WMI_TAG_11D_NEW_COUNTRY_EVENT] = { 190 187 .min_len = sizeof(struct wmi_11d_new_cc_event) }, 188 + [WMI_TAG_PER_CHAIN_RSSI_STATS] = { 189 + .min_len = sizeof(struct wmi_per_chain_rssi_stat_params) }, 191 190 }; 192 191 193 192 __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len) ··· 6467 6462 } 6468 6463 6469 6464 arg->mac_addr = ev->peer_macaddr.addr; 6465 + arg->reason = le32_to_cpu(ev->reason); 6466 + arg->rssi = le32_to_cpu(ev->rssi); 6470 6467 6471 6468 kfree(tb); 6472 6469 return 0; ··· 7305 7298 static void ath12k_peer_sta_kickout_event(struct ath12k_base *ab, struct sk_buff *skb) 7306 7299 { 7307 7300 struct wmi_peer_sta_kickout_arg arg = {}; 7301 + struct ath12k_link_vif *arvif; 7308 7302 struct ieee80211_sta *sta; 7309 7303 struct ath12k_peer *peer; 7304 + unsigned int link_id; 7310 7305 struct ath12k *ar; 7311 7306 7312 7307 if (ath12k_pull_peer_sta_kickout_ev(ab, skb, &arg) != 0) { ··· 7328 7319 goto exit; 7329 7320 } 7330 7321 7331 - ar = ath12k_mac_get_ar_by_vdev_id(ab, peer->vdev_id); 7332 - if (!ar) { 7322 + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, peer->vdev_id); 7323 + if (!arvif) { 7333 7324 ath12k_warn(ab, "invalid vdev id in peer sta kickout ev %d", 7334 7325 peer->vdev_id); 7335 7326 goto exit; 7336 7327 } 7337 7328 7338 - sta = ieee80211_find_sta_by_ifaddr(ath12k_ar_to_hw(ar), 7339 - arg.mac_addr, NULL); 7329 + ar = arvif->ar; 7330 + 7331 + if (peer->mlo) { 7332 + sta = ieee80211_find_sta_by_link_addrs(ath12k_ar_to_hw(ar), 7333 + arg.mac_addr, 7334 + NULL, &link_id); 7335 + if (peer->link_id != link_id) { 7336 + ath12k_warn(ab, 7337 + "Spurious quick kickout for MLO STA %pM with invalid link_id, peer: %d, sta: %d\n", 7338 + arg.mac_addr, peer->link_id, link_id); 7339 + goto exit; 7340 + } 7341 + } else { 7342 + sta = ieee80211_find_sta_by_ifaddr(ath12k_ar_to_hw(ar), 7343 + arg.mac_addr, NULL); 7344 + } 7340 7345 if (!sta) { 7341 - ath12k_warn(ab, "Spurious quick kickout for STA %pM\n", 7342 - arg.mac_addr); 7346 + ath12k_warn(ab, "Spurious quick kickout for %sSTA %pM\n", 7347 + peer->mlo ? "MLO " : "", arg.mac_addr); 7343 7348 goto exit; 7344 7349 } 7345 7350 7346 - ath12k_dbg(ab, ATH12K_DBG_WMI, "peer sta kickout event %pM", 7347 - arg.mac_addr); 7351 + ath12k_dbg(ab, ATH12K_DBG_WMI, 7352 + "peer sta kickout event %pM reason: %d rssi: %d\n", 7353 + arg.mac_addr, arg.reason, arg.rssi); 7348 7354 7349 - ieee80211_report_low_ack(sta, 10); 7355 + switch (arg.reason) { 7356 + case WMI_PEER_STA_KICKOUT_REASON_INACTIVITY: 7357 + if (arvif->ahvif->vif->type == NL80211_IFTYPE_STATION) { 7358 + ath12k_mac_handle_beacon_miss(ar, arvif); 7359 + break; 7360 + } 7361 + fallthrough; 7362 + default: 7363 + ieee80211_report_low_ack(sta, 10); 7364 + } 7350 7365 7351 7366 exit: 7352 7367 spin_unlock_bh(&ab->base_lock); ··· 7379 7346 7380 7347 static void ath12k_roam_event(struct ath12k_base *ab, struct sk_buff *skb) 7381 7348 { 7349 + struct ath12k_link_vif *arvif; 7382 7350 struct wmi_roam_event roam_ev = {}; 7383 7351 struct ath12k *ar; 7384 7352 u32 vdev_id; ··· 7398 7364 "wmi roam event vdev %u reason %d rssi %d\n", 7399 7365 vdev_id, roam_reason, roam_ev.rssi); 7400 7366 7401 - rcu_read_lock(); 7402 - ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_id); 7403 - if (!ar) { 7367 + guard(rcu)(); 7368 + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); 7369 + if (!arvif) { 7404 7370 ath12k_warn(ab, "invalid vdev id in roam ev %d", vdev_id); 7405 - rcu_read_unlock(); 7406 7371 return; 7407 7372 } 7373 + 7374 + ar = arvif->ar; 7408 7375 7409 7376 if (roam_reason >= WMI_ROAM_REASON_MAX) 7410 7377 ath12k_warn(ab, "ignoring unknown roam event reason %d on vdev %i\n", ··· 7413 7378 7414 7379 switch (roam_reason) { 7415 7380 case WMI_ROAM_REASON_BEACON_MISS: 7416 - ath12k_mac_handle_beacon_miss(ar, vdev_id); 7381 + ath12k_mac_handle_beacon_miss(ar, arvif); 7417 7382 break; 7418 7383 case WMI_ROAM_REASON_BETTER_AP: 7419 7384 case WMI_ROAM_REASON_LOW_RSSI: ··· 7423 7388 roam_reason, vdev_id); 7424 7389 break; 7425 7390 } 7426 - 7427 - rcu_read_unlock(); 7428 7391 } 7429 7392 7430 7393 static void ath12k_chan_info_event(struct ath12k_base *ab, struct sk_buff *skb) ··· 8252 8219 return ret; 8253 8220 } 8254 8221 8222 + static int ath12k_wmi_tlv_rssi_chain_parse(struct ath12k_base *ab, 8223 + u16 tag, u16 len, 8224 + const void *ptr, void *data) 8225 + { 8226 + const struct wmi_rssi_stat_params *stats_rssi = ptr; 8227 + struct wmi_tlv_fw_stats_parse *parse = data; 8228 + const struct wmi_stats_event *ev = parse->ev; 8229 + struct ath12k_fw_stats *stats = parse->stats; 8230 + struct ath12k_link_vif *arvif; 8231 + struct ath12k_link_sta *arsta; 8232 + struct ieee80211_sta *sta; 8233 + struct ath12k_sta *ahsta; 8234 + struct ath12k *ar; 8235 + int vdev_id; 8236 + int j; 8237 + 8238 + if (!ev) { 8239 + ath12k_warn(ab, "failed to fetch update stats ev"); 8240 + return -EPROTO; 8241 + } 8242 + 8243 + if (tag != WMI_TAG_RSSI_STATS) 8244 + return -EPROTO; 8245 + 8246 + if (!stats) 8247 + return -EINVAL; 8248 + 8249 + stats->pdev_id = le32_to_cpu(ev->pdev_id); 8250 + vdev_id = le32_to_cpu(stats_rssi->vdev_id); 8251 + guard(rcu)(); 8252 + ar = ath12k_mac_get_ar_by_pdev_id(ab, stats->pdev_id); 8253 + if (!ar) { 8254 + ath12k_warn(ab, "invalid pdev id %d in rssi chain parse\n", 8255 + stats->pdev_id); 8256 + return -EPROTO; 8257 + } 8258 + 8259 + arvif = ath12k_mac_get_arvif(ar, vdev_id); 8260 + if (!arvif) { 8261 + ath12k_warn(ab, "not found vif for vdev id %d\n", vdev_id); 8262 + return -EPROTO; 8263 + } 8264 + 8265 + ath12k_dbg(ab, ATH12K_DBG_WMI, 8266 + "stats bssid %pM vif %p\n", 8267 + arvif->bssid, arvif->ahvif->vif); 8268 + 8269 + sta = ieee80211_find_sta_by_ifaddr(ath12k_ar_to_hw(ar), 8270 + arvif->bssid, 8271 + NULL); 8272 + if (!sta) { 8273 + ath12k_dbg(ab, ATH12K_DBG_WMI, 8274 + "not found station of bssid %pM for rssi chain\n", 8275 + arvif->bssid); 8276 + return -EPROTO; 8277 + } 8278 + 8279 + ahsta = ath12k_sta_to_ahsta(sta); 8280 + arsta = &ahsta->deflink; 8281 + 8282 + BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) > 8283 + ARRAY_SIZE(stats_rssi->rssi_avg_beacon)); 8284 + 8285 + for (j = 0; j < ARRAY_SIZE(arsta->chain_signal); j++) 8286 + arsta->chain_signal[j] = le32_to_cpu(stats_rssi->rssi_avg_beacon[j]); 8287 + 8288 + stats->stats_id = WMI_REQUEST_RSSI_PER_CHAIN_STAT; 8289 + 8290 + return 0; 8291 + } 8292 + 8255 8293 static int ath12k_wmi_tlv_fw_stats_parse(struct ath12k_base *ab, 8256 8294 u16 tag, u16 len, 8257 8295 const void *ptr, void *data) ··· 8336 8232 break; 8337 8233 case WMI_TAG_ARRAY_BYTE: 8338 8234 ret = ath12k_wmi_tlv_fw_stats_data_parse(ab, parse, ptr, len); 8235 + break; 8236 + case WMI_TAG_PER_CHAIN_RSSI_STATS: 8237 + parse->rssi = ptr; 8238 + if (le32_to_cpu(parse->ev->stats_id) & WMI_REQUEST_RSSI_PER_CHAIN_STAT) 8239 + parse->rssi_num = le32_to_cpu(parse->rssi->num_per_chain_rssi); 8240 + break; 8241 + case WMI_TAG_ARRAY_STRUCT: 8242 + if (parse->rssi_num && !parse->chain_rssi_done) { 8243 + ret = ath12k_wmi_tlv_iter(ab, ptr, len, 8244 + ath12k_wmi_tlv_rssi_chain_parse, 8245 + parse); 8246 + if (ret) 8247 + return ret; 8248 + 8249 + parse->chain_rssi_done = true; 8250 + } 8339 8251 break; 8340 8252 default: 8341 8253 break; ··· 8462 8342 /* Handle WMI_REQUEST_PDEV_STAT status update */ 8463 8343 if (stats.stats_id == WMI_REQUEST_PDEV_STAT) { 8464 8344 list_splice_tail_init(&stats.pdevs, &ar->fw_stats.pdevs); 8345 + complete(&ar->fw_stats_done); 8346 + goto complete; 8347 + } 8348 + 8349 + /* Handle WMI_REQUEST_RSSI_PER_CHAIN_STAT status update */ 8350 + if (stats.stats_id == WMI_REQUEST_RSSI_PER_CHAIN_STAT) { 8465 8351 complete(&ar->fw_stats_done); 8466 8352 goto complete; 8467 8353 }

+30 -3

drivers/net/wireless/ath/ath12k/wmi.h

··· 4548 4548 __le32 tsf_timestamp; 4549 4549 } __packed; 4550 4550 4551 + enum wmi_peer_sta_kickout_reason { 4552 + WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED = 0, 4553 + WMI_PEER_STA_KICKOUT_REASON_XRETRY = 1, 4554 + WMI_PEER_STA_KICKOUT_REASON_INACTIVITY = 2, 4555 + WMI_PEER_STA_KICKOUT_REASON_IBSS_DISCONNECT = 3, 4556 + WMI_PEER_STA_KICKOUT_REASON_TDLS_DISCONNECT = 4, 4557 + WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT = 5, 4558 + WMI_PEER_STA_KICKOUT_REASON_ROAMING_EVENT = 6, 4559 + WMI_PEER_STA_KICKOUT_REASON_PMF_ERROR = 7, 4560 + }; 4561 + 4551 4562 struct wmi_peer_sta_kickout_arg { 4552 4563 const u8 *mac_addr; 4564 + enum wmi_peer_sta_kickout_reason reason; 4565 + u32 rssi; 4553 4566 }; 4554 4567 4555 4568 struct wmi_peer_sta_kickout_event { 4556 4569 struct ath12k_wmi_mac_addr_params peer_macaddr; 4570 + __le32 reason; 4571 + __le32 rssi; 4557 4572 } __packed; 4558 4573 4559 4574 #define WMI_ROAM_REASON_MASK GENMASK(3, 0) ··· 5890 5875 } __packed; 5891 5876 5892 5877 enum wmi_stats_id { 5893 - WMI_REQUEST_PDEV_STAT = BIT(2), 5894 - WMI_REQUEST_VDEV_STAT = BIT(3), 5895 - WMI_REQUEST_BCN_STAT = BIT(11), 5878 + WMI_REQUEST_PDEV_STAT = BIT(2), 5879 + WMI_REQUEST_VDEV_STAT = BIT(3), 5880 + WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 5881 + WMI_REQUEST_BCN_STAT = BIT(11), 5896 5882 }; 5897 5883 5898 5884 struct wmi_request_stats_cmd { ··· 5902 5886 __le32 vdev_id; 5903 5887 struct ath12k_wmi_mac_addr_params peer_macaddr; 5904 5888 __le32 pdev_id; 5889 + } __packed; 5890 + 5891 + struct wmi_rssi_stat_params { 5892 + __le32 vdev_id; 5893 + __le32 rssi_avg_beacon[WMI_MAX_CHAINS]; 5894 + __le32 rssi_avg_data[WMI_MAX_CHAINS]; 5895 + struct ath12k_wmi_mac_addr_params peer_macaddr; 5896 + } __packed; 5897 + 5898 + struct wmi_per_chain_rssi_stat_params { 5899 + __le32 num_per_chain_rssi; 5905 5900 } __packed; 5906 5901 5907 5902 #define WLAN_MAX_AC 4

+2 -1

drivers/net/wireless/marvell/libertas/if_sdio.c

··· 1181 1181 spin_lock_init(&card->lock); 1182 1182 INIT_LIST_HEAD(&card->packets); 1183 1183 1184 - card->workqueue = alloc_workqueue("libertas_sdio", WQ_MEM_RECLAIM, 0); 1184 + card->workqueue = alloc_workqueue("libertas_sdio", 1185 + WQ_MEM_RECLAIM | WQ_UNBOUND, 0); 1185 1186 if (unlikely(!card->workqueue)) { 1186 1187 ret = -ENOMEM; 1187 1188 goto err_queue;

+2 -1

drivers/net/wireless/marvell/libertas/if_spi.c

··· 1153 1153 priv->fw_ready = 1; 1154 1154 1155 1155 /* Initialize interrupt handling stuff. */ 1156 - card->workqueue = alloc_workqueue("libertas_spi", WQ_MEM_RECLAIM, 0); 1156 + card->workqueue = alloc_workqueue("libertas_spi", 1157 + WQ_MEM_RECLAIM | WQ_UNBOUND, 0); 1157 1158 if (!card->workqueue) { 1158 1159 err = -ENOMEM; 1159 1160 goto remove_card;

+1 -1

drivers/net/wireless/marvell/libertas_tf/main.c

··· 708 708 static int __init lbtf_init_module(void) 709 709 { 710 710 lbtf_deb_enter(LBTF_DEB_MAIN); 711 - lbtf_wq = alloc_workqueue("libertastf", WQ_MEM_RECLAIM, 0); 711 + lbtf_wq = alloc_workqueue("libertastf", WQ_MEM_RECLAIM | WQ_UNBOUND, 0); 712 712 if (lbtf_wq == NULL) { 713 713 printk(KERN_ERR "libertastf: couldn't create workqueue\n"); 714 714 return -ENOMEM;

+2

drivers/net/wireless/mediatek/mt76/agg-rx.c

··· 173 173 if (ackp == IEEE80211_QOS_CTL_ACK_POLICY_NOACK) 174 174 return; 175 175 176 + if (wcid->def_wcid) 177 + wcid = wcid->def_wcid; 176 178 tid = rcu_dereference(wcid->aggr[tidno]); 177 179 if (!tid) 178 180 return;

+9 -4

drivers/net/wireless/mediatek/mt76/channel.c

··· 314 314 kfree(mlink); 315 315 } 316 316 317 - static void mt76_roc_complete(struct mt76_phy *phy) 317 + void mt76_roc_complete(struct mt76_phy *phy) 318 318 { 319 319 struct mt76_vif_link *mlink = phy->roc_link; 320 + struct mt76_dev *dev = phy->dev; 320 321 321 322 if (!phy->roc_vif) 322 323 return; 323 324 324 325 if (mlink) 325 326 mlink->mvif->roc_phy = NULL; 326 - if (phy->main_chandef.chan) 327 + if (phy->main_chandef.chan && 328 + !test_bit(MT76_MCU_RESET, &dev->phy.state)) 327 329 mt76_set_channel(phy, &phy->main_chandef, false); 328 330 mt76_put_vif_phy_link(phy, phy->roc_vif, phy->roc_link); 329 331 phy->roc_vif = NULL; 330 332 phy->roc_link = NULL; 331 - ieee80211_remain_on_channel_expired(phy->hw); 333 + if (!test_bit(MT76_MCU_RESET, &dev->phy.state)) 334 + ieee80211_remain_on_channel_expired(phy->hw); 332 335 } 333 336 334 337 void mt76_roc_complete_work(struct work_struct *work) ··· 354 351 mt76_roc_complete(phy); 355 352 mutex_unlock(&dev->mutex); 356 353 } 354 + EXPORT_SYMBOL_GPL(mt76_abort_roc); 357 355 358 356 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 359 357 struct ieee80211_channel *chan, int duration, ··· 372 368 373 369 mutex_lock(&dev->mutex); 374 370 375 - if (phy->roc_vif || dev->scan.phy == phy) { 371 + if (phy->roc_vif || dev->scan.phy == phy || 372 + test_bit(MT76_MCU_RESET, &dev->phy.state)) { 376 373 ret = -EBUSY; 377 374 goto out; 378 375 }

+187 -44

drivers/net/wireless/mediatek/mt76/dma.c

··· 186 186 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 187 187 188 188 static void 189 + mt76_dma_queue_magic_cnt_init(struct mt76_dev *dev, struct mt76_queue *q) 190 + { 191 + if (!mt76_queue_is_wed_rro(q)) 192 + return; 193 + 194 + q->magic_cnt = 0; 195 + if (mt76_queue_is_wed_rro_ind(q)) { 196 + struct mt76_wed_rro_desc *rro_desc; 197 + u32 data1 = FIELD_PREP(RRO_IND_DATA1_MAGIC_CNT_MASK, 198 + MT_DMA_WED_IND_CMD_CNT - 1); 199 + int i; 200 + 201 + rro_desc = (struct mt76_wed_rro_desc *)q->desc; 202 + for (i = 0; i < q->ndesc; i++) { 203 + struct mt76_wed_rro_ind *cmd; 204 + 205 + cmd = (struct mt76_wed_rro_ind *)&rro_desc[i]; 206 + cmd->data1 = cpu_to_le32(data1); 207 + } 208 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 209 + struct mt76_rro_rxdmad_c *dmad = (void *)q->desc; 210 + u32 data3 = FIELD_PREP(RRO_RXDMAD_DATA3_MAGIC_CNT_MASK, 211 + MT_DMA_MAGIC_CNT - 1); 212 + int i; 213 + 214 + for (i = 0; i < q->ndesc; i++) 215 + dmad[i].data3 = cpu_to_le32(data3); 216 + } 217 + } 218 + 219 + static void 189 220 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 190 221 { 191 222 Q_WRITE(q, desc_base, q->desc_dma); ··· 228 197 q->tail = q->head; 229 198 } 230 199 231 - void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 232 - bool reset_idx) 200 + void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 201 + bool reset_idx) 233 202 { 234 203 if (!q || !q->ndesc) 235 204 return; 236 205 237 - if (!mt76_queue_is_wed_rro_ind(q)) { 206 + if (!mt76_queue_is_wed_rro_ind(q) && 207 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 238 208 int i; 239 209 240 210 /* clear descriptors */ ··· 243 211 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 244 212 } 245 213 214 + mt76_dma_queue_magic_cnt_init(dev, q); 246 215 if (reset_idx) { 247 - Q_WRITE(q, cpu_idx, 0); 216 + if (mt76_queue_is_emi(q)) 217 + *q->emi_cpu_idx = 0; 218 + else 219 + Q_WRITE(q, cpu_idx, 0); 248 220 Q_WRITE(q, dma_idx, 0); 249 221 } 250 222 mt76_dma_sync_idx(dev, q); 251 - } 252 - 253 - void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 254 - { 255 - __mt76_dma_queue_reset(dev, q, true); 256 223 } 257 224 258 225 static int ··· 260 229 { 261 230 struct mt76_queue_entry *entry = &q->entry[q->head]; 262 231 struct mt76_txwi_cache *txwi = NULL; 232 + u32 buf1 = 0, ctrl, info = 0; 263 233 struct mt76_desc *desc; 264 234 int idx = q->head; 265 - u32 buf1 = 0, ctrl; 266 235 int rx_token; 267 236 268 237 if (mt76_queue_is_wed_rro_ind(q)) { ··· 270 239 271 240 rro_desc = (struct mt76_wed_rro_desc *)q->desc; 272 241 data = &rro_desc[q->head]; 242 + goto done; 243 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 244 + data = &q->desc[q->head]; 273 245 goto done; 274 246 } 275 247 ··· 282 248 buf1 = FIELD_PREP(MT_DMA_CTL_SDP0_H, buf->addr >> 32); 283 249 #endif 284 250 285 - if (mt76_queue_is_wed_rx(q)) { 251 + if (mt76_queue_is_wed_rx(q) || mt76_queue_is_wed_rro_data(q)) { 286 252 txwi = mt76_get_rxwi(dev); 287 253 if (!txwi) 288 254 return -ENOMEM; ··· 295 261 296 262 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 297 263 ctrl |= MT_DMA_CTL_TO_HOST; 264 + 265 + txwi->qid = q - dev->q_rx; 266 + } 267 + 268 + if (mt76_queue_is_wed_rro_msdu_pg(q) && 269 + dev->drv->rx_rro_add_msdu_page) { 270 + if (dev->drv->rx_rro_add_msdu_page(dev, q, buf->addr, data)) 271 + return -ENOMEM; 272 + } 273 + 274 + if (q->flags & MT_QFLAG_WED_RRO_EN) { 275 + info |= FIELD_PREP(MT_DMA_MAGIC_MASK, q->magic_cnt); 276 + if ((q->head + 1) == q->ndesc) 277 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_MAGIC_CNT; 298 278 } 299 279 300 280 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 301 281 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 302 282 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 303 - WRITE_ONCE(desc->info, 0); 283 + WRITE_ONCE(desc->info, cpu_to_le32(info)); 304 284 305 285 done: 306 286 entry->dma_addr[0] = buf->addr; ··· 423 375 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 424 376 { 425 377 wmb(); 426 - Q_WRITE(q, cpu_idx, q->head); 378 + if (mt76_queue_is_emi(q)) 379 + *q->emi_cpu_idx = cpu_to_le16(q->head); 380 + else 381 + Q_WRITE(q, cpu_idx, q->head); 427 382 } 428 383 429 384 static void ··· 470 419 } 471 420 472 421 static void * 422 + mt76_dma_get_rxdmad_c_buf(struct mt76_dev *dev, struct mt76_queue *q, 423 + int idx, int *len, bool *more) 424 + { 425 + struct mt76_queue_entry *e = &q->entry[idx]; 426 + struct mt76_rro_rxdmad_c *dmad = e->buf; 427 + u32 data1 = le32_to_cpu(dmad->data1); 428 + u32 data2 = le32_to_cpu(dmad->data2); 429 + struct mt76_txwi_cache *t; 430 + u16 rx_token_id; 431 + u8 ind_reason; 432 + void *buf; 433 + 434 + rx_token_id = FIELD_GET(RRO_RXDMAD_DATA2_RX_TOKEN_ID_MASK, data2); 435 + t = mt76_rx_token_release(dev, rx_token_id); 436 + if (!t) 437 + return ERR_PTR(-EAGAIN); 438 + 439 + q = &dev->q_rx[t->qid]; 440 + dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 441 + SKB_WITH_OVERHEAD(q->buf_size), 442 + page_pool_get_dma_dir(q->page_pool)); 443 + 444 + if (len) 445 + *len = FIELD_GET(RRO_RXDMAD_DATA1_SDL0_MASK, data1); 446 + if (more) 447 + *more = !FIELD_GET(RRO_RXDMAD_DATA1_LS_MASK, data1); 448 + 449 + buf = t->ptr; 450 + ind_reason = FIELD_GET(RRO_RXDMAD_DATA2_IND_REASON_MASK, data2); 451 + if (ind_reason == MT_DMA_WED_IND_REASON_REPEAT || 452 + ind_reason == MT_DMA_WED_IND_REASON_OLDPKT) { 453 + mt76_put_page_pool_buf(buf, false); 454 + buf = ERR_PTR(-EAGAIN); 455 + } 456 + t->ptr = NULL; 457 + t->dma_addr = 0; 458 + 459 + mt76_put_rxwi(dev, t); 460 + 461 + return buf; 462 + } 463 + 464 + static void * 473 465 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 474 - int *len, u32 *info, bool *more, bool *drop) 466 + int *len, u32 *info, bool *more, bool *drop, bool flush) 475 467 { 476 468 struct mt76_queue_entry *e = &q->entry[idx]; 477 469 struct mt76_desc *desc = &q->desc[idx]; 478 470 u32 ctrl, desc_info, buf1; 479 471 void *buf = e->buf; 480 472 481 - if (mt76_queue_is_wed_rro_ind(q)) 473 + if (mt76_queue_is_wed_rro_rxdmad_c(q) && !flush) 474 + buf = mt76_dma_get_rxdmad_c_buf(dev, q, idx, len, more); 475 + 476 + if (mt76_queue_is_wed_rro(q)) 482 477 goto done; 483 478 484 479 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); ··· 579 482 if (!q->queued) 580 483 return NULL; 581 484 582 - if (mt76_queue_is_wed_rro_data(q)) 583 - return NULL; 485 + if (mt76_queue_is_wed_rro_data(q) || mt76_queue_is_wed_rro_msdu_pg(q)) 486 + goto done; 584 487 585 - if (!mt76_queue_is_wed_rro_ind(q)) { 488 + if (mt76_queue_is_wed_rro_ind(q)) { 489 + struct mt76_wed_rro_ind *cmd; 490 + u8 magic_cnt; 491 + 492 + if (flush) 493 + goto done; 494 + 495 + cmd = q->entry[idx].buf; 496 + magic_cnt = FIELD_GET(RRO_IND_DATA1_MAGIC_CNT_MASK, 497 + le32_to_cpu(cmd->data1)); 498 + if (magic_cnt != q->magic_cnt) 499 + return NULL; 500 + 501 + if (q->tail == q->ndesc - 1) 502 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_WED_IND_CMD_CNT; 503 + } else if (mt76_queue_is_wed_rro_rxdmad_c(q)) { 504 + struct mt76_rro_rxdmad_c *dmad; 505 + u16 magic_cnt; 506 + 507 + if (flush) 508 + goto done; 509 + 510 + dmad = q->entry[idx].buf; 511 + magic_cnt = FIELD_GET(RRO_RXDMAD_DATA3_MAGIC_CNT_MASK, 512 + le32_to_cpu(dmad->data3)); 513 + if (magic_cnt != q->magic_cnt) 514 + return NULL; 515 + 516 + if (q->tail == q->ndesc - 1) 517 + q->magic_cnt = (q->magic_cnt + 1) % MT_DMA_MAGIC_CNT; 518 + } else { 586 519 if (flush) 587 520 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 588 521 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 589 522 return NULL; 590 523 } 591 - 524 + done: 592 525 q->tail = (q->tail + 1) % q->ndesc; 593 526 q->queued--; 594 527 595 - return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 528 + return mt76_dma_get_buf(dev, q, idx, len, info, more, drop, flush); 596 529 } 597 530 598 531 static int ··· 773 646 void *buf = NULL; 774 647 int offset; 775 648 776 - if (mt76_queue_is_wed_rro_ind(q)) 649 + if (mt76_queue_is_wed_rro_ind(q) || 650 + mt76_queue_is_wed_rro_rxdmad_c(q)) 777 651 goto done; 778 652 779 653 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); ··· 803 675 bool allow_direct) 804 676 { 805 677 int frames; 806 - 807 - if (!q->ndesc) 808 - return 0; 809 678 810 679 spin_lock_bh(&q->lock); 811 680 frames = mt76_dma_rx_fill_buf(dev, q, allow_direct); ··· 833 708 if (!q->desc) 834 709 return -ENOMEM; 835 710 836 - if (mt76_queue_is_wed_rro_ind(q)) { 837 - struct mt76_wed_rro_desc *rro_desc; 838 - int i; 839 - 840 - rro_desc = (struct mt76_wed_rro_desc *)q->desc; 841 - for (i = 0; i < q->ndesc; i++) { 842 - struct mt76_wed_rro_ind *cmd; 843 - 844 - cmd = (struct mt76_wed_rro_ind *)&rro_desc[i]; 845 - cmd->magic_cnt = MT_DMA_WED_IND_CMD_CNT - 1; 846 - } 847 - } 848 - 711 + mt76_dma_queue_magic_cnt_init(dev, q); 849 712 size = q->ndesc * sizeof(*q->entry); 850 713 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 851 714 if (!q->entry) ··· 853 740 return 0; 854 741 } 855 742 856 - mt76_dma_queue_reset(dev, q); 743 + /* HW specific driver is supposed to reset brand-new EMI queues since 744 + * it needs to set cpu index pointer. 745 + */ 746 + mt76_dma_queue_reset(dev, q, !mt76_queue_is_emi(q)); 857 747 858 748 return 0; 859 749 } ··· 899 783 if (!q->ndesc) 900 784 return; 901 785 902 - if (!mt76_queue_is_wed_rro_ind(q)) { 786 + if (!mt76_queue_is_wed_rro_ind(q) && 787 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 903 788 int i; 904 789 905 790 for (i = 0; i < q->ndesc; i++) ··· 960 843 bool allow_direct = !mt76_queue_is_wed_rx(q); 961 844 bool more; 962 845 963 - if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 964 - mt76_queue_is_wed_tx_free(q)) { 846 + if ((q->flags & MT_QFLAG_WED_RRO_EN) || 847 + (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 848 + mt76_queue_is_wed_tx_free(q))) { 965 849 dma_idx = Q_READ(q, dma_idx); 966 850 check_ddone = true; 967 851 } ··· 983 865 &drop); 984 866 if (!data) 985 867 break; 868 + 869 + if (PTR_ERR(data) == -EAGAIN) { 870 + done++; 871 + continue; 872 + } 873 + 874 + if (mt76_queue_is_wed_rro_ind(q) && dev->drv->rx_rro_ind_process) 875 + dev->drv->rx_rro_ind_process(dev, data); 876 + 877 + if (mt76_queue_is_wed_rro(q) && 878 + !mt76_queue_is_wed_rro_rxdmad_c(q)) { 879 + done++; 880 + continue; 881 + } 986 882 987 883 if (drop) 988 884 goto free_frag; ··· 1075 943 } 1076 944 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 1077 945 946 + static void 947 + mt76_dma_rx_queue_init(struct mt76_dev *dev, enum mt76_rxq_id qid, 948 + int (*poll)(struct napi_struct *napi, int budget)) 949 + { 950 + netif_napi_add(dev->napi_dev, &dev->napi[qid], poll); 951 + mt76_dma_rx_fill_buf(dev, &dev->q_rx[qid], false); 952 + napi_enable(&dev->napi[qid]); 953 + } 954 + 1078 955 static int 1079 956 mt76_dma_init(struct mt76_dev *dev, 1080 957 int (*poll)(struct napi_struct *napi, int budget)) ··· 1116 975 init_completion(&dev->mmio.wed_reset_complete); 1117 976 1118 977 mt76_for_each_q_rx(dev, i) { 1119 - netif_napi_add(dev->napi_dev, &dev->napi[i], poll); 1120 - mt76_dma_rx_fill_buf(dev, &dev->q_rx[i], false); 1121 - napi_enable(&dev->napi[i]); 978 + if (mt76_queue_is_wed_rro(&dev->q_rx[i])) 979 + continue; 980 + 981 + mt76_dma_rx_queue_init(dev, i, poll); 1122 982 } 1123 983 1124 984 return 0; ··· 1132 990 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 1133 991 .tx_queue_skb = mt76_dma_tx_queue_skb, 1134 992 .tx_cleanup = mt76_dma_tx_cleanup, 993 + .rx_queue_init = mt76_dma_rx_queue_init, 1135 994 .rx_cleanup = mt76_dma_rx_cleanup, 1136 995 .rx_reset = mt76_dma_rx_reset, 1137 996 .kick = mt76_dma_kick_queue,

+24 -5

drivers/net/wireless/mediatek/mt76/dma.h

··· 31 31 #define MT_DMA_CTL_PN_CHK_FAIL BIT(13) 32 32 #define MT_DMA_CTL_VER_MASK BIT(7) 33 33 34 - #define MT_DMA_RRO_EN BIT(13) 34 + #define MT_DMA_SDP0 GENMASK(15, 0) 35 + #define MT_DMA_TOKEN_ID GENMASK(31, 16) 36 + #define MT_DMA_MAGIC_MASK GENMASK(31, 28) 37 + #define MT_DMA_RRO_EN BIT(13) 38 + 39 + #define MT_DMA_MAGIC_CNT 16 35 40 36 41 #define MT_DMA_WED_IND_CMD_CNT 8 37 42 #define MT_DMA_WED_IND_REASON GENMASK(15, 12) ··· 57 52 __le32 buf0; 58 53 __le32 buf1; 59 54 } __packed __aligned(4); 55 + 56 + /* data1 */ 57 + #define RRO_RXDMAD_DATA1_LS_MASK BIT(30) 58 + #define RRO_RXDMAD_DATA1_SDL0_MASK GENMASK(29, 16) 59 + /* data2 */ 60 + #define RRO_RXDMAD_DATA2_RX_TOKEN_ID_MASK GENMASK(31, 16) 61 + #define RRO_RXDMAD_DATA2_IND_REASON_MASK GENMASK(15, 12) 62 + /* data3 */ 63 + #define RRO_RXDMAD_DATA3_MAGIC_CNT_MASK GENMASK(31, 28) 64 + struct mt76_rro_rxdmad_c { 65 + __le32 data0; 66 + __le32 data1; 67 + __le32 data2; 68 + __le32 data3; 69 + }; 60 70 61 71 enum mt76_qsel { 62 72 MT_QSEL_MGMT, ··· 101 81 void mt76_dma_cleanup(struct mt76_dev *dev); 102 82 int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 103 83 bool allow_direct); 104 - void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 105 - bool reset_idx); 106 - void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q); 84 + void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q, 85 + bool reset_idx); 107 86 108 87 static inline void 109 88 mt76_dma_reset_tx_queue(struct mt76_dev *dev, struct mt76_queue *q) 110 89 { 111 - dev->queue_ops->reset_q(dev, q); 90 + dev->queue_ops->reset_q(dev, q, true); 112 91 if (mtk_wed_device_active(&dev->mmio.wed)) 113 92 mt76_wed_dma_setup(dev, q, true); 114 93 }

+7 -2

drivers/net/wireless/mediatek/mt76/eeprom.c

··· 163 163 return mt76_get_of_data_from_nvmem(dev, eep, "eeprom", len); 164 164 } 165 165 166 - void 166 + int 167 167 mt76_eeprom_override(struct mt76_phy *phy) 168 168 { 169 169 struct mt76_dev *dev = phy->dev; 170 170 struct device_node *np = dev->dev->of_node; 171 + int err; 171 172 172 - of_get_mac_address(np, phy->macaddr); 173 + err = of_get_mac_address(np, phy->macaddr); 174 + if (err == -EPROBE_DEFER) 175 + return err; 173 176 174 177 if (!is_valid_ether_addr(phy->macaddr)) { 175 178 eth_random_addr(phy->macaddr); ··· 180 177 "Invalid MAC address, using random address %pM\n", 181 178 phy->macaddr); 182 179 } 180 + 181 + return 0; 183 182 } 184 183 EXPORT_SYMBOL_GPL(mt76_eeprom_override); 185 184

+59

drivers/net/wireless/mediatek/mt76/mac80211.c

··· 824 824 return; 825 825 826 826 INIT_LIST_HEAD(&phy->tx_list); 827 + phy->num_sta = 0; 828 + phy->chanctx = NULL; 829 + mt76_roc_complete(phy); 827 830 } 828 831 829 832 void mt76_reset_device(struct mt76_dev *dev) ··· 846 843 rcu_assign_pointer(dev->wcid[i], NULL); 847 844 } 848 845 rcu_read_unlock(); 846 + 847 + mt76_abort_scan(dev); 849 848 850 849 INIT_LIST_HEAD(&dev->wcid_list); 851 850 INIT_LIST_HEAD(&dev->sta_poll_list); ··· 1239 1234 1240 1235 mstat = *((struct mt76_rx_status *)skb->cb); 1241 1236 memset(status, 0, sizeof(*status)); 1237 + 1238 + skb->priority = mstat.qos_ctl & IEEE80211_QOS_CTL_TID_MASK; 1242 1239 1243 1240 status->flag = mstat.flag; 1244 1241 status->freq = mstat.freq; ··· 2067 2060 mt76_abort_roc(mvif->roc_phy); 2068 2061 } 2069 2062 EXPORT_SYMBOL_GPL(mt76_vif_cleanup); 2063 + 2064 + u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links) 2065 + { 2066 + unsigned long usable_links = ieee80211_vif_usable_links(vif); 2067 + struct { 2068 + u8 link_id; 2069 + enum nl80211_band band; 2070 + } data[IEEE80211_MLD_MAX_NUM_LINKS]; 2071 + unsigned int link_id; 2072 + int i, n_data = 0; 2073 + u16 sel_links = 0; 2074 + 2075 + if (!ieee80211_vif_is_mld(vif)) 2076 + return 0; 2077 + 2078 + if (vif->active_links == usable_links) 2079 + return vif->active_links; 2080 + 2081 + rcu_read_lock(); 2082 + for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 2083 + struct ieee80211_bss_conf *link_conf; 2084 + 2085 + link_conf = rcu_dereference(vif->link_conf[link_id]); 2086 + if (WARN_ON_ONCE(!link_conf)) 2087 + continue; 2088 + 2089 + data[n_data].link_id = link_id; 2090 + data[n_data].band = link_conf->chanreq.oper.chan->band; 2091 + n_data++; 2092 + } 2093 + rcu_read_unlock(); 2094 + 2095 + for (i = 0; i < n_data; i++) { 2096 + int j; 2097 + 2098 + if (!(BIT(data[i].link_id) & vif->active_links)) 2099 + continue; 2100 + 2101 + sel_links = BIT(data[i].link_id); 2102 + for (j = 0; j < n_data; j++) { 2103 + if (data[i].band != data[j].band) { 2104 + sel_links |= BIT(data[j].link_id); 2105 + if (hweight16(sel_links) == max_active_links) 2106 + break; 2107 + } 2108 + } 2109 + break; 2110 + } 2111 + 2112 + return sel_links; 2113 + } 2114 + EXPORT_SYMBOL_GPL(mt76_select_links);

+58 -17

drivers/net/wireless/mediatek/mt76/mt76.h

··· 33 33 #define MT_QFLAG_WED BIT(5) 34 34 #define MT_QFLAG_WED_RRO BIT(6) 35 35 #define MT_QFLAG_WED_RRO_EN BIT(7) 36 + #define MT_QFLAG_EMI_EN BIT(8) 36 37 37 38 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 38 39 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ ··· 46 45 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 47 46 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 48 47 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 48 + #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0) 49 49 50 50 struct mt76_dev; 51 51 struct mt76_phy; ··· 73 71 MT76_WED_RRO_Q_DATA, 74 72 MT76_WED_RRO_Q_MSDU_PG, 75 73 MT76_WED_RRO_Q_IND, 74 + MT76_WED_RRO_Q_RXDMAD_C, 75 + }; 76 + 77 + enum mt76_hwrro_mode { 78 + MT76_HWRRO_OFF, 79 + MT76_HWRRO_V3, 80 + MT76_HWRRO_V3_1, 76 81 }; 77 82 78 83 struct mt76_bus_ops { ··· 138 129 MT_RXQ_TXFREE_BAND1, 139 130 MT_RXQ_TXFREE_BAND2, 140 131 MT_RXQ_RRO_IND, 132 + MT_RXQ_RRO_RXDMAD_C, 141 133 __MT_RXQ_MAX 142 134 }; 143 135 ··· 242 232 243 233 u8 buf_offset; 244 234 u16 flags; 235 + u8 magic_cnt; 236 + 237 + __le16 *emi_cpu_idx; 245 238 246 239 struct mtk_wed_device *wed; 247 240 u32 wed_regs; ··· 299 286 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 300 287 bool flush); 301 288 289 + void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid, 290 + int (*poll)(struct napi_struct *napi, int budget)); 291 + 302 292 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 303 293 304 294 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 305 295 306 - void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 296 + void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q, 297 + bool reset_idx); 307 298 }; 308 299 309 300 enum mt76_phy_type { ··· 415 398 bool aggr; 416 399 }; 417 400 401 + /* data0 */ 402 + #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28) 403 + #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16) 404 + #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0) 405 + /* data1 */ 406 + #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29) 407 + #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0) 418 408 struct mt76_wed_rro_ind { 419 - u32 se_id : 12; 420 - u32 rsv : 4; 421 - u32 start_sn : 12; 422 - u32 ind_reason : 4; 423 - u32 ind_cnt : 13; 424 - u32 win_sz : 3; 425 - u32 rsv2 : 13; 426 - u32 magic_cnt : 3; 409 + __le32 data0; 410 + __le32 data1; 427 411 }; 428 412 429 413 struct mt76_txwi_cache { ··· 435 417 struct sk_buff *skb; 436 418 void *ptr; 437 419 }; 420 + 421 + u8 qid; 438 422 }; 439 423 440 424 struct mt76_rx_tid { ··· 552 532 struct sk_buff *skb, u32 *info); 553 533 554 534 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 535 + 536 + void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data); 537 + int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q, 538 + dma_addr_t p, void *data); 555 539 556 540 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 557 541 bool ps); ··· 934 910 struct mt76_queue q_rx[__MT_RXQ_MAX]; 935 911 const struct mt76_queue_ops *queue_ops; 936 912 int tx_dma_idx[4]; 913 + enum mt76_hwrro_mode hwrro_mode; 937 914 938 915 struct mt76_worker tx_worker; 939 916 struct napi_struct tx_napi; ··· 1239 1214 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1240 1215 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1241 1216 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1217 + #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__) 1242 1218 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1243 1219 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1244 1220 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) ··· 1294 1268 s8 *val, int len); 1295 1269 1296 1270 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1297 - void mt76_eeprom_override(struct mt76_phy *phy); 1271 + int mt76_eeprom_override(struct mt76_phy *phy); 1298 1272 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1299 1273 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1300 1274 const char *cell_name, int len); ··· 1643 1617 void mt76_scan_work(struct work_struct *work); 1644 1618 void mt76_abort_scan(struct mt76_dev *dev); 1645 1619 void mt76_roc_complete_work(struct work_struct *work); 1620 + void mt76_roc_complete(struct mt76_phy *phy); 1646 1621 void mt76_abort_roc(struct mt76_phy *phy); 1647 1622 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1648 1623 struct ieee80211_vif *vif); ··· 1809 1782 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1810 1783 } 1811 1784 1785 + static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q) 1786 + { 1787 + return mt76_queue_is_wed_rro(q) && 1788 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C; 1789 + } 1790 + 1812 1791 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1813 1792 { 1814 1793 return mt76_queue_is_wed_rro(q) && 1815 - (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1816 - FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1794 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA; 1795 + } 1796 + 1797 + static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q) 1798 + { 1799 + return mt76_queue_is_wed_rro(q) && 1800 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == 1801 + MT76_WED_RRO_Q_MSDU_PG; 1817 1802 } 1818 1803 1819 1804 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1820 1805 { 1821 - if (!(q->flags & MT_QFLAG_WED)) 1822 - return false; 1806 + return (q->flags & MT_QFLAG_WED) && 1807 + FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1808 + } 1823 1809 1824 - return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1825 - mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1826 - 1810 + static inline bool mt76_queue_is_emi(struct mt76_queue *q) 1811 + { 1812 + return q->flags & MT_QFLAG_EMI_EN; 1827 1813 } 1828 1814 1829 1815 struct mt76_txwi_cache * ··· 1912 1872 } 1913 1873 1914 1874 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 1875 + u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links); 1915 1876 1916 1877 static inline struct mt76_vif_link * 1917 1878 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id)

+1 -2

drivers/net/wireless/mediatek/mt76/mt7603/eeprom.c

··· 182 182 dev->mphy.antenna_mask = 1; 183 183 184 184 dev->mphy.chainmask = dev->mphy.antenna_mask; 185 - mt76_eeprom_override(&dev->mphy); 186 185 187 - return 0; 186 + return mt76_eeprom_override(&dev->mphy); 188 187 }

+1 -1

drivers/net/wireless/mediatek/mt76/mt7603/soc.c

··· 48 48 49 49 return 0; 50 50 error: 51 - ieee80211_free_hw(mt76_hw(dev)); 51 + mt76_free_device(mdev); 52 52 return ret; 53 53 } 54 54

+1 -3

drivers/net/wireless/mediatek/mt76/mt7615/eeprom.c

··· 351 351 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 352 352 ETH_ALEN); 353 353 354 - mt76_eeprom_override(&dev->mphy); 355 - 356 - return 0; 354 + return mt76_eeprom_override(&dev->mphy); 357 355 } 358 356 EXPORT_SYMBOL_GPL(mt7615_eeprom_init);

+4 -1

drivers/net/wireless/mediatek/mt76/mt7615/init.c

··· 570 570 ETH_ALEN); 571 571 mphy->macaddr[0] |= 2; 572 572 mphy->macaddr[0] ^= BIT(7); 573 - mt76_eeprom_override(mphy); 573 + 574 + ret = mt76_eeprom_override(mphy); 575 + if (ret) 576 + return ret; 574 577 575 578 /* second phy can only handle 5 GHz */ 576 579 mphy->cap.has_5ghz = true;

+7

drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

··· 294 294 #define MT_TXP_BUF_LEN GENMASK(11, 0) 295 295 #define MT_TXP_DMA_ADDR_H GENMASK(15, 12) 296 296 297 + #define MT_TXP0_TOKEN_ID0 GENMASK(14, 0) 298 + #define MT_TXP0_TOKEN_ID0_VALID_MASK BIT(15) 299 + 300 + #define MT_TXP1_TID_ADDBA GENMASK(14, 12) 301 + #define MT_TXP3_ML0_MASK BIT(15) 302 + #define MT_TXP3_DMA_ADDR_H GENMASK(13, 12) 303 + 297 304 #define MT_TX_RATE_STBC BIT(14) 298 305 #define MT_TX_RATE_NSS GENMASK(13, 10) 299 306 #define MT_TX_RATE_MODE GENMASK(9, 6)

+25

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c

··· 1662 1662 return err; 1663 1663 } 1664 1664 1665 + if (enable && vif->bss_conf.bssid_indicator) { 1666 + struct { 1667 + struct { 1668 + u8 bss_idx; 1669 + u8 pad[3]; 1670 + } __packed hdr; 1671 + struct bss_info_uni_mbssid mbssid; 1672 + } mbssid_req = { 1673 + .hdr = { 1674 + .bss_idx = mvif->idx, 1675 + }, 1676 + .mbssid = { 1677 + .tag = cpu_to_le16(UNI_BSS_INFO_11V_MBSSID), 1678 + .len = cpu_to_le16(sizeof(struct bss_info_uni_mbssid)), 1679 + .max_indicator = vif->bss_conf.bssid_indicator, 1680 + .mbss_idx = vif->bss_conf.bssid_index, 1681 + }, 1682 + }; 1683 + 1684 + err = mt76_mcu_send_msg(mdev, MCU_UNI_CMD(BSS_INFO_UPDATE), 1685 + &mbssid_req, sizeof(mbssid_req), true); 1686 + if (err < 0) 1687 + return err; 1688 + } 1689 + 1665 1690 return mt76_connac_mcu_uni_set_chctx(phy, mvif, ctx); 1666 1691 } 1667 1692 EXPORT_SYMBOL_GPL(mt76_connac_mcu_uni_add_bss);

+5 -1

drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c

··· 332 332 333 333 memcpy(dev->mphy.macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 334 334 ETH_ALEN); 335 - mt76_eeprom_override(&dev->mphy); 335 + 336 + err = mt76_eeprom_override(&dev->mphy); 337 + if (err) 338 + return err; 339 + 336 340 mt76x02_mac_setaddr(dev, dev->mphy.macaddr); 337 341 338 342 mt76x0_set_chip_cap(dev);

+3 -1

drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c

··· 499 499 500 500 mt76x02_eeprom_parse_hw_cap(dev); 501 501 mt76x2_eeprom_get_macaddr(dev); 502 - mt76_eeprom_override(&dev->mphy); 502 + ret = mt76_eeprom_override(&dev->mphy); 503 + if (ret) 504 + return ret; 503 505 dev->mphy.macaddr[0] &= ~BIT(1); 504 506 505 507 return 0;

+2 -2

drivers/net/wireless/mediatek/mt76/mt7915/dma.c

··· 624 624 } 625 625 626 626 for (i = 0; i < __MT_MCUQ_MAX; i++) 627 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 627 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 628 628 629 629 mt76_for_each_q_rx(&dev->mt76, i) { 630 630 if (mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i])) 631 631 continue; 632 632 633 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 633 + mt76_queue_reset(dev, &dev->mt76.q_rx[i], true); 634 634 } 635 635 636 636 mt76_tx_status_check(&dev->mt76, true);

+1 -3

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.c

··· 284 284 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 285 285 ETH_ALEN); 286 286 287 - mt76_eeprom_override(&dev->mphy); 288 - 289 - return 0; 287 + return mt76_eeprom_override(&dev->mphy); 290 288 } 291 289 292 290 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,

+3 -3

drivers/net/wireless/mediatek/mt76/mt7915/eeprom.h

··· 50 50 #define MT_EE_CAL_GROUP_SIZE_7975 (54 * MT_EE_CAL_UNIT + 16) 51 51 #define MT_EE_CAL_GROUP_SIZE_7976 (94 * MT_EE_CAL_UNIT + 16) 52 52 #define MT_EE_CAL_GROUP_SIZE_7916_6G (94 * MT_EE_CAL_UNIT + 16) 53 + #define MT_EE_CAL_GROUP_SIZE_7981 (144 * MT_EE_CAL_UNIT + 16) 53 54 #define MT_EE_CAL_DPD_SIZE_V1 (54 * MT_EE_CAL_UNIT) 54 55 #define MT_EE_CAL_DPD_SIZE_V2 (300 * MT_EE_CAL_UNIT) 55 - #define MT_EE_CAL_DPD_SIZE_V2_7981 (102 * MT_EE_CAL_UNIT) /* no 6g dpd data */ 56 56 57 57 #define MT_EE_WIFI_CONF0_TX_PATH GENMASK(2, 0) 58 58 #define MT_EE_WIFI_CONF0_RX_PATH GENMASK(5, 3) ··· 180 180 val = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val); 181 181 return (val == MT_EE_V2_BAND_SEL_6GHZ) ? MT_EE_CAL_GROUP_SIZE_7916_6G : 182 182 MT_EE_CAL_GROUP_SIZE_7916; 183 + } else if (is_mt7981(&dev->mt76)) { 184 + return MT_EE_CAL_GROUP_SIZE_7981; 183 185 } else if (mt7915_check_adie(dev, false)) { 184 186 return MT_EE_CAL_GROUP_SIZE_7976; 185 187 } else { ··· 194 192 { 195 193 if (is_mt7915(&dev->mt76)) 196 194 return MT_EE_CAL_DPD_SIZE_V1; 197 - else if (is_mt7981(&dev->mt76)) 198 - return MT_EE_CAL_DPD_SIZE_V2_7981; 199 195 else 200 196 return MT_EE_CAL_DPD_SIZE_V2; 201 197 }

+3 -1

drivers/net/wireless/mediatek/mt76/mt7915/init.c

··· 702 702 mphy->macaddr[0] |= 2; 703 703 mphy->macaddr[0] ^= BIT(7); 704 704 } 705 - mt76_eeprom_override(mphy); 705 + ret = mt76_eeprom_override(mphy); 706 + if (ret) 707 + return ret; 706 708 707 709 /* init wiphy according to mphy and phy */ 708 710 mt7915_init_wiphy(phy);

+7 -22

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

··· 3052 3052 /* 5G BW160 */ 3053 3053 5250, 5570, 5815 3054 3054 }; 3055 - static const u16 freq_list_v2_7981[] = { 3056 - /* 5G BW20 */ 3057 - 5180, 5200, 5220, 5240, 3058 - 5260, 5280, 5300, 5320, 3059 - 5500, 5520, 5540, 5560, 3060 - 5580, 5600, 5620, 5640, 3061 - 5660, 5680, 5700, 5720, 3062 - 5745, 5765, 5785, 5805, 3063 - 5825, 5845, 5865, 5885, 3064 - /* 5G BW160 */ 3065 - 5250, 5570, 5815 3066 - }; 3067 - const u16 *freq_list = freq_list_v1; 3068 - int n_freqs = ARRAY_SIZE(freq_list_v1); 3069 - int idx; 3055 + const u16 *freq_list; 3056 + int idx, n_freqs; 3070 3057 3071 3058 if (!is_mt7915(&dev->mt76)) { 3072 - if (is_mt7981(&dev->mt76)) { 3073 - freq_list = freq_list_v2_7981; 3074 - n_freqs = ARRAY_SIZE(freq_list_v2_7981); 3075 - } else { 3076 - freq_list = freq_list_v2; 3077 - n_freqs = ARRAY_SIZE(freq_list_v2); 3078 - } 3059 + freq_list = freq_list_v2; 3060 + n_freqs = ARRAY_SIZE(freq_list_v2); 3061 + } else { 3062 + freq_list = freq_list_v1; 3063 + n_freqs = ARRAY_SIZE(freq_list_v1); 3079 3064 } 3080 3065 3081 3066 if (freq < 4000) {

+3 -1

drivers/net/wireless/mediatek/mt76/mt7921/init.c

··· 189 189 if (ret) 190 190 goto out; 191 191 192 - mt76_eeprom_override(&dev->mphy); 192 + ret = mt76_eeprom_override(&dev->mphy); 193 + if (ret) 194 + goto out; 193 195 194 196 ret = mt7921_mcu_set_eeprom(dev); 195 197 if (ret)

+2

drivers/net/wireless/mediatek/mt76/mt7921/main.c

··· 135 135 if (is_mt7922(phy->mt76->dev)) { 136 136 he_cap_elem->phy_cap_info[0] |= 137 137 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 138 + he_cap_elem->phy_cap_info[4] |= 139 + IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 138 140 he_cap_elem->phy_cap_info[8] |= 139 141 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 140 142 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;

+3

drivers/net/wireless/mediatek/mt76/mt7921/usb.c

··· 21 21 /* Netgear, Inc. [A8000,AXE3000] */ 22 22 { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9060, 0xff, 0xff, 0xff), 23 23 .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 24 + /* Netgear, Inc. A7500 */ 25 + { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9065, 0xff, 0xff, 0xff), 26 + .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 24 27 /* TP-Link TXE50UH */ 25 28 { USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0107, 0xff, 0xff, 0xff), 26 29 .driver_info = (kernel_ulong_t)MT7921_FIRMWARE_WM },

+3 -1

drivers/net/wireless/mediatek/mt76/mt7925/init.c

··· 249 249 if (ret) 250 250 goto out; 251 251 252 - mt76_eeprom_override(&dev->mphy); 252 + ret = mt76_eeprom_override(&dev->mphy); 253 + if (ret) 254 + goto out; 253 255 254 256 ret = mt7925_mcu_set_eeprom(dev); 255 257 if (ret)

+4 -1

drivers/net/wireless/mediatek/mt76/mt7925/mac.c

··· 1300 1300 cancel_delayed_work_sync(&dev->mphy.mac_work); 1301 1301 cancel_delayed_work_sync(&pm->ps_work); 1302 1302 cancel_work_sync(&pm->wake_work); 1303 - dev->sar_inited = false; 1304 1303 1305 1304 for (i = 0; i < 10; i++) { 1306 1305 mutex_lock(&dev->mt76.mutex); ··· 1328 1329 IEEE80211_IFACE_ITER_RESUME_ALL, 1329 1330 mt7925_vif_connect_iter, NULL); 1330 1331 mt76_connac_power_save_sched(&dev->mt76.phy, pm); 1332 + 1333 + mt792x_mutex_acquire(dev); 1334 + mt7925_mcu_set_clc(dev, "00", ENVIRON_INDOOR); 1335 + mt792x_mutex_release(dev); 1331 1336 } 1332 1337 1333 1338 void mt7925_coredump_work(struct work_struct *work)

+2 -65

drivers/net/wireless/mediatek/mt76/mt7925/main.c

··· 240 240 { 241 241 struct wiphy *wiphy = phy->mt76->hw->wiphy; 242 242 static const u8 ext_capa_sta[] = { 243 + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 243 244 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 244 245 }; 245 246 static struct wiphy_iftype_ext_capab ext_capab[] = { ··· 311 310 int __mt7925_start(struct mt792x_phy *phy) 312 311 { 313 312 struct mt76_phy *mphy = phy->mt76; 314 - struct mt792x_dev *dev = phy->dev; 315 313 int err; 316 314 317 315 err = mt7925_mcu_set_channel_domain(mphy); ··· 320 320 err = mt7925_mcu_set_rts_thresh(phy, 0x92b); 321 321 if (err) 322 322 return err; 323 - 324 - if (!dev->sar_inited) { 325 - err = mt7925_set_tx_sar_pwr(mphy->hw, NULL); 326 - if (err) 327 - return err; 328 - dev->sar_inited = true; 329 - } 330 323 331 324 mt792x_mac_reset_counters(phy); 332 325 set_bit(MT76_STATE_RUNNING, &mphy->state); ··· 980 987 } 981 988 EXPORT_SYMBOL_GPL(mt7925_mac_sta_add); 982 989 983 - static u16 984 - mt7925_mac_select_links(struct mt76_dev *mdev, struct ieee80211_vif *vif) 985 - { 986 - unsigned long usable_links = ieee80211_vif_usable_links(vif); 987 - struct { 988 - u8 link_id; 989 - enum nl80211_band band; 990 - } data[IEEE80211_MLD_MAX_NUM_LINKS]; 991 - u8 link_id, i, j, n_data = 0; 992 - u16 sel_links = 0; 993 - 994 - if (!ieee80211_vif_is_mld(vif)) 995 - return 0; 996 - 997 - if (vif->active_links == usable_links) 998 - return vif->active_links; 999 - 1000 - rcu_read_lock(); 1001 - for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 1002 - struct ieee80211_bss_conf *link_conf = 1003 - rcu_dereference(vif->link_conf[link_id]); 1004 - 1005 - if (WARN_ON_ONCE(!link_conf)) 1006 - continue; 1007 - 1008 - data[n_data].link_id = link_id; 1009 - data[n_data].band = link_conf->chanreq.oper.chan->band; 1010 - n_data++; 1011 - } 1012 - rcu_read_unlock(); 1013 - 1014 - for (i = 0; i < n_data; i++) { 1015 - if (!(BIT(data[i].link_id) & vif->active_links)) 1016 - continue; 1017 - 1018 - sel_links = BIT(data[i].link_id); 1019 - 1020 - for (j = 0; j < n_data; j++) { 1021 - if (data[i].band != data[j].band) { 1022 - sel_links |= BIT(data[j].link_id); 1023 - break; 1024 - } 1025 - } 1026 - 1027 - break; 1028 - } 1029 - 1030 - return sel_links; 1031 - } 1032 - 1033 990 static void 1034 991 mt7925_mac_set_links(struct mt76_dev *mdev, struct ieee80211_vif *vif) 1035 992 { ··· 990 1047 struct cfg80211_chan_def *chandef = &link_conf->chanreq.oper; 991 1048 enum nl80211_band band = chandef->chan->band, secondary_band; 992 1049 993 - u16 sel_links = mt7925_mac_select_links(mdev, vif); 1050 + u16 sel_links = mt76_select_links(vif, 2); 994 1051 u8 secondary_link_id = __ffs(~BIT(mvif->deflink_id) & sel_links); 995 1052 996 1053 if (!ieee80211_vif_is_mld(vif) || hweight16(sel_links) < 2) ··· 1674 1731 int err; 1675 1732 1676 1733 mt792x_mutex_acquire(dev); 1677 - err = mt7925_mcu_set_clc(dev, dev->mt76.alpha2, 1678 - dev->country_ie_env); 1679 - if (err < 0) 1680 - goto out; 1681 - 1682 1734 err = mt7925_set_tx_sar_pwr(hw, sar); 1683 - out: 1684 1735 mt792x_mutex_release(dev); 1685 1736 1686 1737 return err;

+25 -3

drivers/net/wireless/mediatek/mt76/mt7925/mcu.c

··· 759 759 } 760 760 } 761 761 762 - ret = mt7925_mcu_set_clc(dev, "00", ENVIRON_INDOOR); 763 762 out: 764 763 release_firmware(fw); 765 764 ··· 2621 2622 } 2622 2623 2623 2624 static void 2625 + mt7925_mcu_bss_mbssid_tlv(struct sk_buff *skb, struct ieee80211_bss_conf *link_conf, 2626 + bool enable) 2627 + { 2628 + struct bss_info_uni_mbssid *mbssid; 2629 + struct tlv *tlv; 2630 + 2631 + if (!enable && !link_conf->bssid_indicator) 2632 + return; 2633 + 2634 + tlv = mt76_connac_mcu_add_tlv(skb, UNI_BSS_INFO_11V_MBSSID, 2635 + sizeof(*mbssid)); 2636 + 2637 + mbssid = (struct bss_info_uni_mbssid *)tlv; 2638 + mbssid->max_indicator = link_conf->bssid_indicator; 2639 + mbssid->mbss_idx = link_conf->bssid_index; 2640 + mbssid->tx_bss_omac_idx = 0; 2641 + } 2642 + 2643 + static void 2624 2644 mt7925_mcu_bss_he_tlv(struct sk_buff *skb, struct ieee80211_bss_conf *link_conf, 2625 2645 struct mt792x_phy *phy) 2626 2646 { ··· 2805 2787 mt7925_mcu_bss_color_tlv(skb, link_conf, enable); 2806 2788 } 2807 2789 2808 - if (enable) 2790 + if (enable) { 2809 2791 mt7925_mcu_bss_rlm_tlv(skb, phy->mt76, link_conf, ctx); 2792 + mt7925_mcu_bss_mbssid_tlv(skb, link_conf, enable); 2793 + } 2810 2794 2811 2795 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 2812 2796 MCU_UNI_CMD(BSS_INFO_UPDATE), true); ··· 3723 3703 3724 3704 int mt7925_mcu_set_rate_txpower(struct mt76_phy *phy) 3725 3705 { 3706 + struct mt76_dev *mdev = phy->dev; 3707 + struct mt792x_dev *dev = mt792x_hw_dev(mdev->hw); 3726 3708 int err; 3727 3709 3728 3710 if (phy->cap.has_2ghz) { ··· 3741 3719 return err; 3742 3720 } 3743 3721 3744 - if (phy->cap.has_6ghz) { 3722 + if (phy->cap.has_6ghz && dev->phy.clc_chan_conf) { 3745 3723 err = mt7925_mcu_rate_txpower_band(phy, 3746 3724 NL80211_BAND_6GHZ); 3747 3725 if (err < 0)

+23 -3

drivers/net/wireless/mediatek/mt76/mt7925/pci.c

··· 529 529 return err; 530 530 } 531 531 532 - static int mt7925_pci_resume(struct device *device) 532 + static int _mt7925_pci_resume(struct device *device, bool restore) 533 533 { 534 534 struct pci_dev *pdev = to_pci_dev(device); 535 535 struct mt76_dev *mdev = pci_get_drvdata(pdev); ··· 569 569 napi_schedule(&mdev->tx_napi); 570 570 local_bh_enable(); 571 571 572 + if (restore) 573 + goto failed; 574 + 572 575 mt76_connac_mcu_set_hif_suspend(mdev, false, false); 573 576 ret = wait_event_timeout(dev->wait, 574 577 dev->hif_resumed, 3 * HZ); ··· 588 585 failed: 589 586 pm->suspended = false; 590 587 591 - if (err < 0) 588 + if (err < 0 || restore) 592 589 mt792x_reset(&dev->mt76); 593 590 594 591 return err; ··· 599 596 mt7925_pci_remove(pdev); 600 597 } 601 598 602 - static DEFINE_SIMPLE_DEV_PM_OPS(mt7925_pm_ops, mt7925_pci_suspend, mt7925_pci_resume); 599 + static int mt7925_pci_resume(struct device *device) 600 + { 601 + return _mt7925_pci_resume(device, false); 602 + } 603 + 604 + static int mt7925_pci_restore(struct device *device) 605 + { 606 + return _mt7925_pci_resume(device, true); 607 + } 608 + 609 + static const struct dev_pm_ops mt7925_pm_ops = { 610 + .suspend = pm_sleep_ptr(mt7925_pci_suspend), 611 + .resume = pm_sleep_ptr(mt7925_pci_resume), 612 + .freeze = pm_sleep_ptr(mt7925_pci_suspend), 613 + .thaw = pm_sleep_ptr(mt7925_pci_resume), 614 + .poweroff = pm_sleep_ptr(mt7925_pci_suspend), 615 + .restore = pm_sleep_ptr(mt7925_pci_restore), 616 + }; 603 617 604 618 static struct pci_driver mt7925_pci_driver = { 605 619 .name = KBUILD_MODNAME,

+3

drivers/net/wireless/mediatek/mt76/mt7925/usb.c

··· 12 12 static const struct usb_device_id mt7925u_device_table[] = { 13 13 { USB_DEVICE_AND_INTERFACE_INFO(0x0e8d, 0x7925, 0xff, 0xff, 0xff), 14 14 .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 15 + /* Netgear, Inc. A9000 */ 16 + { USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9072, 0xff, 0xff, 0xff), 17 + .driver_info = (kernel_ulong_t)MT7925_FIRMWARE_WM }, 15 18 { }, 16 19 }; 17 20

-1

drivers/net/wireless/mediatek/mt76/mt792x.h

··· 234 234 bool aspm_supported:1; 235 235 bool hif_idle:1; 236 236 bool hif_resumed:1; 237 - bool sar_inited:1; 238 237 bool regd_change:1; 239 238 wait_queue_head_t wait; 240 239

+5 -1

drivers/net/wireless/mediatek/mt76/mt792x_core.c

··· 689 689 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 690 690 ieee80211_hw_set(hw, CONNECTION_MONITOR); 691 691 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 692 - if (is_mt7921(&dev->mt76)) 692 + ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 693 + ieee80211_hw_set(hw, SUPPORTS_ONLY_HE_MULTI_BSSID); 694 + 695 + if (is_mt7921(&dev->mt76)) { 693 696 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 697 + } 694 698 695 699 if (dev->pm.enable) 696 700 ieee80211_hw_set(hw, CONNECTION_MONITOR);

+3 -3

drivers/net/wireless/mediatek/mt76/mt792x_dma.c

··· 181 181 182 182 /* reset hw queues */ 183 183 for (i = 0; i < __MT_TXQ_MAX; i++) 184 - mt76_queue_reset(dev, dev->mphy.q_tx[i]); 184 + mt76_queue_reset(dev, dev->mphy.q_tx[i], true); 185 185 186 186 for (i = 0; i < __MT_MCUQ_MAX; i++) 187 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 187 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 188 188 189 189 mt76_for_each_q_rx(&dev->mt76, i) 190 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 190 + mt76_queue_reset(dev, &dev->mt76.q_rx[i], true); 191 191 192 192 mt76_tx_status_check(&dev->mt76, true); 193 193

+257 -67

drivers/net/wireless/mediatek/mt76/mt7996/dma.c

··· 17 17 ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; 18 18 idx -= MT_TXQ_ID(0); 19 19 20 - if (phy->mt76->band_idx == MT_BAND2) 20 + if (wed == &dev->mt76.mmio.wed_hif2) 21 21 flags = MT_WED_Q_TX(0); 22 22 else 23 23 flags = MT_WED_Q_TX(idx); ··· 83 83 break; 84 84 } 85 85 86 - if (dev->has_rro) { 86 + if (mt7996_has_hwrro(dev)) { 87 87 /* band0 */ 88 88 RXQ_CONFIG(MT_RXQ_RRO_BAND0, WFDMA0, MT_INT_RX_DONE_RRO_BAND0, 89 89 MT7996_RXQ_RRO_BAND0); 90 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND0, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND0, 91 - MT7996_RXQ_MSDU_PG_BAND0); 92 - RXQ_CONFIG(MT_RXQ_TXFREE_BAND0, WFDMA0, MT_INT_RX_TXFREE_MAIN, 93 - MT7996_RXQ_TXFREE0); 94 - /* band1 */ 95 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND1, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND1, 96 - MT7996_RXQ_MSDU_PG_BAND1); 97 - /* band2 */ 98 - RXQ_CONFIG(MT_RXQ_RRO_BAND2, WFDMA0, MT_INT_RX_DONE_RRO_BAND2, 99 - MT7996_RXQ_RRO_BAND2); 100 - RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND2, WFDMA0, MT_INT_RX_DONE_MSDU_PG_BAND2, 101 - MT7996_RXQ_MSDU_PG_BAND2); 102 - RXQ_CONFIG(MT_RXQ_TXFREE_BAND2, WFDMA0, MT_INT_RX_TXFREE_TRI, 103 - MT7996_RXQ_TXFREE2); 90 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) 91 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND0, WFDMA0, 92 + MT_INT_RX_DONE_MSDU_PG_BAND0, 93 + MT7996_RXQ_MSDU_PG_BAND0); 94 + if (is_mt7996(&dev->mt76)) { 95 + RXQ_CONFIG(MT_RXQ_TXFREE_BAND0, WFDMA0, 96 + MT_INT_RX_TXFREE_MAIN, MT7996_RXQ_TXFREE0); 97 + /* band1 */ 98 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND1, WFDMA0, 99 + MT_INT_RX_DONE_MSDU_PG_BAND1, 100 + MT7996_RXQ_MSDU_PG_BAND1); 101 + /* band2 */ 102 + RXQ_CONFIG(MT_RXQ_RRO_BAND2, WFDMA0, 103 + MT_INT_RX_DONE_RRO_BAND2, 104 + MT7996_RXQ_RRO_BAND2); 105 + RXQ_CONFIG(MT_RXQ_MSDU_PAGE_BAND2, WFDMA0, 106 + MT_INT_RX_DONE_MSDU_PG_BAND2, 107 + MT7996_RXQ_MSDU_PG_BAND2); 108 + RXQ_CONFIG(MT_RXQ_TXFREE_BAND2, WFDMA0, 109 + MT_INT_RX_TXFREE_TRI, MT7996_RXQ_TXFREE2); 110 + } else { 111 + RXQ_CONFIG(MT_RXQ_RRO_BAND1, WFDMA0, 112 + MT_INT_RX_DONE_RRO_BAND1, 113 + MT7996_RXQ_RRO_BAND1); 114 + } 104 115 105 - RXQ_CONFIG(MT_RXQ_RRO_IND, WFDMA0, MT_INT_RX_DONE_RRO_IND, 106 - MT7996_RXQ_RRO_IND); 116 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) 117 + RXQ_CONFIG(MT_RXQ_RRO_IND, WFDMA0, 118 + MT_INT_RX_DONE_RRO_IND, 119 + MT7996_RXQ_RRO_IND); 120 + else 121 + RXQ_CONFIG(MT_RXQ_RRO_RXDMAD_C, WFDMA0, 122 + MT_INT_RX_DONE_RRO_RXDMAD_C, 123 + MT7996_RXQ_RRO_RXDMAD_C); 107 124 } 108 125 109 126 /* data tx queue */ 110 - TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); 111 127 if (is_mt7996(&dev->mt76)) { 112 - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); 113 - TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); 128 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); 129 + if (dev->hif2) { 130 + /* default bn1:ring19 bn2:ring21 */ 131 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, 132 + MT7996_TXQ_BAND1); 133 + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, 134 + MT7996_TXQ_BAND2); 135 + } else { 136 + /* single pcie bn0/1:ring18 bn2:ring19 */ 137 + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, 138 + MT7996_TXQ_BAND1); 139 + } 114 140 } else { 115 - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); 141 + if (dev->hif2) { 142 + /* bn0:ring18 bn1:ring21 */ 143 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, 144 + MT7996_TXQ_BAND0); 145 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, 146 + MT7996_TXQ_BAND2); 147 + } else { 148 + /* single pcie bn0:ring18 bn1:ring19 */ 149 + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, 150 + MT7996_TXQ_BAND0); 151 + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, 152 + MT7996_TXQ_BAND1); 153 + } 116 154 } 117 155 118 156 /* mcu tx queue */ ··· 204 166 205 167 /* Rx TxFreeDone From MAC Rings */ 206 168 val = is_mt7996(&dev->mt76) ? 4 : 8; 207 - if (is_mt7990(&dev->mt76) || (is_mt7996(&dev->mt76) && dev->has_rro)) 169 + if ((is_mt7996(&dev->mt76) && mt7996_has_hwrro(dev)) || 170 + is_mt7990(&dev->mt76)) 208 171 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND0) + ofs, PREFETCH(val)); 209 172 if (is_mt7990(&dev->mt76) && dev->hif2) 210 173 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND1) + ofs, PREFETCH(val)); 211 - else if (is_mt7996(&dev->mt76) && dev->has_rro) 174 + else if (is_mt7996(&dev->mt76) && mt7996_has_hwrro(dev)) 212 175 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TXFREE_BAND2) + ofs, PREFETCH(val)); 213 176 214 177 /* Rx Data Rings */ ··· 218 179 mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10)); 219 180 220 181 /* Rx RRO Rings */ 221 - if (dev->has_rro) { 182 + if (mt7996_has_hwrro(dev)) { 222 183 mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_RRO_BAND0) + ofs, PREFETCH(0x10)); 223 184 queue = is_mt7996(&dev->mt76) ? MT_RXQ_RRO_BAND2 : MT_RXQ_RRO_BAND1; 224 185 mt76_wr(dev, MT_RXQ_EXT_CTRL(queue) + ofs, PREFETCH(0x10)); ··· 327 288 if (mt7996_band_valid(dev, MT_BAND0)) 328 289 irq_mask |= MT_INT_BAND0_RX_DONE; 329 290 330 - if (mt7996_band_valid(dev, MT_BAND1)) 291 + if (mt7996_band_valid(dev, MT_BAND1)) { 331 292 irq_mask |= MT_INT_BAND1_RX_DONE; 293 + if (is_mt7992(&dev->mt76) && dev->hif2) 294 + irq_mask |= MT_INT_RX_TXFREE_BAND1_EXT; 295 + } 332 296 333 297 if (mt7996_band_valid(dev, MT_BAND2)) 334 - irq_mask |= MT_INT_BAND2_RX_DONE; 298 + irq_mask |= MT_INT_BAND2_RX_DONE | MT_INT_TX_RX_DONE_EXT; 335 299 336 300 if (mtk_wed_device_active(wed) && wed_reset) { 337 301 u32 wed_irq_mask = irq_mask; ··· 420 378 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); 421 379 422 380 mt76_set(dev, MT_WFDMA_HOST_CONFIG, 423 - MT_WFDMA_HOST_CONFIG_PDMA_BAND | 424 - MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 381 + MT_WFDMA_HOST_CONFIG_PDMA_BAND); 382 + 383 + mt76_clear(dev, MT_WFDMA_HOST_CONFIG, 384 + MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 | 385 + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 | 386 + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 387 + 388 + if (is_mt7996(&dev->mt76)) 389 + mt76_set(dev, MT_WFDMA_HOST_CONFIG, 390 + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); 391 + else 392 + mt76_set(dev, MT_WFDMA_HOST_CONFIG, 393 + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1); 425 394 426 395 /* AXI read outstanding number */ 427 396 mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL, 428 397 MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14); 398 + 399 + if (dev->hif2->speed < PCIE_SPEED_5_0GT || 400 + (dev->hif2->speed == PCIE_SPEED_5_0GT && 401 + dev->hif2->width < PCIE_LNK_X2)) { 402 + mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, 403 + WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 404 + FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 405 + 0x1)); 406 + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2, 407 + MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 408 + FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 409 + 0x1)); 410 + } else if (dev->hif2->speed < PCIE_SPEED_8_0GT || 411 + (dev->hif2->speed == PCIE_SPEED_8_0GT && 412 + dev->hif2->width < PCIE_LNK_X2)) { 413 + mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, 414 + WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 415 + FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 416 + 0x2)); 417 + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2, 418 + MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 419 + FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 420 + 0x2)); 421 + } 429 422 430 423 /* WFDMA rx threshold */ 431 424 mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c); ··· 474 397 * so, redirect pcie0 rx ring3 interrupt to pcie1 475 398 */ 476 399 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 477 - dev->has_rro) 400 + mt7996_has_hwrro(dev)) { 401 + u32 intr = is_mt7996(&dev->mt76) ? 402 + MT_WFDMA0_RX_INT_SEL_RING6 : 403 + MT_WFDMA0_RX_INT_SEL_RING9 | 404 + MT_WFDMA0_RX_INT_SEL_RING5; 405 + 478 406 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL + hif1_ofs, 479 - MT_WFDMA0_RX_INT_SEL_RING6); 480 - else 407 + intr); 408 + } else { 481 409 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL, 482 410 MT_WFDMA0_RX_INT_SEL_RING3); 411 + } 483 412 } 484 413 485 414 mt7996_dma_start(dev, reset, true); 486 415 } 487 416 488 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 489 417 int mt7996_dma_rro_init(struct mt7996_dev *dev) 490 418 { 491 419 struct mt76_dev *mdev = &dev->mt76; 492 420 u32 irq_mask; 493 421 int ret; 494 422 423 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 424 + /* rxdmad_c */ 425 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].flags = MT_WED_RRO_Q_RXDMAD_C; 426 + if (mtk_wed_device_active(&mdev->mmio.wed)) 427 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].wed = &mdev->mmio.wed; 428 + else 429 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].flags |= MT_QFLAG_EMI_EN; 430 + ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_RRO_RXDMAD_C], 431 + MT_RXQ_ID(MT_RXQ_RRO_RXDMAD_C), 432 + MT7996_RX_RING_SIZE, 433 + MT7996_RX_BUF_SIZE, 434 + MT_RXQ_RRO_AP_RING_BASE); 435 + if (ret) 436 + return ret; 437 + 438 + /* We need to set cpu idx pointer before resetting the EMI 439 + * queues. 440 + */ 441 + mdev->q_rx[MT_RXQ_RRO_RXDMAD_C].emi_cpu_idx = 442 + &dev->wed_rro.emi_rings_cpu.ptr->ring[0].idx; 443 + mt76_queue_reset(dev, &mdev->q_rx[MT_RXQ_RRO_RXDMAD_C], true); 444 + goto start_hw_rro; 445 + } 446 + 495 447 /* ind cmd */ 496 448 mdev->q_rx[MT_RXQ_RRO_IND].flags = MT_WED_RRO_Q_IND; 497 - mdev->q_rx[MT_RXQ_RRO_IND].wed = &mdev->mmio.wed; 449 + if (mtk_wed_device_active(&mdev->mmio.wed) && 450 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 451 + mdev->q_rx[MT_RXQ_RRO_IND].wed = &mdev->mmio.wed; 498 452 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_RRO_IND], 499 453 MT_RXQ_ID(MT_RXQ_RRO_IND), 500 454 MT7996_RX_RING_SIZE, ··· 536 428 /* rx msdu page queue for band0 */ 537 429 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].flags = 538 430 MT_WED_RRO_Q_MSDU_PG(0) | MT_QFLAG_WED_RRO_EN; 539 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].wed = &mdev->mmio.wed; 431 + if (mtk_wed_device_active(&mdev->mmio.wed) && 432 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 433 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].wed = &mdev->mmio.wed; 540 434 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0], 541 435 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND0), 542 436 MT7996_RX_RING_SIZE, ··· 547 437 if (ret) 548 438 return ret; 549 439 550 - if (mt7996_band_valid(dev, MT_BAND1)) { 440 + if (mt7996_band_valid(dev, MT_BAND1) && is_mt7996(&dev->mt76)) { 551 441 /* rx msdu page queue for band1 */ 552 442 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].flags = 553 443 MT_WED_RRO_Q_MSDU_PG(1) | MT_QFLAG_WED_RRO_EN; 554 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].wed = &mdev->mmio.wed; 444 + if (mtk_wed_device_active(&mdev->mmio.wed) && 445 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 446 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].wed = &mdev->mmio.wed; 555 447 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1], 556 448 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND1), 557 449 MT7996_RX_RING_SIZE, ··· 567 455 /* rx msdu page queue for band2 */ 568 456 mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].flags = 569 457 MT_WED_RRO_Q_MSDU_PG(2) | MT_QFLAG_WED_RRO_EN; 570 - mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].wed = &mdev->mmio.wed; 458 + if (mtk_wed_device_active(&mdev->mmio.wed) && 459 + mtk_wed_get_rx_capa(&mdev->mmio.wed)) 460 + mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].wed = &mdev->mmio.wed; 571 461 ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2], 572 462 MT_RXQ_ID(MT_RXQ_MSDU_PAGE_BAND2), 573 463 MT7996_RX_RING_SIZE, ··· 579 465 return ret; 580 466 } 581 467 582 - irq_mask = mdev->mmio.irqmask | MT_INT_RRO_RX_DONE | 583 - MT_INT_TX_DONE_BAND2; 584 - mt76_wr(dev, MT_INT_MASK_CSR, irq_mask); 585 - mtk_wed_device_start_hw_rro(&mdev->mmio.wed, irq_mask, false); 586 - mt7996_irq_enable(dev, irq_mask); 468 + start_hw_rro: 469 + if (mtk_wed_device_active(&mdev->mmio.wed)) { 470 + irq_mask = mdev->mmio.irqmask | 471 + MT_INT_TX_DONE_BAND2; 472 + 473 + mt76_wr(dev, MT_INT_MASK_CSR, irq_mask); 474 + mtk_wed_device_start_hw_rro(&mdev->mmio.wed, irq_mask, false); 475 + mt7996_irq_enable(dev, irq_mask); 476 + } else { 477 + if (is_mt7996(&dev->mt76)) { 478 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND1, 479 + mt76_dma_rx_poll); 480 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND2, 481 + mt76_dma_rx_poll); 482 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND2, 483 + mt76_dma_rx_poll); 484 + } else { 485 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND1, 486 + mt76_dma_rx_poll); 487 + } 488 + 489 + mt76_queue_rx_init(dev, MT_RXQ_RRO_BAND0, mt76_dma_rx_poll); 490 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 491 + mt76_queue_rx_init(dev, MT_RXQ_RRO_RXDMAD_C, 492 + mt76_dma_rx_poll); 493 + } else { 494 + mt76_queue_rx_init(dev, MT_RXQ_RRO_IND, 495 + mt76_dma_rx_poll); 496 + mt76_queue_rx_init(dev, MT_RXQ_MSDU_PAGE_BAND0, 497 + mt76_dma_rx_poll); 498 + } 499 + mt7996_irq_enable(dev, MT_INT_RRO_RX_DONE); 500 + } 587 501 588 502 return 0; 589 503 } 590 - #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 591 504 592 505 int mt7996_dma_init(struct mt7996_dev *dev) 593 506 { ··· 701 560 return ret; 702 561 703 562 /* tx free notify event from WA for band0 */ 704 - if (mtk_wed_device_active(wed) && !dev->has_rro) { 563 + if (mtk_wed_device_active(wed) && 564 + ((is_mt7996(&dev->mt76) && !mt7996_has_hwrro(dev)) || 565 + (is_mt7992(&dev->mt76)))) { 705 566 dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; 706 567 dev->mt76.q_rx[MT_RXQ_MAIN_WA].wed = wed; 707 568 } ··· 758 615 /* tx free notify event from WA for mt7996 band2 759 616 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1 760 617 */ 761 - if (mtk_wed_device_active(wed_hif2) && !dev->has_rro) { 618 + if (mtk_wed_device_active(wed_hif2) && !mt7996_has_hwrro(dev)) { 762 619 dev->mt76.q_rx[MT_RXQ_BAND2_WA].flags = MT_WED_Q_TXFREE; 763 620 dev->mt76.q_rx[MT_RXQ_BAND2_WA].wed = wed_hif2; 764 621 } ··· 773 630 } else if (mt7996_band_valid(dev, MT_BAND1)) { 774 631 /* rx data queue for mt7992 band1 */ 775 632 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs; 633 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 634 + dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(1); 635 + dev->mt76.q_rx[MT_RXQ_BAND1].wed = wed; 636 + } 637 + 776 638 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1], 777 639 MT_RXQ_ID(MT_RXQ_BAND1), 778 640 MT7996_RX_RING_SIZE, ··· 789 641 /* tx free notify event from WA for mt7992 band1 */ 790 642 if (mt7996_has_wa(dev)) { 791 643 rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs; 644 + if (mtk_wed_device_active(wed_hif2)) { 645 + dev->mt76.q_rx[MT_RXQ_BAND1_WA].flags = 646 + MT_WED_Q_TXFREE; 647 + dev->mt76.q_rx[MT_RXQ_BAND1_WA].wed = wed_hif2; 648 + } 649 + 792 650 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA], 793 651 MT_RXQ_ID(MT_RXQ_BAND1_WA), 794 652 MT7996_RX_MCU_RING_SIZE, ··· 805 651 } 806 652 } 807 653 808 - if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed) && 809 - dev->has_rro) { 654 + if (mt7996_has_hwrro(dev)) { 810 655 /* rx rro data queue for band0 */ 811 656 dev->mt76.q_rx[MT_RXQ_RRO_BAND0].flags = 812 657 MT_WED_RRO_Q_DATA(0) | MT_QFLAG_WED_RRO_EN; 813 - dev->mt76.q_rx[MT_RXQ_RRO_BAND0].wed = wed; 658 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) 659 + dev->mt76.q_rx[MT_RXQ_RRO_BAND0].wed = wed; 814 660 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND0], 815 661 MT_RXQ_ID(MT_RXQ_RRO_BAND0), 816 662 MT7996_RX_RING_SIZE, ··· 819 665 if (ret) 820 666 return ret; 821 667 822 - /* tx free notify event from WA for band0 */ 823 - dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE; 824 - dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed; 668 + if (is_mt7992(&dev->mt76)) { 669 + dev->mt76.q_rx[MT_RXQ_RRO_BAND1].flags = 670 + MT_WED_RRO_Q_DATA(1) | MT_QFLAG_WED_RRO_EN; 671 + if (mtk_wed_device_active(wed) && 672 + mtk_wed_get_rx_capa(wed)) 673 + dev->mt76.q_rx[MT_RXQ_RRO_BAND1].wed = wed; 674 + ret = mt76_queue_alloc(dev, 675 + &dev->mt76.q_rx[MT_RXQ_RRO_BAND1], 676 + MT_RXQ_ID(MT_RXQ_RRO_BAND1), 677 + MT7996_RX_RING_SIZE, 678 + MT7996_RX_BUF_SIZE, 679 + MT_RXQ_RING_BASE(MT_RXQ_RRO_BAND1) + hif1_ofs); 680 + if (ret) 681 + return ret; 682 + } else { 683 + if (mtk_wed_device_active(wed)) { 684 + /* tx free notify event from WA for band0 */ 685 + dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE; 686 + dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed; 687 + } 825 688 826 - ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0], 827 - MT_RXQ_ID(MT_RXQ_TXFREE_BAND0), 828 - MT7996_RX_MCU_RING_SIZE, 829 - MT7996_RX_BUF_SIZE, 830 - MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND0)); 831 - if (ret) 832 - return ret; 689 + ret = mt76_queue_alloc(dev, 690 + &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0], 691 + MT_RXQ_ID(MT_RXQ_TXFREE_BAND0), 692 + MT7996_RX_MCU_RING_SIZE, 693 + MT7996_RX_BUF_SIZE, 694 + MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND0)); 695 + if (ret) 696 + return ret; 697 + } 833 698 834 699 if (mt7996_band_valid(dev, MT_BAND2)) { 835 700 /* rx rro data queue for band2 */ 836 701 dev->mt76.q_rx[MT_RXQ_RRO_BAND2].flags = 837 702 MT_WED_RRO_Q_DATA(1) | MT_QFLAG_WED_RRO_EN; 838 - dev->mt76.q_rx[MT_RXQ_RRO_BAND2].wed = wed; 703 + if (mtk_wed_device_active(wed) && 704 + mtk_wed_get_rx_capa(wed)) 705 + dev->mt76.q_rx[MT_RXQ_RRO_BAND2].wed = wed; 839 706 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND2], 840 707 MT_RXQ_ID(MT_RXQ_RRO_BAND2), 841 708 MT7996_RX_RING_SIZE, ··· 927 752 928 753 mt76_tx_status_check(&dev->mt76, true); 929 754 755 + if (mt7996_has_hwrro(dev) && 756 + !mtk_wed_device_active(&dev->mt76.mmio.wed)) 757 + mt7996_rro_msdu_page_map_free(dev); 758 + 930 759 /* reset wfsys */ 931 760 if (force) 932 761 mt7996_wfsys_reset(dev); ··· 954 775 } 955 776 956 777 for (i = 0; i < __MT_MCUQ_MAX; i++) 957 - mt76_queue_reset(dev, dev->mt76.q_mcu[i]); 778 + mt76_queue_reset(dev, dev->mt76.q_mcu[i], true); 958 779 959 780 mt76_for_each_q_rx(&dev->mt76, i) { 960 - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 961 - if (mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]) || 962 - mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i])) 963 - continue; 781 + struct mt76_queue *q = &dev->mt76.q_rx[i]; 964 782 965 - mt76_queue_reset(dev, &dev->mt76.q_rx[i]); 783 + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 784 + if (mt76_queue_is_wed_rro(q) || 785 + mt76_queue_is_wed_tx_free(q)) { 786 + if (force && mt76_queue_is_wed_rro_data(q)) 787 + mt76_queue_reset(dev, q, false); 788 + continue; 789 + } 790 + } 791 + mt76_queue_reset(dev, q, true); 966 792 } 967 793 968 794 mt76_tx_status_check(&dev->mt76, true); 969 795 970 - mt76_for_each_q_rx(&dev->mt76, i) 796 + mt76_for_each_q_rx(&dev->mt76, i) { 797 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && force && 798 + (mt76_queue_is_wed_rro_ind(&dev->mt76.q_rx[i]) || 799 + mt76_queue_is_wed_rro_msdu_pg(&dev->mt76.q_rx[i]))) 800 + continue; 801 + 971 802 mt76_queue_rx_reset(dev, i); 803 + } 972 804 973 805 mt7996_dma_enable(dev, !force); 974 806 }

+1 -2

drivers/net/wireless/mediatek/mt76/mt7996/eeprom.c

··· 334 334 return ret; 335 335 336 336 memcpy(dev->mphy.macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, ETH_ALEN); 337 - mt76_eeprom_override(&dev->mphy); 338 337 339 - return 0; 338 + return mt76_eeprom_override(&dev->mphy); 340 339 } 341 340 342 341 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,

+262 -96

drivers/net/wireless/mediatek/mt76/mt7996/init.c

··· 63 63 .beacon_int_min_gcd = 100, 64 64 }; 65 65 66 + static const u8 if_types_ext_capa_ap[] = { 67 + [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 68 + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 69 + [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 70 + }; 71 + 72 + static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 73 + { 74 + .iftype = NL80211_IFTYPE_AP, 75 + .extended_capabilities = if_types_ext_capa_ap, 76 + .extended_capabilities_mask = if_types_ext_capa_ap, 77 + .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 78 + .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 79 + .mld_capa_and_ops = 80 + FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 81 + MT7996_MAX_RADIOS - 1), 82 + }, { 83 + .iftype = NL80211_IFTYPE_STATION, 84 + .extended_capabilities = if_types_ext_capa_ap, 85 + .extended_capabilities_mask = if_types_ext_capa_ap, 86 + .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 87 + .mld_capa_and_ops = 88 + FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 89 + MT7996_MAX_RADIOS - 1), 90 + }, 91 + }; 92 + 66 93 static ssize_t mt7996_thermal_temp_show(struct device *dev, 67 94 struct device_attribute *attr, 68 95 char *buf) ··· 410 383 411 384 phy->slottime = 9; 412 385 phy->beacon_rate = -1; 386 + phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 413 387 414 388 if (phy->mt76->cap.has_2ghz) { 415 389 phy->mt76->sband_2g.sband.ht_cap.cap |= ··· 491 463 wiphy->radio = dev->radios; 492 464 493 465 wiphy->reg_notifier = mt7996_regd_notifier; 494 - wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 466 + wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 467 + WIPHY_FLAG_SUPPORTS_MLO; 495 468 wiphy->mbssid_max_interfaces = 16; 469 + wiphy->iftype_ext_capab = iftypes_ext_capa; 470 + wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 496 471 497 472 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 498 473 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); ··· 606 575 } 607 576 608 577 /* rro module init */ 609 - if (is_mt7996(&dev->mt76)) 610 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 611 - else 578 + if (dev->hif2) 612 579 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 613 - dev->hif2 ? 7 : 0); 580 + is_mt7996(&dev->mt76) ? 2 : 7); 581 + else 582 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 614 583 615 - if (dev->has_rro) { 584 + if (mt7996_has_hwrro(dev)) { 616 585 u16 timeout; 617 586 618 587 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 619 588 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 620 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 621 - mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 589 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 590 + is_mt7996(&dev->mt76) ? 1 : 2); 591 + mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 592 + !is_mt7996(&dev->mt76)); 622 593 } else { 623 594 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 624 595 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); ··· 667 634 if (!mt7996_band_valid(dev, band)) 668 635 return 0; 669 636 670 - if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 637 + if (dev->hif2 && 638 + ((is_mt7996(&dev->mt76) && band == MT_BAND2) || 639 + (is_mt7992(&dev->mt76) && band == MT_BAND1))) { 671 640 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 672 641 wed = &dev->mt76.mmio.wed_hif2; 673 642 } ··· 702 667 if (band == MT_BAND2) 703 668 mphy->macaddr[0] ^= BIT(6); 704 669 } 705 - mt76_eeprom_override(mphy); 670 + ret = mt76_eeprom_override(mphy); 671 + if (ret) 672 + goto error; 706 673 707 674 /* init wiphy according to mphy and phy */ 708 675 mt7996_init_wiphy_band(mphy->hw, phy); 709 - ret = mt7996_init_tx_queues(mphy->priv, 710 - MT_TXQ_ID(band), 711 - MT7996_TX_RING_SIZE, 712 - MT_TXQ_RING_BASE(band) + hif1_ofs, 713 - wed); 714 - if (ret) 715 - goto error; 676 + 677 + if (is_mt7996(&dev->mt76) && !dev->hif2 && band == MT_BAND1) { 678 + int i; 679 + 680 + for (i = 0; i <= MT_TXQ_PSD; i++) 681 + mphy->q_tx[i] = dev->mt76.phys[MT_BAND0]->q_tx[0]; 682 + } else { 683 + ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), 684 + MT7996_TX_RING_SIZE, 685 + MT_TXQ_RING_BASE(band) + hif1_ofs, 686 + wed); 687 + if (ret) 688 + goto error; 689 + } 716 690 717 691 ret = mt76_register_phy(mphy, true, mt76_rates, 718 692 ARRAY_SIZE(mt76_rates)); ··· 729 685 goto error; 730 686 731 687 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 732 - u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 733 - 734 - mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 735 - mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 688 + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 689 + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 690 + MT_INT_TX_RX_DONE_EXT); 736 691 } 737 692 738 693 return 0; ··· 767 724 msleep(20); 768 725 } 769 726 727 + static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 728 + { 729 + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 730 + u32 session_id; 731 + 732 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 733 + return; 734 + 735 + #ifdef CONFIG_NET_MEDIATEK_SOC_WED 736 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 737 + wed->wlan.ind_cmd.win_size = 738 + ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 739 + if (is_mt7996(&dev->mt76)) 740 + wed->wlan.ind_cmd.particular_sid = 741 + MT7996_RRO_MAX_SESSION; 742 + else 743 + wed->wlan.ind_cmd.particular_sid = 1; 744 + wed->wlan.ind_cmd.particular_se_phys = 745 + dev->wed_rro.session.phy_addr; 746 + wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 747 + wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 748 + } 749 + #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 750 + 751 + if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 752 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 753 + mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 754 + MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 755 + } else { 756 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 757 + mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 758 + } 759 + 760 + /* particular session configure */ 761 + /* use max session idx + 1 as particular session id */ 762 + mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 763 + 764 + session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 765 + mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 766 + MT_RRO_PARTICULAR_CONFG_EN | 767 + FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 768 + } 769 + 770 + void mt7996_rro_hw_init(struct mt7996_dev *dev) 771 + { 772 + u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 773 + int i; 774 + 775 + if (!mt7996_has_hwrro(dev)) 776 + return; 777 + 778 + INIT_LIST_HEAD(&dev->wed_rro.page_cache); 779 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 780 + INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 781 + 782 + if (!is_mt7996(&dev->mt76)) { 783 + reg = MT_RRO_MSDU_PG_SEG_ADDR0; 784 + 785 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 786 + mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 787 + MT_RRO_3_0_EMU_CONF_EN_MASK); 788 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 789 + MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 790 + if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) { 791 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 792 + MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 793 + MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 794 + mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 795 + dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 796 + mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 797 + dev->wed_rro.emi_rings_dma.phy_addr >> 4); 798 + } 799 + } else { 800 + /* set emul 3.0 function */ 801 + mt76_wr(dev, MT_RRO_3_0_EMU_CONF, 802 + MT_RRO_3_0_EMU_CONF_EN_MASK); 803 + 804 + mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 805 + dev->wed_rro.addr_elem[0].phy_addr); 806 + } 807 + 808 + mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 809 + MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 810 + 811 + /* setup Msdu page address */ 812 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 813 + mt76_wr(dev, reg, 814 + dev->wed_rro.msdu_pg[i].phy_addr >> 4); 815 + reg += 4; 816 + } 817 + } else { 818 + /* TODO: remove line after WM has set */ 819 + mt76_clear(dev, WF_RRO_AXI_MST_CFG, 820 + WF_RRO_AXI_MST_CFG_DIDX_OK); 821 + 822 + /* setup BA bitmap cache address */ 823 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 824 + dev->wed_rro.ba_bitmap[0].phy_addr); 825 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 826 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 827 + dev->wed_rro.ba_bitmap[1].phy_addr); 828 + mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 829 + 830 + /* Setup Address element address */ 831 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 832 + mt76_wr(dev, reg, 833 + dev->wed_rro.addr_elem[i].phy_addr >> 4); 834 + reg += 4; 835 + } 836 + 837 + /* Setup Address element address - separate address segment 838 + * mode. 839 + */ 840 + mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 841 + MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 842 + } 843 + 844 + mt7996_rro_hw_init_v3(dev); 845 + 846 + /* interrupt enable */ 847 + mt76_wr(dev, MT_RRO_HOST_INT_ENA, 848 + MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 849 + } 850 + 770 851 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 771 852 { 772 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 773 - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 774 - u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 853 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 775 854 struct mt7996_wed_rro_addr *addr; 776 855 void *ptr; 777 856 int i; 778 857 779 - if (!dev->has_rro) 858 + if (!mt7996_has_hwrro(dev)) 780 859 return 0; 781 860 782 - if (!mtk_wed_device_active(wed)) 783 - return 0; 861 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 862 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 863 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 864 + MT7996_RRO_BA_BITMAP_CR_SIZE, 865 + &dev->wed_rro.ba_bitmap[i].phy_addr, 866 + GFP_KERNEL); 867 + if (!ptr) 868 + return -ENOMEM; 784 869 785 - for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 786 - ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 787 - MT7996_RRO_BA_BITMAP_CR_SIZE, 788 - &dev->wed_rro.ba_bitmap[i].phy_addr, 789 - GFP_KERNEL); 790 - if (!ptr) 791 - return -ENOMEM; 792 - 793 - dev->wed_rro.ba_bitmap[i].ptr = ptr; 870 + dev->wed_rro.ba_bitmap[i].ptr = ptr; 871 + } 794 872 } 795 873 796 874 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { ··· 930 766 931 767 addr = dev->wed_rro.addr_elem[i].ptr; 932 768 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 933 - addr->signature = 0xff; 769 + addr->data = cpu_to_le32(val); 934 770 addr++; 935 771 } 936 772 937 - wed->wlan.ind_cmd.addr_elem_phys[i] = 938 - dev->wed_rro.addr_elem[i].phy_addr; 773 + #ifdef CONFIG_NET_MEDIATEK_SOC_WED 774 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 775 + mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 776 + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 777 + 778 + wed->wlan.ind_cmd.addr_elem_phys[i] = 779 + dev->wed_rro.addr_elem[i].phy_addr; 780 + } 781 + #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 782 + } 783 + 784 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 785 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 786 + MT7996_RRO_MSDU_PG_SIZE_PER_CR, 787 + &dev->wed_rro.msdu_pg[i].phy_addr, 788 + GFP_KERNEL); 789 + if (!ptr) 790 + return -ENOMEM; 791 + 792 + dev->wed_rro.msdu_pg[i].ptr = ptr; 793 + 794 + memset(dev->wed_rro.msdu_pg[i].ptr, 0, 795 + MT7996_RRO_MSDU_PG_SIZE_PER_CR); 796 + } 797 + 798 + if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 799 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 800 + sizeof(dev->wed_rro.emi_rings_cpu.ptr), 801 + &dev->wed_rro.emi_rings_cpu.phy_addr, 802 + GFP_KERNEL); 803 + if (!ptr) 804 + return -ENOMEM; 805 + 806 + dev->wed_rro.emi_rings_cpu.ptr = ptr; 807 + 808 + ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 809 + sizeof(dev->wed_rro.emi_rings_dma.ptr), 810 + &dev->wed_rro.emi_rings_dma.phy_addr, 811 + GFP_KERNEL); 812 + if (!ptr) 813 + return -ENOMEM; 814 + 815 + dev->wed_rro.emi_rings_dma.ptr = ptr; 939 816 } 940 817 941 818 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, ··· 989 784 dev->wed_rro.session.ptr = ptr; 990 785 addr = dev->wed_rro.session.ptr; 991 786 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 992 - addr->signature = 0xff; 787 + addr->data = cpu_to_le32(val); 993 788 addr++; 994 789 } 995 790 996 - /* rro hw init */ 997 - /* TODO: remove line after WM has set */ 998 - mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 791 + mt7996_rro_hw_init(dev); 999 792 1000 - /* setup BA bitmap cache address */ 1001 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 1002 - dev->wed_rro.ba_bitmap[0].phy_addr); 1003 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 1004 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 1005 - dev->wed_rro.ba_bitmap[1].phy_addr); 1006 - mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 1007 - 1008 - /* setup Address element address */ 1009 - for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1010 - mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 1011 - reg += 4; 1012 - } 1013 - 1014 - /* setup Address element address - separate address segment mode */ 1015 - mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 1016 - MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 1017 - 1018 - wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 1019 - wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 1020 - wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 1021 - wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 1022 - wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 1023 - 1024 - mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 1025 - mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 1026 - MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 1027 - 1028 - /* particular session configure */ 1029 - /* use max session idx + 1 as particular session id */ 1030 - mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 1031 - mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 1032 - MT_RRO_PARTICULAR_CONFG_EN | 1033 - FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 1034 - 1035 - /* interrupt enable */ 1036 - mt76_wr(dev, MT_RRO_HOST_INT_ENA, 1037 - MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 1038 - 1039 - /* rro ind cmd queue init */ 1040 793 return mt7996_dma_rro_init(dev); 1041 - #else 1042 - return 0; 1043 - #endif 1044 794 } 1045 795 1046 796 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1047 797 { 1048 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1049 798 int i; 1050 799 1051 - if (!dev->has_rro) 1052 - return; 1053 - 1054 - if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 800 + if (!mt7996_has_hwrro(dev)) 1055 801 return; 1056 802 1057 803 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { ··· 1026 870 dev->wed_rro.addr_elem[i].phy_addr); 1027 871 } 1028 872 873 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 874 + if (!dev->wed_rro.msdu_pg[i].ptr) 875 + continue; 876 + 877 + dmam_free_coherent(dev->mt76.dma_dev, 878 + MT7996_RRO_MSDU_PG_SIZE_PER_CR, 879 + dev->wed_rro.msdu_pg[i].ptr, 880 + dev->wed_rro.msdu_pg[i].phy_addr); 881 + } 882 + 1029 883 if (!dev->wed_rro.session.ptr) 1030 884 return; 1031 885 ··· 1044 878 sizeof(struct mt7996_wed_rro_addr), 1045 879 dev->wed_rro.session.ptr, 1046 880 dev->wed_rro.session.phy_addr); 1047 - #endif 1048 881 } 1049 882 1050 883 static void mt7996_wed_rro_work(struct work_struct *work) 1051 884 { 1052 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 885 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1053 886 struct mt7996_dev *dev; 1054 887 LIST_HEAD(list); 1055 888 ··· 1085 920 MT7996_RRO_WINDOW_MAX_LEN; 1086 921 reset: 1087 922 elem = ptr + elem_id * sizeof(*elem); 1088 - elem->signature = 0xff; 923 + elem->data |= cpu_to_le32(val); 1089 924 } 1090 925 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1091 926 out: 1092 927 kfree(e); 1093 928 } 1094 - #endif 1095 929 } 1096 930 1097 931 static int mt7996_variant_type_init(struct mt7996_dev *dev) ··· 1485 1321 eht_cap->has_eht = true; 1486 1322 1487 1323 eht_cap_elem->mac_cap_info[0] = 1488 - IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1489 1324 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1490 1325 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1491 1326 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); ··· 1714 1551 mt7996_mcu_exit(dev); 1715 1552 mt7996_tx_token_put(dev); 1716 1553 mt7996_dma_cleanup(dev); 1554 + if (mt7996_has_hwrro(dev) && 1555 + !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1556 + mt7996_rro_msdu_page_map_free(dev); 1717 1557 tasklet_disable(&dev->mt76.irq_tasklet); 1718 1558 1719 1559 mt76_free_device(&dev->mt76);

+643 -156

drivers/net/wireless/mediatek/mt76/mt7996/mac.c

··· 229 229 { 230 230 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 231 231 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 232 - struct mt7996_sta *msta = (struct mt7996_sta *)status->wcid; 232 + struct mt7996_sta_link *msta_link = (void *)status->wcid; 233 + struct mt7996_sta *msta = msta_link->sta; 234 + struct ieee80211_bss_conf *link_conf; 233 235 __le32 *rxd = (__le32 *)skb->data; 234 236 struct ieee80211_sta *sta; 235 237 struct ieee80211_vif *vif; ··· 248 246 if (!msta || !msta->vif) 249 247 return -EINVAL; 250 248 251 - sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 249 + sta = wcid_to_sta(status->wcid); 252 250 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 251 + link_conf = rcu_dereference(vif->link_conf[msta_link->wcid.link_id]); 252 + if (!link_conf) 253 + return -EINVAL; 253 254 254 255 /* store the info from RXD and ethhdr to avoid being overridden */ 255 256 frame_control = le32_get_bits(rxd[8], MT_RXD8_FRAME_CONTROL); ··· 265 260 switch (frame_control & (IEEE80211_FCTL_TODS | 266 261 IEEE80211_FCTL_FROMDS)) { 267 262 case 0: 268 - ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 263 + ether_addr_copy(hdr.addr3, link_conf->bssid); 269 264 break; 270 265 case IEEE80211_FCTL_FROMDS: 271 266 ether_addr_copy(hdr.addr3, eth_hdr->h_source); ··· 802 797 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) { 803 798 if (is_mt7990(&dev->mt76)) 804 799 txwi[6] |= cpu_to_le32(FIELD_PREP(MT_TXD6_TID_ADDBA, tid)); 800 + else 801 + txwi[7] |= cpu_to_le32(MT_TXD7_MAC_TXD); 802 + 805 803 tid = MT_TX_ADDBA; 806 804 } else if (ieee80211_is_mgmt(hdr->frame_control)) { 807 805 tid = MT_TX_NORMAL; ··· 968 960 val |= MT_TXD5_TX_STATUS_HOST; 969 961 txwi[5] = cpu_to_le32(val); 970 962 971 - val = MT_TXD6_DAS; 972 - if (q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) 963 + val = MT_TXD6_DAS | MT_TXD6_VTA; 964 + if ((q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0) || 965 + skb->protocol == cpu_to_be16(ETH_P_PAE)) 973 966 val |= MT_TXD6_DIS_MAT; 974 967 975 968 if (is_mt7996(&dev->mt76)) ··· 1038 1029 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1039 1030 struct ieee80211_key_conf *key = info->control.hw_key; 1040 1031 struct ieee80211_vif *vif = info->control.vif; 1041 - struct mt76_connac_txp_common *txp; 1042 1032 struct mt76_txwi_cache *t; 1043 1033 int id, i, pid, nbuf = tx_info->nbuf - 1; 1044 1034 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; 1035 + __le32 *ptr = (__le32 *)txwi_ptr; 1045 1036 u8 *txwi = (u8 *)txwi_ptr; 1046 1037 1047 1038 if (unlikely(tx_info->skb->len <= ETH_HLEN)) ··· 1057 1048 if (id < 0) 1058 1049 return id; 1059 1050 1051 + /* Since the rules of HW MLD address translation are not fully 1052 + * compatible with 802.11 EAPOL frame, we do the translation by 1053 + * software 1054 + */ 1055 + if (tx_info->skb->protocol == cpu_to_be16(ETH_P_PAE) && sta->mlo) { 1056 + struct ieee80211_hdr *hdr = (void *)tx_info->skb->data; 1057 + struct ieee80211_bss_conf *link_conf; 1058 + struct ieee80211_link_sta *link_sta; 1059 + 1060 + link_conf = rcu_dereference(vif->link_conf[wcid->link_id]); 1061 + if (!link_conf) 1062 + return -EINVAL; 1063 + 1064 + link_sta = rcu_dereference(sta->link[wcid->link_id]); 1065 + if (!link_sta) 1066 + return -EINVAL; 1067 + 1068 + dma_sync_single_for_cpu(mdev->dma_dev, tx_info->buf[1].addr, 1069 + tx_info->buf[1].len, DMA_TO_DEVICE); 1070 + 1071 + memcpy(hdr->addr1, link_sta->addr, ETH_ALEN); 1072 + memcpy(hdr->addr2, link_conf->addr, ETH_ALEN); 1073 + if (ieee80211_has_a4(hdr->frame_control)) { 1074 + memcpy(hdr->addr3, sta->addr, ETH_ALEN); 1075 + memcpy(hdr->addr4, vif->addr, ETH_ALEN); 1076 + } else if (ieee80211_has_tods(hdr->frame_control)) { 1077 + memcpy(hdr->addr3, sta->addr, ETH_ALEN); 1078 + } else if (ieee80211_has_fromds(hdr->frame_control)) { 1079 + memcpy(hdr->addr3, vif->addr, ETH_ALEN); 1080 + } 1081 + 1082 + dma_sync_single_for_device(mdev->dma_dev, tx_info->buf[1].addr, 1083 + tx_info->buf[1].len, DMA_TO_DEVICE); 1084 + } 1085 + 1060 1086 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1061 1087 memset(txwi_ptr, 0, MT_TXD_SIZE); 1062 1088 /* Transmit non qos data by 802.11 header and need to fill txd by host*/ ··· 1099 1055 mt7996_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key, 1100 1056 pid, qid, 0); 1101 1057 1102 - txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1103 - for (i = 0; i < nbuf; i++) { 1104 - u16 len; 1058 + /* MT7996 and MT7992 require driver to provide the MAC TXP for AddBA 1059 + * req 1060 + */ 1061 + if (le32_to_cpu(ptr[7]) & MT_TXD7_MAC_TXD) { 1062 + u32 val; 1105 1063 1106 - len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1064 + ptr = (__le32 *)(txwi + MT_TXD_SIZE); 1065 + memset((void *)ptr, 0, sizeof(struct mt76_connac_fw_txp)); 1066 + 1067 + val = FIELD_PREP(MT_TXP0_TOKEN_ID0, id) | 1068 + MT_TXP0_TOKEN_ID0_VALID_MASK; 1069 + ptr[0] = cpu_to_le32(val); 1070 + 1071 + val = FIELD_PREP(MT_TXP1_TID_ADDBA, 1072 + tx_info->skb->priority & 1073 + IEEE80211_QOS_CTL_TID_MASK); 1074 + ptr[1] = cpu_to_le32(val); 1075 + ptr[2] = cpu_to_le32(tx_info->buf[1].addr & 0xFFFFFFFF); 1076 + 1077 + val = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[1].len) | 1078 + MT_TXP3_ML0_MASK; 1107 1079 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1108 - len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1109 - tx_info->buf[i + 1].addr >> 32); 1080 + val |= FIELD_PREP(MT_TXP3_DMA_ADDR_H, 1081 + tx_info->buf[1].addr >> 32); 1082 + #endif 1083 + ptr[3] = cpu_to_le32(val); 1084 + } else { 1085 + struct mt76_connac_txp_common *txp; 1086 + 1087 + txp = (struct mt76_connac_txp_common *)(txwi + MT_TXD_SIZE); 1088 + for (i = 0; i < nbuf; i++) { 1089 + u16 len; 1090 + 1091 + len = FIELD_PREP(MT_TXP_BUF_LEN, tx_info->buf[i + 1].len); 1092 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1093 + len |= FIELD_PREP(MT_TXP_DMA_ADDR_H, 1094 + tx_info->buf[i + 1].addr >> 32); 1110 1095 #endif 1111 1096 1112 - txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1113 - txp->fw.len[i] = cpu_to_le16(len); 1097 + txp->fw.buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 1098 + txp->fw.len[i] = cpu_to_le16(len); 1099 + } 1100 + txp->fw.nbuf = nbuf; 1101 + 1102 + txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1103 + 1104 + if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1105 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1106 + 1107 + if (!key) 1108 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1109 + 1110 + if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb)) 1111 + txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1112 + 1113 + if (vif) { 1114 + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1115 + struct mt76_vif_link *mlink = NULL; 1116 + 1117 + if (wcid->offchannel) 1118 + mlink = rcu_dereference(mvif->mt76.offchannel_link); 1119 + if (!mlink) 1120 + mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]); 1121 + 1122 + txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx; 1123 + } 1124 + 1125 + txp->fw.token = cpu_to_le16(id); 1126 + txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1114 1127 } 1115 - txp->fw.nbuf = nbuf; 1116 - 1117 - txp->fw.flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); 1118 - 1119 - if (!is_8023 || pid >= MT_PACKET_ID_FIRST) 1120 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); 1121 - 1122 - if (!key) 1123 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 1124 - 1125 - if (!is_8023 && mt7996_tx_use_mgmt(dev, tx_info->skb)) 1126 - txp->fw.flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 1127 - 1128 - if (vif) { 1129 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 1130 - struct mt76_vif_link *mlink = NULL; 1131 - 1132 - if (wcid->offchannel) 1133 - mlink = rcu_dereference(mvif->mt76.offchannel_link); 1134 - if (!mlink) 1135 - mlink = rcu_dereference(mvif->mt76.link[wcid->link_id]); 1136 - 1137 - txp->fw.bss_idx = mlink ? mlink->idx : mvif->deflink.mt76.idx; 1138 - } 1139 - 1140 - txp->fw.token = cpu_to_le16(id); 1141 - txp->fw.rept_wds_wcid = cpu_to_le16(sta ? wcid->idx : 0xfff); 1142 1128 1143 1129 tx_info->skb = NULL; 1144 1130 ··· 1257 1183 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); 1258 1184 if (link_sta) { 1259 1185 wcid_idx = wcid->idx; 1260 - if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) 1261 - mt7996_tx_check_aggr(link_sta, wcid, t->skb); 1186 + if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) { 1187 + struct mt7996_sta *msta; 1188 + 1189 + /* AMPDU state is stored in the primary link */ 1190 + msta = (void *)link_sta->sta->drv_priv; 1191 + mt7996_tx_check_aggr(link_sta, &msta->deflink.wcid, 1192 + t->skb); 1193 + } 1262 1194 } else { 1263 1195 wcid_idx = le32_get_bits(txwi[9], MT_TXD9_WLAN_IDX); 1264 1196 } ··· 1322 1242 info = le32_to_cpu(*cur_info); 1323 1243 if (info & MT_TXFREE_INFO_PAIR) { 1324 1244 struct ieee80211_sta *sta; 1245 + unsigned long valid_links; 1246 + struct mt7996_sta *msta; 1247 + unsigned int id; 1325 1248 u16 idx; 1326 1249 1327 1250 idx = FIELD_GET(MT_TXFREE_INFO_WLAN_ID, info); ··· 1339 1256 if (!link_sta) 1340 1257 goto next; 1341 1258 1342 - mt76_wcid_add_poll(&dev->mt76, wcid); 1259 + msta = (struct mt7996_sta *)sta->drv_priv; 1260 + valid_links = sta->valid_links ?: BIT(0); 1261 + 1262 + /* For MLD STA, add all link's wcid to sta_poll_list */ 1263 + for_each_set_bit(id, &valid_links, 1264 + IEEE80211_MLD_MAX_NUM_LINKS) { 1265 + struct mt7996_sta_link *msta_link; 1266 + 1267 + msta_link = rcu_dereference(msta->link[id]); 1268 + if (!msta_link) 1269 + continue; 1270 + 1271 + mt76_wcid_add_poll(&dev->mt76, 1272 + &msta_link->wcid); 1273 + } 1343 1274 next: 1344 1275 /* ver 7 has a new DW with pair = 1, skip it */ 1345 1276 if (ver == 7 && ((void *)(cur_info + 1) < end) && ··· 1671 1574 } 1672 1575 } 1673 1576 1577 + static struct mt7996_msdu_page * 1578 + mt7996_msdu_page_get_from_cache(struct mt7996_dev *dev) 1579 + { 1580 + struct mt7996_msdu_page *p = NULL; 1581 + 1582 + spin_lock(&dev->wed_rro.lock); 1583 + 1584 + if (!list_empty(&dev->wed_rro.page_cache)) { 1585 + p = list_first_entry(&dev->wed_rro.page_cache, 1586 + struct mt7996_msdu_page, list); 1587 + if (p) 1588 + list_del(&p->list); 1589 + } 1590 + 1591 + spin_unlock(&dev->wed_rro.lock); 1592 + 1593 + return p; 1594 + } 1595 + 1596 + static struct mt7996_msdu_page *mt7996_msdu_page_get(struct mt7996_dev *dev) 1597 + { 1598 + struct mt7996_msdu_page *p; 1599 + 1600 + p = mt7996_msdu_page_get_from_cache(dev); 1601 + if (!p) { 1602 + p = kzalloc(L1_CACHE_ALIGN(sizeof(*p)), GFP_ATOMIC); 1603 + if (p) 1604 + INIT_LIST_HEAD(&p->list); 1605 + } 1606 + 1607 + return p; 1608 + } 1609 + 1610 + static void mt7996_msdu_page_put_to_cache(struct mt7996_dev *dev, 1611 + struct mt7996_msdu_page *p) 1612 + { 1613 + if (p->buf) { 1614 + mt76_put_page_pool_buf(p->buf, false); 1615 + p->buf = NULL; 1616 + } 1617 + 1618 + spin_lock(&dev->wed_rro.lock); 1619 + list_add(&p->list, &dev->wed_rro.page_cache); 1620 + spin_unlock(&dev->wed_rro.lock); 1621 + } 1622 + 1623 + static void mt7996_msdu_page_free_cache(struct mt7996_dev *dev) 1624 + { 1625 + while (true) { 1626 + struct mt7996_msdu_page *p; 1627 + 1628 + p = mt7996_msdu_page_get_from_cache(dev); 1629 + if (!p) 1630 + break; 1631 + 1632 + if (p->buf) 1633 + mt76_put_page_pool_buf(p->buf, false); 1634 + 1635 + kfree(p); 1636 + } 1637 + } 1638 + 1639 + static u32 mt7996_msdu_page_hash_from_addr(dma_addr_t dma_addr) 1640 + { 1641 + u32 val = 0; 1642 + int i = 0; 1643 + 1644 + while (dma_addr) { 1645 + val += (u32)((dma_addr & 0xff) + i) % MT7996_RRO_MSDU_PG_HASH_SIZE; 1646 + dma_addr >>= 8; 1647 + i += 13; 1648 + } 1649 + 1650 + return val % MT7996_RRO_MSDU_PG_HASH_SIZE; 1651 + } 1652 + 1653 + static struct mt7996_msdu_page * 1654 + mt7996_rro_msdu_page_get(struct mt7996_dev *dev, dma_addr_t dma_addr) 1655 + { 1656 + u32 hash = mt7996_msdu_page_hash_from_addr(dma_addr); 1657 + struct mt7996_msdu_page *p, *tmp, *addr = NULL; 1658 + 1659 + spin_lock(&dev->wed_rro.lock); 1660 + 1661 + list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[hash], 1662 + list) { 1663 + if (p->dma_addr == dma_addr) { 1664 + list_del(&p->list); 1665 + addr = p; 1666 + break; 1667 + } 1668 + } 1669 + 1670 + spin_unlock(&dev->wed_rro.lock); 1671 + 1672 + return addr; 1673 + } 1674 + 1675 + static void mt7996_rx_token_put(struct mt7996_dev *dev) 1676 + { 1677 + int i; 1678 + 1679 + for (i = 0; i < dev->mt76.rx_token_size; i++) { 1680 + struct mt76_txwi_cache *t; 1681 + 1682 + t = mt76_rx_token_release(&dev->mt76, i); 1683 + if (!t || !t->ptr) 1684 + continue; 1685 + 1686 + mt76_put_page_pool_buf(t->ptr, false); 1687 + t->dma_addr = 0; 1688 + t->ptr = NULL; 1689 + 1690 + mt76_put_rxwi(&dev->mt76, t); 1691 + } 1692 + } 1693 + 1694 + void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev) 1695 + { 1696 + struct mt7996_msdu_page *p, *tmp; 1697 + int i; 1698 + 1699 + local_bh_disable(); 1700 + 1701 + for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) { 1702 + list_for_each_entry_safe(p, tmp, &dev->wed_rro.page_map[i], 1703 + list) { 1704 + list_del_init(&p->list); 1705 + if (p->buf) 1706 + mt76_put_page_pool_buf(p->buf, false); 1707 + kfree(p); 1708 + } 1709 + } 1710 + mt7996_msdu_page_free_cache(dev); 1711 + 1712 + local_bh_enable(); 1713 + 1714 + mt7996_rx_token_put(dev); 1715 + } 1716 + 1717 + int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 1718 + dma_addr_t dma_addr, void *data) 1719 + { 1720 + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1721 + struct mt7996_msdu_page_info *pinfo = data; 1722 + struct mt7996_msdu_page *p; 1723 + u32 hash; 1724 + 1725 + pinfo->data |= cpu_to_le32(FIELD_PREP(MSDU_PAGE_INFO_OWNER_MASK, 1)); 1726 + p = mt7996_msdu_page_get(dev); 1727 + if (!p) 1728 + return -ENOMEM; 1729 + 1730 + p->buf = data; 1731 + p->dma_addr = dma_addr; 1732 + p->q = q; 1733 + 1734 + hash = mt7996_msdu_page_hash_from_addr(dma_addr); 1735 + 1736 + spin_lock(&dev->wed_rro.lock); 1737 + list_add_tail(&p->list, &dev->wed_rro.page_map[hash]); 1738 + spin_unlock(&dev->wed_rro.lock); 1739 + 1740 + return 0; 1741 + } 1742 + 1743 + static struct mt7996_wed_rro_addr * 1744 + mt7996_rro_addr_elem_get(struct mt7996_dev *dev, u16 session_id, u16 seq_num) 1745 + { 1746 + u32 idx = 0; 1747 + void *addr; 1748 + 1749 + if (session_id == MT7996_RRO_MAX_SESSION) { 1750 + addr = dev->wed_rro.session.ptr; 1751 + } else { 1752 + idx = session_id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1753 + addr = dev->wed_rro.addr_elem[idx].ptr; 1754 + 1755 + idx = session_id % MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1756 + idx = idx * MT7996_RRO_WINDOW_MAX_LEN; 1757 + } 1758 + idx += seq_num % MT7996_RRO_WINDOW_MAX_LEN; 1759 + 1760 + return addr + idx * sizeof(struct mt7996_wed_rro_addr); 1761 + } 1762 + 1763 + #define MT996_RRO_SN_MASK GENMASK(11, 0) 1764 + 1765 + void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data) 1766 + { 1767 + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 1768 + struct mt76_wed_rro_ind *cmd = (struct mt76_wed_rro_ind *)data; 1769 + u32 cmd_data0 = le32_to_cpu(cmd->data0); 1770 + u32 cmd_data1 = le32_to_cpu(cmd->data1); 1771 + u8 ind_reason = FIELD_GET(RRO_IND_DATA0_IND_REASON_MASK, cmd_data0); 1772 + u16 start_seq = FIELD_GET(RRO_IND_DATA0_START_SEQ_MASK, cmd_data0); 1773 + u16 seq_id = FIELD_GET(RRO_IND_DATA0_SEQ_ID_MASK, cmd_data0); 1774 + u16 ind_count = FIELD_GET(RRO_IND_DATA1_IND_COUNT_MASK, cmd_data1); 1775 + struct mt7996_msdu_page_info *pinfo = NULL; 1776 + struct mt7996_msdu_page *p = NULL; 1777 + int i, seq_num = 0; 1778 + 1779 + for (i = 0; i < ind_count; i++) { 1780 + struct mt7996_wed_rro_addr *e; 1781 + struct mt76_rx_status *status; 1782 + struct mt7996_rro_hif *rxd; 1783 + int j, len, qid, data_len; 1784 + struct mt76_txwi_cache *t; 1785 + dma_addr_t dma_addr = 0; 1786 + u16 rx_token_id, count; 1787 + struct mt76_queue *q; 1788 + struct sk_buff *skb; 1789 + u32 info = 0, data; 1790 + u8 signature; 1791 + void *buf; 1792 + bool ls; 1793 + 1794 + seq_num = FIELD_GET(MT996_RRO_SN_MASK, start_seq + i); 1795 + e = mt7996_rro_addr_elem_get(dev, seq_id, seq_num); 1796 + data = le32_to_cpu(e->data); 1797 + signature = FIELD_GET(WED_RRO_ADDR_SIGNATURE_MASK, data); 1798 + if (signature != (seq_num / MT7996_RRO_WINDOW_MAX_LEN)) { 1799 + u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 1800 + 0xff); 1801 + 1802 + e->data |= cpu_to_le32(val); 1803 + goto update_ack_seq_num; 1804 + } 1805 + 1806 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1807 + dma_addr = FIELD_GET(WED_RRO_ADDR_HEAD_HIGH_MASK, data); 1808 + dma_addr <<= 32; 1809 + #endif 1810 + dma_addr |= le32_to_cpu(e->head_low); 1811 + 1812 + count = FIELD_GET(WED_RRO_ADDR_COUNT_MASK, data); 1813 + for (j = 0; j < count; j++) { 1814 + if (!p) { 1815 + p = mt7996_rro_msdu_page_get(dev, dma_addr); 1816 + if (!p) 1817 + continue; 1818 + 1819 + dma_sync_single_for_cpu(mdev->dma_dev, p->dma_addr, 1820 + SKB_WITH_OVERHEAD(p->q->buf_size), 1821 + page_pool_get_dma_dir(p->q->page_pool)); 1822 + pinfo = (struct mt7996_msdu_page_info *)p->buf; 1823 + } 1824 + 1825 + rxd = &pinfo->rxd[j % MT7996_MAX_HIF_RXD_IN_PG]; 1826 + len = FIELD_GET(RRO_HIF_DATA1_SDL_MASK, 1827 + le32_to_cpu(rxd->data1)); 1828 + 1829 + rx_token_id = FIELD_GET(RRO_HIF_DATA4_RX_TOKEN_ID_MASK, 1830 + le32_to_cpu(rxd->data4)); 1831 + t = mt76_rx_token_release(mdev, rx_token_id); 1832 + if (!t) 1833 + goto next_page; 1834 + 1835 + qid = t->qid; 1836 + buf = t->ptr; 1837 + q = &mdev->q_rx[qid]; 1838 + dma_sync_single_for_cpu(mdev->dma_dev, t->dma_addr, 1839 + SKB_WITH_OVERHEAD(q->buf_size), 1840 + page_pool_get_dma_dir(q->page_pool)); 1841 + 1842 + t->dma_addr = 0; 1843 + t->ptr = NULL; 1844 + mt76_put_rxwi(mdev, t); 1845 + if (!buf) 1846 + goto next_page; 1847 + 1848 + if (q->rx_head) 1849 + data_len = q->buf_size; 1850 + else 1851 + data_len = SKB_WITH_OVERHEAD(q->buf_size); 1852 + 1853 + if (data_len < len + q->buf_offset) { 1854 + dev_kfree_skb(q->rx_head); 1855 + mt76_put_page_pool_buf(buf, false); 1856 + q->rx_head = NULL; 1857 + goto next_page; 1858 + } 1859 + 1860 + ls = FIELD_GET(RRO_HIF_DATA1_LS_MASK, 1861 + le32_to_cpu(rxd->data1)); 1862 + if (q->rx_head) { 1863 + /* TODO: Take into account non-linear skb. */ 1864 + mt76_put_page_pool_buf(buf, false); 1865 + if (ls) { 1866 + dev_kfree_skb(q->rx_head); 1867 + q->rx_head = NULL; 1868 + } 1869 + goto next_page; 1870 + } 1871 + 1872 + if (ls && !mt7996_rx_check(mdev, buf, len)) 1873 + goto next_page; 1874 + 1875 + skb = build_skb(buf, q->buf_size); 1876 + if (!skb) 1877 + goto next_page; 1878 + 1879 + skb_reserve(skb, q->buf_offset); 1880 + skb_mark_for_recycle(skb); 1881 + __skb_put(skb, len); 1882 + 1883 + if (ind_reason == 1 || ind_reason == 2) { 1884 + dev_kfree_skb(skb); 1885 + goto next_page; 1886 + } 1887 + 1888 + if (!ls) { 1889 + q->rx_head = skb; 1890 + goto next_page; 1891 + } 1892 + 1893 + status = (struct mt76_rx_status *)skb->cb; 1894 + if (seq_id != MT7996_RRO_MAX_SESSION) 1895 + status->aggr = true; 1896 + 1897 + mt7996_queue_rx_skb(mdev, qid, skb, &info); 1898 + next_page: 1899 + if ((j + 1) % MT7996_MAX_HIF_RXD_IN_PG == 0) { 1900 + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 1901 + dma_addr = 1902 + FIELD_GET(MSDU_PAGE_INFO_PG_HIGH_MASK, 1903 + le32_to_cpu(pinfo->data)); 1904 + dma_addr <<= 32; 1905 + dma_addr |= le32_to_cpu(pinfo->pg_low); 1906 + #else 1907 + dma_addr = le32_to_cpu(pinfo->pg_low); 1908 + #endif 1909 + mt7996_msdu_page_put_to_cache(dev, p); 1910 + p = NULL; 1911 + } 1912 + } 1913 + 1914 + update_ack_seq_num: 1915 + if ((i + 1) % 4 == 0) 1916 + mt76_wr(dev, MT_RRO_ACK_SN_CTRL, 1917 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SESSION_MASK, 1918 + seq_id) | 1919 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SN_MASK, 1920 + seq_num)); 1921 + if (p) { 1922 + mt7996_msdu_page_put_to_cache(dev, p); 1923 + p = NULL; 1924 + } 1925 + } 1926 + 1927 + /* Update ack_seq_num for remaining addr_elem */ 1928 + if (i % 4) 1929 + mt76_wr(dev, MT_RRO_ACK_SN_CTRL, 1930 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SESSION_MASK, seq_id) | 1931 + FIELD_PREP(MT_RRO_ACK_SN_CTRL_SN_MASK, seq_num)); 1932 + } 1933 + 1674 1934 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy) 1675 1935 { 1676 1936 struct mt7996_dev *dev = phy->dev; ··· 2176 1722 if (!link || link->phy != phy) 2177 1723 continue; 2178 1724 2179 - mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf); 1725 + mt7996_mcu_add_beacon(dev->mt76.hw, vif, link_conf, 1726 + link_conf->enable_beacon); 2180 1727 } 2181 1728 } 2182 1729 ··· 2221 1766 static int 2222 1767 mt7996_mac_restart(struct mt7996_dev *dev) 2223 1768 { 2224 - struct mt7996_phy *phy2, *phy3; 2225 1769 struct mt76_dev *mdev = &dev->mt76; 1770 + struct mt7996_phy *phy; 2226 1771 int i, ret; 2227 - 2228 - phy2 = mt7996_phy2(dev); 2229 - phy3 = mt7996_phy3(dev); 2230 1772 2231 1773 if (dev->hif2) { 2232 1774 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); ··· 2236 1784 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 2237 1785 } 2238 1786 2239 - set_bit(MT76_RESET, &dev->mphy.state); 2240 1787 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1788 + mt7996_for_each_phy(dev, phy) 1789 + set_bit(MT76_RESET, &phy->mt76->state); 2241 1790 wake_up(&dev->mt76.mcu.wait); 2242 - if (phy2) 2243 - set_bit(MT76_RESET, &phy2->mt76->state); 2244 - if (phy3) 2245 - set_bit(MT76_RESET, &phy3->mt76->state); 2246 1791 2247 1792 /* lock/unlock all queues to ensure that no tx is pending */ 2248 - mt76_txq_schedule_all(&dev->mphy); 2249 - if (phy2) 2250 - mt76_txq_schedule_all(phy2->mt76); 2251 - if (phy3) 2252 - mt76_txq_schedule_all(phy3->mt76); 1793 + mt7996_for_each_phy(dev, phy) 1794 + mt76_txq_schedule_all(phy->mt76); 2253 1795 2254 1796 /* disable all tx/rx napi */ 2255 1797 mt76_worker_disable(&dev->mt76.tx_worker); ··· 2295 1849 if (ret) 2296 1850 goto out; 2297 1851 1852 + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1853 + mt7996_has_hwrro(dev)) { 1854 + u32 wed_irq_mask = dev->mt76.mmio.irqmask | 1855 + MT_INT_TX_DONE_BAND2; 1856 + 1857 + mt7996_rro_hw_init(dev); 1858 + mt76_for_each_q_rx(&dev->mt76, i) { 1859 + if (mt76_queue_is_wed_rro_ind(&dev->mt76.q_rx[i]) || 1860 + mt76_queue_is_wed_rro_msdu_pg(&dev->mt76.q_rx[i])) 1861 + mt76_queue_rx_reset(dev, i); 1862 + } 1863 + 1864 + mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 1865 + mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 1866 + false); 1867 + mt7996_irq_enable(dev, wed_irq_mask); 1868 + mt7996_irq_disable(dev, 0); 1869 + } 1870 + 1871 + if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) { 1872 + mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, 1873 + MT_INT_TX_RX_DONE_EXT); 1874 + mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 1875 + MT_INT_TX_RX_DONE_EXT); 1876 + } 1877 + 2298 1878 /* set the necessary init items */ 2299 1879 ret = mt7996_mcu_set_eeprom(dev); 2300 1880 if (ret) 2301 1881 goto out; 2302 1882 2303 1883 mt7996_mac_init(dev); 2304 - mt7996_init_txpower(&dev->phy); 2305 - mt7996_init_txpower(phy2); 2306 - mt7996_init_txpower(phy3); 1884 + mt7996_for_each_phy(dev, phy) 1885 + mt7996_init_txpower(phy); 2307 1886 ret = mt7996_txbf_init(dev); 1887 + if (ret) 1888 + goto out; 2308 1889 2309 - if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1890 + mt7996_for_each_phy(dev, phy) { 1891 + if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1892 + continue; 1893 + 2310 1894 ret = mt7996_run(&dev->phy); 2311 - if (ret) 2312 - goto out; 2313 - } 2314 - 2315 - if (phy2 && test_bit(MT76_STATE_RUNNING, &phy2->mt76->state)) { 2316 - ret = mt7996_run(phy2); 2317 - if (ret) 2318 - goto out; 2319 - } 2320 - 2321 - if (phy3 && test_bit(MT76_STATE_RUNNING, &phy3->mt76->state)) { 2322 - ret = mt7996_run(phy3); 2323 1895 if (ret) 2324 1896 goto out; 2325 1897 } 2326 1898 2327 1899 out: 2328 1900 /* reset done */ 2329 - clear_bit(MT76_RESET, &dev->mphy.state); 2330 - if (phy2) 2331 - clear_bit(MT76_RESET, &phy2->mt76->state); 2332 - if (phy3) 2333 - clear_bit(MT76_RESET, &phy3->mt76->state); 1901 + mt7996_for_each_phy(dev, phy) 1902 + clear_bit(MT76_RESET, &phy->mt76->state); 2334 1903 2335 1904 napi_enable(&dev->mt76.tx_napi); 2336 1905 local_bh_disable(); ··· 2357 1896 } 2358 1897 2359 1898 static void 2360 - mt7996_mac_full_reset(struct mt7996_dev *dev) 1899 + mt7996_mac_reset_sta_iter(void *data, struct ieee80211_sta *sta) 2361 1900 { 2362 - struct mt7996_phy *phy2, *phy3; 1901 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1902 + struct mt7996_dev *dev = data; 2363 1903 int i; 2364 1904 2365 - phy2 = mt7996_phy2(dev); 2366 - phy3 = mt7996_phy3(dev); 1905 + for (i = 0; i < ARRAY_SIZE(msta->link); i++) { 1906 + struct mt7996_sta_link *msta_link = NULL; 1907 + 1908 + msta_link = rcu_replace_pointer(msta->link[i], msta_link, 1909 + lockdep_is_held(&dev->mt76.mutex)); 1910 + if (!msta_link) 1911 + continue; 1912 + 1913 + mt7996_mac_sta_deinit_link(dev, msta_link); 1914 + 1915 + if (msta->deflink_id == i) { 1916 + msta->deflink_id = IEEE80211_LINK_UNSPECIFIED; 1917 + continue; 1918 + } 1919 + 1920 + kfree_rcu(msta_link, rcu_head); 1921 + } 1922 + } 1923 + 1924 + static void 1925 + mt7996_mac_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1926 + { 1927 + struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1928 + struct mt76_vif_data *mvif = mlink->mvif; 1929 + struct mt7996_dev *dev = data; 1930 + int i; 1931 + 1932 + rcu_read_lock(); 1933 + for (i = 0; i < ARRAY_SIZE(mvif->link); i++) { 1934 + 1935 + mlink = mt76_dereference(mvif->link[i], &dev->mt76); 1936 + if (!mlink || mlink == (struct mt76_vif_link *)vif->drv_priv) 1937 + continue; 1938 + 1939 + rcu_assign_pointer(mvif->link[i], NULL); 1940 + kfree_rcu(mlink, rcu_head); 1941 + } 1942 + rcu_read_unlock(); 1943 + } 1944 + 1945 + static void 1946 + mt7996_mac_full_reset(struct mt7996_dev *dev) 1947 + { 1948 + struct ieee80211_hw *hw = mt76_hw(dev); 1949 + struct mt7996_phy *phy; 1950 + LIST_HEAD(list); 1951 + int i; 1952 + 2367 1953 dev->recovery.hw_full_reset = true; 2368 1954 2369 1955 wake_up(&dev->mt76.mcu.wait); 2370 - ieee80211_stop_queues(mt76_hw(dev)); 2371 - if (phy2) 2372 - ieee80211_stop_queues(phy2->mt76->hw); 2373 - if (phy3) 2374 - ieee80211_stop_queues(phy3->mt76->hw); 1956 + ieee80211_stop_queues(hw); 2375 1957 2376 1958 cancel_work_sync(&dev->wed_rro.work); 2377 - cancel_delayed_work_sync(&dev->mphy.mac_work); 2378 - if (phy2) 2379 - cancel_delayed_work_sync(&phy2->mt76->mac_work); 2380 - if (phy3) 2381 - cancel_delayed_work_sync(&phy3->mt76->mac_work); 1959 + mt7996_for_each_phy(dev, phy) 1960 + cancel_delayed_work_sync(&phy->mt76->mac_work); 2382 1961 2383 1962 mutex_lock(&dev->mt76.mutex); 2384 1963 for (i = 0; i < 10; i++) { 2385 1964 if (!mt7996_mac_restart(dev)) 2386 1965 break; 2387 1966 } 2388 - mutex_unlock(&dev->mt76.mutex); 2389 1967 2390 1968 if (i == 10) 2391 1969 dev_err(dev->mt76.dev, "chip full reset failed\n"); 2392 1970 2393 - ieee80211_restart_hw(mt76_hw(dev)); 2394 - if (phy2) 2395 - ieee80211_restart_hw(phy2->mt76->hw); 2396 - if (phy3) 2397 - ieee80211_restart_hw(phy3->mt76->hw); 1971 + mt7996_for_each_phy(dev, phy) 1972 + phy->omac_mask = 0; 2398 1973 2399 - ieee80211_wake_queues(mt76_hw(dev)); 2400 - if (phy2) 2401 - ieee80211_wake_queues(phy2->mt76->hw); 2402 - if (phy3) 2403 - ieee80211_wake_queues(phy3->mt76->hw); 1974 + ieee80211_iterate_stations_atomic(hw, mt7996_mac_reset_sta_iter, dev); 1975 + ieee80211_iterate_active_interfaces_atomic(hw, 1976 + IEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER, 1977 + mt7996_mac_reset_vif_iter, dev); 1978 + mt76_reset_device(&dev->mt76); 2404 1979 1980 + INIT_LIST_HEAD(&dev->sta_rc_list); 1981 + INIT_LIST_HEAD(&dev->twt_list); 1982 + 1983 + spin_lock_bh(&dev->wed_rro.lock); 1984 + list_splice_init(&dev->wed_rro.poll_list, &list); 1985 + spin_unlock_bh(&dev->wed_rro.lock); 1986 + 1987 + while (!list_empty(&list)) { 1988 + struct mt7996_wed_rro_session_id *e; 1989 + 1990 + e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1991 + list); 1992 + list_del_init(&e->list); 1993 + kfree(e); 1994 + } 1995 + 1996 + i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1997 + dev->mt76.global_wcid.idx = i; 2405 1998 dev->recovery.hw_full_reset = false; 2406 - ieee80211_queue_delayed_work(mt76_hw(dev), 2407 - &dev->mphy.mac_work, 2408 - MT7996_WATCHDOG_TIME); 2409 - if (phy2) 2410 - ieee80211_queue_delayed_work(phy2->mt76->hw, 2411 - &phy2->mt76->mac_work, 2412 - MT7996_WATCHDOG_TIME); 2413 - if (phy3) 2414 - ieee80211_queue_delayed_work(phy3->mt76->hw, 2415 - &phy3->mt76->mac_work, 2416 - MT7996_WATCHDOG_TIME); 1999 + 2000 + mutex_unlock(&dev->mt76.mutex); 2001 + 2002 + ieee80211_restart_hw(mt76_hw(dev)); 2417 2003 } 2418 2004 2419 2005 void mt7996_mac_reset_work(struct work_struct *work) 2420 2006 { 2421 - struct mt7996_phy *phy2, *phy3; 2007 + struct ieee80211_hw *hw; 2422 2008 struct mt7996_dev *dev; 2009 + struct mt7996_phy *phy; 2423 2010 int i; 2424 2011 2425 2012 dev = container_of(work, struct mt7996_dev, reset_work); 2426 - phy2 = mt7996_phy2(dev); 2427 - phy3 = mt7996_phy3(dev); 2013 + hw = mt76_hw(dev); 2428 2014 2429 2015 /* chip full reset */ 2430 2016 if (dev->recovery.restart) { ··· 2502 1994 return; 2503 1995 2504 1996 dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", 2505 - wiphy_name(dev->mt76.hw->wiphy)); 1997 + wiphy_name(hw->wiphy)); 2506 1998 2507 1999 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 2508 2000 mtk_wed_device_stop(&dev->mt76.mmio.wed_hif2); ··· 2511 2003 mtk_wed_device_stop(&dev->mt76.mmio.wed); 2512 2004 2513 2005 ieee80211_stop_queues(mt76_hw(dev)); 2514 - if (phy2) 2515 - ieee80211_stop_queues(phy2->mt76->hw); 2516 - if (phy3) 2517 - ieee80211_stop_queues(phy3->mt76->hw); 2518 2006 2519 2007 set_bit(MT76_RESET, &dev->mphy.state); 2520 2008 set_bit(MT76_MCU_RESET, &dev->mphy.state); 2009 + mt76_abort_scan(&dev->mt76); 2521 2010 wake_up(&dev->mt76.mcu.wait); 2522 2011 2523 2012 cancel_work_sync(&dev->wed_rro.work); 2524 - cancel_delayed_work_sync(&dev->mphy.mac_work); 2525 - if (phy2) { 2526 - set_bit(MT76_RESET, &phy2->mt76->state); 2527 - cancel_delayed_work_sync(&phy2->mt76->mac_work); 2013 + mt7996_for_each_phy(dev, phy) { 2014 + mt76_abort_roc(phy->mt76); 2015 + set_bit(MT76_RESET, &phy->mt76->state); 2016 + cancel_delayed_work_sync(&phy->mt76->mac_work); 2528 2017 } 2529 - if (phy3) { 2530 - set_bit(MT76_RESET, &phy3->mt76->state); 2531 - cancel_delayed_work_sync(&phy3->mt76->mac_work); 2532 - } 2018 + 2533 2019 mt76_worker_disable(&dev->mt76.tx_worker); 2534 2020 mt76_for_each_q_rx(&dev->mt76, i) { 2535 2021 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && ··· 2554 2052 /* enable DMA Tx/Tx and interrupt */ 2555 2053 mt7996_dma_start(dev, false, false); 2556 2054 2055 + if (!is_mt7996(&dev->mt76) && dev->mt76.hwrro_mode == MT76_HWRRO_V3) 2056 + mt76_wr(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK); 2057 + 2557 2058 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { 2558 - u32 wed_irq_mask = MT_INT_RRO_RX_DONE | MT_INT_TX_DONE_BAND2 | 2059 + u32 wed_irq_mask = MT_INT_TX_DONE_BAND2 | 2559 2060 dev->mt76.mmio.irqmask; 2560 2061 2561 - if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) 2562 - wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND; 2563 - 2564 2062 mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); 2565 - 2566 2063 mtk_wed_device_start_hw_rro(&dev->mt76.mmio.wed, wed_irq_mask, 2567 2064 true); 2568 2065 mt7996_irq_enable(dev, wed_irq_mask); ··· 2575 2074 } 2576 2075 2577 2076 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 2578 - clear_bit(MT76_RESET, &dev->mphy.state); 2579 - if (phy2) 2580 - clear_bit(MT76_RESET, &phy2->mt76->state); 2581 - if (phy3) 2582 - clear_bit(MT76_RESET, &phy3->mt76->state); 2077 + mt7996_for_each_phy(dev, phy) 2078 + clear_bit(MT76_RESET, &phy->mt76->state); 2583 2079 2584 2080 mt76_for_each_q_rx(&dev->mt76, i) { 2585 2081 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && ··· 2598 2100 napi_schedule(&dev->mt76.tx_napi); 2599 2101 local_bh_enable(); 2600 2102 2601 - ieee80211_wake_queues(mt76_hw(dev)); 2602 - if (phy2) 2603 - ieee80211_wake_queues(phy2->mt76->hw); 2604 - if (phy3) 2605 - ieee80211_wake_queues(phy3->mt76->hw); 2103 + ieee80211_wake_queues(hw); 2606 2104 2607 2105 mutex_unlock(&dev->mt76.mutex); 2608 2106 2609 2107 mt7996_update_beacons(dev); 2610 2108 2611 - ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 2612 - MT7996_WATCHDOG_TIME); 2613 - if (phy2) 2614 - ieee80211_queue_delayed_work(phy2->mt76->hw, 2615 - &phy2->mt76->mac_work, 2616 - MT7996_WATCHDOG_TIME); 2617 - if (phy3) 2618 - ieee80211_queue_delayed_work(phy3->mt76->hw, 2619 - &phy3->mt76->mac_work, 2109 + mt7996_for_each_phy(dev, phy) 2110 + ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, 2620 2111 MT7996_WATCHDOG_TIME); 2621 2112 dev_info(dev->mt76.dev,"\n%s L1 SER recovery completed.", 2622 2113 wiphy_name(dev->mt76.hw->wiphy));

+317 -204

drivers/net/wireless/mediatek/mt76/mt7996/main.c

··· 138 138 return -1; 139 139 } 140 140 141 + static int get_own_mld_idx(u64 mask, bool group_mld) 142 + { 143 + u8 start = group_mld ? 0 : 16; 144 + u8 end = group_mld ? 15 : 63; 145 + int idx; 146 + 147 + idx = get_free_idx(mask, start, end); 148 + if (idx) 149 + return idx - 1; 150 + 151 + /* If the 16-63 range is not available, perform another lookup in the 152 + * range 0-15 153 + */ 154 + if (!group_mld) { 155 + idx = get_free_idx(mask, 0, 15); 156 + if (idx) 157 + return idx - 1; 158 + } 159 + 160 + return -EINVAL; 161 + } 162 + 141 163 static void 142 164 mt7996_init_bitrate_mask(struct ieee80211_vif *vif, struct mt7996_vif_link *mlink) 143 165 { ··· 182 160 static int 183 161 mt7996_set_hw_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 184 162 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 185 - struct ieee80211_key_conf *key) 163 + unsigned int link_id, struct ieee80211_key_conf *key) 186 164 { 187 165 struct mt7996_dev *dev = mt7996_hw_dev(hw); 166 + struct ieee80211_bss_conf *link_conf; 167 + struct mt7996_sta_link *msta_link; 168 + struct mt7996_vif_link *link; 188 169 int idx = key->keyidx; 189 - unsigned int link_id; 190 - unsigned long links; 170 + u8 *wcid_keyidx; 171 + bool is_bigtk; 172 + int err; 191 173 192 - if (key->link_id >= 0) 193 - links = BIT(key->link_id); 194 - else if (sta && sta->valid_links) 195 - links = sta->valid_links; 196 - else if (vif->valid_links) 197 - links = vif->valid_links; 198 - else 199 - links = BIT(0); 174 + link = mt7996_vif_link(dev, vif, link_id); 175 + if (!link) 176 + return 0; 200 177 201 - for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { 202 - struct mt7996_sta_link *msta_link; 203 - struct mt7996_vif_link *link; 204 - u8 *wcid_keyidx; 205 - int err; 178 + if (!mt7996_vif_link_phy(link)) 179 + return 0; 206 180 207 - link = mt7996_vif_link(dev, vif, link_id); 208 - if (!link) 209 - continue; 181 + if (sta) { 182 + struct mt7996_sta *msta; 210 183 211 - if (sta) { 212 - struct mt7996_sta *msta; 184 + msta = (struct mt7996_sta *)sta->drv_priv; 185 + msta_link = mt76_dereference(msta->link[link_id], 186 + &dev->mt76); 187 + if (!msta_link) 188 + return 0; 213 189 214 - msta = (struct mt7996_sta *)sta->drv_priv; 215 - msta_link = mt76_dereference(msta->link[link_id], 216 - &dev->mt76); 217 - if (!msta_link) 218 - continue; 190 + if (!msta_link->wcid.sta) 191 + return -EOPNOTSUPP; 192 + } else { 193 + msta_link = &link->msta_link; 194 + } 195 + wcid_keyidx = &msta_link->wcid.hw_key_idx; 219 196 220 - if (!msta_link->wcid.sta) 221 - return -EOPNOTSUPP; 222 - } else { 223 - msta_link = &link->msta_link; 197 + is_bigtk = key->keyidx == 6 || key->keyidx == 7; 198 + switch (key->cipher) { 199 + case WLAN_CIPHER_SUITE_AES_CMAC: 200 + case WLAN_CIPHER_SUITE_BIP_CMAC_256: 201 + case WLAN_CIPHER_SUITE_BIP_GMAC_128: 202 + case WLAN_CIPHER_SUITE_BIP_GMAC_256: 203 + if (is_bigtk) { 204 + wcid_keyidx = &msta_link->wcid.hw_key_idx2; 205 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIE; 224 206 } 225 - wcid_keyidx = &msta_link->wcid.hw_key_idx; 226 - 227 - switch (key->cipher) { 228 - case WLAN_CIPHER_SUITE_AES_CMAC: 229 - case WLAN_CIPHER_SUITE_BIP_CMAC_256: 230 - case WLAN_CIPHER_SUITE_BIP_GMAC_128: 231 - case WLAN_CIPHER_SUITE_BIP_GMAC_256: 232 - if (key->keyidx == 6 || key->keyidx == 7) { 233 - wcid_keyidx = &msta_link->wcid.hw_key_idx2; 234 - key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIE; 235 - } 236 - break; 237 - default: 238 - break; 239 - } 240 - 241 - if (cmd == SET_KEY && !sta && !link->mt76.cipher) { 242 - struct ieee80211_bss_conf *link_conf; 243 - 244 - link_conf = link_conf_dereference_protected(vif, 245 - link_id); 246 - if (!link_conf) 247 - link_conf = &vif->bss_conf; 248 - 249 - link->mt76.cipher = 250 - mt76_connac_mcu_get_cipher(key->cipher); 251 - mt7996_mcu_add_bss_info(link->phy, vif, link_conf, 252 - &link->mt76, msta_link, true); 253 - } 254 - 255 - if (cmd == SET_KEY) { 256 - *wcid_keyidx = idx; 257 - } else { 258 - if (idx == *wcid_keyidx) 259 - *wcid_keyidx = -1; 260 - continue; 261 - } 262 - 263 - mt76_wcid_key_setup(&dev->mt76, &msta_link->wcid, key); 264 - 265 - if (key->keyidx == 6 || key->keyidx == 7) { 266 - err = mt7996_mcu_bcn_prot_enable(dev, link, 267 - msta_link, key); 268 - if (err) 269 - return err; 270 - } 271 - 272 - err = mt7996_mcu_add_key(&dev->mt76, vif, key, 273 - MCU_WMWA_UNI_CMD(STA_REC_UPDATE), 274 - &msta_link->wcid, cmd); 275 - if (err) 276 - return err; 207 + break; 208 + default: 209 + break; 277 210 } 278 211 279 - return 0; 212 + link_conf = link_conf_dereference_protected(vif, link_id); 213 + if (!link_conf) 214 + link_conf = &vif->bss_conf; 215 + 216 + if (cmd == SET_KEY && !sta && !link->mt76.cipher) { 217 + link->mt76.cipher = 218 + mt76_connac_mcu_get_cipher(key->cipher); 219 + mt7996_mcu_add_bss_info(link->phy, vif, link_conf, 220 + &link->mt76, msta_link, true); 221 + } 222 + 223 + if (cmd == SET_KEY) 224 + *wcid_keyidx = idx; 225 + else if (idx == *wcid_keyidx) 226 + *wcid_keyidx = -1; 227 + 228 + if (cmd != SET_KEY && sta) 229 + return 0; 230 + 231 + mt76_wcid_key_setup(&dev->mt76, &msta_link->wcid, key); 232 + 233 + err = mt7996_mcu_add_key(&dev->mt76, vif, key, 234 + MCU_WMWA_UNI_CMD(STA_REC_UPDATE), 235 + &msta_link->wcid, cmd); 236 + 237 + /* remove and add beacon in order to enable beacon protection */ 238 + if (cmd == SET_KEY && is_bigtk && link_conf->enable_beacon) { 239 + mt7996_mcu_add_beacon(hw, vif, link_conf, false); 240 + mt7996_mcu_add_beacon(hw, vif, link_conf, true); 241 + } 242 + 243 + return err; 280 244 } 245 + 246 + struct mt7996_key_iter_data { 247 + enum set_key_cmd cmd; 248 + unsigned int link_id; 249 + }; 281 250 282 251 static void 283 252 mt7996_key_iter(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 284 253 struct ieee80211_sta *sta, struct ieee80211_key_conf *key, 285 254 void *data) 286 255 { 256 + struct mt7996_key_iter_data *it = data; 257 + 287 258 if (sta) 288 259 return; 289 260 290 - WARN_ON(mt7996_set_hw_key(hw, SET_KEY, vif, NULL, key)); 261 + WARN_ON(mt7996_set_hw_key(hw, it->cmd, vif, NULL, it->link_id, key)); 291 262 } 292 263 293 264 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, ··· 293 278 struct mt7996_phy *phy = mphy->priv; 294 279 struct mt7996_dev *dev = phy->dev; 295 280 u8 band_idx = phy->mt76->band_idx; 281 + struct mt7996_key_iter_data it = { 282 + .cmd = SET_KEY, 283 + .link_id = link_conf->link_id, 284 + }; 296 285 struct mt76_txq *mtxq; 297 - int idx, ret; 286 + int mld_idx, idx, ret; 298 287 299 288 mlink->idx = __ffs64(~dev->mt76.vif_mask); 300 289 if (mlink->idx >= mt7996_max_interface_num(dev)) ··· 308 289 if (idx < 0) 309 290 return -ENOSPC; 310 291 292 + if (!dev->mld_idx_mask) { /* first link in the group */ 293 + mvif->mld_group_idx = get_own_mld_idx(dev->mld_idx_mask, true); 294 + mvif->mld_remap_idx = get_free_idx(dev->mld_remap_idx_mask, 295 + 0, 15); 296 + } 297 + 298 + mld_idx = get_own_mld_idx(dev->mld_idx_mask, false); 299 + if (mld_idx < 0) 300 + return -ENOSPC; 301 + 302 + link->mld_idx = mld_idx; 311 303 link->phy = phy; 312 304 mlink->omac_idx = idx; 313 305 mlink->band_idx = band_idx; ··· 331 301 return ret; 332 302 333 303 dev->mt76.vif_mask |= BIT_ULL(mlink->idx); 304 + if (!dev->mld_idx_mask) { 305 + dev->mld_idx_mask |= BIT_ULL(mvif->mld_group_idx); 306 + dev->mld_remap_idx_mask |= BIT_ULL(mvif->mld_remap_idx); 307 + } 308 + dev->mld_idx_mask |= BIT_ULL(link->mld_idx); 334 309 phy->omac_mask |= BIT_ULL(mlink->omac_idx); 335 310 336 311 idx = MT7996_WTBL_RESERVED - mlink->idx; ··· 374 339 CONN_STATE_PORT_SECURE, true); 375 340 rcu_assign_pointer(dev->mt76.wcid[idx], &msta_link->wcid); 376 341 377 - ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, NULL); 342 + ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, &it); 378 343 379 344 if (mvif->mt76.deflink_id == IEEE80211_LINK_UNSPECIFIED) 380 345 mvif->mt76.deflink_id = link_conf->link_id; ··· 391 356 struct mt7996_sta_link *msta_link = &link->msta_link; 392 357 struct mt7996_phy *phy = mphy->priv; 393 358 struct mt7996_dev *dev = phy->dev; 359 + struct mt7996_key_iter_data it = { 360 + .cmd = SET_KEY, 361 + .link_id = link_conf->link_id, 362 + }; 394 363 int idx = msta_link->wcid.idx; 364 + 365 + ieee80211_iter_keys(mphy->hw, vif, mt7996_key_iter, &it); 395 366 396 367 mt7996_mcu_add_sta(dev, link_conf, NULL, link, NULL, 397 368 CONN_STATE_DISCONNECT, false); ··· 421 380 } 422 381 423 382 dev->mt76.vif_mask &= ~BIT_ULL(mlink->idx); 383 + dev->mld_idx_mask &= ~BIT_ULL(link->mld_idx); 424 384 phy->omac_mask &= ~BIT_ULL(mlink->omac_idx); 385 + if (!(dev->mld_idx_mask & ~BIT_ULL(mvif->mld_group_idx))) { 386 + /* last link */ 387 + dev->mld_idx_mask &= ~BIT_ULL(mvif->mld_group_idx); 388 + dev->mld_remap_idx_mask &= ~BIT_ULL(mvif->mld_remap_idx); 389 + } 425 390 426 391 spin_lock_bh(&dev->mt76.sta_poll_lock); 427 392 if (!list_empty(&msta_link->wcid.poll_list)) ··· 598 551 struct ieee80211_key_conf *key) 599 552 { 600 553 struct mt7996_dev *dev = mt7996_hw_dev(hw); 601 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 602 - int err; 554 + unsigned int link_id; 555 + unsigned long links; 556 + int err = 0; 603 557 604 558 /* The hardware does not support per-STA RX GTK, fallback 605 559 * to software mode for these. ··· 634 586 return -EOPNOTSUPP; 635 587 } 636 588 637 - if (!mt7996_vif_link_phy(&mvif->deflink)) 638 - return 0; /* defer until after link add */ 639 - 640 589 mutex_lock(&dev->mt76.mutex); 641 - err = mt7996_set_hw_key(hw, cmd, vif, sta, key); 590 + 591 + if (key->link_id >= 0) 592 + links = BIT(key->link_id); 593 + else if (sta && sta->valid_links) 594 + links = sta->valid_links; 595 + else if (vif->valid_links) 596 + links = vif->valid_links; 597 + else 598 + links = BIT(0); 599 + 600 + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { 601 + err = mt7996_set_hw_key(hw, cmd, vif, sta, link_id, key); 602 + if (err) 603 + break; 604 + } 642 605 mutex_unlock(&dev->mt76.mutex); 643 606 644 607 return err; ··· 909 850 link->mt76.beacon_rates_idx = 910 851 mt7996_get_rates_table(phy, info, true, false); 911 852 912 - mt7996_mcu_add_beacon(hw, vif, info); 853 + mt7996_mcu_add_beacon(hw, vif, info, info->enable_beacon); 913 854 } 914 855 915 856 if (changed & (BSS_CHANGED_UNSOL_BCAST_PROBE_RESP | ··· 937 878 struct mt7996_dev *dev = mt7996_hw_dev(hw); 938 879 939 880 mutex_lock(&dev->mt76.mutex); 940 - mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf); 881 + mt7996_mcu_add_beacon(hw, vif, &vif->bss_conf, vif->bss_conf.enable_beacon); 941 882 mutex_unlock(&dev->mt76.mutex); 942 883 } 943 884 ··· 984 925 msta_link->wcid.sta = 1; 985 926 msta_link->wcid.idx = idx; 986 927 msta_link->wcid.link_id = link_id; 928 + msta_link->wcid.def_wcid = &msta->deflink.wcid; 987 929 988 930 ewma_avg_signal_init(&msta_link->avg_ack_signal); 989 931 ewma_signal_init(&msta_link->wcid.rssi); ··· 1001 941 return 0; 1002 942 } 1003 943 1004 - static void 1005 - mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 1006 - struct mt7996_sta_link *msta_link) 944 + void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 945 + struct mt7996_sta_link *msta_link) 1007 946 { 1008 - int i; 1009 - 1010 - for (i = 0; i < ARRAY_SIZE(msta_link->wcid.aggr); i++) 1011 - mt76_rx_aggr_stop(&dev->mt76, &msta_link->wcid, i); 1012 - 1013 - mt7996_mac_wtbl_update(dev, msta_link->wcid.idx, 1014 - MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 1015 - 1016 947 spin_lock_bh(&dev->mt76.sta_poll_lock); 1017 948 if (!list_empty(&msta_link->wcid.poll_list)) 1018 949 list_del_init(&msta_link->wcid.poll_list); ··· 1032 981 lockdep_is_held(&mdev->mutex)); 1033 982 if (!msta_link) 1034 983 continue; 984 + 985 + mt7996_mac_wtbl_update(dev, msta_link->wcid.idx, 986 + MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 1035 987 1036 988 mt7996_mac_sta_deinit_link(dev, msta_link); 1037 989 link = mt7996_vif_link(dev, vif, link_id); ··· 1090 1036 goto error_unlink; 1091 1037 } 1092 1038 1093 - err = mt7996_mac_sta_init_link(dev, link_conf, link_sta, link, 1094 - link_id); 1095 - if (err) 1096 - goto error_unlink; 1097 - 1098 1039 mphy = mt76_vif_link_phy(&link->mt76); 1099 1040 if (!mphy) { 1100 1041 err = -EINVAL; 1101 1042 goto error_unlink; 1102 1043 } 1044 + 1045 + err = mt7996_mac_sta_init_link(dev, link_conf, link_sta, link, 1046 + link_id); 1047 + if (err) 1048 + goto error_unlink; 1049 + 1103 1050 mphy->num_sta++; 1104 1051 } 1105 1052 ··· 1234 1179 mutex_unlock(&dev->mt76.mutex); 1235 1180 } 1236 1181 1182 + static void 1183 + mt7996_set_active_links(struct ieee80211_vif *vif) 1184 + { 1185 + u16 active_links; 1186 + 1187 + if (vif->type != NL80211_IFTYPE_STATION) 1188 + return; 1189 + 1190 + if (!ieee80211_vif_is_mld(vif)) 1191 + return; 1192 + 1193 + active_links = mt76_select_links(vif, MT7996_MAX_RADIOS); 1194 + if (hweight16(active_links) < 2) 1195 + return; 1196 + 1197 + ieee80211_set_active_links_async(vif, active_links); 1198 + } 1199 + 1237 1200 static int 1238 1201 mt7996_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1239 1202 struct ieee80211_sta *sta, enum ieee80211_sta_state old_state, ··· 1269 1196 mt7996_mac_sta_remove(dev, vif, sta); 1270 1197 1271 1198 if (old_state == IEEE80211_STA_AUTH && 1272 - new_state == IEEE80211_STA_ASSOC) 1199 + new_state == IEEE80211_STA_ASSOC) { 1200 + mt7996_set_active_links(vif); 1273 1201 ev = MT76_STA_EVENT_ASSOC; 1274 - else if (old_state == IEEE80211_STA_ASSOC && 1275 - new_state == IEEE80211_STA_AUTHORIZED) 1202 + } else if (old_state == IEEE80211_STA_ASSOC && 1203 + new_state == IEEE80211_STA_AUTHORIZED) { 1276 1204 ev = MT76_STA_EVENT_AUTHORIZE; 1277 - else if (old_state == IEEE80211_STA_ASSOC && 1278 - new_state == IEEE80211_STA_AUTH) 1205 + } else if (old_state == IEEE80211_STA_ASSOC && 1206 + new_state == IEEE80211_STA_AUTH) { 1279 1207 ev = MT76_STA_EVENT_DISASSOC; 1280 - else 1208 + } else { 1281 1209 return 0; 1210 + } 1282 1211 1283 1212 return mt7996_mac_sta_event(dev, vif, sta, ev); 1284 1213 } ··· 1289 1214 struct ieee80211_tx_control *control, 1290 1215 struct sk_buff *skb) 1291 1216 { 1217 + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1292 1218 struct mt7996_dev *dev = mt7996_hw_dev(hw); 1219 + struct ieee80211_sta *sta = control->sta; 1220 + struct mt7996_sta *msta = sta ? (void *)sta->drv_priv : NULL; 1293 1221 struct mt76_phy *mphy = hw->priv; 1294 1222 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1295 1223 struct ieee80211_vif *vif = info->control.vif; 1224 + struct mt7996_vif *mvif = vif ? (void *)vif->drv_priv : NULL; 1296 1225 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1297 1226 u8 link_id = u32_get_bits(info->control.flags, 1298 1227 IEEE80211_TX_CTRL_MLO_LINK); 1299 1228 1300 1229 rcu_read_lock(); 1301 1230 1302 - if (vif) { 1303 - struct mt7996_vif *mvif = (void *)vif->drv_priv; 1231 + /* Use primary link_id if the value from mac80211 is set to 1232 + * IEEE80211_LINK_UNSPECIFIED. 1233 + */ 1234 + if (link_id == IEEE80211_LINK_UNSPECIFIED) { 1235 + if (msta) 1236 + link_id = msta->deflink_id; 1237 + else if (mvif) 1238 + link_id = mvif->mt76.deflink_id; 1239 + } 1240 + 1241 + if (vif && ieee80211_vif_is_mld(vif)) { 1242 + struct ieee80211_bss_conf *link_conf; 1243 + 1244 + if (msta) { 1245 + struct ieee80211_link_sta *link_sta; 1246 + 1247 + link_sta = rcu_dereference(sta->link[link_id]); 1248 + if (!link_sta) 1249 + link_sta = rcu_dereference(sta->link[msta->deflink_id]); 1250 + 1251 + if (link_sta) { 1252 + memcpy(hdr->addr1, link_sta->addr, ETH_ALEN); 1253 + if (ether_addr_equal(sta->addr, hdr->addr3)) 1254 + memcpy(hdr->addr3, link_sta->addr, ETH_ALEN); 1255 + } 1256 + } 1257 + 1258 + link_conf = rcu_dereference(vif->link_conf[link_id]); 1259 + if (link_conf) { 1260 + memcpy(hdr->addr2, link_conf->addr, ETH_ALEN); 1261 + if (ether_addr_equal(vif->addr, hdr->addr3)) 1262 + memcpy(hdr->addr3, link_conf->addr, ETH_ALEN); 1263 + } 1264 + } 1265 + 1266 + if (mvif) { 1304 1267 struct mt76_vif_link *mlink = &mvif->deflink.mt76; 1305 1268 1306 1269 if (link_id < IEEE80211_LINK_UNSPECIFIED) 1307 1270 mlink = rcu_dereference(mvif->mt76.link[link_id]); 1308 - 1309 - if (!mlink) { 1310 - ieee80211_free_txskb(hw, skb); 1311 - goto unlock; 1312 - } 1313 1271 1314 1272 if (mlink->wcid) 1315 1273 wcid = mlink->wcid; ··· 1362 1254 goto unlock; 1363 1255 } 1364 1256 1365 - if (control->sta && link_id < IEEE80211_LINK_UNSPECIFIED) { 1366 - struct mt7996_sta *msta = (void *)control->sta->drv_priv; 1257 + if (msta && link_id < IEEE80211_LINK_UNSPECIFIED) { 1367 1258 struct mt7996_sta_link *msta_link; 1368 1259 1369 1260 msta_link = rcu_dereference(msta->link[link_id]); ··· 1399 1292 mt7996_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1400 1293 struct ieee80211_ampdu_params *params) 1401 1294 { 1402 - enum ieee80211_ampdu_mlme_action action = params->action; 1403 1295 struct mt7996_dev *dev = mt7996_hw_dev(hw); 1404 1296 struct ieee80211_sta *sta = params->sta; 1405 1297 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1406 1298 struct ieee80211_txq *txq = sta->txq[params->tid]; 1407 - struct ieee80211_link_sta *link_sta; 1408 1299 u16 tid = params->tid; 1409 1300 u16 ssn = params->ssn; 1410 1301 struct mt76_txq *mtxq; 1411 - unsigned int link_id; 1412 1302 int ret = 0; 1413 1303 1414 1304 if (!txq) ··· 1415 1311 1416 1312 mutex_lock(&dev->mt76.mutex); 1417 1313 1418 - for_each_sta_active_link(vif, sta, link_sta, link_id) { 1419 - struct mt7996_sta_link *msta_link; 1420 - struct mt7996_vif_link *link; 1421 - 1422 - msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1423 - if (!msta_link) 1424 - continue; 1425 - 1426 - link = mt7996_vif_link(dev, vif, link_id); 1427 - if (!link) 1428 - continue; 1429 - 1430 - switch (action) { 1431 - case IEEE80211_AMPDU_RX_START: 1432 - mt76_rx_aggr_start(&dev->mt76, &msta_link->wcid, tid, 1433 - ssn, params->buf_size); 1434 - ret = mt7996_mcu_add_rx_ba(dev, params, link, true); 1435 - break; 1436 - case IEEE80211_AMPDU_RX_STOP: 1437 - mt76_rx_aggr_stop(&dev->mt76, &msta_link->wcid, tid); 1438 - ret = mt7996_mcu_add_rx_ba(dev, params, link, false); 1439 - break; 1440 - case IEEE80211_AMPDU_TX_OPERATIONAL: 1441 - mtxq->aggr = true; 1442 - mtxq->send_bar = false; 1443 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1444 - msta_link, true); 1445 - break; 1446 - case IEEE80211_AMPDU_TX_STOP_FLUSH: 1447 - case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1448 - mtxq->aggr = false; 1449 - clear_bit(tid, &msta_link->wcid.ampdu_state); 1450 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1451 - msta_link, false); 1452 - break; 1453 - case IEEE80211_AMPDU_TX_START: 1454 - set_bit(tid, &msta_link->wcid.ampdu_state); 1455 - ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1456 - break; 1457 - case IEEE80211_AMPDU_TX_STOP_CONT: 1458 - mtxq->aggr = false; 1459 - clear_bit(tid, &msta_link->wcid.ampdu_state); 1460 - ret = mt7996_mcu_add_tx_ba(dev, params, link, 1461 - msta_link, false); 1462 - break; 1463 - } 1464 - 1465 - if (ret) 1466 - break; 1467 - } 1468 - 1469 - if (action == IEEE80211_AMPDU_TX_STOP_CONT) 1314 + switch (params->action) { 1315 + case IEEE80211_AMPDU_RX_START: 1316 + /* Since packets belonging to the same TID can be split over 1317 + * multiple links, store the AMPDU state for reordering in the 1318 + * primary link 1319 + */ 1320 + mt76_rx_aggr_start(&dev->mt76, &msta->deflink.wcid, tid, 1321 + ssn, params->buf_size); 1322 + ret = mt7996_mcu_add_rx_ba(dev, params, vif, true); 1323 + break; 1324 + case IEEE80211_AMPDU_RX_STOP: 1325 + mt76_rx_aggr_stop(&dev->mt76, &msta->deflink.wcid, tid); 1326 + ret = mt7996_mcu_add_rx_ba(dev, params, vif, false); 1327 + break; 1328 + case IEEE80211_AMPDU_TX_OPERATIONAL: 1329 + mtxq->aggr = true; 1330 + mtxq->send_bar = false; 1331 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, true); 1332 + break; 1333 + case IEEE80211_AMPDU_TX_STOP_FLUSH: 1334 + case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1335 + mtxq->aggr = false; 1336 + clear_bit(tid, &msta->deflink.wcid.ampdu_state); 1337 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, false); 1338 + break; 1339 + case IEEE80211_AMPDU_TX_START: 1340 + set_bit(tid, &msta->deflink.wcid.ampdu_state); 1341 + ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1342 + break; 1343 + case IEEE80211_AMPDU_TX_STOP_CONT: 1344 + mtxq->aggr = false; 1345 + clear_bit(tid, &msta->deflink.wcid.ampdu_state); 1346 + ret = mt7996_mcu_add_tx_ba(dev, params, vif, false); 1470 1347 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1348 + break; 1349 + } 1471 1350 1472 1351 mutex_unlock(&dev->mt76.mutex); 1473 1352 ··· 1704 1617 } 1705 1618 } 1706 1619 1707 - static void mt7996_link_rate_ctrl_update(void *data, struct ieee80211_sta *sta) 1620 + static void mt7996_link_rate_ctrl_update(void *data, 1621 + struct mt7996_sta_link *msta_link) 1708 1622 { 1709 - struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1623 + struct mt7996_sta *msta = msta_link->sta; 1710 1624 struct mt7996_dev *dev = msta->vif->deflink.phy->dev; 1711 - struct mt7996_sta_link *msta_link; 1712 1625 u32 *changed = data; 1713 - 1714 - rcu_read_lock(); 1715 - 1716 - msta_link = rcu_dereference(msta->link[msta->deflink_id]); 1717 - if (!msta_link) 1718 - goto out; 1719 1626 1720 1627 spin_lock_bh(&dev->mt76.sta_poll_lock); 1721 1628 ··· 1718 1637 list_add_tail(&msta_link->rc_list, &dev->sta_rc_list); 1719 1638 1720 1639 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1721 - out: 1722 - rcu_read_unlock(); 1723 1640 } 1724 1641 1725 1642 static void mt7996_link_sta_rc_update(struct ieee80211_hw *hw, ··· 1725 1646 struct ieee80211_link_sta *link_sta, 1726 1647 u32 changed) 1727 1648 { 1728 - struct mt7996_dev *dev = mt7996_hw_dev(hw); 1729 1649 struct ieee80211_sta *sta = link_sta->sta; 1650 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1651 + struct mt7996_sta_link *msta_link; 1730 1652 1731 - mt7996_link_rate_ctrl_update(&changed, sta); 1732 - ieee80211_queue_work(hw, &dev->rc_work); 1653 + rcu_read_lock(); 1654 + 1655 + msta_link = rcu_dereference(msta->link[link_sta->link_id]); 1656 + if (msta_link) { 1657 + struct mt7996_dev *dev = mt7996_hw_dev(hw); 1658 + 1659 + mt7996_link_rate_ctrl_update(&changed, msta_link); 1660 + ieee80211_queue_work(hw, &dev->rc_work); 1661 + } 1662 + 1663 + rcu_read_unlock(); 1664 + } 1665 + 1666 + static void mt7996_sta_rate_ctrl_update(void *data, struct ieee80211_sta *sta) 1667 + { 1668 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1669 + struct mt7996_sta_link *msta_link; 1670 + u32 *changed = data; 1671 + 1672 + msta_link = rcu_dereference(msta->link[msta->deflink_id]); 1673 + if (msta_link) 1674 + mt7996_link_rate_ctrl_update(&changed, msta_link); 1733 1675 } 1734 1676 1735 1677 static int ··· 1771 1671 * - multiple rates: if it's not in range format i.e 0-{7,8,9} for VHT 1772 1672 * then multiple MCS setting (MCS 4,5,6) is not supported. 1773 1673 */ 1774 - ieee80211_iterate_stations_atomic(hw, mt7996_link_rate_ctrl_update, 1674 + ieee80211_iterate_stations_atomic(hw, mt7996_sta_rate_ctrl_update, 1775 1675 &changed); 1776 1676 ieee80211_queue_work(hw, &dev->rc_work); 1777 1677 ··· 2172 2072 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2173 2073 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 2174 2074 struct mt7996_sta_link *msta_link; 2175 - struct mt7996_vif_link *link; 2176 2075 struct mt76_vif_link *mlink; 2177 - struct mt7996_phy *phy; 2178 2076 2179 2077 mlink = rcu_dereference(mvif->mt76.link[msta->deflink_id]); 2180 2078 if (!mlink) ··· 2185 2087 if (!msta_link->wcid.sta || msta_link->wcid.idx > MT7996_WTBL_STA) 2186 2088 return -EIO; 2187 2089 2188 - link = (struct mt7996_vif_link *)mlink; 2189 - phy = mt7996_vif_link_phy(link); 2190 - if (!phy) 2191 - return -ENODEV; 2192 - 2193 - if (phy != &dev->phy && phy->mt76->band_idx == MT_BAND2) 2090 + if (dev->hif2 && 2091 + ((is_mt7996(&dev->mt76) && msta_link->wcid.phy_idx == MT_BAND2) || 2092 + (is_mt7992(&dev->mt76) && msta_link->wcid.phy_idx == MT_BAND1))) 2194 2093 wed = &dev->mt76.mmio.wed_hif2; 2195 2094 2196 2095 if (!mtk_wed_device_active(wed)) ··· 2200 2105 path->mtk_wdma.queue = 0; 2201 2106 path->mtk_wdma.wcid = msta_link->wcid.idx; 2202 2107 2203 - path->mtk_wdma.amsdu = mtk_wed_is_amsdu_supported(wed); 2108 + if (ieee80211_hw_check(hw, SUPPORTS_AMSDU_IN_AMPDU) && 2109 + mtk_wed_is_amsdu_supported(wed)) 2110 + path->mtk_wdma.amsdu = msta_link->wcid.amsdu; 2111 + else 2112 + path->mtk_wdma.amsdu = 0; 2204 2113 ctx->dev = NULL; 2205 2114 2206 2115 return 0; ··· 2218 2119 struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS]) 2219 2120 { 2220 2121 return 0; 2122 + } 2123 + 2124 + static void 2125 + mt7996_reconfig_complete(struct ieee80211_hw *hw, 2126 + enum ieee80211_reconfig_type reconfig_type) 2127 + { 2128 + struct mt7996_dev *dev = mt7996_hw_dev(hw); 2129 + struct mt7996_phy *phy; 2130 + 2131 + ieee80211_wake_queues(hw); 2132 + mt7996_for_each_phy(dev, phy) 2133 + ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work, 2134 + MT7996_WATCHDOG_TIME); 2221 2135 } 2222 2136 2223 2137 const struct ieee80211_ops mt7996_ops = { ··· 2291 2179 #endif 2292 2180 .change_vif_links = mt7996_change_vif_links, 2293 2181 .change_sta_links = mt7996_mac_sta_change_links, 2182 + .reconfig_complete = mt7996_reconfig_complete, 2294 2183 };

+151 -157

drivers/net/wireless/mediatek/mt76/mt7996/mcu.c

··· 242 242 return ret; 243 243 } 244 244 245 + static void 246 + mt7996_mcu_set_timeout(struct mt76_dev *mdev, int cmd) 247 + { 248 + mdev->mcu.timeout = 5 * HZ; 249 + 250 + if (!(cmd & __MCU_CMD_FIELD_UNI)) 251 + return; 252 + 253 + switch (FIELD_GET(__MCU_CMD_FIELD_ID, cmd)) { 254 + case MCU_UNI_CMD_THERMAL: 255 + case MCU_UNI_CMD_TWT: 256 + case MCU_UNI_CMD_GET_MIB_INFO: 257 + case MCU_UNI_CMD_STA_REC_UPDATE: 258 + case MCU_UNI_CMD_BSS_INFO_UPDATE: 259 + mdev->mcu.timeout = 2 * HZ; 260 + return; 261 + case MCU_UNI_CMD_EFUSE_CTRL: 262 + mdev->mcu.timeout = 20 * HZ; 263 + return; 264 + default: 265 + break; 266 + } 267 + } 268 + 245 269 static int 246 270 mt7996_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 247 271 int cmd, int *wait_seq) ··· 279 255 u32 val; 280 256 u8 seq; 281 257 282 - mdev->mcu.timeout = 20 * HZ; 258 + mt7996_mcu_set_timeout(mdev, cmd); 283 259 284 260 seq = ++dev->mt76.mcu.msg_seq & 0xf; 285 261 if (!seq) ··· 684 660 { 685 661 struct mt7996_mcu_wed_rro_event *event = (void *)skb->data; 686 662 687 - if (!dev->has_rro) 663 + if (!mt7996_has_hwrro(dev)) 688 664 return; 689 665 690 666 skb_pull(skb, sizeof(struct mt7996_mcu_rxd) + 4); ··· 923 899 } 924 900 925 901 static void 926 - mt7996_mcu_bss_mld_tlv(struct sk_buff *skb, struct mt76_vif_link *mlink) 902 + mt7996_mcu_bss_mld_tlv(struct sk_buff *skb, 903 + struct ieee80211_bss_conf *link_conf, 904 + struct mt7996_vif_link *link) 927 905 { 906 + struct ieee80211_vif *vif = link_conf->vif; 907 + struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 928 908 struct bss_mld_tlv *mld; 929 909 struct tlv *tlv; 930 910 931 911 tlv = mt7996_mcu_add_uni_tlv(skb, UNI_BSS_INFO_MLD, sizeof(*mld)); 932 - 933 912 mld = (struct bss_mld_tlv *)tlv; 934 - mld->group_mld_id = 0xff; 935 - mld->own_mld_id = mlink->idx; 936 - mld->remap_idx = 0xff; 913 + mld->own_mld_id = link->mld_idx; 914 + mld->link_id = link_conf->link_id; 915 + 916 + if (ieee80211_vif_is_mld(vif)) { 917 + mld->group_mld_id = mvif->mld_group_idx; 918 + mld->remap_idx = mvif->mld_remap_idx; 919 + memcpy(mld->mac_addr, vif->addr, ETH_ALEN); 920 + } else { 921 + mld->group_mld_id = 0xff; 922 + mld->remap_idx = 0xff; 923 + } 937 924 } 938 925 939 926 static void ··· 1143 1108 goto out; 1144 1109 1145 1110 if (enable) { 1111 + struct mt7996_vif_link *link; 1112 + 1146 1113 mt7996_mcu_bss_rfch_tlv(skb, phy); 1147 1114 mt7996_mcu_bss_bmc_tlv(skb, mlink, phy); 1148 1115 mt7996_mcu_bss_ra_tlv(skb, phy); ··· 1155 1118 mt7996_mcu_bss_he_tlv(skb, vif, link_conf, phy); 1156 1119 1157 1120 /* this tag is necessary no matter if the vif is MLD */ 1158 - mt7996_mcu_bss_mld_tlv(skb, mlink); 1121 + link = container_of(mlink, struct mt7996_vif_link, mt76); 1122 + mt7996_mcu_bss_mld_tlv(skb, link_conf, link); 1159 1123 } 1160 1124 1161 1125 mt7996_mcu_bss_mbssid_tlv(skb, link_conf, enable); ··· 1187 1149 static int 1188 1150 mt7996_mcu_sta_ba(struct mt7996_dev *dev, struct mt76_vif_link *mvif, 1189 1151 struct ieee80211_ampdu_params *params, 1190 - bool enable, bool tx) 1152 + struct mt76_wcid *wcid, bool enable, bool tx) 1191 1153 { 1192 - struct mt76_wcid *wcid = (struct mt76_wcid *)params->sta->drv_priv; 1193 1154 struct sta_rec_ba_uni *ba; 1194 1155 struct sk_buff *skb; 1195 1156 struct tlv *tlv; ··· 1207 1170 ba->ba_en = enable << params->tid; 1208 1171 ba->amsdu = params->amsdu; 1209 1172 ba->tid = params->tid; 1210 - ba->ba_rdd_rro = !tx && enable && dev->has_rro; 1173 + ba->ba_rdd_rro = !tx && enable && mt7996_has_hwrro(dev); 1211 1174 1212 1175 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1213 1176 MCU_WMWA_UNI_CMD(STA_REC_UPDATE), true); ··· 1216 1179 /** starec & wtbl **/ 1217 1180 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 1218 1181 struct ieee80211_ampdu_params *params, 1219 - struct mt7996_vif_link *link, 1220 - struct mt7996_sta_link *msta_link, bool enable) 1182 + struct ieee80211_vif *vif, bool enable) 1221 1183 { 1222 - if (enable && !params->amsdu) 1223 - msta_link->wcid.amsdu = false; 1184 + struct ieee80211_sta *sta = params->sta; 1185 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1186 + struct ieee80211_link_sta *link_sta; 1187 + unsigned int link_id; 1188 + int ret = 0; 1224 1189 1225 - return mt7996_mcu_sta_ba(dev, &link->mt76, params, enable, true); 1190 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 1191 + struct mt7996_sta_link *msta_link; 1192 + struct mt7996_vif_link *link; 1193 + 1194 + msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1195 + if (!msta_link) 1196 + continue; 1197 + 1198 + link = mt7996_vif_link(dev, vif, link_id); 1199 + if (!link) 1200 + continue; 1201 + 1202 + if (enable && !params->amsdu) 1203 + msta_link->wcid.amsdu = false; 1204 + 1205 + ret = mt7996_mcu_sta_ba(dev, &link->mt76, params, 1206 + &msta_link->wcid, enable, true); 1207 + if (ret) 1208 + break; 1209 + } 1210 + 1211 + return ret; 1226 1212 } 1227 1213 1228 1214 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 1229 1215 struct ieee80211_ampdu_params *params, 1230 - struct mt7996_vif_link *link, bool enable) 1216 + struct ieee80211_vif *vif, bool enable) 1231 1217 { 1232 - return mt7996_mcu_sta_ba(dev, &link->mt76, params, enable, false); 1218 + struct ieee80211_sta *sta = params->sta; 1219 + struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 1220 + struct ieee80211_link_sta *link_sta; 1221 + unsigned int link_id; 1222 + int ret = 0; 1223 + 1224 + for_each_sta_active_link(vif, sta, link_sta, link_id) { 1225 + struct mt7996_sta_link *msta_link; 1226 + struct mt7996_vif_link *link; 1227 + 1228 + msta_link = mt76_dereference(msta->link[link_id], &dev->mt76); 1229 + if (!msta_link) 1230 + continue; 1231 + 1232 + link = mt7996_vif_link(dev, vif, link_id); 1233 + if (!link) 1234 + continue; 1235 + 1236 + ret = mt7996_mcu_sta_ba(dev, &link->mt76, params, 1237 + &msta_link->wcid, enable, false); 1238 + if (ret) 1239 + break; 1240 + } 1241 + 1242 + return ret; 1233 1243 } 1234 1244 1235 1245 static void ··· 1837 1753 bf->mem_20m = bf->nrow < BF_MAT_ORDER ? 1838 1754 matrix[bf->nrow][bf->ncol] : 0; 1839 1755 } 1840 - 1841 - switch (link_sta->bandwidth) { 1842 - case IEEE80211_STA_RX_BW_160: 1843 - case IEEE80211_STA_RX_BW_80: 1844 - bf->mem_total = bf->mem_20m * 2; 1845 - break; 1846 - case IEEE80211_STA_RX_BW_40: 1847 - bf->mem_total = bf->mem_20m; 1848 - break; 1849 - case IEEE80211_STA_RX_BW_20: 1850 - default: 1851 - break; 1852 - } 1853 1756 } 1854 1757 1855 1758 static void ··· 2336 2265 } 2337 2266 2338 2267 static int 2339 - mt7996_mcu_add_group(struct mt7996_dev *dev, struct ieee80211_vif *vif, 2340 - struct ieee80211_sta *sta) 2268 + mt7996_mcu_add_group(struct mt7996_dev *dev, struct mt7996_vif_link *link, 2269 + struct mt76_wcid *wcid) 2341 2270 { 2342 2271 #define MT_STA_BSS_GROUP 1 2343 - struct mt7996_vif *mvif = (struct mt7996_vif *)vif->drv_priv; 2344 - struct mt7996_sta_link *msta_link; 2345 - struct mt7996_sta *msta; 2346 2272 struct { 2347 2273 u8 __rsv1[4]; 2348 2274 ··· 2354 2286 .tag = cpu_to_le16(UNI_VOW_DRR_CTRL), 2355 2287 .len = cpu_to_le16(sizeof(req) - 4), 2356 2288 .action = cpu_to_le32(MT_STA_BSS_GROUP), 2357 - .val = cpu_to_le32(mvif->deflink.mt76.idx % 16), 2289 + .val = cpu_to_le32(link->mt76.idx % 16), 2290 + .wlan_idx = cpu_to_le16(wcid->idx), 2358 2291 }; 2359 - 2360 - msta = sta ? (struct mt7996_sta *)sta->drv_priv : NULL; 2361 - msta_link = msta ? &msta->deflink : &mvif->deflink.msta_link; 2362 - req.wlan_idx = cpu_to_le16(msta_link->wcid.idx); 2363 2292 2364 2293 return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(VOW), &req, 2365 2294 sizeof(req), true); ··· 2497 2432 } 2498 2433 } 2499 2434 2500 - ret = mt7996_mcu_add_group(dev, link_conf->vif, sta); 2435 + ret = mt7996_mcu_add_group(dev, link, wcid); 2501 2436 if (ret) { 2502 2437 dev_kfree_skb(skb); 2503 2438 return ret; ··· 2532 2467 enum set_key_cmd cmd) 2533 2468 { 2534 2469 struct sta_rec_sec_uni *sec; 2470 + struct sec_key_uni *sec_key; 2535 2471 struct tlv *tlv; 2472 + u8 cipher; 2536 2473 2537 2474 tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_KEY_V2, sizeof(*sec)); 2538 2475 sec = (struct sta_rec_sec_uni *)tlv; 2539 - sec->add = cmd; 2476 + sec->add = 0; 2477 + sec->n_cipher = 1; 2478 + sec_key = &sec->key[0]; 2479 + sec_key->wlan_idx = cpu_to_le16(wcid->idx); 2480 + sec_key->key_id = key->keyidx; 2540 2481 2541 - if (cmd == SET_KEY) { 2542 - struct sec_key_uni *sec_key; 2543 - u8 cipher; 2482 + if (cmd != SET_KEY) 2483 + return 0; 2544 2484 2545 - cipher = mt76_connac_mcu_get_cipher(key->cipher); 2546 - if (cipher == MCU_CIPHER_NONE) 2547 - return -EOPNOTSUPP; 2485 + cipher = mt76_connac_mcu_get_cipher(key->cipher); 2486 + if (cipher == MCU_CIPHER_NONE) 2487 + return -EOPNOTSUPP; 2548 2488 2549 - sec_key = &sec->key[0]; 2550 - sec_key->wlan_idx = cpu_to_le16(wcid->idx); 2551 - sec_key->mgmt_prot = 0; 2552 - sec_key->cipher_id = cipher; 2553 - sec_key->cipher_len = sizeof(*sec_key); 2554 - sec_key->key_id = key->keyidx; 2555 - sec_key->key_len = key->keylen; 2556 - sec_key->need_resp = 0; 2557 - memcpy(sec_key->key, key->key, key->keylen); 2489 + sec_key->mgmt_prot = 0; 2490 + sec_key->cipher_id = cipher; 2491 + sec_key->cipher_len = sizeof(*sec_key); 2492 + sec_key->key_len = key->keylen; 2493 + sec_key->need_resp = 0; 2494 + memcpy(sec_key->key, key->key, key->keylen); 2558 2495 2559 - if (cipher == MCU_CIPHER_TKIP) { 2560 - /* Rx/Tx MIC keys are swapped */ 2561 - memcpy(sec_key->key + 16, key->key + 24, 8); 2562 - memcpy(sec_key->key + 24, key->key + 16, 8); 2563 - } 2564 - 2565 - sec->n_cipher = 1; 2566 - } else { 2567 - sec->n_cipher = 0; 2496 + if (cipher == MCU_CIPHER_TKIP) { 2497 + /* Rx/Tx MIC keys are swapped */ 2498 + memcpy(sec_key->key + 16, key->key + 24, 8); 2499 + memcpy(sec_key->key + 24, key->key + 16, 8); 2500 + return 0; 2568 2501 } 2502 + 2503 + if (sec_key->key_id != 6 && sec_key->key_id != 7) 2504 + return 0; 2505 + 2506 + switch (key->cipher) { 2507 + case WLAN_CIPHER_SUITE_AES_CMAC: 2508 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_CMAC_128; 2509 + break; 2510 + case WLAN_CIPHER_SUITE_BIP_GMAC_128: 2511 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_128; 2512 + break; 2513 + case WLAN_CIPHER_SUITE_BIP_GMAC_256: 2514 + sec_key->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_256; 2515 + break; 2516 + default: 2517 + return -EOPNOTSUPP; 2518 + } 2519 + 2520 + sec_key->bcn_mode = BP_SW_MODE; 2569 2521 2570 2522 return 0; 2571 2523 } ··· 2601 2519 return PTR_ERR(skb); 2602 2520 2603 2521 ret = mt7996_mcu_sta_key_tlv(wcid, skb, key, cmd); 2604 - if (ret) 2605 - return ret; 2606 - 2607 - return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true); 2608 - } 2609 - 2610 - static int mt7996_mcu_get_pn(struct mt7996_dev *dev, 2611 - struct mt7996_vif_link *link, 2612 - struct mt7996_sta_link *msta_link, u8 *pn) 2613 - { 2614 - #define TSC_TYPE_BIGTK_PN 2 2615 - struct sta_rec_pn_info *pn_info; 2616 - struct sk_buff *skb, *rskb; 2617 - struct tlv *tlv; 2618 - int ret; 2619 - 2620 - skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &link->mt76, 2621 - &msta_link->wcid); 2622 - if (IS_ERR(skb)) 2623 - return PTR_ERR(skb); 2624 - 2625 - tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_PN_INFO, sizeof(*pn_info)); 2626 - pn_info = (struct sta_rec_pn_info *)tlv; 2627 - 2628 - pn_info->tsc_type = TSC_TYPE_BIGTK_PN; 2629 - ret = mt76_mcu_skb_send_and_get_msg(&dev->mt76, skb, 2630 - MCU_WM_UNI_CMD_QUERY(STA_REC_UPDATE), 2631 - true, &rskb); 2632 - if (ret) 2633 - return ret; 2634 - 2635 - skb_pull(rskb, 4); 2636 - 2637 - pn_info = (struct sta_rec_pn_info *)rskb->data; 2638 - if (le16_to_cpu(pn_info->tag) == STA_REC_PN_INFO) 2639 - memcpy(pn, pn_info->pn, 6); 2640 - 2641 - dev_kfree_skb(rskb); 2642 - return 0; 2643 - } 2644 - 2645 - int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, 2646 - struct mt7996_vif_link *link, 2647 - struct mt7996_sta_link *msta_link, 2648 - struct ieee80211_key_conf *key) 2649 - { 2650 - struct mt7996_mcu_bcn_prot_tlv *bcn_prot; 2651 - struct sk_buff *skb; 2652 - struct tlv *tlv; 2653 - u8 pn[6] = {}; 2654 - int len = sizeof(struct bss_req_hdr) + 2655 - sizeof(struct mt7996_mcu_bcn_prot_tlv); 2656 - int ret; 2657 - 2658 - skb = __mt7996_mcu_alloc_bss_req(&dev->mt76, &link->mt76, len); 2659 - if (IS_ERR(skb)) 2660 - return PTR_ERR(skb); 2661 - 2662 - tlv = mt76_connac_mcu_add_tlv(skb, UNI_BSS_INFO_BCN_PROT, sizeof(*bcn_prot)); 2663 - 2664 - bcn_prot = (struct mt7996_mcu_bcn_prot_tlv *)tlv; 2665 - 2666 - ret = mt7996_mcu_get_pn(dev, link, msta_link, pn); 2667 2522 if (ret) { 2668 2523 dev_kfree_skb(skb); 2669 2524 return ret; 2670 2525 } 2671 2526 2672 - switch (key->cipher) { 2673 - case WLAN_CIPHER_SUITE_AES_CMAC: 2674 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_CMAC_128; 2675 - break; 2676 - case WLAN_CIPHER_SUITE_BIP_GMAC_128: 2677 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_128; 2678 - break; 2679 - case WLAN_CIPHER_SUITE_BIP_GMAC_256: 2680 - bcn_prot->cipher_id = MCU_CIPHER_BCN_PROT_GMAC_256; 2681 - break; 2682 - case WLAN_CIPHER_SUITE_BIP_CMAC_256: 2683 - default: 2684 - dev_err(dev->mt76.dev, "Not supported Bigtk Cipher\n"); 2685 - dev_kfree_skb(skb); 2686 - return -EOPNOTSUPP; 2687 - } 2688 - 2689 - pn[0]++; 2690 - memcpy(bcn_prot->pn, pn, 6); 2691 - bcn_prot->enable = BP_SW_MODE; 2692 - memcpy(bcn_prot->key, key->key, WLAN_MAX_KEY_LEN); 2693 - bcn_prot->key_id = key->keyidx; 2694 - 2695 - return mt76_mcu_skb_send_msg(&dev->mt76, skb, 2696 - MCU_WMWA_UNI_CMD(BSS_INFO_UPDATE), true); 2527 + return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true); 2697 2528 } 2698 2529 2699 2530 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, ··· 2747 2752 } 2748 2753 2749 2754 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2750 - struct ieee80211_bss_conf *link_conf) 2755 + struct ieee80211_bss_conf *link_conf, bool enabled) 2751 2756 { 2752 2757 struct mt7996_dev *dev = mt7996_hw_dev(hw); 2753 2758 struct mt7996_vif_link *link = mt7996_vif_conf_link(dev, vif, link_conf); ··· 2758 2763 struct tlv *tlv; 2759 2764 struct bss_bcn_content_tlv *bcn; 2760 2765 int len, extra_len = 0; 2761 - bool enabled = link_conf->enable_beacon; 2762 2766 2763 2767 if (link_conf->nontransmitted) 2764 2768 return 0;

+5 -12

drivers/net/wireless/mediatek/mt76/mt7996/mcu.h

··· 351 351 BP_HW_MODE, 352 352 }; 353 353 354 - struct mt7996_mcu_bcn_prot_tlv { 355 - __le16 tag; 356 - __le16 len; 357 - u8 pn[6]; 358 - u8 enable; 359 - u8 cipher_id; 360 - u8 key[WLAN_MAX_KEY_LEN]; 361 - u8 key_id; 362 - u8 __rsv[3]; 363 - } __packed; 364 - 365 354 struct bss_ra_tlv { 366 355 __le16 tag; 367 356 __le16 len; ··· 470 481 u8 own_mld_id; 471 482 u8 mac_addr[ETH_ALEN]; 472 483 u8 remap_idx; 473 - u8 __rsv[3]; 484 + u8 link_id; 485 + u8 __rsv[2]; 474 486 } __packed; 475 487 476 488 struct sta_rec_ht_uni { ··· 520 530 u8 key_len; 521 531 u8 need_resp; 522 532 u8 key[32]; 533 + u8 pn[6]; 534 + u8 bcn_mode; 535 + u8 _rsv; 523 536 } __packed; 524 537 525 538 struct sta_rec_sec_uni {

+66 -23

drivers/net/wireless/mediatek/mt76/mt7996/mmio.c

··· 459 459 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 460 460 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 461 461 struct pci_dev *pci_dev = pdev_ptr; 462 - u32 hif1_ofs = 0; 462 + u32 hif1_ofs; 463 463 464 464 if (!wed_enable) 465 465 return 0; 466 466 467 - dev->has_rro = true; 467 + dev->mt76.hwrro_mode = is_mt7996(&dev->mt76) ? MT76_HWRRO_V3 468 + : MT76_HWRRO_V3_1; 468 469 469 - hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 470 + hif1_ofs = dev->hif2 ? MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0) : 0; 470 471 471 472 if (hif2) 472 473 wed = &dev->mt76.mmio.wed_hif2; ··· 491 490 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 492 491 MT_TXQ_RING_BASE(0) + 493 492 MT7996_TXQ_BAND2 * MT_RING_SIZE; 494 - if (dev->has_rro) { 495 - wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 496 - MT_RXQ_RING_BASE(0) + 497 - MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 498 - wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 493 + if (mt7996_has_hwrro(dev)) { 494 + if (is_mt7996(&dev->mt76)) { 495 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 496 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 497 + MT_RXQ_RING_BASE(0) + 498 + MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 499 + } else { 500 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_BAND1_EXT) - 1; 501 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 502 + MT_RXQ_RING_BASE(0) + 503 + MT7996_RXQ_MCU_WA_EXT * MT_RING_SIZE; 504 + } 499 505 } else { 500 506 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 501 507 MT_RXQ_RING_BASE(0) + ··· 512 504 513 505 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 514 506 wed->wlan.wpdma_rx[0] = wed->wlan.phy_base + hif1_ofs + 515 - MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 516 - MT7996_RXQ_BAND0 * MT_RING_SIZE; 507 + MT_RXQ_RING_BASE(MT7996_RXQ_BAND2) + 508 + MT7996_RXQ_BAND2 * MT_RING_SIZE; 517 509 518 510 wed->wlan.id = MT7996_DEVICE_ID_2; 519 511 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 520 512 } else { 521 - wed->wlan.hw_rro = dev->has_rro; /* default on */ 513 + wed->wlan.hw_rro = mt7996_has_hwrro(dev); 522 514 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 523 515 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 524 516 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + ··· 533 525 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 534 526 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 535 527 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 536 - wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 537 - MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 538 - MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 528 + if (is_mt7996(&dev->mt76)) { 529 + wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 530 + MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 531 + MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 532 + } else { 533 + wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 534 + MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND1) + 535 + MT7996_RXQ_RRO_BAND1 * MT_RING_SIZE; 536 + wed->wlan.wpdma_rx[1] = wed->wlan.phy_base + hif1_ofs + 537 + MT_RXQ_RING_BASE(MT7996_RXQ_BAND1) + 538 + MT7996_RXQ_BAND1 * MT_RING_SIZE; 539 + } 540 + 539 541 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 540 542 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 541 543 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; ··· 555 537 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 556 538 557 539 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 558 - wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 559 - 560 540 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 561 - wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 541 + if (is_mt7996(&dev->mt76)) { 542 + wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 543 + wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 544 + } else { 545 + wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND1) - 1; 546 + wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND1) - 1; 547 + } 562 548 563 549 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 564 550 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; ··· 570 548 571 549 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 572 550 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 573 - if (dev->has_rro) { 574 - wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 575 - MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 576 - wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 551 + if (is_mt7996(&dev->mt76)) { 552 + if (mt7996_has_hwrro(dev)) { 553 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + 554 + MT_RXQ_RING_BASE(0) + 555 + MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 556 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 557 + } else { 558 + wed->wlan.wpdma_txfree = wed->wlan.phy_base + 559 + MT_RXQ_RING_BASE(0) + 560 + MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 561 + wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 562 + } 577 563 } else { 578 564 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 579 565 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 580 566 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 581 567 } 582 568 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 569 + 570 + if (dev->hif2 && is_mt7992(&dev->mt76)) 571 + wed->wlan.id = 0x7992; 583 572 } 584 573 585 574 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; ··· 609 576 wed->wlan.reset_complete = mt76_wed_reset_complete; 610 577 } 611 578 612 - if (mtk_wed_device_attach(wed)) 579 + if (mtk_wed_device_attach(wed)) { 580 + dev->mt76.hwrro_mode = MT76_HWRRO_OFF; 613 581 return 0; 582 + } 614 583 615 584 *irq = wed->irq; 616 585 dev->mt76.dma_dev = wed->dev; ··· 725 690 dev->mt76.mmio.irqmask); 726 691 if (intr1 & MT_INT_RX_TXFREE_EXT) 727 692 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 693 + 694 + if (intr1 & MT_INT_RX_DONE_BAND2_EXT) 695 + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND2]); 696 + 697 + if (intr1 & MT_INT_RX_TXFREE_BAND1_EXT) 698 + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 728 699 } 729 700 730 701 if (mtk_wed_device_active(wed)) { 731 702 mtk_wed_device_irq_set_mask(wed, 0); 732 703 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 733 - intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); 704 + intr |= (intr1 & ~MT_INT_TX_RX_DONE_EXT); 734 705 } else { 735 706 mt76_wr(dev, MT_INT_MASK_CSR, 0); 736 707 if (dev->hif2) ··· 822 781 .rx_skb = mt7996_queue_rx_skb, 823 782 .rx_check = mt7996_rx_check, 824 783 .rx_poll_complete = mt7996_rx_poll_complete, 784 + .rx_rro_ind_process = mt7996_rro_rx_process, 785 + .rx_rro_add_msdu_page = mt7996_rro_msdu_page_add, 825 786 .update_survey = mt7996_update_channel, 826 787 .set_channel = mt7996_set_channel, 827 788 .vif_link_add = mt7996_vif_link_add,

+92 -14

drivers/net/wireless/mediatek/mt76/mt7996/mt7996.h

··· 112 112 #define MT7996_CRIT_TEMP 110 113 113 #define MT7996_MAX_TEMP 120 114 114 115 + #define MT7996_MAX_HIF_RXD_IN_PG 5 116 + #define MT7996_RRO_MSDU_PG_HASH_SIZE 127 115 117 #define MT7996_RRO_MAX_SESSION 1024 116 118 #define MT7996_RRO_WINDOW_MAX_LEN 1024 117 119 #define MT7996_RRO_ADDR_ELEM_LEN 128 ··· 129 127 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 130 128 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 131 129 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 130 + 131 + /* RRO 3.1 */ 132 + #define MT7996_RRO_MSDU_PG_CR_CNT 8 133 + #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000 132 134 133 135 struct mt7996_vif; 134 136 struct mt7996_sta; ··· 184 178 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 185 179 MT7996_RXQ_BAND2 = 5, 186 180 MT7996_RXQ_RRO_BAND0 = 8, 187 - MT7996_RXQ_RRO_BAND1 = 8,/* unused */ 181 + MT7996_RXQ_RRO_BAND1 = 9, 188 182 MT7996_RXQ_RRO_BAND2 = 6, 189 183 MT7996_RXQ_MSDU_PG_BAND0 = 10, 190 184 MT7996_RXQ_MSDU_PG_BAND1 = 11, ··· 193 187 MT7996_RXQ_TXFREE1 = 9, 194 188 MT7996_RXQ_TXFREE2 = 7, 195 189 MT7996_RXQ_RRO_IND = 0, 190 + MT7996_RXQ_RRO_RXDMAD_C = 0, 196 191 MT7990_RXQ_TXFREE0 = 6, 197 192 MT7990_RXQ_TXFREE1 = 7, 198 193 }; ··· 255 248 256 249 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 257 250 struct cfg80211_bitrate_mask bitrate_mask; 251 + 252 + u8 mld_idx; 258 253 }; 259 254 260 255 struct mt7996_vif { 261 256 struct mt7996_vif_link deflink; /* must be first */ 262 257 struct mt76_vif_data mt76; 258 + 259 + u8 mld_group_idx; 260 + u8 mld_remap_idx; 263 261 }; 264 262 265 263 /* crash-dump */ ··· 282 270 struct device *dev; 283 271 void __iomem *regs; 284 272 int irq; 273 + 274 + enum pci_bus_speed speed; 275 + enum pcie_link_width width; 285 276 }; 286 277 278 + #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24) 279 + #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4) 280 + #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0) 287 281 struct mt7996_wed_rro_addr { 288 - u32 head_low; 289 - u32 head_high : 4; 290 - u32 count: 11; 291 - u32 oor: 1; 292 - u32 rsv : 8; 293 - u32 signature : 8; 282 + __le32 head_low; 283 + __le32 data; 294 284 }; 295 285 296 286 struct mt7996_wed_rro_session_id { 297 287 struct list_head list; 298 288 u16 id; 289 + }; 290 + 291 + struct mt7996_msdu_page { 292 + struct list_head list; 293 + 294 + struct mt76_queue *q; 295 + dma_addr_t dma_addr; 296 + void *buf; 297 + }; 298 + 299 + /* data1 */ 300 + #define RRO_HIF_DATA1_LS_MASK BIT(30) 301 + #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16) 302 + /* data4 */ 303 + #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0) 304 + struct mt7996_rro_hif { 305 + __le32 data0; 306 + __le32 data1; 307 + __le32 data2; 308 + __le32 data3; 309 + __le32 data4; 310 + __le32 data5; 311 + }; 312 + 313 + #define MSDU_PAGE_INFO_OWNER_MASK BIT(31) 314 + #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0) 315 + struct mt7996_msdu_page_info { 316 + struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG]; 317 + __le32 pg_low; 318 + __le32 data; 319 + }; 320 + 321 + #define MT7996_MAX_RRO_RRS_RING 4 322 + struct mt7996_rro_queue_regs_emi { 323 + struct { 324 + __le16 idx; 325 + __le16 rsv; 326 + } ring[MT7996_MAX_RRO_RRS_RING]; 299 327 }; 300 328 301 329 struct mt7996_phy { ··· 389 337 u32 q_int_mask[MT7996_MAX_QUEUE]; 390 338 u32 q_wfdma_mask; 391 339 340 + u64 mld_idx_mask; 341 + u64 mld_remap_idx_mask; 342 + 392 343 const struct mt76_bus_ops *bus_ops; 393 344 struct mt7996_phy phy; 394 345 ··· 432 377 433 378 bool flash_mode:1; 434 379 bool has_eht:1; 435 - bool has_rro:1; 436 380 437 381 struct { 438 382 struct { ··· 446 392 void *ptr; 447 393 dma_addr_t phy_addr; 448 394 } session; 395 + struct { 396 + void *ptr; 397 + dma_addr_t phy_addr; 398 + } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT]; 399 + struct { 400 + struct mt7996_rro_queue_regs_emi *ptr; 401 + dma_addr_t phy_addr; 402 + } emi_rings_cpu; 403 + struct { 404 + struct mt7996_rro_queue_regs_emi *ptr; 405 + dma_addr_t phy_addr; 406 + } emi_rings_dma; 449 407 450 408 struct work_struct work; 451 409 struct list_head poll_list; 452 410 spinlock_t lock; 411 + 412 + struct list_head page_cache; 413 + struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE]; 453 414 } wed_rro; 454 415 455 416 bool ibf; ··· 621 552 622 553 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 623 554 void __iomem *mem_base, u32 device_id); 555 + void mt7996_rro_hw_init(struct mt7996_dev *dev); 624 556 void mt7996_wfsys_reset(struct mt7996_dev *dev); 625 557 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 626 558 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link); ··· 674 604 struct mt7996_sta_link *msta_link); 675 605 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 676 606 struct ieee80211_ampdu_params *params, 677 - struct mt7996_vif_link *link, 678 - struct mt7996_sta_link *msta_link, bool enable); 607 + struct ieee80211_vif *vif, bool enable); 679 608 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 680 609 struct ieee80211_ampdu_params *params, 681 - struct mt7996_vif_link *link, bool enable); 610 + struct ieee80211_vif *vif, bool enable); 682 611 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 683 612 struct mt76_vif_link *mlink, 684 613 struct cfg80211_he_bss_color *he_bss_color); 685 614 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 686 - struct ieee80211_bss_conf *link_conf); 615 + struct ieee80211_bss_conf *link_conf, bool enabled); 687 616 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 688 617 struct ieee80211_bss_conf *link_conf, 689 618 struct mt7996_vif_link *link, u32 changed); ··· 737 668 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 738 669 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 739 670 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 671 + 672 + static inline bool mt7996_has_hwrro(struct mt7996_dev *dev) 673 + { 674 + return dev->mt76.hwrro_mode != MT76_HWRRO_OFF; 675 + } 740 676 741 677 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 742 678 { ··· 817 743 struct mt7996_vif_link *link, 818 744 struct mt7996_sta_link *msta_link, 819 745 u8 flowid); 746 + void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev, 747 + struct mt7996_sta_link *msta_link); 820 748 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 821 749 struct ieee80211_sta *sta, 822 750 struct ieee80211_twt_setup *twt); ··· 829 753 void mt7996_tx_token_put(struct mt7996_dev *dev); 830 754 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 831 755 struct sk_buff *skb, u32 *info); 756 + void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev); 757 + int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q, 758 + dma_addr_t dma_addr, void *data); 759 + void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data); 832 760 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 833 761 void mt7996_stats_work(struct work_struct *work); 834 762 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); ··· 867 787 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); 868 788 #endif 869 789 870 - #ifdef CONFIG_NET_MEDIATEK_SOC_WED 871 790 int mt7996_dma_rro_init(struct mt7996_dev *dev); 872 - #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 873 791 874 792 #endif

+2 -1

drivers/net/wireless/mediatek/mt76/mt7996/pci.c

··· 87 87 hif->dev = &pdev->dev; 88 88 hif->regs = pcim_iomap_table(pdev)[0]; 89 89 hif->irq = pdev->irq; 90 + pcie_bandwidth_available(pdev, NULL, &hif->speed, &hif->width); 90 91 spin_lock_bh(&hif_lock); 91 92 list_add(&hif->list, &hif_list); 92 93 spin_unlock_bh(&hif_lock); ··· 138 137 mdev = &dev->mt76; 139 138 mt7996_wfsys_reset(dev); 140 139 hif2 = mt7996_pci_init_hif2(pdev); 140 + dev->hif2 = hif2; 141 141 142 142 ret = mt7996_mmio_wed_init(dev, pdev, false, &irq); 143 143 if (ret < 0) ··· 163 161 164 162 if (hif2) { 165 163 hif2_dev = container_of(hif2->dev, struct pci_dev, dev); 166 - dev->hif2 = hif2; 167 164 168 165 ret = mt7996_mmio_wed_init(dev, hif2_dev, true, &hif2_irq); 169 166 if (ret < 0)

+31 -1

drivers/net/wireless/mediatek/mt76/mt7996/regs.h

··· 88 88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC) 89 89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8) 90 90 #define WF_RRO_AXI_MST_CFG_DIDX_OK BIT(12) 91 + 92 + #define MT_RRO_ADDR_ARRAY_BASE0 MT_RRO_TOP(0x30) 91 93 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34) 92 94 #define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE BIT(31) 93 95 ··· 109 107 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0) 110 108 111 109 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400) 110 + 111 + #define MT_RRO_3_0_EMU_CONF MT_RRO_TOP(0x600) 112 + #define MT_RRO_3_0_EMU_CONF_EN_MASK BIT(11) 113 + 114 + #define MT_RRO_3_1_GLOBAL_CONFIG MT_RRO_TOP(0x604) 115 + #define MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL BIT(6) 116 + #define MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN BIT(3) 117 + #define MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN BIT(2) 118 + #define MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN BIT(0) 119 + 120 + #define MT_RRO_MSDU_PG_SEG_ADDR0 MT_RRO_TOP(0x620) 121 + #define MT_RRO_RX_RING_AP_CIDX_ADDR MT_RRO_TOP(0x6f0) 122 + #define MT_RRO_RX_RING_AP_DIDX_ADDR MT_RRO_TOP(0x6f4) 112 123 113 124 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50) 114 125 #define MT_RRO_ACK_SN_CTRL_SN_MASK GENMASK(27, 16) ··· 427 412 428 413 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154) 429 414 #define MT_WFDMA0_RX_INT_SEL_RING3 BIT(3) 415 + #define MT_WFDMA0_RX_INT_SEL_RING5 BIT(5) 430 416 #define MT_WFDMA0_RX_INT_SEL_RING6 BIT(6) 417 + #define MT_WFDMA0_RX_INT_SEL_RING9 BIT(9) 431 418 432 419 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 433 420 ··· 447 430 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) 448 431 449 432 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) 433 + #define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24) 450 434 #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) 451 435 #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) 452 436 ··· 469 451 470 452 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) 471 453 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 454 + #define MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 BIT(20) 455 + #define MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 BIT(21) 472 456 #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) 473 457 474 458 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) ··· 478 458 479 459 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) 480 460 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) 461 + 462 + #define MT_WFDMA_AXI_R2A_CTRL2 MT_WFDMA_EXT_CSR(0x508) 463 + #define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28) 481 464 482 465 #define MT_PCIE_RECOG_ID 0xd7090 483 466 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) ··· 515 492 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 516 493 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40) 517 494 495 + #define MT_RXQ_RRO_AP_RING_BASE MT_RRO_TOP(0x650) 496 + 518 497 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 519 498 MT_MCUQ_ID(q) * 0x4) 520 499 #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ ··· 539 514 #define MT_INT_RX_DONE_WA_EXT BIT(3) /* for mt7992 */ 540 515 #define MT_INT_RX_DONE_WA_TRI BIT(3) 541 516 #define MT_INT_RX_TXFREE_MAIN BIT(17) 517 + #define MT_INT_RX_TXFREE_BAND1 BIT(15) 542 518 #define MT_INT_RX_TXFREE_TRI BIT(15) 519 + #define MT_INT_RX_TXFREE_BAND1_EXT BIT(19) /* for mt7992 two PCIE*/ 543 520 #define MT_INT_RX_TXFREE_BAND0_MT7990 BIT(14) 544 521 #define MT_INT_RX_TXFREE_BAND1_MT7990 BIT(15) 545 522 #define MT_INT_RX_DONE_BAND2_EXT BIT(23) ··· 549 522 #define MT_INT_MCU_CMD BIT(29) 550 523 551 524 #define MT_INT_RX_DONE_RRO_BAND0 BIT(16) 552 - #define MT_INT_RX_DONE_RRO_BAND1 BIT(16) 525 + #define MT_INT_RX_DONE_RRO_BAND1 BIT(17) 553 526 #define MT_INT_RX_DONE_RRO_BAND2 BIT(14) 554 527 #define MT_INT_RX_DONE_RRO_IND BIT(11) 528 + #define MT_INT_RX_DONE_RRO_RXDMAD_C BIT(11) 555 529 #define MT_INT_RX_DONE_MSDU_PG_BAND0 BIT(18) 556 530 #define MT_INT_RX_DONE_MSDU_PG_BAND1 BIT(19) 557 531 #define MT_INT_RX_DONE_MSDU_PG_BAND2 BIT(23) ··· 580 552 #define MT_INT_RRO_RX_DONE (MT_INT_RX(MT_RXQ_RRO_BAND0) | \ 581 553 MT_INT_RX(MT_RXQ_RRO_BAND1) | \ 582 554 MT_INT_RX(MT_RXQ_RRO_BAND2) | \ 555 + MT_INT_RX(MT_RXQ_RRO_IND) | \ 556 + MT_INT_RX(MT_RXQ_RRO_RXDMAD_C) | \ 583 557 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND0) | \ 584 558 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND1) | \ 585 559 MT_INT_RX(MT_RXQ_MSDU_PAGE_BAND2))

+7 -6

drivers/net/wireless/mediatek/mt76/scan.c

··· 16 16 17 17 clear_bit(MT76_SCANNING, &phy->state); 18 18 19 - if (dev->scan.chan && phy->main_chandef.chan) 19 + if (dev->scan.chan && phy->main_chandef.chan && 20 + !test_bit(MT76_MCU_RESET, &dev->phy.state)) 20 21 mt76_set_channel(phy, &phy->main_chandef, false); 21 22 mt76_put_vif_phy_link(phy, dev->scan.vif, dev->scan.mlink); 22 23 memset(&dev->scan, 0, sizeof(dev->scan)); 23 - ieee80211_scan_completed(phy->hw, &info); 24 + if (!test_bit(MT76_MCU_RESET, &dev->phy.state)) 25 + ieee80211_scan_completed(phy->hw, &info); 24 26 } 25 27 26 28 void mt76_abort_scan(struct mt76_dev *dev) ··· 30 28 cancel_delayed_work_sync(&dev->scan_work); 31 29 mt76_scan_complete(dev, true); 32 30 } 31 + EXPORT_SYMBOL_GPL(mt76_abort_scan); 33 32 34 33 static void 35 34 mt76_scan_send_probe(struct mt76_dev *dev, struct cfg80211_ssid *ssid) ··· 115 112 local_bh_enable(); 116 113 117 114 out: 118 - if (!duration) 119 - return; 120 - 121 115 if (dev->scan.chan) 122 116 duration = max_t(int, duration, 123 117 msecs_to_jiffies(req->duration + ··· 139 139 140 140 mutex_lock(&dev->mutex); 141 141 142 - if (dev->scan.req || phy->roc_vif) { 142 + if (dev->scan.req || phy->roc_vif || 143 + test_bit(MT76_MCU_RESET, &dev->phy.state)) { 143 144 ret = -EBUSY; 144 145 goto out; 145 146 }

+2 -1

drivers/net/wireless/mediatek/mt76/tx.c

··· 618 618 !(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 619 619 !ieee80211_is_data(hdr->frame_control) && 620 620 (!ieee80211_is_bufferable_mmpdu(skb) || 621 - ieee80211_is_deauth(hdr->frame_control))) 621 + ieee80211_is_deauth(hdr->frame_control) || 622 + head == &wcid->tx_offchannel)) 622 623 qid = MT_TXQ_PSD; 623 624 624 625 q = phy->q_tx[qid];

+4 -4

drivers/net/wireless/mediatek/mt76/wed.c

··· 118 118 case MT76_WED_Q_TXFREE: 119 119 /* WED txfree queue needs ring to be initialized before setup */ 120 120 q->flags = 0; 121 - mt76_dma_queue_reset(dev, q); 121 + mt76_dma_queue_reset(dev, q, true); 122 122 mt76_dma_rx_fill(dev, q, false); 123 123 124 124 ret = mtk_wed_device_txfree_ring_setup(q->wed, q->regs); ··· 133 133 break; 134 134 case MT76_WED_RRO_Q_DATA: 135 135 q->flags &= ~MT_QFLAG_WED; 136 - __mt76_dma_queue_reset(dev, q, false); 136 + mt76_dma_queue_reset(dev, q, false); 137 137 mtk_wed_device_rro_rx_ring_setup(q->wed, ring, q->regs); 138 138 q->head = q->ndesc - 1; 139 139 q->queued = q->head; 140 140 break; 141 141 case MT76_WED_RRO_Q_MSDU_PG: 142 142 q->flags &= ~MT_QFLAG_WED; 143 - __mt76_dma_queue_reset(dev, q, false); 143 + mt76_dma_queue_reset(dev, q, false); 144 144 mtk_wed_device_msdu_pg_rx_ring_setup(q->wed, ring, q->regs); 145 145 q->head = q->ndesc - 1; 146 146 q->queued = q->head; 147 147 break; 148 148 case MT76_WED_RRO_Q_IND: 149 149 q->flags &= ~MT_QFLAG_WED; 150 - mt76_dma_queue_reset(dev, q); 150 + mt76_dma_queue_reset(dev, q, true); 151 151 mt76_dma_rx_fill(dev, q, false); 152 152 mtk_wed_device_ind_rx_ring_setup(q->wed, q->regs); 153 153 break;

+24 -3

drivers/net/wireless/realtek/rtl8xxxu/core.c

··· 1901 1901 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); 1902 1902 } 1903 1903 1904 + static ssize_t read_file_efuse(struct file *file, char __user *user_buf, 1905 + size_t count, loff_t *ppos) 1906 + { 1907 + struct rtl8xxxu_priv *priv = file_inode(file)->i_private; 1908 + 1909 + return simple_read_from_buffer(user_buf, count, ppos, 1910 + priv->efuse_wifi.raw, EFUSE_MAP_LEN); 1911 + } 1912 + 1913 + static const struct debugfs_short_fops fops_efuse = { 1914 + .read = read_file_efuse, 1915 + }; 1916 + 1917 + static void rtl8xxxu_debugfs_init(struct rtl8xxxu_priv *priv) 1918 + { 1919 + struct dentry *phydir; 1920 + 1921 + phydir = debugfs_create_dir("rtl8xxxu", priv->hw->wiphy->debugfsdir); 1922 + debugfs_create_file("efuse", 0400, phydir, priv, &fops_efuse); 1923 + } 1924 + 1904 1925 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) 1905 1926 { 1906 1927 u8 val8; ··· 7836 7815 untested = 0; 7837 7816 break; 7838 7817 case 0x2357: 7839 - if (id->idProduct == 0x0109 || id->idProduct == 0x0135) 7818 + if (id->idProduct == 0x0109 || id->idProduct == 0x010c || 7819 + id->idProduct == 0x0135) 7840 7820 untested = 0; 7841 7821 break; 7842 7822 case 0x0b05: ··· 7996 7974 } 7997 7975 7998 7976 rtl8xxxu_init_led(priv); 7977 + rtl8xxxu_debugfs_init(priv); 7999 7978 8000 7979 return 0; 8001 7980 ··· 8194 8171 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x11f2, 0xff, 0xff, 0xff), 8195 8172 .driver_info = (unsigned long)&rtl8192cu_fops}, 8196 8173 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), 8197 - .driver_info = (unsigned long)&rtl8192cu_fops}, 8198 - {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8188, 0xff, 0xff, 0xff), 8199 8174 .driver_info = (unsigned long)&rtl8192cu_fops}, 8200 8175 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), 8201 8176 .driver_info = (unsigned long)&rtl8192cu_fops},

-1

drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c

··· 291 291 {RTL_USB_DEVICE(0x050d, 0x1102, rtl92cu_hal_cfg)}, /*Belkin - Edimax*/ 292 292 {RTL_USB_DEVICE(0x050d, 0x11f2, rtl92cu_hal_cfg)}, /*Belkin - ISY*/ 293 293 {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/ 294 - {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/ 295 294 {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/ 296 295 {RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/ 297 296 {RTL_USB_DEVICE(0x0846, 0x9043, rtl92cu_hal_cfg)}, /*NG WNA1000Mv2*/

+7 -6

drivers/net/wireless/realtek/rtw88/led.c

··· 6 6 #include "debug.h" 7 7 #include "led.h" 8 8 9 - static int rtw_led_set_blocking(struct led_classdev *led, 10 - enum led_brightness brightness) 9 + static int rtw_led_set(struct led_classdev *led, 10 + enum led_brightness brightness) 11 11 { 12 12 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev); 13 13 14 + mutex_lock(&rtwdev->mutex); 15 + 14 16 rtwdev->chip->ops->led_set(led, brightness); 17 + 18 + mutex_unlock(&rtwdev->mutex); 15 19 16 20 return 0; 17 21 } ··· 40 36 if (!rtwdev->chip->ops->led_set) 41 37 return; 42 38 43 - if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 44 - led->brightness_set = rtwdev->chip->ops->led_set; 45 - else 46 - led->brightness_set_blocking = rtw_led_set_blocking; 39 + led->brightness_set_blocking = rtw_led_set; 47 40 48 41 snprintf(rtwdev->led_name, sizeof(rtwdev->led_name), 49 42 "rtw88-%s", dev_name(rtwdev->dev));

+4

drivers/net/wireless/realtek/rtw88/sdio.c

··· 144 144 145 145 static bool rtw_sdio_use_direct_io(struct rtw_dev *rtwdev, u32 addr) 146 146 { 147 + if (!test_bit(RTW_FLAG_POWERON, rtwdev->flags) && 148 + !rtw_sdio_is_bus_addr(addr)) 149 + return false; 150 + 147 151 return !rtw_sdio_is_sdio30_supported(rtwdev) || 148 152 rtw_sdio_is_bus_addr(addr); 149 153 }

+10 -1

drivers/net/wireless/realtek/rtw89/chan.c

··· 281 281 { 282 282 struct rtw89_hal *hal = &rtwdev->hal; 283 283 struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt; 284 + int i, j; 284 285 285 286 hal->entity_pause = false; 286 287 bitmap_zero(hal->entity_map, NUM_OF_RTW89_CHANCTX); ··· 289 288 atomic_set(&hal->roc_chanctx_idx, RTW89_CHANCTX_IDLE); 290 289 291 290 INIT_LIST_HEAD(&mgnt->active_list); 291 + 292 + for (i = 0; i < RTW89_MAX_INTERFACE_NUM; i++) { 293 + for (j = 0; j < __RTW89_MLD_MAX_LINK_NUM; j++) 294 + mgnt->chanctx_tbl[i][j] = RTW89_CHANCTX_IDLE; 295 + } 292 296 293 297 rtw89_config_default_chandef(rtwdev); 294 298 } ··· 359 353 360 354 const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev, 361 355 const char *caller_message, 362 - u8 link_index) 356 + u8 link_index, bool nullchk) 363 357 { 364 358 struct rtw89_hal *hal = &rtwdev->hal; 365 359 struct rtw89_entity_mgnt *mgnt = &hal->entity_mgnt; ··· 406 400 return rtw89_chan_get(rtwdev, chanctx_idx); 407 401 408 402 dflt: 403 + if (unlikely(nullchk)) 404 + return NULL; 405 + 409 406 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 410 407 "%s (%s): prefetch NULL on link index %u\n", 411 408 __func__, caller_message ?: "", link_index);

+8 -2

drivers/net/wireless/realtek/rtw89/chan.h

··· 180 180 181 181 const struct rtw89_chan *__rtw89_mgnt_chan_get(struct rtw89_dev *rtwdev, 182 182 const char *caller_message, 183 - u8 link_index); 183 + u8 link_index, bool nullchk); 184 184 185 185 #define rtw89_mgnt_chan_get(rtwdev, link_index) \ 186 - __rtw89_mgnt_chan_get(rtwdev, __func__, link_index) 186 + __rtw89_mgnt_chan_get(rtwdev, __func__, link_index, false) 187 + 188 + static inline const struct rtw89_chan * 189 + rtw89_mgnt_chan_get_or_null(struct rtw89_dev *rtwdev, u8 link_index) 190 + { 191 + return __rtw89_mgnt_chan_get(rtwdev, NULL, link_index, true); 192 + } 187 193 188 194 struct rtw89_mcc_links_info { 189 195 struct rtw89_vif_link *links[NUM_OF_RTW89_MCC_ROLES];

+4 -1

drivers/net/wireless/realtek/rtw89/coex.c

··· 93 93 [CXST_E2G] = __DEF_FBTC_SLOT(5, 0xea5a5a5a, SLOT_MIX), 94 94 [CXST_E5G] = __DEF_FBTC_SLOT(5, 0xffffffff, SLOT_ISO), 95 95 [CXST_EBT] = __DEF_FBTC_SLOT(5, 0xe5555555, SLOT_MIX), 96 - [CXST_ENULL] = __DEF_FBTC_SLOT(5, 0xaaaaaaaa, SLOT_ISO), 96 + [CXST_ENULL] = __DEF_FBTC_SLOT(5, 0x55555555, SLOT_MIX), 97 97 [CXST_WLK] = __DEF_FBTC_SLOT(250, 0xea5a5a5a, SLOT_MIX), 98 98 [CXST_W1FDD] = __DEF_FBTC_SLOT(50, 0xffffffff, SLOT_ISO), 99 99 [CXST_B1FDD] = __DEF_FBTC_SLOT(50, 0xffffdfff, SLOT_ISO), ··· 4153 4153 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 4154 4154 _slot_set_le(btc, CXST_ENULL, s_def[CXST_ENULL].dur, 4155 4155 s_def[CXST_ENULL].cxtbl, s_def[CXST_ENULL].cxtype); 4156 + _slot_set_dur(btc, CXST_EBT, dur_2); 4156 4157 break; 4157 4158 case BTC_CXP_OFFE_DEF2: 4158 4159 _slot_set(btc, CXST_E2G, 20, cxtbl[1], SLOT_ISO); ··· 4163 4162 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 4164 4163 _slot_set_le(btc, CXST_ENULL, s_def[CXST_ENULL].dur, 4165 4164 s_def[CXST_ENULL].cxtbl, s_def[CXST_ENULL].cxtype); 4165 + _slot_set_dur(btc, CXST_EBT, dur_2); 4166 4166 break; 4167 4167 case BTC_CXP_OFFE_2GBWMIXB: 4168 4168 if (a2dp->exist) ··· 4172 4170 _slot_set(btc, CXST_E2G, 5, tbl_w1, SLOT_MIX); 4173 4171 _slot_set_le(btc, CXST_EBT, cpu_to_le16(40), 4174 4172 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 4173 + _slot_set_dur(btc, CXST_EBT, dur_2); 4175 4174 break; 4176 4175 case BTC_CXP_OFFE_WL: /* for 4-way */ 4177 4176 _slot_set(btc, CXST_E2G, 5, cxtbl[1], SLOT_MIX);

+642 -44

drivers/net/wireless/realtek/rtw89/core.c

··· 2 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 3 */ 4 4 #include <linux/ip.h> 5 + #include <linux/sort.h> 5 6 #include <linux/udp.h> 6 7 7 8 #include "cam.h" ··· 273 272 return NULL; 274 273 } 275 274 276 - bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 275 + bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate) 277 276 { 278 - struct ieee80211_rate rate; 277 + const struct ieee80211_rate *rate; 279 278 280 - if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 281 - rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 279 + if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) { 280 + rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 281 + "invalid legacy rate %d\n", legacy_rate); 282 282 return false; 283 283 } 284 284 285 - rate = rtw89_bitrates[rpt_rate]; 286 - *bitrate = rate.bitrate; 285 + rate = &rtw89_bitrates[legacy_rate]; 286 + *bitrate = rate->bitrate; 287 287 288 288 return true; 289 289 } ··· 699 697 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 700 698 } 701 699 700 + u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 701 + { 702 + switch (qsel) { 703 + default: 704 + rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 705 + fallthrough; 706 + case RTW89_TX_QSEL_BE_0: 707 + case RTW89_TX_QSEL_BE_1: 708 + case RTW89_TX_QSEL_BE_2: 709 + case RTW89_TX_QSEL_BE_3: 710 + return RTW89_TXCH_ACH0; 711 + case RTW89_TX_QSEL_BK_0: 712 + case RTW89_TX_QSEL_BK_1: 713 + case RTW89_TX_QSEL_BK_2: 714 + case RTW89_TX_QSEL_BK_3: 715 + return RTW89_TXCH_ACH1; 716 + case RTW89_TX_QSEL_VI_0: 717 + case RTW89_TX_QSEL_VI_1: 718 + case RTW89_TX_QSEL_VI_2: 719 + case RTW89_TX_QSEL_VI_3: 720 + return RTW89_TXCH_ACH2; 721 + case RTW89_TX_QSEL_VO_0: 722 + case RTW89_TX_QSEL_VO_1: 723 + case RTW89_TX_QSEL_VO_2: 724 + case RTW89_TX_QSEL_VO_3: 725 + return RTW89_TXCH_ACH3; 726 + case RTW89_TX_QSEL_B0_MGMT: 727 + return RTW89_TXCH_CH8; 728 + case RTW89_TX_QSEL_B0_HI: 729 + return RTW89_TXCH_CH9; 730 + case RTW89_TX_QSEL_B1_MGMT: 731 + return RTW89_TXCH_CH10; 732 + case RTW89_TX_QSEL_B1_HI: 733 + return RTW89_TXCH_CH11; 734 + } 735 + } 736 + EXPORT_SYMBOL(rtw89_core_get_ch_dma); 737 + 738 + u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel) 739 + { 740 + switch (qsel) { 741 + default: 742 + rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel); 743 + fallthrough; 744 + case RTW89_TX_QSEL_BE_0: 745 + case RTW89_TX_QSEL_BK_0: 746 + return RTW89_TXCH_ACH0; 747 + case RTW89_TX_QSEL_VI_0: 748 + case RTW89_TX_QSEL_VO_0: 749 + return RTW89_TXCH_ACH2; 750 + case RTW89_TX_QSEL_B0_MGMT: 751 + case RTW89_TX_QSEL_B0_HI: 752 + return RTW89_TXCH_CH8; 753 + case RTW89_TX_QSEL_B1_MGMT: 754 + case RTW89_TX_QSEL_B1_HI: 755 + return RTW89_TXCH_CH10; 756 + } 757 + } 758 + EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1); 759 + 702 760 static void 703 761 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 704 762 struct rtw89_core_tx_request *tx_req) ··· 772 710 u8 qsel, ch_dma; 773 711 774 712 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 775 - ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 713 + ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 776 714 777 715 desc_info->qsel = qsel; 778 716 desc_info->ch_dma = ch_dma; ··· 989 927 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 990 928 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 991 929 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 992 - ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 930 + ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 993 931 994 932 desc_info->ch_dma = ch_dma; 995 933 desc_info->tid_indicate = tid_indicate; ··· 1135 1073 } 1136 1074 } 1137 1075 1076 + static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work) 1077 + { 1078 + struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1079 + tx_wait_work.work); 1080 + 1081 + rtw89_tx_wait_list_clear(rtwdev); 1082 + } 1083 + 1138 1084 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1139 1085 { 1140 1086 u8 ch_dma; 1141 1087 1142 - ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1088 + ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1143 1089 1144 1090 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1145 1091 } 1146 1092 1147 1093 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1148 - int qsel, unsigned int timeout) 1094 + struct rtw89_tx_wait_info *wait, int qsel, 1095 + unsigned int timeout) 1149 1096 { 1150 - struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1151 - struct rtw89_tx_wait_info *wait; 1152 1097 unsigned long time_left; 1153 1098 int ret = 0; 1154 1099 1155 - wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1156 - if (!wait) { 1157 - rtw89_core_tx_kick_off(rtwdev, qsel); 1158 - return 0; 1159 - } 1160 - 1161 - init_completion(&wait->completion); 1162 - rcu_assign_pointer(skb_data->wait, wait); 1100 + lockdep_assert_wiphy(rtwdev->hw->wiphy); 1163 1101 1164 1102 rtw89_core_tx_kick_off(rtwdev, qsel); 1165 1103 time_left = wait_for_completion_timeout(&wait->completion, 1166 1104 msecs_to_jiffies(timeout)); 1167 - if (time_left == 0) 1168 - ret = -ETIMEDOUT; 1169 - else if (!wait->tx_done) 1170 - ret = -EAGAIN; 1171 1105 1172 - rcu_assign_pointer(skb_data->wait, NULL); 1173 - kfree_rcu(wait, rcu_head); 1106 + if (time_left == 0) { 1107 + ret = -ETIMEDOUT; 1108 + list_add_tail(&wait->list, &rtwdev->tx_waits); 1109 + wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work, 1110 + RTW89_TX_WAIT_WORK_TIMEOUT); 1111 + } else { 1112 + if (!wait->tx_done) 1113 + ret = -EAGAIN; 1114 + rtw89_tx_wait_release(wait); 1115 + } 1174 1116 1175 1117 return ret; 1176 1118 } ··· 1223 1157 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1224 1158 struct rtw89_vif_link *rtwvif_link, 1225 1159 struct rtw89_sta_link *rtwsta_link, 1226 - struct sk_buff *skb, int *qsel, bool sw_mld) 1160 + struct sk_buff *skb, int *qsel, bool sw_mld, 1161 + struct rtw89_tx_wait_info *wait) 1227 1162 { 1228 1163 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1229 1164 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1165 + struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1230 1166 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1231 1167 struct rtw89_core_tx_request tx_req = {}; 1232 1168 int ret; ··· 1244 1176 rtw89_wow_parse_akm(rtwdev, skb); 1245 1177 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1246 1178 rtw89_core_tx_wake(rtwdev, &tx_req); 1179 + 1180 + rcu_assign_pointer(skb_data->wait, wait); 1247 1181 1248 1182 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1249 1183 if (ret) { ··· 1283 1213 } 1284 1214 } 1285 1215 1286 - return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false); 1216 + return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false, 1217 + NULL); 1287 1218 } 1288 1219 1289 1220 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) ··· 1906 1835 1907 1836 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1908 1837 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1838 + 1839 + if (!phy_ppdu->hdr_2_en) 1840 + phy_ppdu->rx_path_en = 1841 + le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN); 1909 1842 } 1910 1843 1911 1844 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, ··· 2296 2221 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2297 2222 } 2298 2223 2224 + static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2) 2225 + { 2226 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2227 + u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th; 2228 + u32 tbtt_diff_th = bcn_track->tbtt_diff_th; 2229 + 2230 + if (tbtt2 > tbtt1) 2231 + swap(tbtt1, tbtt2); 2232 + 2233 + if (tbtt1 - tbtt2 > tbtt_diff_th) 2234 + return tbtt1; 2235 + else if (tbtt2 > close_bcn_intvl_th) 2236 + return tbtt2; 2237 + else if (tbtt1 > close_bcn_intvl_th) 2238 + return tbtt1; 2239 + else 2240 + return tbtt2; 2241 + } 2242 + 2243 + static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev, 2244 + struct rtw89_vif_link *rtwvif_link) 2245 + { 2246 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2247 + enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2248 + u32 offset = bcn_track->tbtt_offset; 2249 + 2250 + if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2251 + const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2252 + const struct rtw89_port_reg *p = mac->port_base; 2253 + u32 bcnspc, val; 2254 + 2255 + bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link, 2256 + p->bcn_space, B_AX_BCN_SPACE_MASK); 2257 + val = bcnspc - (offset / 1024); 2258 + val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) | 2259 + B_AX_TBTT_SHIFT_OFST_SIGN; 2260 + 2261 + rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 2262 + B_AX_TBTT_SHIFT_OFST_MASK, val); 2263 + 2264 + return; 2265 + } 2266 + 2267 + rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset); 2268 + } 2269 + 2270 + static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev, 2271 + struct rtw89_vif_link *rtwvif_link) 2272 + { 2273 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2274 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2275 + u32 *tbtt_us = bcn_stat->tbtt_us; 2276 + u32 offset = tbtt_us[0]; 2277 + u8 i; 2278 + 2279 + for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++) 2280 + offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset); 2281 + 2282 + if (bcn_track->tbtt_offset == offset) 2283 + return; 2284 + 2285 + bcn_track->tbtt_offset = offset; 2286 + rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link); 2287 + } 2288 + 2289 + static int cmp_u16(const void *a, const void *b) 2290 + { 2291 + return *(const u16 *)a - *(const u16 *)b; 2292 + } 2293 + 2294 + static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int) 2295 + { 2296 + if (tbtt < offset) 2297 + return beacon_int - offset + tbtt; 2298 + 2299 + return tbtt - offset; 2300 + } 2301 + 2302 + static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev) 2303 + { 2304 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2305 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2306 + u16 offset_tu = bcn_track->tbtt_offset / 1024; 2307 + u16 *tbtt_tu = bcn_stat->tbtt_tu; 2308 + u16 *drift = bcn_stat->drift; 2309 + u8 i; 2310 + 2311 + bcn_stat->tbtt_tu_min = U16_MAX; 2312 + bcn_stat->tbtt_tu_max = 0; 2313 + for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2314 + drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu, 2315 + bcn_track->beacon_int); 2316 + 2317 + bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]); 2318 + bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]); 2319 + } 2320 + 2321 + sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL); 2322 + } 2323 + 2324 + static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev) 2325 + { 2326 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2327 + struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2328 + u16 lower_bound, upper_bound, outlier_count = 0; 2329 + u16 *drift = bcn_stat->drift; 2330 + u16 *bins = bcn_dist->bins; 2331 + u16 q1, q3, iqr, tmp; 2332 + u8 i; 2333 + 2334 + BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0); 2335 + 2336 + memset(bcn_dist, 0, sizeof(*bcn_dist)); 2337 + 2338 + bcn_dist->min = drift[0]; 2339 + bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1]; 2340 + 2341 + tmp = RTW89_BCN_TRACK_STAT_NR / 4; 2342 + q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2343 + 2344 + tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4; 2345 + q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2346 + 2347 + iqr = q3 - q1; 2348 + tmp = (3 * iqr) / 2; 2349 + 2350 + if (bcn_dist->min <= 5) 2351 + lower_bound = bcn_dist->min; 2352 + else if (q1 > tmp) 2353 + lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2354 + else 2355 + lower_bound = 0; 2356 + 2357 + upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2358 + 2359 + for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2360 + u16 tbtt = bcn_stat->tbtt_tu[i]; 2361 + u16 min = bcn_stat->tbtt_tu_min; 2362 + u8 bin_idx; 2363 + 2364 + /* histogram */ 2365 + bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH, 2366 + RTW89_BCN_TRACK_MAX_BIN_NUM - 1); 2367 + bins[bin_idx]++; 2368 + 2369 + /* boxplot outlier */ 2370 + if (drift[i] < lower_bound || drift[i] > upper_bound) 2371 + outlier_count++; 2372 + } 2373 + 2374 + bcn_dist->outlier_count = outlier_count; 2375 + bcn_dist->lower_bound = lower_bound; 2376 + bcn_dist->upper_bound = upper_bound; 2377 + } 2378 + 2379 + static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold) 2380 + { 2381 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2382 + int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m; 2383 + u16 *drift = bcn_stat->drift; 2384 + int index = -1; 2385 + u8 count = 0; 2386 + 2387 + while (l <= r) { 2388 + m = l + (r - l) / 2; 2389 + 2390 + if (drift[m] <= threshold) { 2391 + index = m; 2392 + l = m + 1; 2393 + } else { 2394 + r = m - 1; 2395 + } 2396 + } 2397 + 2398 + count = (index == -1) ? 0 : (index + 1); 2399 + 2400 + return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR; 2401 + } 2402 + 2403 + static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target) 2404 + { 2405 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2406 + struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2407 + u16 tbtt_tu_max = bcn_stat->tbtt_tu_max; 2408 + u16 upper, lower = bcn_stat->tbtt_tu_min; 2409 + u8 i, count = 0; 2410 + 2411 + for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 2412 + upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 2413 + if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 2414 + upper = max(upper, tbtt_tu_max); 2415 + 2416 + count += bcn_dist->bins[i]; 2417 + if (count > target) 2418 + break; 2419 + 2420 + lower = upper + 1; 2421 + } 2422 + 2423 + return upper; 2424 + } 2425 + 2426 + static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev, 2427 + const struct rtw89_chan *chan) 2428 + { 2429 + #define RTW89_SYMBOL_TIME_2GHZ 192 2430 + #define RTW89_SYMBOL_TIME_5GHZ 20 2431 + #define RTW89_SYMBOL_TIME_6GHZ 20 2432 + struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2433 + u16 bitrate, val; 2434 + 2435 + if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate)) 2436 + return 0; 2437 + 2438 + val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate; 2439 + 2440 + switch (chan->band_type) { 2441 + default: 2442 + case RTW89_BAND_2G: 2443 + val += RTW89_SYMBOL_TIME_2GHZ; 2444 + break; 2445 + case RTW89_BAND_5G: 2446 + val += RTW89_SYMBOL_TIME_5GHZ; 2447 + break; 2448 + case RTW89_BAND_6G: 2449 + val += RTW89_SYMBOL_TIME_6GHZ; 2450 + break; 2451 + } 2452 + 2453 + /* convert to millisecond */ 2454 + return DIV_ROUND_UP(val, 1000); 2455 + } 2456 + 2457 + static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev, 2458 + struct rtw89_vif_link *rtwvif_link) 2459 + { 2460 + #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5 2461 + #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */ 2462 + #define RTW89_BCN_TRACK_STRONG_RSSI 80 2463 + const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2464 + struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2465 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2466 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2467 + struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2468 + u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th; 2469 + u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th; 2470 + u8 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2471 + u16 target_bcn_th = bcn_track->target_bcn_th; 2472 + u16 low_bcn_th = bcn_track->low_bcn_th; 2473 + u16 med_bcn_th = bcn_track->med_bcn_th; 2474 + u16 beacon_int = bcn_track->beacon_int; 2475 + u16 bcn_timeout; 2476 + 2477 + if (pkt_stat->beacon_nr < low_bcn_th) { 2478 + bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT; 2479 + goto out; 2480 + } 2481 + 2482 + if (bcn_dist->outlier_count >= outlier_high_bcn_th) { 2483 + bcn_timeout = bcn_dist->max; 2484 + goto out; 2485 + } 2486 + 2487 + if (pkt_stat->beacon_nr < med_bcn_th) { 2488 + if (bcn_dist->outlier_count > outlier_low_bcn_th) 2489 + bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2; 2490 + else 2491 + bcn_timeout = bcn_dist->upper_bound + 2492 + RTW89_BCN_TRACK_EXTEND_TIMEOUT; 2493 + 2494 + goto out; 2495 + } 2496 + 2497 + if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) { 2498 + if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) { 2499 + /* ideal case */ 2500 + bcn_timeout = 0; 2501 + } else { 2502 + u16 offset_tu = bcn_track->tbtt_offset / 1024; 2503 + u16 upper_bound; 2504 + 2505 + upper_bound = 2506 + rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th); 2507 + bcn_timeout = 2508 + _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int); 2509 + } 2510 + 2511 + goto out; 2512 + } 2513 + 2514 + bcn_timeout = bcn_stat->drift[target_bcn_th]; 2515 + 2516 + out: 2517 + bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, chan); 2518 + } 2519 + 2520 + static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev, 2521 + struct rtw89_vif_link *rtwvif_link) 2522 + { 2523 + rtw89_bcn_calc_drift(rtwdev); 2524 + rtw89_bcn_calc_distribution(rtwdev); 2525 + rtw89_bcn_calc_timeout(rtwdev, rtwvif_link); 2526 + } 2527 + 2528 + static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev) 2529 + { 2530 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2531 + struct rtw89_vif_link *rtwvif_link; 2532 + struct rtw89_vif *rtwvif; 2533 + unsigned int link_id; 2534 + 2535 + if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2536 + return; 2537 + 2538 + if (!rtwdev->lps_enabled) 2539 + return; 2540 + 2541 + if (!bcn_track->is_data_ready) 2542 + return; 2543 + 2544 + rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2545 + rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 2546 + if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION || 2547 + rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)) 2548 + continue; 2549 + 2550 + rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link); 2551 + rtw89_bcn_update_timeout(rtwdev, rtwvif_link); 2552 + } 2553 + } 2554 + } 2555 + 2556 + static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev) 2557 + { 2558 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2559 + 2560 + if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2561 + return true; 2562 + 2563 + return bcn_track->is_data_ready; 2564 + } 2565 + 2566 + static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev, 2567 + struct rtw89_vif_link *rtwvif_link) 2568 + { 2569 + #define RTW89_BCN_TRACK_MED_BCN 70 2570 + #define RTW89_BCN_TRACK_LOW_BCN 30 2571 + #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30 2572 + #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20 2573 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2574 + u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD); 2575 + struct ieee80211_bss_conf *bss_conf; 2576 + u32 beacons_in_period; 2577 + u32 bcn_intvl_us; 2578 + u16 beacon_int; 2579 + u8 dtim; 2580 + 2581 + rcu_read_lock(); 2582 + bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 2583 + beacon_int = bss_conf->beacon_int; 2584 + dtim = bss_conf->dtim_period; 2585 + rcu_read_unlock(); 2586 + 2587 + beacons_in_period = period / beacon_int / dtim; 2588 + bcn_intvl_us = ieee80211_tu_to_usec(beacon_int); 2589 + 2590 + bcn_track->low_bcn_th = 2591 + (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT; 2592 + bcn_track->med_bcn_th = 2593 + (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT; 2594 + bcn_track->outlier_low_bcn_th = 2595 + (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT; 2596 + bcn_track->outlier_high_bcn_th = 2597 + (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT; 2598 + bcn_track->target_bcn_th = 2599 + (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT; 2600 + 2601 + bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3); 2602 + bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT; 2603 + bcn_track->beacon_int = beacon_int; 2604 + bcn_track->dtim = dtim; 2605 + } 2606 + 2607 + static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev) 2608 + { 2609 + memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat)); 2610 + memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track)); 2611 + } 2612 + 2613 + static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, 2614 + struct ieee80211_bss_conf *bss_conf, 2615 + struct sk_buff *skb) 2616 + { 2617 + #define RTW89_APPEND_TSF_2GHZ 384 2618 + #define RTW89_APPEND_TSF_5GHZ 52 2619 + #define RTW89_APPEND_TSF_6GHZ 52 2620 + struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2621 + struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2622 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2623 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2624 + u32 bcn_intvl_us = ieee80211_tu_to_usec(bss_conf->beacon_int); 2625 + u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp); 2626 + u8 wp, num = bcn_stat->num; 2627 + u16 append; 2628 + 2629 + if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2630 + return; 2631 + 2632 + switch (rx_status->band) { 2633 + default: 2634 + case NL80211_BAND_2GHZ: 2635 + append = RTW89_APPEND_TSF_2GHZ; 2636 + break; 2637 + case NL80211_BAND_5GHZ: 2638 + append = RTW89_APPEND_TSF_5GHZ; 2639 + break; 2640 + case NL80211_BAND_6GHZ: 2641 + append = RTW89_APPEND_TSF_6GHZ; 2642 + break; 2643 + } 2644 + 2645 + wp = bcn_stat->wp; 2646 + div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]); 2647 + bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024; 2648 + bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR; 2649 + bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR); 2650 + bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR; 2651 + } 2652 + 2299 2653 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2300 2654 struct ieee80211_vif *vif) 2301 2655 { ··· 2741 2237 struct ieee80211_bss_conf *bss_conf; 2742 2238 struct rtw89_vif_link *rtwvif_link; 2743 2239 const u8 *bssid = iter_data->bssid; 2240 + const u8 *target_bssid; 2744 2241 2745 2242 if (rtwdev->scanning && 2746 2243 (ieee80211_is_beacon(hdr->frame_control) || ··· 2763 2258 goto out; 2764 2259 } 2765 2260 2766 - if (!ether_addr_equal(bss_conf->bssid, bssid)) 2261 + target_bssid = ieee80211_is_beacon(hdr->frame_control) && 2262 + bss_conf->nontransmitted ? 2263 + bss_conf->transmitter_bssid : bss_conf->bssid; 2264 + if (!ether_addr_equal(target_bssid, bssid)) 2767 2265 goto out; 2768 2266 2769 2267 if (is_mld) { ··· 2780 2272 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2781 2273 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2782 2274 } 2783 - pkt_stat->beacon_nr++; 2784 2275 2785 2276 if (phy_ppdu) { 2786 2277 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); ··· 2787 2280 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2788 2281 } 2789 2282 2283 + pkt_stat->beacon_nr++; 2790 2284 pkt_stat->beacon_rate = desc_info->data_rate; 2285 + pkt_stat->beacon_len = skb->len; 2286 + 2287 + rtw89_vif_rx_bcn_stat(rtwdev, bss_conf, skb); 2791 2288 } 2792 2289 2793 2290 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) ··· 3737 3226 u8 qsel, ch_dma; 3738 3227 3739 3228 qsel = rtw89_core_get_qsel(rtwdev, tid); 3740 - ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3229 + ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 3741 3230 3742 3231 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3743 3232 } ··· 3922 3411 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3923 3412 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3924 3413 struct rtw89_sta_link *rtwsta_link; 3414 + struct rtw89_tx_wait_info *wait; 3925 3415 struct ieee80211_sta *sta; 3926 3416 struct ieee80211_hdr *hdr; 3927 3417 struct rtw89_sta *rtwsta; ··· 3931 3419 3932 3420 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3933 3421 return 0; 3422 + 3423 + wait = kzalloc(sizeof(*wait), GFP_KERNEL); 3424 + if (!wait) 3425 + return -ENOMEM; 3426 + 3427 + init_completion(&wait->completion); 3934 3428 3935 3429 rcu_read_lock(); 3936 3430 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); ··· 3952 3434 goto out; 3953 3435 } 3954 3436 3437 + wait->skb = skb; 3438 + 3955 3439 hdr = (struct ieee80211_hdr *)skb->data; 3956 3440 if (ps) 3957 3441 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); ··· 3961 3441 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 3962 3442 if (unlikely(!rtwsta_link)) { 3963 3443 ret = -ENOLINK; 3444 + dev_kfree_skb_any(skb); 3964 3445 goto out; 3965 3446 } 3966 3447 3967 - ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true); 3448 + ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true, 3449 + wait); 3968 3450 if (ret) { 3969 3451 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3970 3452 dev_kfree_skb_any(skb); ··· 3975 3453 3976 3454 rcu_read_unlock(); 3977 3455 3978 - return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3456 + return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel, 3979 3457 timeout); 3980 3458 out: 3981 3459 rcu_read_unlock(); 3460 + kfree(wait); 3982 3461 3983 3462 return ret; 3984 3463 } ··· 4220 3697 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 4221 3698 continue; 4222 3699 3700 + if (!rtw89_core_bcn_track_can_lps(rtwdev)) 3701 + continue; 3702 + 4223 3703 rtw89_enter_lps(rtwdev, rtwvif, true); 4224 3704 } 4225 3705 } ··· 4409 3883 rtw89_btc_ntfy_wl_sta(rtwdev); 4410 3884 } 4411 3885 rtw89_mac_bf_monitor_track(rtwdev); 3886 + rtw89_core_bcn_track(rtwdev); 4412 3887 rtw89_phy_stat_track(rtwdev); 4413 3888 rtw89_phy_env_monitor_track(rtwdev); 4414 3889 rtw89_phy_dig(rtwdev); ··· 4656 4129 4657 4130 rtw89_assoc_link_clr(rtwsta_link); 4658 4131 4659 - if (vif->type == NL80211_IFTYPE_STATION) 4132 + if (vif->type == NL80211_IFTYPE_STATION) { 4660 4133 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 4134 + rtw89_core_bcn_track_reset(rtwdev); 4135 + } 4661 4136 4662 4137 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 4663 4138 rtw89_p2p_noa_once_deinit(rtwvif_link); ··· 4800 4271 BTC_ROLE_MSTS_STA_CONN_END); 4801 4272 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 4802 4273 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 4274 + rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link); 4803 4275 4804 4276 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 4805 4277 if (ret) { ··· 5359 4829 } 5360 4830 } 5361 4831 5362 - int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4832 + struct rtw89_wait_response * 4833 + rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 5363 4834 { 5364 - struct completion *cmpl = &wait->completion; 5365 - unsigned long time_left; 4835 + struct rtw89_wait_response *prep; 5366 4836 unsigned int cur; 4837 + 4838 + /* use -EPERM _iff_ telling eval side not to make any changes */ 5367 4839 5368 4840 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 5369 4841 if (cur != RTW89_WAIT_COND_IDLE) 5370 - return -EBUSY; 4842 + return ERR_PTR(-EPERM); 5371 4843 5372 - time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 5373 - if (time_left == 0) { 5374 - atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 5375 - return -ETIMEDOUT; 4844 + prep = kzalloc(sizeof(*prep), GFP_KERNEL); 4845 + if (!prep) 4846 + return ERR_PTR(-ENOMEM); 4847 + 4848 + init_completion(&prep->completion); 4849 + 4850 + rcu_assign_pointer(wait->resp, prep); 4851 + 4852 + return prep; 4853 + } 4854 + 4855 + int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 4856 + struct rtw89_wait_response *prep, int err) 4857 + { 4858 + unsigned long time_left; 4859 + 4860 + if (IS_ERR(prep)) { 4861 + err = err ?: PTR_ERR(prep); 4862 + 4863 + /* special error case: no permission to reset anything */ 4864 + if (PTR_ERR(prep) == -EPERM) 4865 + return err; 4866 + 4867 + goto reset; 5376 4868 } 4869 + 4870 + if (err) 4871 + goto cleanup; 4872 + 4873 + time_left = wait_for_completion_timeout(&prep->completion, 4874 + RTW89_WAIT_FOR_COND_TIMEOUT); 4875 + if (time_left == 0) { 4876 + err = -ETIMEDOUT; 4877 + goto cleanup; 4878 + } 4879 + 4880 + wait->data = prep->data; 4881 + 4882 + cleanup: 4883 + rcu_assign_pointer(wait->resp, NULL); 4884 + kfree_rcu(prep, rcu_head); 4885 + 4886 + reset: 4887 + atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4888 + 4889 + if (err) 4890 + return err; 5377 4891 5378 4892 if (wait->data.err) 5379 4893 return -EFAULT; ··· 5425 4851 return 0; 5426 4852 } 5427 4853 4854 + static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp, 4855 + const struct rtw89_completion_data *data) 4856 + { 4857 + resp->data = *data; 4858 + complete(&resp->completion); 4859 + } 4860 + 5428 4861 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5429 4862 const struct rtw89_completion_data *data) 5430 4863 { 4864 + struct rtw89_wait_response *resp; 5431 4865 unsigned int cur; 4866 + 4867 + guard(rcu)(); 4868 + 4869 + resp = rcu_dereference(wait->resp); 4870 + if (!resp) 4871 + return; 5432 4872 5433 4873 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 5434 4874 if (cur != cond) 5435 4875 return; 5436 4876 5437 - wait->data = *data; 5438 - complete(&wait->completion); 4877 + rtw89_complete_cond_resp(resp, data); 5439 4878 } 5440 4879 5441 4880 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) ··· 5495 4908 { 5496 4909 int ret; 5497 4910 4911 + rtw89_phy_init_bb_afe(rtwdev); 4912 + 5498 4913 ret = rtw89_mac_init(rtwdev); 5499 4914 if (ret) { 5500 4915 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); ··· 5541 4952 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 5542 4953 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 5543 4954 rtw89_fw_h2c_init_ba_cam(rtwdev); 4955 + rtw89_tas_fw_timer_enable(rtwdev, true); 5544 4956 5545 4957 return 0; 5546 4958 } ··· 5557 4967 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 5558 4968 return; 5559 4969 4970 + rtw89_tas_fw_timer_enable(rtwdev, false); 5560 4971 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 5561 4972 5562 4973 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ··· 5569 4978 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 5570 4979 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 5571 4980 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4981 + wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work); 5572 4982 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 5573 4983 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work); 5574 4984 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); ··· 5795 5203 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 5796 5204 } 5797 5205 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 5206 + INIT_LIST_HEAD(&rtwdev->tx_waits); 5798 5207 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 5799 5208 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 5800 5209 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); ··· 5807 5214 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 5808 5215 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 5809 5216 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 5217 + wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work); 5810 5218 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 5811 5219 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 5812 5220 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); ··· 6407 5813 return ret; 6408 5814 } 6409 5815 5816 + rtw89_phy_dm_init_data(rtwdev); 6410 5817 rtw89_debugfs_init(rtwdev); 6411 5818 6412 5819 return 0; ··· 6457 5862 ops->remain_on_channel = NULL; 6458 5863 ops->cancel_remain_on_channel = NULL; 6459 5864 } 5865 + 5866 + if (!chip->support_noise) 5867 + ops->get_survey = NULL; 6460 5868 6461 5869 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 6462 5870 hw = ieee80211_alloc_hw(driver_data_size, ops);

+138 -12

drivers/net/wireless/realtek/rtw89/core.h

··· 1011 1011 u32 ptcl_dbg; 1012 1012 u32 ptcl_dbg_info; 1013 1013 u32 bcn_drop_all; 1014 + u32 bcn_psr_rpt; 1014 1015 u32 hiq_win[RTW89_PORT_NUM]; 1015 1016 }; 1016 1017 ··· 3507 3506 bool enable; 3508 3507 }; 3509 3508 3509 + #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 3510 3510 struct rtw89_tx_wait_info { 3511 3511 struct rcu_head rcu_head; 3512 + struct list_head list; 3512 3513 struct completion completion; 3514 + struct sk_buff *skb; 3513 3515 bool tx_done; 3514 3516 }; 3515 3517 ··· 3763 3759 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3764 3760 struct rtw89_tx_desc_info *desc_info, 3765 3761 void *txdesc); 3762 + u8 (*get_ch_dma)(struct rtw89_dev *rtwdev, u8 qsel); 3766 3763 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3767 3764 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3768 3765 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); ··· 4368 4363 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4369 4364 }; 4370 4365 4366 + #define RTW89_NHM_TH_NUM 11 4367 + #define RTW89_NHM_RPT_NUM 12 4368 + 4371 4369 struct rtw89_chip_info { 4372 4370 enum rtw89_core_chip_id chip_id; 4373 4371 enum rtw89_chip_gen chip_gen; ··· 4405 4397 bool support_ant_gain; 4406 4398 bool support_tas; 4407 4399 bool support_sar_by_ant; 4400 + bool support_noise; 4408 4401 bool ul_tb_waveform_ctrl; 4409 4402 bool ul_tb_pwr_diff; 4410 4403 bool rx_freq_frome_ie; ··· 4490 4481 bool cfo_hw_comp; 4491 4482 const struct rtw89_reg_def *dcfo_comp; 4492 4483 u8 dcfo_comp_sft; 4484 + const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 4485 + const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 4493 4486 const struct rtw89_imr_info *imr_info; 4494 4487 const struct rtw89_imr_table *imr_dmac_table; 4495 4488 const struct rtw89_imr_table *imr_cmac_table; ··· 4553 4542 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4554 4543 }; 4555 4544 4556 - struct rtw89_wait_info { 4557 - atomic_t cond; 4545 + struct rtw89_wait_response { 4546 + struct rcu_head rcu_head; 4558 4547 struct completion completion; 4559 4548 struct rtw89_completion_data data; 4549 + }; 4550 + 4551 + struct rtw89_wait_info { 4552 + atomic_t cond; 4553 + struct rtw89_completion_data data; 4554 + struct rtw89_wait_response __rcu *resp; 4560 4555 }; 4561 4556 4562 4557 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4563 4558 4564 4559 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4565 4560 { 4566 - init_completion(&wait->completion); 4561 + rcu_assign_pointer(wait->resp, NULL); 4567 4562 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4568 4563 } 4569 4564 ··· 4639 4622 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4640 4623 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4641 4624 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4625 + RTW89_FW_FEATURE_BEACON_TRACKING, 4642 4626 }; 4643 4627 4644 4628 struct rtw89_fw_suit { ··· 4699 4681 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4700 4682 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4701 4683 const struct rtw89_regd_data *regd; 4684 + const struct rtw89_fw_element_hdr *afe; 4702 4685 }; 4703 4686 4704 4687 enum rtw89_fw_mss_dev_type { ··· 5093 5074 struct rtw89_pkt_stat { 5094 5075 u16 beacon_nr; 5095 5076 u8 beacon_rate; 5077 + u32 beacon_len; 5096 5078 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5079 + }; 5080 + 5081 + #define RTW89_BCN_TRACK_STAT_NR 32 5082 + #define RTW89_BCN_TRACK_SCALE_FACTOR 10 5083 + #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 5084 + #define RTW89_BCN_TRACK_BIN_WIDTH 5 5085 + #define RTW89_BCN_TRACK_TARGET_BCN 80 5086 + 5087 + struct rtw89_beacon_dist { 5088 + u16 min; 5089 + u16 max; 5090 + u16 outlier_count; 5091 + u16 lower_bound; 5092 + u16 upper_bound; 5093 + u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 5094 + }; 5095 + 5096 + struct rtw89_beacon_stat { 5097 + u8 num; 5098 + u8 wp; 5099 + u16 tbtt_tu_min; 5100 + u16 tbtt_tu_max; 5101 + u16 drift[RTW89_BCN_TRACK_STAT_NR]; 5102 + u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 5103 + u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 5104 + struct rtw89_beacon_dist bcn_dist; 5097 5105 }; 5098 5106 5099 5107 DECLARE_EWMA(thermal, 4, 4); ··· 5131 5085 struct ewma_rssi bcn_rssi; 5132 5086 struct rtw89_pkt_stat cur_pkt_stat; 5133 5087 struct rtw89_pkt_stat last_pkt_stat; 5088 + struct rtw89_beacon_stat bcn_stat; 5134 5089 }; 5135 5090 5136 5091 enum rtw89_rfk_report_state { ··· 5481 5434 struct rtw89_ccx_para_info { 5482 5435 enum rtw89_env_racing_lv rac_lv; 5483 5436 u16 mntr_time; 5437 + bool nhm_incld_cca; 5484 5438 u8 nhm_manual_th_ofst; 5485 5439 u8 nhm_manual_th0; 5486 5440 enum rtw89_ifs_clm_application ifs_clm_app; ··· 5515 5467 RTW89_CCX_EDCCA_BW20_7 = 7 5516 5468 }; 5517 5469 5518 - #define RTW89_NHM_TH_NUM 11 5470 + struct rtw89_nhm_report { 5471 + struct list_head list; 5472 + struct ieee80211_channel *channel; 5473 + u8 noise; 5474 + }; 5475 + 5519 5476 #define RTW89_FAHM_TH_NUM 11 5520 - #define RTW89_NHM_RPT_NUM 12 5521 5477 #define RTW89_FAHM_RPT_NUM 12 5522 5478 #define RTW89_IFS_CLM_NUM 4 5523 5479 struct rtw89_env_monitor_info { ··· 5555 5503 u16 ifs_clm_ofdm_fa_permil; 5556 5504 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5557 5505 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5506 + bool nhm_include_cca; 5507 + u32 nhm_sum; 5508 + u32 nhm_mntr_time; 5509 + u16 nhm_result[RTW89_NHM_RPT_NUM]; 5510 + u8 nhm_th[RTW89_NHM_RPT_NUM]; 5511 + struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 5512 + struct list_head nhm_rpt_list; 5558 5513 }; 5559 5514 5560 5515 enum rtw89_ser_rcvy_step { ··· 5774 5715 u8 kck[32]; 5775 5716 u8 kek[32]; 5776 5717 u8 tk1[16]; 5777 - u8 txmickey[8]; 5778 5718 u8 rxmickey[8]; 5719 + u8 txmickey[8]; 5779 5720 __le32 igtk_keyid; 5780 5721 __le64 ipn; 5781 5722 u8 igtk[2][32]; ··· 5941 5882 struct rtw89_wait_info wait; 5942 5883 }; 5943 5884 5885 + struct rtw89_beacon_track_info { 5886 + bool is_data_ready; 5887 + u32 tbtt_offset; /* in unit of microsecond */ 5888 + u16 bcn_timeout; /* in unit of millisecond */ 5889 + 5890 + /* The following are constant and set at association. */ 5891 + u8 dtim; 5892 + u16 beacon_int; 5893 + u16 low_bcn_th; 5894 + u16 med_bcn_th; 5895 + u16 high_bcn_th; 5896 + u16 target_bcn_th; 5897 + u16 outlier_low_bcn_th; 5898 + u16 outlier_high_bcn_th; 5899 + u32 close_bcn_intvl_th; 5900 + u32 tbtt_diff_th; 5901 + }; 5902 + 5944 5903 struct rtw89_dev { 5945 5904 struct ieee80211_hw *hw; 5946 5905 struct device *dev; ··· 5973 5896 const struct rtw89_pci_info *pci_info; 5974 5897 const struct rtw89_rfe_parms *rfe_parms; 5975 5898 struct rtw89_hal hal; 5899 + struct rtw89_beacon_track_info bcn_track; 5976 5900 struct rtw89_mcc_info mcc; 5977 5901 struct rtw89_mlo_info mlo; 5978 5902 struct rtw89_mac_info mac; ··· 6002 5924 struct work_struct ba_work; 6003 5925 /* used to protect rpwm */ 6004 5926 spinlock_t rpwm_lock; 5927 + 5928 + struct list_head tx_waits; 5929 + struct wiphy_delayed_work tx_wait_work; 6005 5930 6006 5931 struct rtw89_cam_info cam_info; 6007 5932 ··· 6262 6181 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6263 6182 }) 6264 6183 6184 + static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 6185 + { 6186 + dev_kfree_skb_any(wait->skb); 6187 + kfree_rcu(wait, rcu_head); 6188 + } 6189 + 6190 + static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 6191 + { 6192 + struct rtw89_tx_wait_info *wait, *tmp; 6193 + 6194 + lockdep_assert_wiphy(rtwdev->hw->wiphy); 6195 + 6196 + list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 6197 + if (!completion_done(&wait->completion)) 6198 + continue; 6199 + list_del(&wait->list); 6200 + rtw89_tx_wait_release(wait); 6201 + } 6202 + } 6203 + 6265 6204 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6266 6205 struct rtw89_core_tx_request *tx_req) 6267 6206 { ··· 6291 6190 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6292 6191 { 6293 6192 rtwdev->hci.ops->reset(rtwdev); 6193 + rtw89_tx_wait_list_clear(rtwdev); 6294 6194 } 6295 6195 6296 6196 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) ··· 6424 6322 static inline 6425 6323 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6426 6324 { 6325 + /* 6326 + * This should be used by/after rtw89_hci_tx_write() and before doing 6327 + * ieee80211_tx_info_clear_status(). 6328 + */ 6427 6329 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6428 6330 6429 - return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6331 + return (struct rtw89_tx_skb_data *)info->driver_data; 6430 6332 } 6431 6333 6432 6334 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) ··· 7237 7131 } 7238 7132 7239 7133 static inline 7134 + u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 7135 + { 7136 + const struct rtw89_chip_info *chip = rtwdev->chip; 7137 + 7138 + return chip->ops->get_ch_dma(rtwdev, qsel); 7139 + } 7140 + 7141 + static inline 7240 7142 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7241 7143 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7242 7144 { ··· 7372 7258 return dev_alloc_skb(length); 7373 7259 } 7374 7260 7375 - static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7261 + static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7376 7262 struct rtw89_tx_skb_data *skb_data, 7377 7263 bool tx_done) 7378 7264 { 7379 7265 struct rtw89_tx_wait_info *wait; 7266 + bool ret = false; 7380 7267 7381 7268 rcu_read_lock(); 7382 7269 ··· 7385 7270 if (!wait) 7386 7271 goto out; 7387 7272 7273 + ret = true; 7388 7274 wait->tx_done = tx_done; 7389 - complete(&wait->completion); 7275 + /* Don't access skb anymore after completion */ 7276 + complete_all(&wait->completion); 7390 7277 7391 7278 out: 7392 7279 rcu_read_unlock(); 7280 + return ret; 7393 7281 } 7394 7282 7395 7283 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) ··· 7476 7358 struct sk_buff *skb, bool fwdl); 7477 7359 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7478 7360 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7479 - int qsel, unsigned int timeout); 7361 + struct rtw89_tx_wait_info *wait, int qsel, 7362 + unsigned int timeout); 7480 7363 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7481 7364 struct rtw89_tx_desc_info *desc_info, 7482 7365 void *txdesc); ··· 7493 7374 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7494 7375 struct rtw89_tx_desc_info *desc_info, 7495 7376 void *txdesc); 7377 + u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 7378 + u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 7496 7379 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7497 7380 struct rtw89_rx_desc_info *desc_info, 7498 7381 struct sk_buff *skb); ··· 7575 7454 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7576 7455 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7577 7456 struct rtw89_vif_link *rtwvif_link); 7578 - bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7457 + bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 7579 7458 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7580 7459 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7581 7460 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7582 7461 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7583 7462 struct rtw89_traffic_stats *stats); 7584 - int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7463 + struct rtw89_wait_response * 7464 + rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 7465 + __acquires(rtw89_wait); 7466 + int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 7467 + struct rtw89_wait_response *prep, int err) 7468 + __releases(rtw89_wait); 7585 7469 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7586 7470 const struct rtw89_completion_data *data); 7587 7471 int rtw89_core_start(struct rtw89_dev *rtwdev);

+124 -1

drivers/net/wireless/realtek/rtw89/debug.c

··· 86 86 struct rtw89_debugfs_priv stations; 87 87 struct rtw89_debugfs_priv disable_dm; 88 88 struct rtw89_debugfs_priv mlo_mode; 89 + struct rtw89_debugfs_priv beacon_info; 89 90 }; 90 91 91 92 struct rtw89_debugfs_iter_data { ··· 3563 3562 return 0; 3564 3563 } 3565 3564 3565 + static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) 3566 + { 3567 + u16 val16; 3568 + u8 val8; 3569 + int ret; 3570 + 3571 + ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3572 + if (ret) 3573 + return ret; 3574 + 3575 + val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3576 + rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3577 + mdelay(1); 3578 + rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3579 + 3580 + val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3581 + rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3582 + rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3583 + 3584 + return 0; 3585 + } 3586 + 3587 + static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) 3588 + { 3589 + int ret; 3590 + 3591 + ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3592 + if (ret) 3593 + return ret; 3594 + 3595 + rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3596 + B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3597 + 3598 + return 0; 3599 + } 3600 + 3601 + static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev) 3602 + { 3603 + const struct rtw89_chip_info *chip = rtwdev->chip; 3604 + 3605 + rtw89_leave_ps_mode(rtwdev); 3606 + 3607 + switch (chip->chip_gen) { 3608 + case RTW89_CHIP_AX: 3609 + return rtw89_dbg_trigger_mac_error_ax(rtwdev); 3610 + case RTW89_CHIP_BE: 3611 + return rtw89_dbg_trigger_mac_error_be(rtwdev); 3612 + default: 3613 + return -EOPNOTSUPP; 3614 + } 3615 + } 3616 + 3566 3617 static ssize_t 3567 3618 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3568 3619 struct rtw89_debugfs_priv *debugfs_priv, ··· 3630 3577 enum rtw89_dbg_crash_simulation_type { 3631 3578 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3632 3579 RTW89_DBG_SIM_CTRL_ERROR = 2, 3580 + RTW89_DBG_SIM_MAC_ERROR = 3, 3633 3581 }; 3634 3582 3635 3583 static ssize_t ··· 3639 3585 const char *buf, size_t count) 3640 3586 { 3641 3587 int (*sim)(struct rtw89_dev *rtwdev); 3588 + bool announce = true; 3642 3589 u8 crash_type; 3643 3590 int ret; 3644 3591 ··· 3658 3603 case RTW89_DBG_SIM_CTRL_ERROR: 3659 3604 sim = rtw89_dbg_trigger_ctrl_error; 3660 3605 break; 3606 + case RTW89_DBG_SIM_MAC_ERROR: 3607 + sim = rtw89_dbg_trigger_mac_error; 3608 + 3609 + /* Driver SER flow won't get involved; only FW will. */ 3610 + announce = false; 3611 + break; 3661 3612 default: 3662 3613 return -EINVAL; 3663 3614 } 3664 3615 3665 - set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3616 + if (announce) 3617 + set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3618 + 3666 3619 ret = sim(rtwdev); 3667 3620 3668 3621 if (ret) ··· 4361 4298 return count; 4362 4299 } 4363 4300 4301 + static ssize_t 4302 + rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 4303 + struct rtw89_debugfs_priv *debugfs_priv, 4304 + char *buf, size_t bufsz) 4305 + { 4306 + struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 4307 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 4308 + struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 4309 + struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 4310 + u16 upper, lower = bcn_stat->tbtt_tu_min; 4311 + char *p = buf, *end = buf + bufsz; 4312 + u16 *drift = bcn_stat->drift; 4313 + u8 bcn_num = bcn_stat->num; 4314 + u8 count; 4315 + u8 i; 4316 + 4317 + p += scnprintf(p, end - p, "[Beacon info]\n"); 4318 + p += scnprintf(p, end - p, "count: %u\n", pkt_stat->beacon_nr); 4319 + p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 4320 + p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 4321 + p += scnprintf(p, end - p, "raw rssi: %lu\n", 4322 + ewma_rssi_read(&rtwdev->phystat.bcn_rssi)); 4323 + p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 4324 + p += scnprintf(p, end - p, "length: %u\n", pkt_stat->beacon_len); 4325 + 4326 + p += scnprintf(p, end - p, "\n[Distribution]\n"); 4327 + p += scnprintf(p, end - p, "tbtt\n"); 4328 + for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 4329 + upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 4330 + if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 4331 + upper = max(upper, bcn_stat->tbtt_tu_max); 4332 + 4333 + p += scnprintf(p, end - p, "%02u - %02u: %u\n", 4334 + lower, upper, bcn_dist->bins[i]); 4335 + 4336 + lower = upper + 1; 4337 + } 4338 + 4339 + p += scnprintf(p, end - p, "\ndrift\n"); 4340 + 4341 + for (i = 0; i < bcn_num; i += count) { 4342 + count = 1; 4343 + while (i + count < bcn_num && drift[i] == drift[i + count]) 4344 + count++; 4345 + 4346 + p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 4347 + } 4348 + p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 4349 + p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 4350 + p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 4351 + 4352 + p += scnprintf(p, end - p, "\n[Tracking]\n"); 4353 + p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 4354 + p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 4355 + 4356 + return p - buf; 4357 + } 4358 + 4364 4359 #define rtw89_debug_priv_get(name, opts...) \ 4365 4360 { \ 4366 4361 .cb_read = rtw89_debug_priv_ ##name## _get, \ ··· 4477 4356 .stations = rtw89_debug_priv_get(stations, RLOCK), 4478 4357 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4479 4358 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4359 + .beacon_info = rtw89_debug_priv_get(beacon_info), 4480 4360 }; 4481 4361 4482 4362 #define rtw89_debugfs_add(name, mode, fopname, parent) \ ··· 4523 4401 rtw89_debugfs_add_r(stations); 4524 4402 rtw89_debugfs_add_rw(disable_dm); 4525 4403 rtw89_debugfs_add_rw(mlo_mode); 4404 + rtw89_debugfs_add_r(beacon_info); 4526 4405 } 4527 4406 4528 4407 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)

+1

drivers/net/wireless/realtek/rtw89/debug.h

··· 56 56 #endif 57 57 58 58 #define rtw89_info(rtwdev, a...) dev_info((rtwdev)->dev, ##a) 59 + #define rtw89_info_once(rtwdev, a...) dev_info_once((rtwdev)->dev, ##a) 59 60 #define rtw89_warn(rtwdev, a...) dev_warn((rtwdev)->dev, ##a) 60 61 #define rtw89_err(rtwdev, a...) dev_err((rtwdev)->dev, ##a) 61 62

+165 -12

drivers/net/wireless/realtek/rtw89/fw.c

··· 830 830 __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG), 831 831 __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, CRASH_TRIGGER_TYPE_1), 832 832 __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, SCAN_OFFLOAD_EXTRA_OP), 833 + __CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, BEACON_TRACKING), 833 834 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, NO_LPS_PG), 834 835 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, TX_WAKE), 835 836 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 90, 0, CRASH_TRIGGER_TYPE_0), 836 837 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 91, 0, SCAN_OFFLOAD), 837 838 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 110, 0, BEACON_FILTER), 839 + __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 122, 0, BEACON_TRACKING), 838 840 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, SCAN_OFFLOAD_EXTRA_OP), 839 841 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG), 840 842 __CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, CRASH_TRIGGER_TYPE_1), ··· 848 846 __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 56, 10, BEACON_FILTER), 849 847 __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 80, 0, WOW_REASON_V1), 850 848 __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, BEACON_LOSS_COUNT_V1), 849 + __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, LPS_DACK_BY_C2H_REG), 850 + __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, CRASH_TRIGGER_TYPE_1), 851 + __CFG_FW_FEAT(RTL8852C, ge, 0, 27, 129, 1, BEACON_TRACKING), 851 852 __CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER_TYPE_0), 852 853 __CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP), 853 854 __CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD), ··· 869 864 __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 71, 0, BEACON_LOSS_COUNT_V1), 870 865 __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 76, 0, LPS_DACK_BY_C2H_REG), 871 866 __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 79, 0, CRASH_TRIGGER_TYPE_1), 867 + __CFG_FW_FEAT(RTL8922A, ge, 0, 35, 80, 0, BEACON_TRACKING), 872 868 }; 873 869 874 870 static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw, ··· 1286 1280 return 0; 1287 1281 } 1288 1282 1283 + static 1284 + int rtw89_build_afe_pwr_seq_from_elm(struct rtw89_dev *rtwdev, 1285 + const struct rtw89_fw_element_hdr *elm, 1286 + const union rtw89_fw_element_arg arg) 1287 + { 1288 + struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1289 + 1290 + elm_info->afe = elm; 1291 + 1292 + return 0; 1293 + } 1294 + 1289 1295 static const struct rtw89_fw_element_handler __fw_element_handlers[] = { 1290 1296 [RTW89_FW_ELEMENT_ID_BBMCU0] = {__rtw89_fw_recognize_from_elm, 1291 1297 { .fw_type = RTW89_FW_BBMCU0 }, NULL}, ··· 1382 1364 }, 1383 1365 [RTW89_FW_ELEMENT_ID_REGD] = { 1384 1366 rtw89_recognize_regd_from_elm, {}, "REGD", 1367 + }, 1368 + [RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ] = { 1369 + rtw89_build_afe_pwr_seq_from_elm, {}, "AFE", 1385 1370 }, 1386 1371 }; 1387 1372 ··· 1558 1537 struct rtw89_fw_hdr *fw_hdr; 1559 1538 struct sk_buff *skb; 1560 1539 u32 truncated; 1561 - u32 ret = 0; 1540 + int ret; 1562 1541 1563 1542 skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 1564 1543 if (!skb) { ··· 4010 3989 return ret; 4011 3990 } 4012 3991 EXPORT_SYMBOL(rtw89_fw_h2c_update_beacon_be); 3992 + 3993 + int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev, 3994 + struct rtw89_vif_link *rtwvif_link, u32 offset) 3995 + { 3996 + struct rtw89_h2c_tbtt_tuning *h2c; 3997 + u32 len = sizeof(*h2c); 3998 + struct sk_buff *skb; 3999 + int ret; 4000 + 4001 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 4002 + if (!skb) { 4003 + rtw89_err(rtwdev, "failed to alloc skb for h2c tbtt tuning\n"); 4004 + return -ENOMEM; 4005 + } 4006 + skb_put(skb, len); 4007 + h2c = (struct rtw89_h2c_tbtt_tuning *)skb->data; 4008 + 4009 + h2c->w0 = le32_encode_bits(rtwvif_link->phy_idx, RTW89_H2C_TBTT_TUNING_W0_BAND) | 4010 + le32_encode_bits(rtwvif_link->port, RTW89_H2C_TBTT_TUNING_W0_PORT); 4011 + h2c->w1 = le32_encode_bits(offset, RTW89_H2C_TBTT_TUNING_W1_SHIFT); 4012 + 4013 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 4014 + H2C_CAT_MAC, H2C_CL_MAC_PS, 4015 + H2C_FUNC_TBTT_TUNING, 0, 0, 4016 + len); 4017 + 4018 + ret = rtw89_h2c_tx(rtwdev, skb, false); 4019 + if (ret) { 4020 + rtw89_err(rtwdev, "failed to send h2c\n"); 4021 + goto fail; 4022 + } 4023 + 4024 + return 0; 4025 + fail: 4026 + dev_kfree_skb_any(skb); 4027 + 4028 + return ret; 4029 + } 4030 + 4031 + int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 4032 + { 4033 + #define RTW89_BCN_TO_VAL_MIN 4 4034 + #define RTW89_BCN_TO_VAL_MAX 64 4035 + #define RTW89_DTIM_TO_VAL_MIN 7 4036 + #define RTW89_DTIM_TO_VAL_MAX 15 4037 + struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 4038 + struct rtw89_h2c_pwr_lvl *h2c; 4039 + u32 len = sizeof(*h2c); 4040 + struct sk_buff *skb; 4041 + u8 bcn_to_val; 4042 + int ret; 4043 + 4044 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 4045 + if (!skb) { 4046 + rtw89_err(rtwdev, "failed to alloc skb for h2c pwr lvl\n"); 4047 + return -ENOMEM; 4048 + } 4049 + skb_put(skb, len); 4050 + h2c = (struct rtw89_h2c_pwr_lvl *)skb->data; 4051 + 4052 + bcn_to_val = clamp_t(u8, bcn_track->bcn_timeout, 4053 + RTW89_BCN_TO_VAL_MIN, RTW89_BCN_TO_VAL_MAX); 4054 + 4055 + h2c->w0 = le32_encode_bits(rtwvif_link->mac_id, RTW89_H2C_PWR_LVL_W0_MACID) | 4056 + le32_encode_bits(bcn_to_val, RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL) | 4057 + le32_encode_bits(0, RTW89_H2C_PWR_LVL_W0_PS_LVL) | 4058 + le32_encode_bits(0, RTW89_H2C_PWR_LVL_W0_TRX_LVL) | 4059 + le32_encode_bits(RTW89_DTIM_TO_VAL_MIN, 4060 + RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL); 4061 + 4062 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 4063 + H2C_CAT_MAC, H2C_CL_MAC_PS, 4064 + H2C_FUNC_PS_POWER_LEVEL, 0, 0, 4065 + len); 4066 + 4067 + ret = rtw89_h2c_tx(rtwdev, skb, false); 4068 + if (ret) { 4069 + rtw89_err(rtwdev, "failed to send h2c\n"); 4070 + goto fail; 4071 + } 4072 + 4073 + return 0; 4074 + fail: 4075 + dev_kfree_skb_any(skb); 4076 + 4077 + return ret; 4078 + } 4013 4079 4014 4080 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 4015 4081 struct rtw89_vif_link *rtwvif_link, ··· 6688 6580 return ret; 6689 6581 } 6690 6582 6583 + int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable) 6584 + { 6585 + struct rtw89_h2c_rf_tas *h2c; 6586 + u32 len = sizeof(*h2c); 6587 + struct sk_buff *skb; 6588 + int ret; 6589 + 6590 + skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len); 6591 + if (!skb) { 6592 + rtw89_err(rtwdev, "failed to alloc skb for h2c RF TAS\n"); 6593 + return -ENOMEM; 6594 + } 6595 + skb_put(skb, len); 6596 + h2c = (struct rtw89_h2c_rf_tas *)skb->data; 6597 + 6598 + h2c->enable = cpu_to_le32(enable); 6599 + 6600 + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, 6601 + H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK, 6602 + H2C_FUNC_RFK_TAS_OFFLOAD, 0, 0, len); 6603 + 6604 + ret = rtw89_h2c_tx(rtwdev, skb, false); 6605 + if (ret) { 6606 + rtw89_err(rtwdev, "failed to send h2c\n"); 6607 + goto fail; 6608 + } 6609 + 6610 + return 0; 6611 + fail: 6612 + dev_kfree_skb_any(skb); 6613 + 6614 + return ret; 6615 + } 6616 + 6691 6617 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 6692 6618 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 6693 6619 bool rack, bool dack) ··· 6968 6826 const struct rtw89_chip_info *chip = rtwdev->chip; 6969 6827 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6970 6828 const u32 *c2h_reg = chip->c2h_regs; 6971 - u32 ret, timeout; 6829 + u32 timeout; 6972 6830 u8 i, val; 6831 + int ret; 6973 6832 6974 6833 info->id = RTW89_FWCMD_C2HREG_FUNC_NULL; 6975 6834 ··· 7008 6865 struct rtw89_mac_h2c_info *h2c_info, 7009 6866 struct rtw89_mac_c2h_info *c2h_info) 7010 6867 { 7011 - u32 ret; 6868 + int ret; 7012 6869 7013 6870 if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE) 7014 6871 lockdep_assert_wiphy(rtwdev->hw->wiphy); ··· 7266 7123 struct rtw89_pktofld_info *info; 7267 7124 u8 probe_count = 0; 7268 7125 7269 - ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK; 7270 7126 ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS; 7271 7127 ch_info->bw = RTW89_SCAN_WIDTH; 7272 7128 ch_info->tx_pkt = true; ··· 7406 7264 struct rtw89_pktofld_info *info; 7407 7265 u8 probe_count = 0, i; 7408 7266 7409 - ch_info->notify_action = RTW89_SCANOFLD_DEBUG_MASK; 7410 7267 ch_info->dfs_ch = chan_type == RTW89_CHAN_DFS; 7411 7268 ch_info->bw = RTW89_SCAN_WIDTH; 7412 7269 ch_info->tx_null = false; ··· 8726 8585 goto fail; 8727 8586 } 8728 8587 8729 - /* not support TKIP yet */ 8730 8588 h2c->w0 = le32_encode_bits(enable, RTW89_H2C_WOW_GTK_OFLD_W0_EN) | 8731 - le32_encode_bits(0, RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN) | 8589 + le32_encode_bits(!!memchr_inv(gtk_info->txmickey, 0, 8590 + sizeof(gtk_info->txmickey)), 8591 + RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN) | 8732 8592 le32_encode_bits(gtk_info->igtk_keyid ? 1 : 0, 8733 8593 RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN) | 8734 8594 le32_encode_bits(macid, RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID) | ··· 8821 8679 static int rtw89_h2c_tx_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 8822 8680 struct rtw89_wait_info *wait, unsigned int cond) 8823 8681 { 8824 - int ret; 8682 + struct rtw89_wait_response *prep; 8683 + int ret = 0; 8684 + 8685 + lockdep_assert_wiphy(rtwdev->hw->wiphy); 8686 + 8687 + prep = rtw89_wait_for_cond_prep(wait, cond); 8688 + if (IS_ERR(prep)) 8689 + goto out; 8825 8690 8826 8691 ret = rtw89_h2c_tx(rtwdev, skb, false); 8827 8692 if (ret) { 8828 8693 rtw89_err(rtwdev, "failed to send h2c\n"); 8829 8694 dev_kfree_skb_any(skb); 8830 - return -EBUSY; 8695 + ret = -EBUSY; 8696 + goto out; 8831 8697 } 8832 8698 8833 - if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) 8834 - return 1; 8699 + if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 8700 + ret = 1; 8701 + goto out; 8702 + } 8835 8703 8836 - return rtw89_wait_for_cond(wait, cond); 8704 + out: 8705 + return rtw89_wait_for_cond_eval(wait, prep, ret); 8837 8706 } 8838 8707 8839 8708 #define H2C_ADD_MCC_LEN 16

+75 -2

drivers/net/wireless/realtek/rtw89/fw.h

··· 1602 1602 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16) 1603 1603 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31) 1604 1604 1605 + struct rtw89_h2c_tbtt_tuning { 1606 + __le32 w0; 1607 + __le32 w1; 1608 + } __packed; 1609 + 1610 + #define RTW89_H2C_TBTT_TUNING_W0_BAND GENMASK(3, 0) 1611 + #define RTW89_H2C_TBTT_TUNING_W0_PORT GENMASK(7, 4) 1612 + #define RTW89_H2C_TBTT_TUNING_W1_SHIFT GENMASK(31, 0) 1613 + 1614 + struct rtw89_h2c_pwr_lvl { 1615 + __le32 w0; 1616 + __le32 w1; 1617 + } __packed; 1618 + 1619 + #define RTW89_H2C_PWR_LVL_W0_MACID GENMASK(7, 0) 1620 + #define RTW89_H2C_PWR_LVL_W0_BCN_TO_VAL GENMASK(15, 8) 1621 + #define RTW89_H2C_PWR_LVL_W0_PS_LVL GENMASK(19, 16) 1622 + #define RTW89_H2C_PWR_LVL_W0_TRX_LVL GENMASK(23, 20) 1623 + #define RTW89_H2C_PWR_LVL_W0_BCN_TO_LVL GENMASK(27, 24) 1624 + #define RTW89_H2C_PWR_LVL_W0_DTIM_TO_VAL GENMASK(31, 28) 1625 + #define RTW89_H2C_PWR_LVL_W1_MACID_EXT GENMASK(7, 0) 1626 + 1605 1627 struct rtw89_h2c_role_maintain { 1606 1628 __le32 w0; 1607 1629 }; ··· 3984 3962 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24, 3985 3963 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25, 3986 3964 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26, 3965 + RTW89_FW_ELEMENT_ID_AFE_PWR_SEQ = 27, 3987 3966 3988 3967 RTW89_FW_ELEMENT_ID_NUM, 3989 3968 }; ··· 4090 4067 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \ 4091 4068 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P)) 4092 4069 4070 + enum rtw89_fw_afe_action { 4071 + RTW89_FW_AFE_ACTION_WRITE = 0, 4072 + RTW89_FW_AFE_ACTION_DELAY = 1, 4073 + RTW89_FW_AFE_ACTION_POLL = 2, 4074 + }; 4075 + 4076 + enum rtw89_fw_afe_cat { 4077 + RTW89_FW_AFE_CAT_BB = 0, 4078 + RTW89_FW_AFE_CAT_BB1 = 1, 4079 + RTW89_FW_AFE_CAT_MAC = 2, 4080 + RTW89_FW_AFE_CAT_MAC1 = 3, 4081 + RTW89_FW_AFE_CAT_AFEDIG = 4, 4082 + RTW89_FW_AFE_CAT_AFEDIG1 = 5, 4083 + }; 4084 + 4085 + enum rtw89_fw_afe_class { 4086 + RTW89_FW_AFE_CLASS_P0 = 0, 4087 + RTW89_FW_AFE_CLASS_P1 = 1, 4088 + RTW89_FW_AFE_CLASS_P2 = 2, 4089 + RTW89_FW_AFE_CLASS_P3 = 3, 4090 + RTW89_FW_AFE_CLASS_P4 = 4, 4091 + RTW89_FW_AFE_CLASS_CMN = 5, 4092 + }; 4093 + 4093 4094 struct rtw89_fw_element_hdr { 4094 4095 __le32 id; /* enum rtw89_fw_element_id */ 4095 4096 __le32 size; /* exclude header size */ ··· 4151 4104 u8 rsvd1[3]; 4152 4105 __le16 offset[]; 4153 4106 } __packed rfk_log_fmt; 4107 + struct { 4108 + u8 rsvd[8]; 4109 + struct rtw89_phy_afe_info { 4110 + __le32 action; /* enum rtw89_fw_afe_action */ 4111 + __le32 cat; /* enum rtw89_fw_afe_cat */ 4112 + __le32 class; /* enum rtw89_fw_afe_class */ 4113 + __le32 addr; 4114 + __le32 mask; 4115 + __le32 val; 4116 + } __packed infos[]; 4117 + } __packed afe; 4154 4118 struct __rtw89_fw_txpwr_element txpwr; 4155 4119 struct __rtw89_fw_regd_element regd; 4156 4120 } __packed u; ··· 4259 4201 H2C_FUNC_MAC_LPS_PARM = 0x0, 4260 4202 H2C_FUNC_P2P_ACT = 0x1, 4261 4203 H2C_FUNC_IPS_CFG = 0x3, 4204 + H2C_FUNC_PS_POWER_LEVEL = 0x7, 4205 + H2C_FUNC_TBTT_TUNING = 0xA, 4262 4206 4263 4207 NUM_OF_RTW89_PS_H2C_FUNC, 4264 4208 }; ··· 4430 4370 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5, 4431 4371 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6, 4432 4372 H2C_FUNC_RFK_PRE_NOTIFY = 0x8, 4373 + H2C_FUNC_RFK_TAS_OFFLOAD = 0x9, 4433 4374 }; 4434 4375 4435 4376 struct rtw89_fw_h2c_rf_get_mccch { ··· 4612 4551 u8 rxdck_dbg_en; 4613 4552 } __packed; 4614 4553 4554 + struct rtw89_h2c_rf_tas { 4555 + __le32 enable; 4556 + } __packed; 4557 + 4615 4558 struct rtw89_h2c_rf_rxdck { 4616 4559 struct rtw89_h2c_rf_rxdck_v0 v0; 4617 4560 u8 is_chl_k; ··· 4748 4683 u8 version; 4749 4684 } __packed; 4750 4685 4751 - struct rtw89_c2h_rf_tas_info { 4752 - struct rtw89_c2h_hdr hdr; 4686 + struct rtw89_c2h_rf_tas_rpt_log { 4753 4687 __le32 cur_idx; 4754 4688 __le16 txpwr_history[20]; 4689 + } __packed; 4690 + 4691 + struct rtw89_c2h_rf_tas_info { 4692 + struct rtw89_c2h_hdr hdr; 4693 + struct rtw89_c2h_rf_tas_rpt_log content; 4755 4694 } __packed; 4756 4695 4757 4696 #define RTW89_FW_RSVD_PLE_SIZE 0x800 ··· 4819 4750 struct rtw89_vif_link *rtwvif_link); 4820 4751 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev, 4821 4752 struct rtw89_vif_link *rtwvif_link); 4753 + int rtw89_fw_h2c_tbtt_tuning(struct rtw89_dev *rtwdev, 4754 + struct rtw89_vif_link *rtwvif_link, u32 offset); 4755 + int rtw89_fw_h2c_pwr_lvl(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 4822 4756 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif, 4823 4757 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr); 4824 4758 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, ··· 4898 4826 const struct rtw89_chan *chan); 4899 4827 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 4900 4828 const struct rtw89_chan *chan, bool is_chl_k); 4829 + int rtw89_fw_h2c_rf_tas_trigger(struct rtw89_dev *rtwdev, bool enable); 4901 4830 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 4902 4831 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 4903 4832 bool rack, bool dack);

+45 -27

drivers/net/wireless/realtek/rtw89/mac.c

··· 9 9 #include "fw.h" 10 10 #include "mac.h" 11 11 #include "pci.h" 12 + #include "phy.h" 12 13 #include "ps.h" 13 14 #include "reg.h" 14 15 #include "util.h" ··· 178 177 struct rtw89_mac_dle_dfi_qempty *qempty) 179 178 { 180 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 181 - u32 ret; 180 + int ret; 182 181 183 182 ctrl.type = qempty->dle_type; 184 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; ··· 986 985 struct rtw89_hfc_ch_info *info = param->ch_info; 987 986 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 987 u32 val; 989 - u32 ret; 988 + int ret; 990 989 991 990 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 991 if (ret) ··· 1177 1176 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 1177 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 1178 u32 dma_ch_mask = chip->dma_ch_mask; 1179 + int ret = 0; 1180 1180 u8 ch; 1181 - u32 ret = 0; 1182 1181 1183 1182 if (reset) 1184 1183 ret = hfc_reset_param(rtwdev); ··· 1194 1193 if (!en && h2c_en) { 1195 1194 mac->hfc_h2c_cfg(rtwdev); 1196 1195 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 - return ret; 1196 + return 0; 1198 1197 } 1199 1198 1200 1199 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { ··· 2414 2413 2415 2414 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2416 2415 { 2417 - u32 ret; 2416 + int ret; 2418 2417 u32 reg; 2419 2418 u32 val; 2420 2419 ··· 2955 2954 struct rtw89_mac_h2c_info h2c_info = {}; 2956 2955 enum rtw89_mac_c2h_type c2h_type; 2957 2956 u8 content_len; 2958 - u32 ret; 2957 + int ret; 2959 2958 2960 2959 if (chip->chip_gen == RTW89_CHIP_AX) 2961 2960 content_len = 0; ··· 3106 3105 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3107 3106 u16 tx_en_u16, u16 mask_u16) 3108 3107 { 3109 - u32 ret; 3110 3108 struct rtw89_mac_c2h_info c2h_info = {0}; 3111 3109 struct rtw89_mac_h2c_info h2c_info = {0}; 3112 3110 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3111 + int ret; 3113 3112 3114 3113 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3115 3114 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; ··· 4198 4197 .ptcl_dbg = R_AX_PTCL_DBG, 4199 4198 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4200 4199 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4200 + .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4201 4201 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4202 4202 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4203 4203 R_AX_PORT_HGQ_WINDOW_CFG + 3}, ··· 4651 4649 BCN_ERLY_DEF); 4652 4650 } 4653 4651 4654 - static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4655 - struct rtw89_vif_link *rtwvif_link) 4652 + static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4653 + struct rtw89_vif_link *rtwvif_link) 4656 4654 { 4657 4655 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4658 4656 const struct rtw89_port_reg *p = mac->port_base; 4659 - u16 val; 4657 + struct ieee80211_bss_conf *bss_conf; 4658 + u8 bssid_index; 4659 + u32 reg; 4660 4660 4661 - if (rtwdev->chip->chip_id != RTL8852C) 4662 - return; 4661 + rcu_read_lock(); 4663 4662 4664 - if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4665 - rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION) 4666 - return; 4663 + bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4664 + if (bss_conf->nontransmitted) 4665 + bssid_index = bss_conf->bssid_index; 4666 + else 4667 + bssid_index = 0; 4667 4668 4668 - val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4669 - B_AX_TBTT_SHIFT_OFST_SIGN; 4669 + rcu_read_unlock(); 4670 4670 4671 - rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 4672 - B_AX_TBTT_SHIFT_OFST_MASK, val); 4671 + reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4672 + rtwvif_link->mac_idx); 4673 + rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4673 4674 } 4674 4675 4675 4676 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, ··· 4825 4820 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 4826 4821 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 4827 4822 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 4828 - rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif_link); 4829 4823 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 4830 4824 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 4831 4825 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 4832 4826 rtw89_mac_port_tsf_resync_all(rtwdev); 4833 4827 fsleep(BCN_ERLY_SET_DLY); 4834 4828 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 4829 + rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 4835 4830 4836 4831 return 0; 4837 4832 } ··· 5046 5041 if (op_chan) { 5047 5042 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5048 5043 ieee80211_stop_queues(rtwdev->hw); 5044 + } else { 5045 + rtw89_phy_nhm_get_result(rtwdev, band, chan); 5049 5046 } 5050 5047 return; 5051 5048 case RTW89_SCAN_END_SCAN_NOTIFY: ··· 5078 5071 RTW89_CHANNEL_WIDTH_20); 5079 5072 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5080 5073 &new); 5074 + rtw89_phy_nhm_trigger(rtwdev); 5081 5075 } 5082 5076 break; 5083 5077 default: ··· 5244 5236 } 5245 5237 5246 5238 static void 5239 + rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5240 + { 5241 + } 5242 + 5243 + static void 5247 5244 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5248 5245 u32 len) 5249 5246 { ··· 5268 5255 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5269 5256 5270 5257 rtw89_complete_cond(wait, cond, &data); 5258 + } 5259 + 5260 + static void 5261 + rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5262 + { 5271 5263 } 5272 5264 5273 5265 static void ··· 5664 5646 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5665 5647 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5666 5648 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5667 - [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5649 + [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 5668 5650 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5669 5651 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5670 5652 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, ··· 5679 5661 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5680 5662 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5681 5663 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5664 + [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 5682 5665 }; 5683 5666 5684 5667 static ··· 5832 5813 case RTW89_MAC_C2H_CLASS_ROLE: 5833 5814 return; 5834 5815 default: 5835 - rtw89_info(rtwdev, "MAC c2h class %d not support\n", class); 5836 - return; 5816 + break; 5837 5817 } 5838 5818 if (!handler) { 5839 - rtw89_info(rtwdev, "MAC c2h class %d func %d not support\n", class, 5840 - func); 5819 + rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 5820 + class, func); 5841 5821 return; 5842 5822 } 5843 5823 handler(rtwdev, skb, len); ··· 6738 6720 u8 mac_idx = rtwvif_link->mac_idx; 6739 6721 u16 set = mac->muedca_ctrl.mask; 6740 6722 u32 reg; 6741 - u32 ret; 6723 + int ret; 6742 6724 6743 6725 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6744 6726 if (ret) ··· 6880 6862 { 6881 6863 struct rtw89_mac_h2c_info h2c_info = {}; 6882 6864 struct rtw89_mac_c2h_info c2h_info = {}; 6883 - u32 ret; 6865 + int ret; 6884 6866 6885 6867 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 6886 6868 return 0;

+1

drivers/net/wireless/realtek/rtw89/mac.h

··· 419 419 RTW89_MAC_C2H_FUNC_DONE_ACK, 420 420 RTW89_MAC_C2H_FUNC_C2H_LOG, 421 421 RTW89_MAC_C2H_FUNC_BCN_CNT, 422 + RTW89_MAC_C2H_FUNC_BCN_UPD_DONE = 0x06, 422 423 RTW89_MAC_C2H_FUNC_INFO_MAX, 423 424 }; 424 425

+35

drivers/net/wireless/realtek/rtw89/mac80211.c

··· 1837 1837 } 1838 1838 #endif 1839 1839 1840 + static int rtw89_ops_get_survey(struct ieee80211_hw *hw, int idx, 1841 + struct survey_info *survey) 1842 + { 1843 + struct ieee80211_conf *conf = &hw->conf; 1844 + struct rtw89_dev *rtwdev = hw->priv; 1845 + struct rtw89_bb_ctx *bb; 1846 + 1847 + if (idx == 0) { 1848 + survey->channel = conf->chandef.chan; 1849 + survey->filled = SURVEY_INFO_NOISE_DBM; 1850 + survey->noise = RTW89_NOISE_DEFAULT; 1851 + 1852 + return 0; 1853 + } 1854 + 1855 + rtw89_for_each_active_bb(rtwdev, bb) { 1856 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 1857 + struct rtw89_nhm_report *rpt; 1858 + 1859 + rpt = list_first_entry_or_null(&env->nhm_rpt_list, typeof(*rpt), list); 1860 + if (!rpt) 1861 + continue; 1862 + 1863 + survey->filled = SURVEY_INFO_NOISE_DBM; 1864 + survey->noise = rpt->noise - MAX_RSSI; 1865 + survey->channel = rpt->channel; 1866 + list_del_init(&rpt->list); 1867 + 1868 + return 0; 1869 + } 1870 + 1871 + return -EINVAL; 1872 + } 1873 + 1840 1874 static void rtw89_ops_rfkill_poll(struct ieee80211_hw *hw) 1841 1875 { 1842 1876 struct rtw89_dev *rtwdev = hw->priv; ··· 1903 1869 .sta_state = rtw89_ops_sta_state, 1904 1870 .set_key = rtw89_ops_set_key, 1905 1871 .ampdu_action = rtw89_ops_ampdu_action, 1872 + .get_survey = rtw89_ops_get_survey, 1906 1873 .set_rts_threshold = rtw89_ops_set_rts_threshold, 1907 1874 .sta_statistics = rtw89_ops_sta_statistics, 1908 1875 .flush = rtw89_ops_flush,

+1

drivers/net/wireless/realtek/rtw89/mac_be.c

··· 56 56 .ptcl_dbg = R_BE_PTCL_DBG, 57 57 .ptcl_dbg_info = R_BE_PTCL_DBG_INFO, 58 58 .bcn_drop_all = R_BE_BCN_DROP_ALL0, 59 + .bcn_psr_rpt = R_BE_BCN_PSR_RPT_P0, 59 60 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG, 60 61 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2, 61 62 R_BE_PORT_HGQ_WINDOW_CFG + 3},

+353 -113

drivers/net/wireless/realtek/rtw89/pci.c

··· 134 134 static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, 135 135 struct rtw89_pci *rtwpci) 136 136 { 137 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 137 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[RTW89_TXCH_CH12]; 138 138 u32 cnt; 139 139 140 140 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); ··· 440 440 int countdown = rtwdev->napi_budget_countdown; 441 441 u32 cnt; 442 442 443 - rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; 443 + rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RXQ]; 444 444 445 445 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 446 446 if (!cnt) ··· 464 464 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 465 465 struct ieee80211_tx_info *info; 466 466 467 - rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status == RTW89_TX_DONE); 467 + if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status == RTW89_TX_DONE)) 468 + return; 468 469 469 470 info = IEEE80211_SKB_CB(skb); 470 471 ieee80211_tx_info_clear_status(info); ··· 569 568 rtw89_pci_enqueue_txwd(tx_ring, txwd); 570 569 } 571 570 572 - static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, 573 - struct rtw89_pci_rpp_fmt *rpp) 571 + void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp, 572 + struct rtw89_pci_rpp_info *rpp_info) 573 + { 574 + const struct rtw89_pci_rpp_fmt *rpp = _rpp; 575 + 576 + rpp_info->seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); 577 + rpp_info->qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); 578 + rpp_info->tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); 579 + rpp_info->txch = rtw89_chip_get_ch_dma(rtwdev, rpp_info->qsel); 580 + } 581 + EXPORT_SYMBOL(rtw89_pci_parse_rpp); 582 + 583 + void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp, 584 + struct rtw89_pci_rpp_info *rpp_info) 585 + { 586 + const struct rtw89_pci_rpp_fmt_v1 *rpp = _rpp; 587 + 588 + rpp_info->seq = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK); 589 + rpp_info->qsel = le32_get_bits(rpp->w1, RTW89_PCI_RPP_W1_QSEL_V1_MASK); 590 + rpp_info->tx_status = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK); 591 + rpp_info->txch = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_DMA_CH_MASK); 592 + } 593 + EXPORT_SYMBOL(rtw89_pci_parse_rpp_v1); 594 + 595 + static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp) 574 596 { 575 597 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 576 - struct rtw89_pci_tx_ring *tx_ring; 598 + const struct rtw89_pci_info *info = rtwdev->pci_info; 599 + struct rtw89_pci_rpp_info rpp_info = {}; 577 600 struct rtw89_pci_tx_wd_ring *wd_ring; 601 + struct rtw89_pci_tx_ring *tx_ring; 578 602 struct rtw89_pci_tx_wd *txwd; 579 - u16 seq; 580 - u8 qsel, tx_status, txch; 581 603 582 - seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); 583 - qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); 584 - tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); 585 - txch = rtw89_core_get_ch_dma(rtwdev, qsel); 604 + info->parse_rpp(rtwdev, rpp, &rpp_info); 586 605 587 - if (txch == RTW89_TXCH_CH12) { 606 + if (rpp_info.txch == RTW89_TXCH_CH12) { 588 607 rtw89_warn(rtwdev, "should no fwcmd release report\n"); 589 608 return; 590 609 } 591 610 592 - tx_ring = &rtwpci->tx_rings[txch]; 611 + tx_ring = &rtwpci->tx.rings[rpp_info.txch]; 593 612 wd_ring = &tx_ring->wd_ring; 594 - txwd = &wd_ring->pages[seq]; 613 + txwd = &wd_ring->pages[rpp_info.seq]; 595 614 596 - rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); 615 + rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, rpp_info.seq, 616 + rpp_info.tx_status); 597 617 } 598 618 599 619 static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, ··· 639 617 u32 max_cnt) 640 618 { 641 619 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 642 - struct rtw89_pci_rx_info *rx_info; 643 - struct rtw89_pci_rpp_fmt *rpp; 620 + const struct rtw89_pci_info *info = rtwdev->pci_info; 644 621 struct rtw89_rx_desc_info desc_info = {}; 622 + struct rtw89_pci_rx_info *rx_info; 645 623 struct sk_buff *skb; 646 - u32 cnt = 0; 647 - u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); 624 + void *rpp; 648 625 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 626 + u32 rpp_size = info->rpp_fmt_size; 627 + u32 cnt = 0; 649 628 u32 skb_idx; 650 629 u32 offset; 651 630 int ret; ··· 672 649 /* first segment has RX desc */ 673 650 offset = desc_info.offset + desc_info.rxd_len; 674 651 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { 675 - rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); 652 + rpp = skb->data + offset; 676 653 rtw89_pci_release_rpp(rtwdev, rpp); 677 654 } 678 655 ··· 717 694 u32 cnt; 718 695 int work_done; 719 696 720 - rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 697 + rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 721 698 722 699 spin_lock_bh(&rtwpci->trx_lock); 723 700 ··· 747 724 int i; 748 725 749 726 for (i = 0; i < RTW89_RXCH_NUM; i++) { 750 - rx_ring = &rtwpci->rx_rings[i]; 727 + rx_ring = &rtwpci->rx.rings[i]; 751 728 bd_ring = &rx_ring->bd_ring; 752 729 753 730 reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); ··· 820 797 } 821 798 EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v2); 822 799 800 + void rtw89_pci_recognize_intrs_v3(struct rtw89_dev *rtwdev, 801 + struct rtw89_pci *rtwpci, 802 + struct rtw89_pci_isrs *isrs) 803 + { 804 + isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs; 805 + isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ? 806 + rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0; 807 + isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1]; 808 + 809 + /* isrs[0] is not used, so borrow to store RDU status to share common 810 + * flow in rtw89_pci_interrupt_threadfn(). 811 + */ 812 + isrs->isrs[0] = isrs->isrs[1] & (B_BE_PCIE_RDU_CH1_INT | 813 + B_BE_PCIE_RDU_CH0_INT); 814 + 815 + if (isrs->halt_c2h_isrs) 816 + rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs); 817 + if (isrs->isrs[1]) 818 + rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]); 819 + rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs); 820 + } 821 + EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v3); 822 + 823 823 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 824 824 { 825 825 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); ··· 890 844 } 891 845 EXPORT_SYMBOL(rtw89_pci_disable_intr_v2); 892 846 847 + void rtw89_pci_enable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 848 + { 849 + rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs); 850 + rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]); 851 + rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs); 852 + } 853 + EXPORT_SYMBOL(rtw89_pci_enable_intr_v3); 854 + 855 + void rtw89_pci_disable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 856 + { 857 + rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, 0); 858 + rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, 0); 859 + } 860 + EXPORT_SYMBOL(rtw89_pci_disable_intr_v3); 861 + 893 862 static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev) 894 863 { 895 864 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ··· 946 885 struct rtw89_dev *rtwdev = dev; 947 886 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 948 887 const struct rtw89_pci_info *info = rtwdev->pci_info; 949 - const struct rtw89_pci_gen_def *gen_def = info->gen_def; 888 + const struct rtw89_pci_isr_def *isr_def = info->isr_def; 950 889 struct rtw89_pci_isrs isrs; 951 890 unsigned long flags; 952 891 ··· 954 893 rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs); 955 894 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 956 895 957 - if (unlikely(isrs.isrs[0] & gen_def->isr_rdu)) 896 + if (unlikely(isrs.isrs[0] & isr_def->isr_rdu)) 958 897 rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); 959 898 960 - if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_halt_c2h)) 899 + if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_halt_c2h)) 961 900 rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); 962 901 963 - if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_wdt_timeout)) 902 + if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_wdt_timeout)) 964 903 rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); 965 904 966 905 if (unlikely(rtwpci->under_recovery)) ··· 1011 950 return irqret; 1012 951 } 1013 952 953 + #define DEF_TXCHADDRS_TYPE3(gen, ch_idx, txch, v...) \ 954 + [RTW89_TXCH_##ch_idx] = { \ 955 + .num = R_##gen##_##txch##_TXBD_CFG, \ 956 + .idx = R_##gen##_##txch##_TXBD_IDX ##v, \ 957 + .bdram = 0, \ 958 + .desa_l = 0, \ 959 + .desa_h = 0, \ 960 + } 961 + 962 + #define DEF_TXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, txch, grp, v...) \ 963 + [RTW89_TXCH_##ch_idx] = { \ 964 + .num = R_##gen##_##txch##_TXBD_CFG, \ 965 + .idx = R_##gen##_##txch##_TXBD_IDX ##v, \ 966 + .bdram = 0, \ 967 + .desa_l = R_##gen##_##grp##_TXBD_DESA_L, \ 968 + .desa_h = R_##gen##_##grp##_TXBD_DESA_H, \ 969 + } 970 + 1014 971 #define DEF_TXCHADDRS_TYPE2(gen, ch_idx, txch, v...) \ 1015 972 [RTW89_TXCH_##ch_idx] = { \ 1016 973 .num = R_##gen##_##txch##_TXBD_NUM ##v, \ ··· 1054 975 .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ 1055 976 .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ 1056 977 .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ 978 + } 979 + 980 + #define DEF_RXCHADDRS_TYPE3(gen, ch_idx, rxch, v...) \ 981 + [RTW89_RXCH_##ch_idx] = { \ 982 + .num = R_##gen##_RX_##rxch##_RXBD_CONFIG, \ 983 + .idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \ 984 + .desa_l = 0, \ 985 + .desa_h = 0, \ 986 + } 987 + 988 + #define DEF_RXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, rxch, grp, v...) \ 989 + [RTW89_RXCH_##ch_idx] = { \ 990 + .num = R_##gen##_RX_##rxch##_RXBD_CONFIG, \ 991 + .idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \ 992 + .desa_l = R_##gen##_##grp##_RXBD_DESA_L, \ 993 + .desa_h = R_##gen##_##grp##_RXBD_DESA_H, \ 1057 994 } 1058 995 1059 996 #define DEF_RXCHADDRS(gen, ch_idx, rxch, v...) \ ··· 1149 1054 }; 1150 1055 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_be); 1151 1056 1057 + const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be_v1 = { 1058 + .tx = { 1059 + DEF_TXCHADDRS_TYPE3_GRP_BASE(BE, ACH0, CH0, ACQ, _V1), 1060 + /* no CH1 */ 1061 + DEF_TXCHADDRS_TYPE3(BE, ACH2, CH2, _V1), 1062 + /* no CH3 */ 1063 + DEF_TXCHADDRS_TYPE3(BE, ACH4, CH4, _V1), 1064 + /* no CH5 */ 1065 + DEF_TXCHADDRS_TYPE3(BE, ACH6, CH6, _V1), 1066 + /* no CH7 */ 1067 + DEF_TXCHADDRS_TYPE3_GRP_BASE(BE, CH8, CH8, NACQ, _V1), 1068 + /* no CH9 */ 1069 + DEF_TXCHADDRS_TYPE3(BE, CH10, CH10, _V1), 1070 + /* no CH11 */ 1071 + DEF_TXCHADDRS_TYPE3(BE, CH12, CH12, _V1), 1072 + }, 1073 + .rx = { 1074 + DEF_RXCHADDRS_TYPE3_GRP_BASE(BE, RXQ, CH0, HOST0, _V1), 1075 + DEF_RXCHADDRS_TYPE3(BE, RPQ, CH1, _V1), 1076 + }, 1077 + }; 1078 + EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_be_v1); 1079 + 1080 + #undef DEF_TXCHADDRS_TYPE3 1081 + #undef DEF_TXCHADDRS_TYPE3_GRP_BASE 1082 + #undef DEF_TXCHADDRS_TYPE2 1152 1083 #undef DEF_TXCHADDRS_TYPE1 1153 1084 #undef DEF_TXCHADDRS 1085 + #undef DEF_RXCHADDRS_TYPE3 1086 + #undef DEF_RXCHADDRS_TYPE3_GRP_BASE 1154 1087 #undef DEF_RXCHADDRS 1155 1088 1156 1089 static int rtw89_pci_get_txch_addrs(struct rtw89_dev *rtwdev, ··· 1224 1101 u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) 1225 1102 { 1226 1103 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1227 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 1104 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[RTW89_TXCH_CH12]; 1228 1105 u32 cnt; 1229 1106 1230 1107 spin_lock_bh(&rtwpci->trx_lock); ··· 1240 1117 u8 txch) 1241 1118 { 1242 1119 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1243 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1120 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1244 1121 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 1245 1122 u32 cnt; 1246 1123 ··· 1257 1134 u8 txch) 1258 1135 { 1259 1136 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1260 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1137 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1261 1138 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 1262 1139 const struct rtw89_chip_info *chip = rtwdev->chip; 1263 1140 u32 bd_cnt, wd_cnt, min_cnt = 0; ··· 1265 1142 enum rtw89_debug_mask debug_mask; 1266 1143 u32 cnt; 1267 1144 1268 - rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 1145 + rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 1269 1146 1270 1147 spin_lock_bh(&rtwpci->trx_lock); 1271 1148 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ··· 1350 1227 static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 1351 1228 { 1352 1229 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1353 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1230 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1354 1231 1355 1232 if (rtwdev->hci.paused) { 1356 1233 set_bit(txch, rtwpci->kick_map); ··· 1370 1247 if (!test_and_clear_bit(txch, rtwpci->kick_map)) 1371 1248 continue; 1372 1249 1373 - tx_ring = &rtwpci->tx_rings[txch]; 1250 + tx_ring = &rtwpci->tx.rings[txch]; 1374 1251 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 1375 1252 } 1376 1253 } ··· 1378 1255 static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) 1379 1256 { 1380 1257 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1381 - struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1258 + struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1382 1259 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1383 1260 u32 cur_idx, cur_rp; 1384 1261 u8 i; ··· 1494 1371 struct pci_dev *pdev = rtwpci->pdev; 1495 1372 struct sk_buff *skb = tx_req->skb; 1496 1373 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 1497 - struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1498 1374 bool en_wd_info = desc_info->en_wd_info; 1499 1375 u32 txwd_len; 1500 1376 u32 txwp_len; ··· 1509 1387 } 1510 1388 1511 1389 tx_data->dma = dma; 1512 - rcu_assign_pointer(skb_data->wait, NULL); 1513 1390 1514 1391 txwp_len = sizeof(*txwp_info); 1515 1392 txwd_len = chip->txwd_body_size; ··· 1642 1521 return -EINVAL; 1643 1522 } 1644 1523 1645 - tx_ring = &rtwpci->tx_rings[txch]; 1524 + tx_ring = &rtwpci->tx.rings[txch]; 1646 1525 spin_lock_bh(&rtwpci->trx_lock); 1647 1526 1648 1527 n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); ··· 1728 1607 } 1729 1608 } 1730 1609 1610 + static u16 rtw89_pci_enc_bd_cfg(struct rtw89_dev *rtwdev, u16 bd_num, 1611 + u32 dma_offset) 1612 + { 1613 + u16 dma_offset_sel; 1614 + u16 num_sel; 1615 + 1616 + /* B_BE_TX_NUM_SEL_MASK, B_BE_RX_NUM_SEL_MASK: 1617 + * 0 -> 0 1618 + * 1 -> 64 = 2^6 1619 + * 2 -> 128 = 2^7 1620 + * ... 1621 + * 7 -> 4096 = 2^12 1622 + */ 1623 + num_sel = ilog2(bd_num) - 5; 1624 + 1625 + if (hweight16(bd_num) != 1) 1626 + rtw89_warn(rtwdev, "bd_num %u is not power of 2\n", bd_num); 1627 + 1628 + /* B_BE_TX_START_OFFSET_MASK, B_BE_RX_START_OFFSET_MASK: 1629 + * 0 -> 0 = 0 * 2^9 1630 + * 1 -> 512 = 1 * 2^9 1631 + * 2 -> 1024 = 2 * 2^9 1632 + * 3 -> 1536 = 3 * 2^9 1633 + * ... 1634 + * 255 -> 130560 = 255 * 2^9 1635 + */ 1636 + dma_offset_sel = dma_offset >> 9; 1637 + 1638 + if (dma_offset % 512) 1639 + rtw89_warn(rtwdev, "offset %u is not multiple of 512\n", dma_offset); 1640 + 1641 + return u16_encode_bits(num_sel, B_BE_TX_NUM_SEL_MASK) | 1642 + u16_encode_bits(dma_offset_sel, B_BE_TX_START_OFFSET_MASK); 1643 + } 1644 + 1731 1645 static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) 1732 1646 { 1733 1647 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ··· 1772 1616 struct rtw89_pci_rx_ring *rx_ring; 1773 1617 struct rtw89_pci_dma_ring *bd_ring; 1774 1618 const struct rtw89_pci_bd_ram *bd_ram; 1619 + dma_addr_t group_dma_base = 0; 1620 + u16 num_or_offset; 1621 + u32 addr_desa_l; 1622 + u32 addr_bdram; 1775 1623 u32 addr_num; 1776 1624 u32 addr_idx; 1777 - u32 addr_bdram; 1778 - u32 addr_desa_l; 1779 1625 u32 val32; 1780 1626 int i; 1781 1627 ··· 1785 1627 if (info->tx_dma_ch_mask & BIT(i)) 1786 1628 continue; 1787 1629 1788 - tx_ring = &rtwpci->tx_rings[i]; 1630 + tx_ring = &rtwpci->tx.rings[i]; 1789 1631 bd_ring = &tx_ring->bd_ring; 1790 1632 bd_ram = bd_ram_table ? &bd_ram_table[i] : NULL; 1791 1633 addr_num = bd_ring->addr.num; ··· 1794 1636 bd_ring->wp = 0; 1795 1637 bd_ring->rp = 0; 1796 1638 1797 - rtw89_write16(rtwdev, addr_num, bd_ring->len); 1639 + if (info->group_bd_addr) { 1640 + if (addr_desa_l) 1641 + group_dma_base = bd_ring->dma; 1642 + 1643 + num_or_offset = 1644 + rtw89_pci_enc_bd_cfg(rtwdev, bd_ring->len, 1645 + bd_ring->dma - group_dma_base); 1646 + } else { 1647 + num_or_offset = bd_ring->len; 1648 + } 1649 + rtw89_write16(rtwdev, addr_num, num_or_offset); 1650 + 1798 1651 if (addr_bdram && bd_ram) { 1799 1652 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | 1800 1653 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | ··· 1813 1644 1814 1645 rtw89_write32(rtwdev, addr_bdram, val32); 1815 1646 } 1816 - rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1817 - rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1647 + if (addr_desa_l) { 1648 + rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1649 + rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1650 + } 1818 1651 } 1819 1652 1820 1653 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1821 - rx_ring = &rtwpci->rx_rings[i]; 1654 + rx_ring = &rtwpci->rx.rings[i]; 1822 1655 bd_ring = &rx_ring->bd_ring; 1823 1656 addr_num = bd_ring->addr.num; 1824 1657 addr_idx = bd_ring->addr.idx; ··· 1834 1663 rx_ring->diliver_desc.ready = false; 1835 1664 rx_ring->target_rx_tag = 0; 1836 1665 1837 - rtw89_write16(rtwdev, addr_num, bd_ring->len); 1838 - rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1839 - rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1666 + if (info->group_bd_addr) { 1667 + if (addr_desa_l) 1668 + group_dma_base = bd_ring->dma; 1669 + 1670 + num_or_offset = 1671 + rtw89_pci_enc_bd_cfg(rtwdev, bd_ring->len, 1672 + bd_ring->dma - group_dma_base); 1673 + } else { 1674 + num_or_offset = bd_ring->len; 1675 + } 1676 + rtw89_write16(rtwdev, addr_num, num_or_offset); 1677 + 1678 + if (addr_desa_l) { 1679 + rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1680 + rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1681 + } 1840 1682 1841 1683 if (info->rx_ring_eq_is_full) 1842 1684 rtw89_write16(rtwdev, addr_idx, bd_ring->wp); ··· 1882 1698 skb_queue_len(&rtwpci->h2c_queue), true); 1883 1699 continue; 1884 1700 } 1885 - rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); 1701 + rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx.rings[txch]); 1886 1702 } 1887 1703 spin_unlock_bh(&rtwpci->trx_lock); 1888 1704 } ··· 1958 1774 return; 1959 1775 1960 1776 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1961 - tx_ring = &rtwpci->tx_rings[i]; 1777 + tx_ring = &rtwpci->tx.rings[i]; 1962 1778 tx_ring->bd_ring.addr.idx = low_power ? 1963 1779 bd_idx_addr->tx_bd_addrs[i] : 1964 1780 dma_addr_set->tx[i].idx; 1965 1781 } 1966 1782 1967 1783 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1968 - rx_ring = &rtwpci->rx_rings[i]; 1784 + rx_ring = &rtwpci->rx.rings[i]; 1969 1785 rx_ring->bd_ring.addr.idx = low_power ? 1970 1786 bd_idx_addr->rx_bd_addrs[i] : 1971 1787 dma_addr_set->rx[i].idx; ··· 2909 2725 2910 2726 static int rtw89_pci_poll_dma_all_idle(struct rtw89_dev *rtwdev) 2911 2727 { 2912 - u32 ret; 2728 + int ret; 2913 2729 2914 2730 ret = rtw89_pci_poll_txdma_ch_idle_ax(rtwdev); 2915 2731 if (ret) { ··· 3395 3211 struct pci_dev *pdev, 3396 3212 struct rtw89_pci_tx_ring *tx_ring) 3397 3213 { 3398 - int ring_sz; 3399 - u8 *head; 3400 - dma_addr_t dma; 3401 - 3402 - head = tx_ring->bd_ring.head; 3403 - dma = tx_ring->bd_ring.dma; 3404 - ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; 3405 - dma_free_coherent(&pdev->dev, ring_sz, head, dma); 3406 - 3407 3214 tx_ring->bd_ring.head = NULL; 3408 3215 } 3409 3216 ··· 3402 3227 struct pci_dev *pdev) 3403 3228 { 3404 3229 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3230 + struct rtw89_pci_dma_pool *bd_pool = &rtwpci->tx.bd_pool; 3405 3231 const struct rtw89_pci_info *info = rtwdev->pci_info; 3406 3232 struct rtw89_pci_tx_ring *tx_ring; 3407 3233 int i; ··· 3410 3234 for (i = 0; i < RTW89_TXCH_NUM; i++) { 3411 3235 if (info->tx_dma_ch_mask & BIT(i)) 3412 3236 continue; 3413 - tx_ring = &rtwpci->tx_rings[i]; 3237 + tx_ring = &rtwpci->tx.rings[i]; 3414 3238 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 3415 3239 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 3416 3240 } 3241 + 3242 + dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3417 3243 } 3418 3244 3419 3245 static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, ··· 3426 3248 struct sk_buff *skb; 3427 3249 dma_addr_t dma; 3428 3250 u32 buf_sz; 3429 - u8 *head; 3430 - int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; 3431 3251 int i; 3432 3252 3433 3253 buf_sz = rx_ring->buf_sz; ··· 3441 3265 rx_ring->buf[i] = NULL; 3442 3266 } 3443 3267 3444 - head = rx_ring->bd_ring.head; 3445 - dma = rx_ring->bd_ring.dma; 3446 - dma_free_coherent(&pdev->dev, ring_sz, head, dma); 3447 - 3448 3268 rx_ring->bd_ring.head = NULL; 3449 3269 } 3450 3270 ··· 3448 3276 struct pci_dev *pdev) 3449 3277 { 3450 3278 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3279 + struct rtw89_pci_dma_pool *bd_pool = &rtwpci->rx.bd_pool; 3451 3280 struct rtw89_pci_rx_ring *rx_ring; 3452 3281 int i; 3453 3282 3454 3283 for (i = 0; i < RTW89_RXCH_NUM; i++) { 3455 - rx_ring = &rtwpci->rx_rings[i]; 3284 + rx_ring = &rtwpci->rx.rings[i]; 3456 3285 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 3457 3286 } 3287 + 3288 + dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3458 3289 } 3459 3290 3460 3291 static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, ··· 3549 3374 struct pci_dev *pdev, 3550 3375 struct rtw89_pci_tx_ring *tx_ring, 3551 3376 u32 desc_size, u32 len, 3552 - enum rtw89_tx_channel txch) 3377 + enum rtw89_tx_channel txch, 3378 + void *head, dma_addr_t dma) 3553 3379 { 3554 3380 const struct rtw89_pci_ch_dma_addr *txch_addr; 3555 - int ring_sz = desc_size * len; 3556 - u8 *head; 3557 - dma_addr_t dma; 3558 3381 int ret; 3559 3382 3560 3383 ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); ··· 3564 3391 ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr); 3565 3392 if (ret) { 3566 3393 rtw89_err(rtwdev, "failed to get address of txch %d", txch); 3567 - goto err_free_wd_ring; 3568 - } 3569 - 3570 - head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 3571 - if (!head) { 3572 - ret = -ENOMEM; 3573 3394 goto err_free_wd_ring; 3574 3395 } 3575 3396 ··· 3589 3422 struct pci_dev *pdev) 3590 3423 { 3591 3424 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3425 + struct rtw89_pci_dma_pool *bd_pool = &rtwpci->tx.bd_pool; 3592 3426 const struct rtw89_pci_info *info = rtwdev->pci_info; 3593 3427 struct rtw89_pci_tx_ring *tx_ring; 3594 - u32 desc_size; 3595 - u32 len; 3596 3428 u32 i, tx_allocated; 3429 + dma_addr_t dma; 3430 + u32 desc_size; 3431 + u32 ring_sz; 3432 + u32 pool_sz; 3433 + u32 ch_num; 3434 + void *head; 3435 + u32 len; 3597 3436 int ret; 3437 + 3438 + BUILD_BUG_ON(RTW89_PCI_TXBD_NUM_MAX % 16); 3439 + 3440 + desc_size = sizeof(struct rtw89_pci_tx_bd_32); 3441 + len = RTW89_PCI_TXBD_NUM_MAX; 3442 + ch_num = RTW89_TXCH_NUM - hweight32(info->tx_dma_ch_mask); 3443 + ring_sz = desc_size * len; 3444 + pool_sz = ring_sz * ch_num; 3445 + 3446 + head = dma_alloc_coherent(&pdev->dev, pool_sz, &dma, GFP_KERNEL); 3447 + if (!head) 3448 + return -ENOMEM; 3449 + 3450 + bd_pool->head = head; 3451 + bd_pool->dma = dma; 3452 + bd_pool->size = pool_sz; 3598 3453 3599 3454 for (i = 0; i < RTW89_TXCH_NUM; i++) { 3600 3455 if (info->tx_dma_ch_mask & BIT(i)) 3601 3456 continue; 3602 - tx_ring = &rtwpci->tx_rings[i]; 3603 - desc_size = sizeof(struct rtw89_pci_tx_bd_32); 3604 - len = RTW89_PCI_TXBD_NUM_MAX; 3457 + tx_ring = &rtwpci->tx.rings[i]; 3605 3458 ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, 3606 - desc_size, len, i); 3459 + desc_size, len, i, head, dma); 3607 3460 if (ret) { 3608 3461 rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); 3609 3462 goto err_free; 3610 3463 } 3464 + 3465 + head += ring_sz; 3466 + dma += ring_sz; 3611 3467 } 3612 3468 3613 3469 return 0; ··· 3638 3448 err_free: 3639 3449 tx_allocated = i; 3640 3450 for (i = 0; i < tx_allocated; i++) { 3641 - tx_ring = &rtwpci->tx_rings[i]; 3451 + tx_ring = &rtwpci->tx.rings[i]; 3642 3452 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 3643 3453 } 3454 + 3455 + dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3644 3456 3645 3457 return ret; 3646 3458 } ··· 3650 3458 static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 3651 3459 struct pci_dev *pdev, 3652 3460 struct rtw89_pci_rx_ring *rx_ring, 3653 - u32 desc_size, u32 len, u32 rxch) 3461 + u32 desc_size, u32 len, u32 rxch, 3462 + void *head, dma_addr_t dma) 3654 3463 { 3655 3464 const struct rtw89_pci_info *info = rtwdev->pci_info; 3656 3465 const struct rtw89_pci_ch_dma_addr *rxch_addr; 3657 3466 struct sk_buff *skb; 3658 - u8 *head; 3659 - dma_addr_t dma; 3660 - int ring_sz = desc_size * len; 3661 3467 int buf_sz = RTW89_PCI_RX_BUF_SIZE; 3662 3468 int i, allocated; 3663 3469 int ret; ··· 3664 3474 if (ret) { 3665 3475 rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); 3666 3476 return ret; 3667 - } 3668 - 3669 - head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 3670 - if (!head) { 3671 - ret = -ENOMEM; 3672 - goto err; 3673 3477 } 3674 3478 3675 3479 rx_ring->bd_ring.head = head; ··· 3714 3530 rx_ring->buf[i] = NULL; 3715 3531 } 3716 3532 3717 - head = rx_ring->bd_ring.head; 3718 - dma = rx_ring->bd_ring.dma; 3719 - dma_free_coherent(&pdev->dev, ring_sz, head, dma); 3720 - 3721 3533 rx_ring->bd_ring.head = NULL; 3722 - err: 3534 + 3723 3535 return ret; 3724 3536 } 3725 3537 ··· 3723 3543 struct pci_dev *pdev) 3724 3544 { 3725 3545 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3546 + struct rtw89_pci_dma_pool *bd_pool = &rtwpci->rx.bd_pool; 3726 3547 struct rtw89_pci_rx_ring *rx_ring; 3727 - u32 desc_size; 3728 - u32 len; 3729 3548 int i, rx_allocated; 3549 + dma_addr_t dma; 3550 + u32 desc_size; 3551 + u32 ring_sz; 3552 + u32 pool_sz; 3553 + void *head; 3554 + u32 len; 3730 3555 int ret; 3731 3556 3557 + desc_size = sizeof(struct rtw89_pci_rx_bd_32); 3558 + len = RTW89_PCI_RXBD_NUM_MAX; 3559 + ring_sz = desc_size * len; 3560 + pool_sz = ring_sz * RTW89_RXCH_NUM; 3561 + 3562 + head = dma_alloc_coherent(&pdev->dev, pool_sz, &dma, GFP_KERNEL); 3563 + if (!head) 3564 + return -ENOMEM; 3565 + 3566 + bd_pool->head = head; 3567 + bd_pool->dma = dma; 3568 + bd_pool->size = pool_sz; 3569 + 3732 3570 for (i = 0; i < RTW89_RXCH_NUM; i++) { 3733 - rx_ring = &rtwpci->rx_rings[i]; 3734 - desc_size = sizeof(struct rtw89_pci_rx_bd_32); 3735 - len = RTW89_PCI_RXBD_NUM_MAX; 3571 + rx_ring = &rtwpci->rx.rings[i]; 3572 + 3736 3573 ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, 3737 - desc_size, len, i); 3574 + desc_size, len, i, 3575 + head, dma); 3738 3576 if (ret) { 3739 3577 rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); 3740 3578 goto err_free; 3741 3579 } 3580 + 3581 + head += ring_sz; 3582 + dma += ring_sz; 3742 3583 } 3743 3584 3744 3585 return 0; ··· 3767 3566 err_free: 3768 3567 rx_allocated = i; 3769 3568 for (i = 0; i < rx_allocated; i++) { 3770 - rx_ring = &rtwpci->rx_rings[i]; 3569 + rx_ring = &rtwpci->rx.rings[i]; 3771 3570 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 3772 3571 } 3572 + 3573 + dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3773 3574 3774 3575 return ret; 3775 3576 } ··· 3978 3775 rtw89_pci_default_intr_mask_v2(rtwdev); 3979 3776 } 3980 3777 EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v2); 3778 + 3779 + static void rtw89_pci_recovery_intr_mask_v3(struct rtw89_dev *rtwdev) 3780 + { 3781 + struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3782 + 3783 + rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 3784 + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 3785 + rtwpci->intrs[0] = 0; 3786 + rtwpci->intrs[1] = 0; 3787 + } 3788 + 3789 + static void rtw89_pci_default_intr_mask_v3(struct rtw89_dev *rtwdev) 3790 + { 3791 + struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3792 + 3793 + rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 3794 + rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 3795 + rtwpci->intrs[0] = 0; 3796 + rtwpci->intrs[1] = B_BE_PCIE_RDU_CH1_IMR | 3797 + B_BE_PCIE_RDU_CH0_IMR | 3798 + B_BE_PCIE_RX_RX0P2_IMR0_V1 | 3799 + B_BE_PCIE_RX_RPQ0_IMR0_V1; 3800 + } 3801 + 3802 + void rtw89_pci_config_intr_mask_v3(struct rtw89_dev *rtwdev) 3803 + { 3804 + struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3805 + 3806 + if (rtwpci->under_recovery) 3807 + rtw89_pci_recovery_intr_mask_v3(rtwdev); 3808 + else 3809 + rtw89_pci_default_intr_mask_v3(rtwdev); 3810 + } 3811 + EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v3); 3981 3812 3982 3813 static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, 3983 3814 struct pci_dev *pdev) ··· 4395 4158 4396 4159 static int rtw89_pci_lv1rst_start_dma_ax(struct rtw89_dev *rtwdev) 4397 4160 { 4398 - u32 ret; 4161 + int ret; 4399 4162 4400 4163 if (rtwdev->chip->chip_id == RTL8852C) 4401 4164 return 0; ··· 4409 4172 return ret; 4410 4173 4411 4174 rtw89_pci_ctrl_dma_all(rtwdev, true); 4412 - return ret; 4175 + return 0; 4413 4176 } 4414 4177 4415 4178 static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, ··· 4465 4228 struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); 4466 4229 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4467 4230 const struct rtw89_pci_info *info = rtwdev->pci_info; 4468 - const struct rtw89_pci_gen_def *gen_def = info->gen_def; 4231 + const struct rtw89_pci_isr_def *isr_def = info->isr_def; 4469 4232 unsigned long flags; 4470 4233 int work_done; 4471 4234 4472 4235 rtwdev->napi_budget_countdown = budget; 4473 4236 4474 - rtw89_write32(rtwdev, gen_def->isr_clear_rpq.addr, gen_def->isr_clear_rpq.data); 4237 + rtw89_write32(rtwdev, isr_def->isr_clear_rpq.addr, isr_def->isr_clear_rpq.data); 4475 4238 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 4476 4239 if (work_done == budget) 4477 4240 return budget; 4478 4241 4479 - rtw89_write32(rtwdev, gen_def->isr_clear_rxq.addr, gen_def->isr_clear_rxq.data); 4242 + rtw89_write32(rtwdev, isr_def->isr_clear_rxq.addr, isr_def->isr_clear_rxq.data); 4480 4243 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 4481 4244 if (work_done < budget && napi_complete_done(napi, work_done)) { 4482 4245 spin_lock_irqsave(&rtwpci->irq_lock, flags); ··· 4631 4394 }; 4632 4395 EXPORT_SYMBOL(rtw89_pci_err_handler); 4633 4396 4634 - const struct rtw89_pci_gen_def rtw89_pci_gen_ax = { 4397 + const struct rtw89_pci_isr_def rtw89_pci_isr_ax = { 4635 4398 .isr_rdu = B_AX_RDU_INT, 4636 4399 .isr_halt_c2h = B_AX_HALT_C2H_INT_EN, 4637 4400 .isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN, 4638 4401 .isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT}, 4639 4402 .isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | 4640 4403 B_AX_RDU_INT}, 4404 + }; 4405 + EXPORT_SYMBOL(rtw89_pci_isr_ax); 4641 4406 4407 + const struct rtw89_pci_gen_def rtw89_pci_gen_ax = { 4642 4408 .mac_pre_init = rtw89_pci_ops_mac_pre_init_ax, 4643 4409 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_ax, 4644 4410 .mac_post_init = rtw89_pci_ops_mac_post_init_ax,

+120 -8

drivers/net/wireless/realtek/rtw89/pci.h

··· 372 372 #define B_BE_HS0ISR_IND_INT BIT(0) 373 373 374 374 #define R_BE_PCIE_DMA_IMR_0_V1 0x30B8 375 + #define B_BE_PCIE_RDU_CH7_IMR BIT(31) 376 + #define B_BE_PCIE_RDU_CH6_IMR BIT(30) 377 + #define B_BE_PCIE_RDU_CH5_IMR BIT(29) 378 + #define B_BE_PCIE_RDU_CH4_IMR BIT(28) 379 + #define B_BE_PCIE_RDU_CH3_IMR BIT(27) 380 + #define B_BE_PCIE_RDU_CH2_IMR BIT(26) 381 + #define B_BE_PCIE_RDU_CH1_IMR BIT(25) 382 + #define B_BE_PCIE_RDU_CH0_IMR BIT(24) 375 383 #define B_BE_PCIE_RX_RX1P1_IMR0_V1 BIT(23) 376 384 #define B_BE_PCIE_RX_RX0P1_IMR0_V1 BIT(22) 377 385 #define B_BE_PCIE_RX_ROQ1_IMR0_V1 BIT(21) ··· 405 397 #define B_BE_PCIE_TX_CH0_IMR0 BIT(0) 406 398 407 399 #define R_BE_PCIE_DMA_ISR 0x30BC 400 + #define B_BE_PCIE_RDU_CH7_INT BIT(31) 401 + #define B_BE_PCIE_RDU_CH6_INT BIT(30) 402 + #define B_BE_PCIE_RDU_CH5_INT BIT(29) 403 + #define B_BE_PCIE_RDU_CH4_INT BIT(28) 404 + #define B_BE_PCIE_RDU_CH3_INT BIT(27) 405 + #define B_BE_PCIE_RDU_CH2_INT BIT(26) 406 + #define B_BE_PCIE_RDU_CH1_INT BIT(25) 407 + #define B_BE_PCIE_RDU_CH0_INT BIT(24) 408 408 #define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23) 409 409 #define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22) 410 410 #define B_BE_PCIE_RX_ROQ1_ISR_V1 BIT(21) ··· 442 426 #define B_BE_RDU_CH4_INT_IMR_V1 BIT(29) 443 427 #define B_BE_RDU_CH3_INT_IMR_V1 BIT(28) 444 428 #define B_BE_RDU_CH2_INT_IMR_V1 BIT(27) 429 + #define B_BE_RDU_CH1_INT_EN_V2 BIT(27) 445 430 #define B_BE_RDU_CH1_INT_IMR_V1 BIT(26) 431 + #define B_BE_RDU_CH0_INT_EN_V2 BIT(26) 446 432 #define B_BE_RDU_CH0_INT_IMR_V1 BIT(25) 433 + #define B_BE_RXDMA_STUCK_INT_EN_V2 BIT(25) 447 434 #define B_BE_RXDMA_STUCK_INT_EN_V1 BIT(24) 435 + #define B_BE_TXDMA_STUCK_INT_EN_V2 BIT(24) 448 436 #define B_BE_TXDMA_STUCK_INT_EN_V1 BIT(23) 449 437 #define B_BE_TXDMA_CH14_INT_EN_V1 BIT(22) 450 438 #define B_BE_TXDMA_CH13_INT_EN_V1 BIT(21) ··· 479 459 #define B_BE_RDU_CH4_INT_V1 BIT(29) 480 460 #define B_BE_RDU_CH3_INT_V1 BIT(28) 481 461 #define B_BE_RDU_CH2_INT_V1 BIT(27) 462 + #define B_BE_RDU_CH1_INT_V2 BIT(27) 482 463 #define B_BE_RDU_CH1_INT_V1 BIT(26) 464 + #define B_BE_RDU_CH0_INT_V2 BIT(26) 483 465 #define B_BE_RDU_CH0_INT_V1 BIT(25) 466 + #define B_BE_RXDMA_STUCK_INT_V2 BIT(25) 484 467 #define B_BE_RXDMA_STUCK_INT_V1 BIT(24) 468 + #define B_BE_TXDMA_STUCK_INT_V2 BIT(24) 485 469 #define B_BE_TXDMA_STUCK_INT_V1 BIT(23) 486 470 #define B_BE_TXDMA_CH14_INT_V1 BIT(22) 487 471 #define B_BE_TXDMA_CH13_INT_V1 BIT(21) ··· 808 784 #define R_BE_CH13_TXBD_NUM_V1 0xB04C 809 785 #define R_BE_CH14_TXBD_NUM_V1 0xB04E 810 786 787 + #define R_BE_CH0_TXBD_CFG 0xB030 788 + #define R_BE_CH2_TXBD_CFG 0xB034 789 + #define R_BE_CH4_TXBD_CFG 0xB038 790 + #define R_BE_CH6_TXBD_CFG 0xB03C 791 + #define R_BE_CH8_TXBD_CFG 0xB040 792 + #define R_BE_CH10_TXBD_CFG 0xB044 793 + #define R_BE_CH12_TXBD_CFG 0xB048 794 + #define B_BE_TX_FLAG BIT(14) 795 + #define B_BE_TX_START_OFFSET_MASK GENMASK(12, 4) 796 + #define B_BE_TX_NUM_SEL_MASK GENMASK(2, 0) 797 + 811 798 #define R_BE_RXQ0_RXBD_NUM_V1 0xB050 812 799 #define R_BE_RPQ0_RXBD_NUM_V1 0xB052 800 + 801 + #define R_BE_RX_CH0_RXBD_CONFIG 0xB050 802 + #define R_BE_RX_CH1_RXBD_CONFIG 0xB052 803 + #define B_BE_RX_START_OFFSET_MASK GENMASK(11, 4) 804 + #define B_BE_RX_NUM_SEL_MASK GENMASK(2, 0) 813 805 814 806 #define R_BE_CH0_TXBD_IDX_V1 0xB100 815 807 #define R_BE_CH1_TXBD_IDX_V1 0xB104 ··· 877 837 #define R_BE_CH14_TXBD_DESA_L_V1 0xB270 878 838 #define R_BE_CH14_TXBD_DESA_H_V1 0xB274 879 839 840 + #define R_BE_ACQ_TXBD_DESA_L 0xB200 841 + #define B_BE_TX_ACQ_DESA_L_MASK GENMASK(31, 3) 842 + #define R_BE_ACQ_TXBD_DESA_H 0xB204 843 + #define B_BE_TX_ACQ_DESA_H_MASK GENMASK(7, 0) 844 + #define R_BE_NACQ_TXBD_DESA_L 0xB240 845 + #define B_BE_TX_NACQ_DESA_L_MASK GENMASK(31, 3) 846 + #define R_BE_NACQ_TXBD_DESA_H 0xB244 847 + #define B_BE_TX_NACQ_DESA_H_MASK GENMASK(7, 0) 848 + 880 849 #define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300 881 850 #define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304 882 851 #define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308 883 852 #define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C 853 + 854 + #define R_BE_HOST0_RXBD_DESA_L 0xB300 855 + #define B_BE_RX_HOST0_DESA_L_MASK GENMASK(31, 3) 856 + #define R_BE_HOST0_RXBD_DESA_H 0xB304 857 + #define B_BE_RX_HOST0_DESA_H_MASK GENMASK(7, 0) 884 858 885 859 #define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420 886 860 #define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424 ··· 1303 1249 }; 1304 1250 1305 1251 struct rtw89_pci_ch_dma_addr { 1306 - u32 num; 1252 + u32 num; /* also `offset` addr for group_bd_addr design */ 1307 1253 u32 idx; 1308 1254 u32 bdram; 1309 1255 u32 desa_l; ··· 1321 1267 u8 min_num; 1322 1268 }; 1323 1269 1324 - struct rtw89_pci_gen_def { 1270 + struct rtw89_pci_isr_def { 1325 1271 u32 isr_rdu; 1326 1272 u32 isr_halt_c2h; 1327 1273 u32 isr_wdt_timeout; 1328 1274 struct rtw89_reg2_def isr_clear_rpq; 1329 1275 struct rtw89_reg2_def isr_clear_rxq; 1276 + }; 1330 1277 1278 + struct rtw89_pci_gen_def { 1331 1279 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 1332 1280 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 1333 1281 int (*mac_post_init)(struct rtw89_dev *rtwdev); ··· 1365 1309 unsigned long bitmap; /* bitmap of rtw89_quirks */ 1366 1310 }; 1367 1311 1312 + struct rtw89_pci_rpp_info { 1313 + u16 seq; 1314 + u8 qsel; 1315 + u8 tx_status; 1316 + u8 txch; 1317 + }; 1318 + 1368 1319 struct rtw89_pci_info { 1369 1320 const struct rtw89_pci_gen_def *gen_def; 1321 + const struct rtw89_pci_isr_def *isr_def; 1370 1322 enum mac_ax_bd_trunc_mode txbd_trunc_mode; 1371 1323 enum mac_ax_bd_trunc_mode rxbd_trunc_mode; 1372 1324 enum mac_ax_rxbd_mode rxbd_mode; ··· 1392 1328 bool rx_ring_eq_is_full; 1393 1329 bool check_rx_tag; 1394 1330 bool no_rxbd_fs; 1331 + bool group_bd_addr; 1332 + u32 rpp_fmt_size; 1395 1333 1396 1334 u32 init_cfg_reg; 1397 1335 u32 txhci_en_bit; ··· 1423 1357 u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev, 1424 1358 void *txaddr_info_addr, u32 total_len, 1425 1359 dma_addr_t dma, u8 *add_info_nr); 1360 + void (*parse_rpp)(struct rtw89_dev *rtwdev, void *rpp, 1361 + struct rtw89_pci_rpp_info *rpp_info); 1426 1362 void (*config_intr_mask)(struct rtw89_dev *rtwdev); 1427 1363 void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1428 1364 void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); ··· 1498 1430 __le32 dword; 1499 1431 } __packed; 1500 1432 1433 + #define RTW89_PCI_RPP_W0_MACID_V1_MASK GENMASK(9, 0) 1434 + #define RTW89_PCI_RPP_W0_DMA_CH_MASK GENMASK(13, 10) 1435 + #define RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK GENMASK(16, 14) 1436 + #define RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK GENMASK(31, 17) 1437 + #define RTW89_PCI_RPP_W1_QSEL_V1_MASK GENMASK(5, 0) 1438 + #define RTW89_PCI_RPP_W1_TID_IND BIT(6) 1439 + #define RTW89_PCI_RPP_W1_CHANGE_LINK BIT(7) 1440 + 1441 + struct rtw89_pci_rpp_fmt_v1 { 1442 + __le32 w0; 1443 + __le32 w1; 1444 + } __packed; 1445 + 1501 1446 struct rtw89_pci_rx_bd_32 { 1502 1447 __le16 buf_size; 1503 1448 __le16 opt; ··· 1549 1468 u32 rp; /* hw idx */ 1550 1469 }; 1551 1470 1471 + struct rtw89_pci_dma_pool { 1472 + void *head; 1473 + dma_addr_t dma; 1474 + u32 size; 1475 + }; 1476 + 1552 1477 struct rtw89_pci_tx_wd_ring { 1553 1478 void *head; 1554 1479 dma_addr_t dma; ··· 1584 1497 u64 tx_mac_id_drop; 1585 1498 }; 1586 1499 1500 + struct rtw89_pci_tx_rings { 1501 + struct rtw89_pci_tx_ring rings[RTW89_TXCH_NUM]; 1502 + struct rtw89_pci_dma_pool bd_pool; 1503 + }; 1504 + 1587 1505 struct rtw89_pci_rx_ring { 1588 1506 struct rtw89_pci_dma_ring bd_ring; 1589 1507 struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; ··· 1596 1504 struct sk_buff *diliver_skb; 1597 1505 struct rtw89_rx_desc_info diliver_desc; 1598 1506 u32 target_rx_tag:13; 1507 + }; 1508 + 1509 + struct rtw89_pci_rx_rings { 1510 + struct rtw89_pci_rx_ring rings[RTW89_RXCH_NUM]; 1511 + struct rtw89_pci_dma_pool bd_pool; 1599 1512 }; 1600 1513 1601 1514 struct rtw89_pci_isrs { ··· 1620 1523 bool low_power; 1621 1524 bool under_recovery; 1622 1525 bool enable_dac; 1623 - struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; 1624 - struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; 1526 + struct rtw89_pci_tx_rings tx; 1527 + struct rtw89_pci_rx_rings rx; 1625 1528 struct sk_buff_head h2c_queue; 1626 1529 struct sk_buff_head h2c_release_queue; 1627 1530 DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM); ··· 1634 1537 1635 1538 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) 1636 1539 { 1637 - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1638 - 1639 - BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > 1640 - sizeof(info->status.status_driver_data)); 1540 + BUILD_BUG_ON(sizeof(struct rtw89_pci_rx_info) > sizeof(skb->cb)); 1641 1541 1642 1542 return (struct rtw89_pci_rx_info *)skb->cb; 1643 1543 } ··· 1664 1570 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) 1665 1571 { 1666 1572 struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb); 1573 + 1574 + BUILD_BUG_ON(sizeof(struct rtw89_tx_skb_data) + 1575 + sizeof(struct rtw89_pci_tx_data) > 1576 + sizeof_field(struct ieee80211_tx_info, driver_data)); 1667 1577 1668 1578 return (struct rtw89_pci_tx_data *)data->hci_priv; 1669 1579 } ··· 1724 1626 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set; 1725 1627 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1; 1726 1628 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be; 1629 + extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be_v1; 1727 1630 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM]; 1728 1631 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM]; 1632 + extern const struct rtw89_pci_isr_def rtw89_pci_isr_ax; 1633 + extern const struct rtw89_pci_isr_def rtw89_pci_isr_be; 1634 + extern const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1; 1729 1635 extern const struct rtw89_pci_gen_def rtw89_pci_gen_ax; 1730 1636 extern const struct rtw89_pci_gen_def rtw89_pci_gen_be; 1731 1637 ··· 1748 1646 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev, 1749 1647 void *txaddr_info_addr, u32 total_len, 1750 1648 dma_addr_t dma, u8 *add_info_nr); 1649 + void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp, 1650 + struct rtw89_pci_rpp_info *rpp_info); 1651 + void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp, 1652 + struct rtw89_pci_rpp_info *rpp_info); 1751 1653 void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable); 1752 1654 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev); 1753 1655 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev); 1754 1656 void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev); 1657 + void rtw89_pci_config_intr_mask_v3(struct rtw89_dev *rtwdev); 1755 1658 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1756 1659 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1757 1660 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1758 1661 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1759 1662 void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1760 1663 void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1664 + void rtw89_pci_enable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1665 + void rtw89_pci_disable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1761 1666 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, 1762 1667 struct rtw89_pci *rtwpci, 1763 1668 struct rtw89_pci_isrs *isrs); ··· 1772 1663 struct rtw89_pci *rtwpci, 1773 1664 struct rtw89_pci_isrs *isrs); 1774 1665 void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev, 1666 + struct rtw89_pci *rtwpci, 1667 + struct rtw89_pci_isrs *isrs); 1668 + void rtw89_pci_recognize_intrs_v3(struct rtw89_dev *rtwdev, 1775 1669 struct rtw89_pci *rtwpci, 1776 1670 struct rtw89_pci_isrs *isrs); 1777 1671

+15 -3

drivers/net/wireless/realtek/rtw89/pci_be.c

··· 175 175 rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1, 176 176 B_BE_CLR_RXQ0_IDX | B_BE_CLR_RPQ0_IDX); 177 177 178 - rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; 178 + rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RXQ]; 179 179 rtw89_write16(rtwdev, R_BE_RXQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 180 180 181 - rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 181 + rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 182 182 rtw89_write16(rtwdev, R_BE_RPQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1); 183 183 } 184 184 ··· 665 665 SIMPLE_DEV_PM_OPS(rtw89_pm_ops_be, rtw89_pci_suspend_be, rtw89_pci_resume_be); 666 666 EXPORT_SYMBOL(rtw89_pm_ops_be); 667 667 668 - const struct rtw89_pci_gen_def rtw89_pci_gen_be = { 668 + const struct rtw89_pci_isr_def rtw89_pci_isr_be = { 669 669 .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1, 670 670 .isr_halt_c2h = B_BE_HALT_C2H_INT, 671 671 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 672 672 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 673 673 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 674 + }; 675 + EXPORT_SYMBOL(rtw89_pci_isr_be); 674 676 677 + const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1 = { 678 + .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT, 679 + .isr_halt_c2h = B_BE_HALT_C2H_INT, 680 + .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT, 681 + .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1}, 682 + .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1}, 683 + }; 684 + EXPORT_SYMBOL(rtw89_pci_isr_be_v1); 685 + 686 + const struct rtw89_pci_gen_def rtw89_pci_gen_be = { 675 687 .mac_pre_init = rtw89_pci_ops_mac_pre_init_be, 676 688 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_be, 677 689 .mac_post_init = rtw89_pci_ops_mac_post_init_be,

+440 -36

drivers/net/wireless/realtek/rtw89/phy.c

··· 1702 1702 rtw89_phy_bb_reset(rtwdev); 1703 1703 } 1704 1704 1705 + void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev) 1706 + { 1707 + struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1708 + const struct rtw89_fw_element_hdr *afe_elm = elm_info->afe; 1709 + const struct rtw89_phy_afe_info *info; 1710 + u32 action, cat, class; 1711 + u32 addr, mask, val; 1712 + u32 poll, rpt; 1713 + u32 n, i; 1714 + 1715 + if (!afe_elm) 1716 + return; 1717 + 1718 + n = le32_to_cpu(afe_elm->size) / sizeof(*info); 1719 + 1720 + for (i = 0; i < n; i++) { 1721 + info = &afe_elm->u.afe.infos[i]; 1722 + 1723 + class = le32_to_cpu(info->class); 1724 + switch (class) { 1725 + case RTW89_FW_AFE_CLASS_P0: 1726 + case RTW89_FW_AFE_CLASS_P1: 1727 + case RTW89_FW_AFE_CLASS_CMN: 1728 + /* Currently support two paths */ 1729 + break; 1730 + case RTW89_FW_AFE_CLASS_P2: 1731 + case RTW89_FW_AFE_CLASS_P3: 1732 + case RTW89_FW_AFE_CLASS_P4: 1733 + default: 1734 + rtw89_warn(rtwdev, "unexpected AFE class %u\n", class); 1735 + continue; 1736 + } 1737 + 1738 + addr = le32_to_cpu(info->addr); 1739 + mask = le32_to_cpu(info->mask); 1740 + val = le32_to_cpu(info->val); 1741 + cat = le32_to_cpu(info->cat); 1742 + action = le32_to_cpu(info->action); 1743 + 1744 + switch (action) { 1745 + case RTW89_FW_AFE_ACTION_WRITE: 1746 + switch (cat) { 1747 + case RTW89_FW_AFE_CAT_MAC: 1748 + case RTW89_FW_AFE_CAT_MAC1: 1749 + rtw89_write32_mask(rtwdev, addr, mask, val); 1750 + break; 1751 + case RTW89_FW_AFE_CAT_AFEDIG: 1752 + case RTW89_FW_AFE_CAT_AFEDIG1: 1753 + rtw89_write32_mask(rtwdev, addr, mask, val); 1754 + break; 1755 + case RTW89_FW_AFE_CAT_BB: 1756 + rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1757 + break; 1758 + case RTW89_FW_AFE_CAT_BB1: 1759 + rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1760 + break; 1761 + default: 1762 + rtw89_warn(rtwdev, 1763 + "unexpected AFE writing action %u\n", action); 1764 + break; 1765 + } 1766 + break; 1767 + case RTW89_FW_AFE_ACTION_POLL: 1768 + for (poll = 0; poll <= 10; poll++) { 1769 + /* 1770 + * For CAT_BB, AFE reads register with mcu_offset 0, 1771 + * so both CAT_MAC and CAT_BB use the same method. 1772 + */ 1773 + rpt = rtw89_read32_mask(rtwdev, addr, mask); 1774 + if (rpt == val) 1775 + goto poll_done; 1776 + 1777 + fsleep(1); 1778 + } 1779 + rtw89_warn(rtwdev, "failed to poll AFE cat=%u addr=0x%x mask=0x%x\n", 1780 + cat, addr, mask); 1781 + poll_done: 1782 + break; 1783 + case RTW89_FW_AFE_ACTION_DELAY: 1784 + fsleep(addr); 1785 + break; 1786 + } 1787 + } 1788 + } 1789 + 1705 1790 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1706 1791 { 1707 1792 rtw89_phy_write32(rtwdev, 0x8080, 0x4); ··· 3028 2943 } 3029 2944 3030 2945 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 3031 - valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2946 + valid = rtw89_legacy_rate_to_bitrate(rtwdev, rate, &legacy_bitrate); 3032 2947 if (!valid) 3033 2948 return; 3034 2949 } ··· 3171 3086 [RTW89_PHY_C2H_DM_FUNC_MCC_DIG] = NULL, 3172 3087 [RTW89_PHY_C2H_DM_FUNC_FW_SCAN] = rtw89_phy_c2h_fw_scan_rpt, 3173 3088 }; 3089 + 3090 + static 3091 + void rtw89_phy_c2h_rfk_tas_pwr(struct rtw89_dev *rtwdev, 3092 + const struct rtw89_c2h_rf_tas_rpt_log *content) 3093 + { 3094 + const enum rtw89_sar_sources src = rtwdev->sar.src; 3095 + struct rtw89_tas_info *tas = &rtwdev->tas; 3096 + u64 linear = 0; 3097 + u32 i, cur_idx; 3098 + s16 txpwr; 3099 + 3100 + if (!tas->enable || src == RTW89_SAR_SOURCE_NONE) 3101 + return; 3102 + 3103 + cur_idx = le32_to_cpu(content->cur_idx); 3104 + for (i = 0; i < cur_idx; i++) { 3105 + txpwr = le16_to_cpu(content->txpwr_history[i]); 3106 + linear += rtw89_db_quarter_to_linear(txpwr); 3107 + 3108 + rtw89_debug(rtwdev, RTW89_DBG_SAR, 3109 + "tas: index: %u, txpwr: %d\n", i, txpwr); 3110 + } 3111 + 3112 + if (cur_idx == 0) 3113 + tas->instant_txpwr = rtw89_db_to_linear(0); 3114 + else 3115 + tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx); 3116 + } 3174 3117 3175 3118 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 3176 3119 enum rtw89_phy_c2h_rfk_log_func func, ··· 3451 3338 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 3452 3339 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 3453 3340 return; 3341 + case RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR: 3342 + if (len != sizeof(struct rtw89_c2h_rf_tas_rpt_log)) 3343 + goto out; 3344 + 3345 + rtw89_phy_c2h_rfk_tas_pwr(rtwdev, content); 3346 + 3347 + return; 3454 3348 default: 3455 3349 break; 3456 3350 } ··· 3509 3389 u16 content_len; 3510 3390 u16 chunk_len; 3511 3391 bool handled; 3512 - 3513 - if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 3514 - return; 3515 3392 3516 3393 log_ptr += sizeof(*c2h_hdr); 3517 3394 len -= sizeof(*c2h_hdr); ··· 3586 3469 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 3587 3470 } 3588 3471 3472 + static void 3473 + rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3474 + { 3475 + rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 3476 + RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR, "TAS"); 3477 + } 3478 + 3589 3479 static 3590 3480 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 3591 3481 struct sk_buff *c2h, u32 len) = { ··· 3602 3478 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 3603 3479 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 3604 3480 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 3481 + [RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, 3605 3482 }; 3606 3483 3607 3484 static ··· 3665 3540 } 3666 3541 3667 3542 static void 3668 - rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3543 + rtw89_phy_c2h_rfk_report_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3669 3544 { 3670 - const struct rtw89_c2h_rf_tas_info *rf_tas = 3545 + const struct rtw89_c2h_rf_tas_info *report = 3671 3546 (const struct rtw89_c2h_rf_tas_info *)c2h->data; 3672 - const enum rtw89_sar_sources src = rtwdev->sar.src; 3673 - struct rtw89_tas_info *tas = &rtwdev->tas; 3674 - u64 linear = 0; 3675 - u32 i, cur_idx; 3676 - s16 txpwr; 3677 3547 3678 - if (!tas->enable || src == RTW89_SAR_SOURCE_NONE) 3679 - return; 3680 - 3681 - cur_idx = le32_to_cpu(rf_tas->cur_idx); 3682 - for (i = 0; i < cur_idx; i++) { 3683 - txpwr = (s16)le16_to_cpu(rf_tas->txpwr_history[i]); 3684 - linear += rtw89_db_quarter_to_linear(txpwr); 3685 - 3686 - rtw89_debug(rtwdev, RTW89_DBG_SAR, 3687 - "tas: index: %u, txpwr: %d\n", i, txpwr); 3688 - } 3689 - 3690 - if (cur_idx == 0) 3691 - tas->instant_txpwr = rtw89_db_to_linear(0); 3692 - else 3693 - tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx); 3548 + rtw89_phy_c2h_rfk_tas_pwr(rtwdev, &report->content); 3694 3549 } 3695 3550 3696 3551 static 3697 3552 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3698 3553 struct sk_buff *c2h, u32 len) = { 3699 3554 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3700 - [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr, 3555 + [RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR] = rtw89_phy_c2h_rfk_report_tas_pwr, 3701 3556 }; 3702 3557 3703 3558 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) ··· 3731 3626 handler = rtw89_phy_c2h_dm_handler[func]; 3732 3627 break; 3733 3628 default: 3734 - rtw89_info(rtwdev, "PHY c2h class %d not support\n", class); 3735 - return; 3629 + break; 3736 3630 } 3737 3631 if (!handler) { 3738 - rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class, 3739 - func); 3632 + rtw89_info_once(rtwdev, "PHY c2h class %d func %d not support\n", 3633 + class, func); 3740 3634 return; 3741 3635 } 3742 3636 handler(rtwdev, skb, len); ··· 5601 5497 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 5602 5498 } 5603 5499 5500 + static void __rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev, 5501 + struct rtw89_bb_ctx *bb) 5502 + { 5503 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5504 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 5505 + const struct rtw89_ccx_regs *ccx = phy->ccx; 5506 + 5507 + env->nhm_include_cca = false; 5508 + env->nhm_mntr_time = 0; 5509 + env->nhm_sum = 0; 5510 + 5511 + rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config, ccx->nhm_en_mask, bb->phy_idx); 5512 + rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_method, ccx->nhm_pwr_method_msk, 5513 + bb->phy_idx); 5514 + } 5515 + 5516 + void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev) 5517 + { 5518 + const struct rtw89_chip_info *chip = rtwdev->chip; 5519 + struct rtw89_bb_ctx *bb; 5520 + 5521 + if (!chip->support_noise) 5522 + return; 5523 + 5524 + rtw89_for_each_active_bb(rtwdev, bb) 5525 + __rtw89_phy_nhm_setting_init(rtwdev, bb); 5526 + } 5527 + 5604 5528 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev, 5605 5529 struct rtw89_bb_ctx *bb) 5606 5530 { ··· 5690 5558 } 5691 5559 5692 5560 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev, 5693 - struct rtw89_bb_ctx *bb) 5561 + struct rtw89_bb_ctx *bb, u8 sel) 5694 5562 { 5695 5563 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5696 5564 struct rtw89_env_monitor_info *env = &bb->env_monitor; ··· 5700 5568 bb->phy_idx); 5701 5569 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0, 5702 5570 bb->phy_idx); 5571 + if (sel & RTW89_PHY_ENV_MON_NHM) 5572 + rtw89_phy_write32_idx_clr(rtwdev, ccx->nhm_config, 5573 + ccx->nhm_en_mask, bb->phy_idx); 5574 + 5703 5575 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1, 5704 5576 bb->phy_idx); 5705 5577 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1, 5706 5578 bb->phy_idx); 5579 + if (sel & RTW89_PHY_ENV_MON_NHM) 5580 + rtw89_phy_write32_idx_set(rtwdev, ccx->nhm_config, 5581 + ccx->nhm_en_mask, bb->phy_idx); 5707 5582 5708 5583 env->ccx_ongoing = true; 5709 5584 } ··· 5779 5640 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 5780 5641 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 5781 5642 env->ifs_clm_cca_avg[i]); 5643 + } 5644 + 5645 + static u8 rtw89_nhm_weighted_avg(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 5646 + { 5647 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 5648 + u8 nhm_weight[RTW89_NHM_RPT_NUM]; 5649 + u32 nhm_weighted_sum = 0; 5650 + u8 weight_zero; 5651 + u8 i; 5652 + 5653 + if (env->nhm_sum == 0) 5654 + return 0; 5655 + 5656 + weight_zero = clamp_t(u16, env->nhm_th[0] - RTW89_NHM_WEIGHT_OFFSET, 0, U8_MAX); 5657 + 5658 + for (i = 0; i < RTW89_NHM_RPT_NUM; i++) { 5659 + if (i == 0) 5660 + nhm_weight[i] = weight_zero; 5661 + else if (i == (RTW89_NHM_RPT_NUM - 1)) 5662 + nhm_weight[i] = env->nhm_th[i - 1] + RTW89_NHM_WEIGHT_OFFSET; 5663 + else 5664 + nhm_weight[i] = (env->nhm_th[i - 1] + env->nhm_th[i]) / 2; 5665 + } 5666 + 5667 + if (rtwdev->chip->chip_id == RTL8852A || rtwdev->chip->chip_id == RTL8852B || 5668 + rtwdev->chip->chip_id == RTL8852C) { 5669 + if (env->nhm_th[RTW89_NHM_TH_NUM - 1] == RTW89_NHM_WA_TH) { 5670 + nhm_weight[RTW89_NHM_RPT_NUM - 1] = 5671 + env->nhm_th[RTW89_NHM_TH_NUM - 2] + 5672 + RTW89_NHM_WEIGHT_OFFSET; 5673 + nhm_weight[RTW89_NHM_RPT_NUM - 2] = 5674 + nhm_weight[RTW89_NHM_RPT_NUM - 1]; 5675 + } 5676 + 5677 + env->nhm_result[0] += env->nhm_result[RTW89_NHM_RPT_NUM - 1]; 5678 + env->nhm_result[RTW89_NHM_RPT_NUM - 1] = 0; 5679 + } 5680 + 5681 + for (i = 0; i < RTW89_NHM_RPT_NUM; i++) 5682 + nhm_weighted_sum += env->nhm_result[i] * nhm_weight[i]; 5683 + 5684 + return (nhm_weighted_sum / env->nhm_sum) >> RTW89_NHM_TH_FACTOR; 5685 + } 5686 + 5687 + static void __rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, 5688 + struct rtw89_bb_ctx *bb, enum rtw89_band hw_band, 5689 + u16 ch_hw_value) 5690 + { 5691 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5692 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 5693 + const struct rtw89_chip_info *chip = rtwdev->chip; 5694 + const struct rtw89_ccx_regs *ccx = phy->ccx; 5695 + struct ieee80211_supported_band *sband; 5696 + const struct rtw89_reg_def *nhm_rpt; 5697 + enum nl80211_band band; 5698 + u32 sum = 0; 5699 + u8 chan_idx; 5700 + u8 nhm_pwr; 5701 + u8 i; 5702 + 5703 + if (!rtw89_phy_read32_idx(rtwdev, ccx->nhm, ccx->nhm_ready, bb->phy_idx)) { 5704 + rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] Get NHM report Fail\n"); 5705 + return; 5706 + } 5707 + 5708 + for (i = 0; i < RTW89_NHM_RPT_NUM; i++) { 5709 + nhm_rpt = &(*chip->nhm_report)[i]; 5710 + 5711 + env->nhm_result[i] = 5712 + rtw89_phy_read32_idx(rtwdev, nhm_rpt->addr, 5713 + nhm_rpt->mask, bb->phy_idx); 5714 + sum += env->nhm_result[i]; 5715 + } 5716 + env->nhm_sum = sum; 5717 + nhm_pwr = rtw89_nhm_weighted_avg(rtwdev, bb); 5718 + 5719 + if (!ch_hw_value) 5720 + return; 5721 + 5722 + band = rtw89_hw_to_nl80211_band(hw_band); 5723 + sband = rtwdev->hw->wiphy->bands[band]; 5724 + if (!sband) 5725 + return; 5726 + 5727 + for (chan_idx = 0; chan_idx < sband->n_channels; chan_idx++) { 5728 + struct ieee80211_channel *channel; 5729 + struct rtw89_nhm_report *rpt; 5730 + struct list_head *nhm_list; 5731 + 5732 + channel = &sband->channels[chan_idx]; 5733 + if (channel->hw_value != ch_hw_value) 5734 + continue; 5735 + 5736 + rpt = &env->nhm_his[hw_band][chan_idx]; 5737 + nhm_list = &env->nhm_rpt_list; 5738 + 5739 + rpt->channel = channel; 5740 + rpt->noise = nhm_pwr; 5741 + 5742 + if (list_empty(&rpt->list)) 5743 + list_add_tail(&rpt->list, nhm_list); 5744 + 5745 + return; 5746 + } 5747 + 5748 + rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "[NHM] channel not found\n"); 5749 + } 5750 + 5751 + void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band, 5752 + u16 ch_hw_value) 5753 + { 5754 + const struct rtw89_chip_info *chip = rtwdev->chip; 5755 + struct rtw89_bb_ctx *bb; 5756 + 5757 + if (!chip->support_noise) 5758 + return; 5759 + 5760 + rtw89_for_each_active_bb(rtwdev, bb) 5761 + __rtw89_phy_nhm_get_result(rtwdev, bb, hw_band, ch_hw_value); 5782 5762 } 5783 5763 5784 5764 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev, ··· 6000 5742 return true; 6001 5743 } 6002 5744 5745 + static void rtw89_phy_nhm_th_update(struct rtw89_dev *rtwdev, 5746 + struct rtw89_bb_ctx *bb) 5747 + { 5748 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 5749 + static const u8 nhm_th_11k[RTW89_NHM_RPT_NUM] = { 5750 + 18, 21, 24, 27, 30, 35, 40, 45, 50, 55, 60, 0 5751 + }; 5752 + const struct rtw89_chip_info *chip = rtwdev->chip; 5753 + const struct rtw89_reg_def *nhm_th; 5754 + u8 i; 5755 + 5756 + for (i = 0; i < RTW89_NHM_RPT_NUM; i++) 5757 + env->nhm_th[i] = nhm_th_11k[i] << RTW89_NHM_TH_FACTOR; 5758 + 5759 + if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 5760 + chip->chip_id == RTL8852C) 5761 + env->nhm_th[RTW89_NHM_TH_NUM - 1] = RTW89_NHM_WA_TH; 5762 + 5763 + for (i = 0; i < RTW89_NHM_TH_NUM; i++) { 5764 + nhm_th = &(*chip->nhm_th)[i]; 5765 + 5766 + rtw89_phy_write32_idx(rtwdev, nhm_th->addr, nhm_th->mask, 5767 + env->nhm_th[i], bb->phy_idx); 5768 + } 5769 + } 5770 + 5771 + static int rtw89_phy_nhm_set(struct rtw89_dev *rtwdev, 5772 + struct rtw89_bb_ctx *bb, 5773 + struct rtw89_ccx_para_info *para) 5774 + { 5775 + const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5776 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 5777 + const struct rtw89_ccx_regs *ccx = phy->ccx; 5778 + u32 unit_idx = 0; 5779 + u32 period = 0; 5780 + 5781 + if (para->mntr_time == 0) { 5782 + rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5783 + "[NHM] MNTR_TIME is 0\n"); 5784 + return -EINVAL; 5785 + } 5786 + 5787 + if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv)) 5788 + return -EINVAL; 5789 + 5790 + rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5791 + "[NHM]nhm_incld_cca=%d, mntr_time=%d ms\n", 5792 + para->nhm_incld_cca, para->mntr_time); 5793 + 5794 + if (para->mntr_time != env->nhm_mntr_time) { 5795 + rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5796 + &period, &unit_idx); 5797 + rtw89_phy_write32_idx(rtwdev, ccx->nhm_config, 5798 + ccx->nhm_period_mask, period, bb->phy_idx); 5799 + rtw89_phy_write32_idx(rtwdev, ccx->nhm_config, 5800 + ccx->nhm_unit_mask, period, bb->phy_idx); 5801 + 5802 + env->nhm_mntr_time = para->mntr_time; 5803 + env->ccx_period = period; 5804 + env->ccx_unit_idx = unit_idx; 5805 + } 5806 + 5807 + if (para->nhm_incld_cca != env->nhm_include_cca) { 5808 + rtw89_phy_write32_idx(rtwdev, ccx->nhm_config, 5809 + ccx->nhm_include_cca_mask, para->nhm_incld_cca, 5810 + bb->phy_idx); 5811 + 5812 + env->nhm_include_cca = para->nhm_incld_cca; 5813 + } 5814 + 5815 + rtw89_phy_nhm_th_update(rtwdev, bb); 5816 + 5817 + return 0; 5818 + } 5819 + 5820 + static void __rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 5821 + { 5822 + struct rtw89_ccx_para_info para = { 5823 + .mntr_time = RTW89_NHM_MNTR_TIME, 5824 + .rac_lv = RTW89_RAC_LV_1, 5825 + .nhm_incld_cca = true, 5826 + }; 5827 + 5828 + rtw89_phy_ccx_racing_release(rtwdev, bb); 5829 + 5830 + rtw89_phy_nhm_set(rtwdev, bb, &para); 5831 + rtw89_phy_ccx_trigger(rtwdev, bb, RTW89_PHY_ENV_MON_NHM); 5832 + } 5833 + 5834 + void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev) 5835 + { 5836 + const struct rtw89_chip_info *chip = rtwdev->chip; 5837 + struct rtw89_bb_ctx *bb; 5838 + 5839 + if (!chip->support_noise) 5840 + return; 5841 + 5842 + rtw89_for_each_active_bb(rtwdev, bb) 5843 + __rtw89_phy_nhm_trigger(rtwdev, bb); 5844 + } 5845 + 6003 5846 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 6004 5847 struct rtw89_bb_ctx *bb, 6005 5848 struct rtw89_ccx_para_info *para) ··· 6175 5816 if (rtw89_phy_ifs_clm_set(rtwdev, bb, &para) == 0) 6176 5817 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 6177 5818 if (chk_result) 6178 - rtw89_phy_ccx_trigger(rtwdev, bb); 5819 + rtw89_phy_ccx_trigger(rtwdev, bb, chk_result); 6179 5820 6180 5821 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 6181 5822 "get_result=0x%x, chk_result:0x%x\n", ··· 6289 5930 val |= BIT(RTW89_PHYSTS_IE13_DL_MU_DEF) | 6290 5931 BIT(RTW89_PHYSTS_IE01_CMN_OFDM); 6291 5932 } else if (i >= RTW89_CCK_PKT) { 6292 - val |= BIT(RTW89_PHYSTS_IE09_FTR_0); 6293 - 6294 5933 val &= ~(GENMASK(RTW89_PHYSTS_IE07_CMN_EXT_PATH_D, 6295 5934 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A)); 6296 5935 ··· 7267 6910 rtw89_chip_bb_sethw(rtwdev); 7268 6911 7269 6912 rtw89_phy_env_monitor_init(rtwdev); 6913 + rtw89_phy_nhm_setting_init(rtwdev); 7270 6914 rtw89_physts_parsing_init(rtwdev); 7271 6915 rtw89_phy_dig_init(rtwdev); 7272 6916 rtw89_phy_cfo_init(rtwdev); ··· 7291 6933 { 7292 6934 rtw89_phy_env_monitor_init(rtwdev); 7293 6935 rtw89_physts_parsing_init(rtwdev); 6936 + } 6937 + 6938 + static void __rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb) 6939 + { 6940 + struct rtw89_env_monitor_info *env = &bb->env_monitor; 6941 + const struct rtw89_chip_info *chip = rtwdev->chip; 6942 + struct ieee80211_supported_band *sband; 6943 + enum rtw89_band hw_band; 6944 + enum nl80211_band band; 6945 + u8 idx; 6946 + 6947 + if (!chip->support_noise) 6948 + return; 6949 + 6950 + for (band = 0; band < NUM_NL80211_BANDS; band++) { 6951 + sband = rtwdev->hw->wiphy->bands[band]; 6952 + if (!sband) 6953 + continue; 6954 + 6955 + hw_band = rtw89_nl80211_to_hw_band(band); 6956 + env->nhm_his[hw_band] = 6957 + devm_kcalloc(rtwdev->dev, sband->n_channels, 6958 + sizeof(*env->nhm_his[0]), GFP_KERNEL); 6959 + 6960 + for (idx = 0; idx < sband->n_channels; idx++) 6961 + INIT_LIST_HEAD(&env->nhm_his[hw_band][idx].list); 6962 + 6963 + INIT_LIST_HEAD(&env->nhm_rpt_list); 6964 + } 6965 + } 6966 + 6967 + void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev) 6968 + { 6969 + struct rtw89_bb_ctx *bb; 6970 + 6971 + rtw89_for_each_capab_bb(rtwdev, bb) 6972 + __rtw89_phy_dm_init_data(rtwdev, bb); 7294 6973 } 7295 6974 7296 6975 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, ··· 7985 7590 .ifs_total_addr = R_IFSCNT, 7986 7591 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 7987 7592 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 7593 + .nhm = R_NHM_AX, 7594 + .nhm_ready = B_NHM_READY_MSK, 7595 + .nhm_config = R_NHM_CFG, 7596 + .nhm_period_mask = B_NHM_PERIOD_MSK, 7597 + .nhm_unit_mask = B_NHM_COUNTER_MSK, 7598 + .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK, 7599 + .nhm_en_mask = B_NHM_EN_MSK, 7600 + .nhm_method = R_NHM_TH9, 7601 + .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK, 7988 7602 }; 7989 7603 7990 7604 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {

+23 -1

drivers/net/wireless/realtek/rtw89/phy.h

··· 149 149 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3, 150 150 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4, 151 151 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5, 152 + RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9, 152 153 153 154 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM, 154 155 }; 155 156 156 157 enum rtw89_phy_c2h_rfk_report_func { 157 158 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0, 158 - RTW89_PHY_C2H_RFK_LOG_TAS_PWR = 6, 159 + RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR = 6, 159 160 }; 160 161 161 162 enum rtw89_phy_c2h_dm_func { ··· 188 187 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 189 188 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 190 189 }; 190 + 191 + #define RTW89_NHM_WEIGHT_OFFSET 2 192 + #define RTW89_NHM_WA_TH (109 << 1) 193 + #define RTW89_NOISE_DEFAULT -96 194 + #define RTW89_NHM_MNTR_TIME 40 195 + #define RTW89_NHM_TH_FACTOR 1 191 196 192 197 #define CCX_US_BASE_RATIO 4 193 198 enum rtw89_ccx_unit { ··· 435 428 u32 ifs_total_addr; 436 429 u32 ifs_cnt_done_mask; 437 430 u32 ifs_total_mask; 431 + u32 nhm; 432 + u32 nhm_ready; 433 + u32 nhm_config; 434 + u32 nhm_period_mask; 435 + u32 nhm_unit_mask; 436 + u32 nhm_include_cca_mask; 437 + u32 nhm_en_mask; 438 + u32 nhm_method; 439 + u32 nhm_pwr_method_msk; 438 440 }; 439 441 440 442 struct rtw89_physts_regs { ··· 830 814 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 831 815 u32 addr, u32 mask, u32 data); 832 816 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 817 + void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev); 833 818 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 834 819 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 835 820 const struct rtw89_reg2_def *reg, ··· 838 821 void *extra_data); 839 822 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 840 823 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev); 824 + void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev); 841 825 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 842 826 u32 data, enum rtw89_phy_idx phy_idx); 843 827 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits, ··· 1056 1038 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 1057 1039 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 1058 1040 const struct rtw89_chan *target_chan); 1041 + void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev); 1042 + void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band, 1043 + u16 ch_hw_value); 1044 + void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev); 1059 1045 1060 1046 #endif

+9

drivers/net/wireless/realtek/rtw89/phy_be.c

··· 63 63 .ifs_total_addr = R_IFSCNT_V1, 64 64 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 65 65 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 66 + .nhm = R_NHM_BE, 67 + .nhm_ready = B_NHM_READY_BE_MSK, 68 + .nhm_config = R_NHM_CFG, 69 + .nhm_period_mask = B_NHM_PERIOD_MSK, 70 + .nhm_unit_mask = B_NHM_COUNTER_MSK, 71 + .nhm_include_cca_mask = B_NHM_INCLUDE_CCA_MSK, 72 + .nhm_en_mask = B_NHM_EN_MSK, 73 + .nhm_method = R_NHM_TH9, 74 + .nhm_pwr_method_msk = B_NHM_PWDB_METHOD_MSK, 66 75 }; 67 76 68 77 static const struct rtw89_physts_regs rtw89_physts_regs_be = {

+3

drivers/net/wireless/realtek/rtw89/ps.c

··· 119 119 120 120 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_FW_CTRL); 121 121 rtw89_fw_h2c_lps_parm(rtwdev, &lps_param); 122 + 123 + if (RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 124 + rtw89_fw_h2c_pwr_lvl(rtwdev, rtwvif_link); 122 125 } 123 126 124 127 static void __rtw89_leave_lps(struct rtw89_dev *rtwdev,

+56

drivers/net/wireless/realtek/rtw89/reg.h

··· 3370 3370 #define B_AX_CSIPRT_HESU_AID_EN BIT(25) 3371 3371 #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24) 3372 3372 3373 + #define R_AX_BCN_PSR_RPT_P0 0xCE84 3374 + #define R_AX_BCN_PSR_RPT_P0_C1 0xEE84 3375 + #define B_AX_BCAID_P0_MASK GENMASK(10, 0) 3376 + 3373 3377 #define R_AX_RX_STATE_MONITOR 0xCEF0 3374 3378 #define R_AX_RX_STATE_MONITOR_C1 0xEEF0 3375 3379 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) ··· 6262 6258 #define B_BE_PTCL_TOP_ERR_IND BIT(1) 6263 6259 #define B_BE_SCHEDULE_TOP_ERR_IND BIT(0) 6264 6260 6261 + #define R_BE_CMAC_FW_TRIGGER_IDCT_ISR 0x10168 6262 + #define R_BE_CMAC_FW_TRIGGER_IDCT_ISR_C1 0x14168 6263 + #define B_BE_CMAC_FW_ERR_IDCT_IMR BIT(31) 6264 + #define B_BE_CMAC_FW_TRIG_IDCT BIT(0) 6265 + 6265 6266 #define R_BE_SER_L0_DBG_CNT 0x10170 6266 6267 #define R_BE_SER_L0_DBG_CNT_C1 0x14170 6267 6268 #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24) ··· 7503 7494 #define R_BE_DRV_INFO_OPTION_C1 0x15470 7504 7495 #define B_BE_DRV_INFO_PHYRPT_EN BIT(0) 7505 7496 7497 + #define R_BE_BCN_PSR_RPT_P0 0x11484 7498 + #define R_BE_BCN_PSR_RPT_P0_C1 0x15484 7499 + #define B_BE_BCAID_P0_MASK GENMASK(10, 0) 7500 + 7506 7501 #define R_BE_RX_ERR_ISR 0x114F4 7507 7502 #define R_BE_RX_ERR_ISR_C1 0x154F4 7508 7503 #define B_BE_RX_ERR_TRIG_ACT_TO BIT(9) ··· 8105 8092 #define B_MEASUREMENT_TRIG_MSK BIT(2) 8106 8093 #define B_CCX_TRIG_OPT_MSK BIT(1) 8107 8094 #define B_CCX_EN_MSK BIT(0) 8095 + #define R_NHM_CFG 0x0C08 8096 + #define B_NHM_PERIOD_MSK GENMASK(15, 0) 8097 + #define B_NHM_COUNTER_MSK GENMASK(17, 16) 8098 + #define B_NHM_EN_MSK BIT(18) 8099 + #define B_NHM_INCLUDE_CCA_MSK BIT(19) 8100 + #define B_NHM_TH0_MSK GENMASK(31, 24) 8101 + #define R_NHM_TH1 0x0C0C 8102 + #define B_NHM_TH1_MSK GENMASK(7, 0) 8103 + #define B_NHM_TH2_MSK GENMASK(15, 8) 8104 + #define B_NHM_TH3_MSK GENMASK(23, 16) 8105 + #define B_NHM_TH4_MSK GENMASK(31, 24) 8106 + #define R_NHM_TH5 0x0C10 8107 + #define B_NHM_TH5_MSK GENMASK(7, 0) 8108 + #define B_NHM_TH6_MSK GENMASK(15, 8) 8109 + #define B_NHM_TH7_MSK GENMASK(23, 16) 8110 + #define B_NHM_TH8_MSK GENMASK(31, 24) 8111 + #define R_NHM_TH9 0x0C14 8112 + #define B_NHM_TH9_MSK GENMASK(7, 0) 8113 + #define B_NHM_TH10_MSK GENMASK(15, 8) 8114 + #define B_NHM_PWDB_METHOD_MSK GENMASK(17, 16) 8108 8115 #define R_FAHM 0x0C1C 8109 8116 #define B_RXTD_CKEN BIT(2) 8110 8117 #define R_IFS_COUNTER 0x0C28 ··· 8194 8161 #define R_BRK_ASYNC_RST_EN_1 0x0DC0 8195 8162 #define R_BRK_ASYNC_RST_EN_2 0x0DC4 8196 8163 #define R_BRK_ASYNC_RST_EN_3 0x0DC8 8164 + #define R_NHM_BE 0x0EA4 8165 + #define B_NHM_READY_BE_MSK BIT(16) 8197 8166 #define R_CTLTOP 0x1008 8198 8167 #define B_CTLTOP_ON BIT(23) 8199 8168 #define B_CTLTOP_VAL GENMASK(15, 12) ··· 8251 8216 #define B_SWSI_R_BUSY_V1 BIT(25) 8252 8217 #define B_SWSI_R_DATA_DONE_V1 BIT(26) 8253 8218 #define R_TX_COUNTER 0x1A40 8219 + #define R_NHM_CNT0 0x1A88 8220 + #define B_NHM_CNT0_MSK GENMASK(15, 0) 8221 + #define B_NHM_CNT1_MSK GENMASK(31, 16) 8222 + #define R_NHM_CNT2 0x1A8C 8223 + #define B_NHM_CNT2_MSK GENMASK(15, 0) 8224 + #define B_NHM_CNT3_MSK GENMASK(31, 16) 8225 + #define R_NHM_CNT4 0x1A90 8226 + #define B_NHM_CNT4_MSK GENMASK(15, 0) 8227 + #define B_NHM_CNT5_MSK GENMASK(31, 16) 8228 + #define R_NHM_CNT6 0x1A94 8229 + #define B_NHM_CNT6_MSK GENMASK(15, 0) 8230 + #define B_NHM_CNT7_MSK GENMASK(31, 16) 8231 + #define R_NHM_CNT8 0x1A98 8232 + #define B_NHM_CNT8_MSK GENMASK(15, 0) 8233 + #define B_NHM_CNT9_MSK GENMASK(31, 16) 8234 + #define R_NHM_CNT10 0x1A9C 8235 + #define B_NHM_CNT10_MSK GENMASK(15, 0) 8236 + #define B_NHM_CNT11_MSK GENMASK(31, 16) 8237 + #define R_NHM_AX 0x1AA4 8238 + #define B_NHM_READY_MSK BIT(16) 8254 8239 #define R_IFS_CLM_TX_CNT 0x1ACC 8255 8240 #define R_IFS_CLM_TX_CNT_V1 0x0ECC 8256 8241 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) ··· 9181 9126 #define B_COEF_SEL_MDPD BIT(8) 9182 9127 #define B_COEF_SEL_MDPD_V1 GENMASK(9, 8) 9183 9128 #define B_COEF_SEL_EN BIT(31) 9129 + #define R_CFIR_COEF 0x810c 9184 9130 #define R_CFIR_SYS 0x8120 9185 9131 #define R_IQK_RES 0x8124 9186 9132 #define B_IQK_RES_K BIT(28)

+4

drivers/net/wireless/realtek/rtw89/rtw8851b.c

··· 2537 2537 .query_rxdesc = rtw89_core_query_rxdesc, 2538 2538 .fill_txdesc = rtw89_core_fill_txdesc, 2539 2539 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2540 + .get_ch_dma = rtw89_core_get_ch_dma, 2540 2541 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2541 2542 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2542 2543 .stop_sch_tx = rtw89_mac_stop_sch_tx, ··· 2629 2628 .support_ant_gain = false, 2630 2629 .support_tas = false, 2631 2630 .support_sar_by_ant = false, 2631 + .support_noise = false, 2632 2632 .ul_tb_waveform_ctrl = true, 2633 2633 .ul_tb_pwr_diff = false, 2634 2634 .rx_freq_frome_ie = true, ··· 2691 2689 .cfo_hw_comp = true, 2692 2690 .dcfo_comp = &rtw8851b_dcfo_comp, 2693 2691 .dcfo_comp_sft = 12, 2692 + .nhm_report = NULL, 2693 + .nhm_th = NULL, 2694 2694 .imr_info = &rtw8851b_imr_info, 2695 2695 .imr_dmac_table = NULL, 2696 2696 .imr_cmac_table = NULL,

+95 -62

drivers/net/wireless/realtek/rtw89/rtw8851b_rfk.c

··· 17 17 #define DPK_RF_REG_NUM_8851B 4 18 18 #define DPK_KSET_NUM 4 19 19 #define RTW8851B_RXK_GROUP_NR 4 20 - #define RTW8851B_RXK_GROUP_IDX_NR 2 21 - #define RTW8851B_TXK_GROUP_NR 1 20 + #define RTW8851B_RXK_GROUP_IDX_NR 4 21 + #define RTW8851B_A_TXK_GROUP_NR 2 22 + #define RTW8851B_G_TXK_GROUP_NR 1 22 23 #define RTW8851B_IQK_VER 0x14 23 24 #define RTW8851B_IQK_SS 1 24 25 #define RTW8851B_LOK_GRAM 10 ··· 115 114 static const u32 g_idxrxgain[RTW8851B_RXK_GROUP_NR] = {0x10e, 0x116, 0x28e, 0x296}; 116 115 static const u32 g_idxattc2[RTW8851B_RXK_GROUP_NR] = {0x0, 0xf, 0x0, 0xf}; 117 116 static const u32 g_idxrxagc[RTW8851B_RXK_GROUP_NR] = {0x0, 0x1, 0x2, 0x3}; 118 - static const u32 a_idxrxgain[RTW8851B_RXK_GROUP_IDX_NR] = {0x10C, 0x28c}; 119 - static const u32 a_idxattc2[RTW8851B_RXK_GROUP_IDX_NR] = {0xf, 0xf}; 120 - static const u32 a_idxrxagc[RTW8851B_RXK_GROUP_IDX_NR] = {0x4, 0x6}; 121 - static const u32 a_power_range[RTW8851B_TXK_GROUP_NR] = {0x0}; 122 - static const u32 a_track_range[RTW8851B_TXK_GROUP_NR] = {0x6}; 123 - static const u32 a_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x0a}; 124 - static const u32 a_itqt[RTW8851B_TXK_GROUP_NR] = {0x12}; 125 - static const u32 g_power_range[RTW8851B_TXK_GROUP_NR] = {0x0}; 126 - static const u32 g_track_range[RTW8851B_TXK_GROUP_NR] = {0x6}; 127 - static const u32 g_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x10}; 128 - static const u32 g_itqt[RTW8851B_TXK_GROUP_NR] = {0x12}; 117 + static const u32 a_idxrxgain[RTW8851B_RXK_GROUP_IDX_NR] = {0x10C, 0x112, 0x28c, 0x292}; 118 + static const u32 a_idxattc2[RTW8851B_RXK_GROUP_IDX_NR] = {0xf, 0xf, 0xf, 0xf}; 119 + static const u32 a_idxrxagc[RTW8851B_RXK_GROUP_IDX_NR] = {0x4, 0x5, 0x6, 0x7}; 120 + static const u32 a_power_range[RTW8851B_A_TXK_GROUP_NR] = {0x0, 0x0}; 121 + static const u32 a_track_range[RTW8851B_A_TXK_GROUP_NR] = {0x7, 0x7}; 122 + static const u32 a_gain_bb[RTW8851B_A_TXK_GROUP_NR] = {0x08, 0x0d}; 123 + static const u32 a_itqt[RTW8851B_A_TXK_GROUP_NR] = {0x12, 0x12}; 124 + static const u32 a_att_smxr[RTW8851B_A_TXK_GROUP_NR] = {0x0, 0x2}; 125 + static const u32 g_power_range[RTW8851B_G_TXK_GROUP_NR] = {0x0}; 126 + static const u32 g_track_range[RTW8851B_G_TXK_GROUP_NR] = {0x6}; 127 + static const u32 g_gain_bb[RTW8851B_G_TXK_GROUP_NR] = {0x10}; 128 + static const u32 g_itqt[RTW8851B_G_TXK_GROUP_NR] = {0x12}; 129 129 130 - static const u32 rtw8851b_backup_bb_regs[] = {0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8}; 130 + static const u32 rtw8851b_backup_bb_regs[] = { 131 + 0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8, 0x12a0, 0xc0f0}; 131 132 static const u32 rtw8851b_backup_rf_regs[] = { 132 133 0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5}; 133 134 ··· 141 138 static const u32 dpk_rf_reg[DPK_RF_REG_NUM_8851B] = {0xde, 0x8f, 0x5, 0x10005}; 142 139 143 140 static void _set_ch(struct rtw89_dev *rtwdev, u32 val); 144 - 145 - static u8 _rxk_5ghz_group_from_idx(u8 idx) 146 - { 147 - /* There are four RXK groups (RTW8851B_RXK_GROUP_NR), but only group 0 148 - * and 2 are used in 5 GHz band, so reduce elements to 2. 149 - */ 150 - if (idx < RTW8851B_RXK_GROUP_IDX_NR) 151 - return idx * 2; 152 - 153 - return 0; 154 - } 155 141 156 142 static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 157 143 { ··· 188 196 static void _rxck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 189 197 bool force, enum adc_ck ck) 190 198 { 191 - static const u32 ck960_8851b[] = {0x8, 0x2, 0x2, 0x4, 0xf, 0xa, 0x93}; 199 + static const u32 ck960_8851b[] = {0x8, 0x2, 0x2, 0x4, 0xf, 0xa, 0x92}; 192 200 static const u32 ck1920_8851b[] = {0x9, 0x0, 0x0, 0x3, 0xf, 0xa, 0x49}; 193 201 const u32 *data; 194 202 ··· 792 800 "[IQK]============ S%d ID_NBTXK ============\n", path); 793 801 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0); 794 802 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 795 - 0x00b); 803 + 0x11); 796 804 iqk_cmd = 0x408 | (1 << (4 + path)); 797 805 break; 798 806 case ID_NBRXK: ··· 810 818 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1); 811 819 notready = _iqk_check_cal(rtwdev, path); 812 820 if (iqk_info->iqk_sram_en && 813 - (ktype == ID_NBRXK || ktype == ID_RXK)) 821 + (ktype == ID_NBRXK || ktype == ID_RXK || ktype == ID_NBTXK)) 814 822 _iqk_sram(rtwdev, path); 815 823 816 824 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0); ··· 897 905 bool kfail = false; 898 906 bool notready; 899 907 u32 rf_0; 900 - u8 idx; 908 + u32 val; 901 909 u8 gp; 902 910 903 911 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 904 912 905 - for (idx = 0; idx < RTW8851B_RXK_GROUP_IDX_NR; idx++) { 906 - gp = _rxk_5ghz_group_from_idx(idx); 913 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x1000); 914 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x4); 915 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x17); 916 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x5); 917 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x27); 918 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x0); 907 919 920 + val = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20); 921 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0xc); 922 + 923 + for (gp = 0; gp < RTW8851B_RXK_GROUP_IDX_NR; gp++) { 908 924 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp); 909 925 910 - rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]); 911 - rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]); 926 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[gp]); 927 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[gp]); 928 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20, 0x1); 912 929 913 930 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1); 914 931 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0); ··· 927 926 fsleep(100); 928 927 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); 929 928 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0); 930 - rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]); 929 + rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[gp]); 931 930 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); 932 931 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC); 933 932 ··· 960 959 _iqk_sram(rtwdev, path); 961 960 962 961 if (kfail) { 962 + rtw89_phy_write32_mask(rtwdev, R_IQK_RES, B_IQK_RES_RXCFIR, 0x0); 963 963 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 964 964 iqk_info->nb_rxcfir[path] | 0x2); 965 965 iqk_info->is_wb_txiqk[path] = false; ··· 969 967 0x40000000); 970 968 iqk_info->is_wb_txiqk[path] = true; 971 969 } 970 + 971 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20, val); 972 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x1000); 973 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x4); 974 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x37); 975 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x5); 976 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x27); 977 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x0); 972 978 973 979 rtw89_debug(rtwdev, RTW89_DBG_RFK, 974 980 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail, ··· 990 980 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 991 981 bool kfail = false; 992 982 bool notready; 993 - u8 idx = 0x1; 983 + u8 gp = 2; 994 984 u32 rf_0; 995 - u8 gp; 996 - 997 - gp = _rxk_5ghz_group_from_idx(idx); 985 + u32 val; 998 986 999 987 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1000 988 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp); 1001 989 1002 - rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]); 1003 - rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]); 990 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x1000); 991 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x4); 992 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x17); 993 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x5); 994 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x27); 995 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x0); 996 + 997 + val = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20); 998 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0xc); 999 + 1000 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[gp]); 1001 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[gp]); 1002 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20, 0x1); 1004 1003 1005 1004 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1); 1006 1005 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0); ··· 1019 1000 fsleep(100); 1020 1001 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); 1021 1002 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0); 1022 - rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]); 1003 + rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[gp]); 1023 1004 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); 1024 1005 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC); 1025 1006 ··· 1045 1026 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG); 1046 1027 1047 1028 if (kfail) { 1029 + rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), 0xf, 0x0); 1048 1030 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), 1049 1031 MASKDWORD, 0x40000002); 1050 1032 iqk_info->is_wb_rxiqk[path] = false; 1051 1033 } else { 1052 1034 iqk_info->is_wb_rxiqk[path] = false; 1053 1035 } 1036 + 1037 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, 0x20, val); 1038 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x1000); 1039 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x4); 1040 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x37); 1041 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x5); 1042 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x27); 1043 + rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x0); 1054 1044 1055 1045 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1056 1046 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail, ··· 1177 1149 static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev, 1178 1150 enum rtw89_phy_idx phy_idx, u8 path) 1179 1151 { 1152 + static const u8 a_idx[RTW8851B_A_TXK_GROUP_NR] = {2, 3}; 1180 1153 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1181 1154 bool kfail = false; 1182 1155 bool notready; ··· 1185 1156 1186 1157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1187 1158 1188 - for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) { 1159 + rtw89_phy_write32_mask(rtwdev, R_CFIR_COEF, MASKDWORD, 0x33332222); 1160 + 1161 + for (gp = 0x0; gp < RTW8851B_A_TXK_GROUP_NR; gp++) { 1189 1162 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]); 1190 1163 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]); 1191 1164 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]); 1165 + rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, a_att_smxr[gp]); 1192 1166 1193 1167 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1); 1194 1168 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1); 1195 1169 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0); 1196 - rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp); 1170 + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, a_idx[gp]); 1197 1171 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 1172 + rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x11); 1198 1173 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]); 1199 1174 1200 1175 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); ··· 1239 1206 1240 1207 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1241 1208 1242 - for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) { 1209 + rtw89_phy_write32_mask(rtwdev, R_CFIR_COEF, MASKDWORD, 0x0); 1210 + 1211 + for (gp = 0x0; gp < RTW8851B_G_TXK_GROUP_NR; gp++) { 1243 1212 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]); 1244 1213 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]); 1245 1214 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]); ··· 1284 1249 static bool _iqk_5g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, 1285 1250 u8 path) 1286 1251 { 1252 + static const u8 a_idx[RTW8851B_A_TXK_GROUP_NR] = {2, 3}; 1287 1253 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1288 1254 bool kfail = false; 1289 1255 bool notready; 1290 - u8 gp; 1256 + u8 gp = 0; 1291 1257 1292 1258 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1293 1259 1294 - for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) { 1295 - rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]); 1296 - rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]); 1297 - rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]); 1260 + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]); 1261 + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]); 1262 + rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]); 1263 + rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, a_att_smxr[gp]); 1298 1264 1299 - rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1); 1300 - rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1); 1301 - rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0); 1302 - rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp); 1303 - rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 1304 - rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]); 1265 + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1); 1266 + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1); 1267 + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0); 1268 + rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, a_idx[gp]); 1269 + rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00); 1270 + rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]); 1305 1271 1306 - notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); 1307 - iqk_info->nb_txcfir[path] = 1308 - rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2; 1309 - } 1272 + notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); 1273 + iqk_info->nb_txcfir[path] = 1274 + rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2; 1310 1275 1311 1276 if (!notready) 1312 1277 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG); ··· 1335 1300 1336 1301 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); 1337 1302 1338 - for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) { 1303 + for (gp = 0x0; gp < RTW8851B_G_TXK_GROUP_NR; gp++) { 1339 1304 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]); 1340 1305 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]); 1341 1306 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]); ··· 1698 1663 { 1699 1664 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; 1700 1665 u8 idx, path; 1701 - 1702 - rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0); 1703 1666 1704 1667 if (iqk_info->is_iqk_init) 1705 1668 return;

+4

drivers/net/wireless/realtek/rtw89/rtw8851be.c

··· 11 11 12 12 static const struct rtw89_pci_info rtw8851b_pci_info = { 13 13 .gen_def = &rtw89_pci_gen_ax, 14 + .isr_def = &rtw89_pci_isr_ax, 14 15 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 15 16 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 16 17 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 29 28 .rx_ring_eq_is_full = false, 30 29 .check_rx_tag = false, 31 30 .no_rxbd_fs = false, 31 + .group_bd_addr = false, 32 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 32 33 33 34 .init_cfg_reg = R_AX_PCIE_INIT_CFG1, 34 35 .txhci_en_bit = B_AX_TXHCI_EN, ··· 60 57 61 58 .ltr_set = rtw89_pci_ltr_set, 62 59 .fill_txaddr_info = rtw89_pci_fill_txaddr_info, 60 + .parse_rpp = rtw89_pci_parse_rpp, 63 61 .config_intr_mask = rtw89_pci_config_intr_mask, 64 62 .enable_intr = rtw89_pci_enable_intr, 65 63 .disable_intr = rtw89_pci_disable_intr,

+3

drivers/net/wireless/realtek/rtw89/rtw8851bu.c

··· 16 16 static const struct usb_device_id rtw_8851bu_id_table[] = { 17 17 { USB_DEVICE_AND_INTERFACE_INFO(0x0bda, 0xb851, 0xff, 0xff, 0xff), 18 18 .driver_info = (kernel_ulong_t)&rtw89_8851bu_info }, 19 + /* D-Link AX9U rev. A1 */ 20 + { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x332a, 0xff, 0xff, 0xff), 21 + .driver_info = (kernel_ulong_t)&rtw89_8851bu_info }, 19 22 /* TP-Link Archer TX10UB Nano */ 20 23 { USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010b, 0xff, 0xff, 0xff), 21 24 .driver_info = (kernel_ulong_t)&rtw89_8851bu_info },

+43 -3

drivers/net/wireless/realtek/rtw89/rtw8852a.c

··· 426 426 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 427 427 }; 428 428 429 + static const struct rtw89_reg_def rtw8852a_nhm_th[RTW89_NHM_TH_NUM] = { 430 + {R_NHM_CFG, B_NHM_TH0_MSK}, 431 + {R_NHM_TH1, B_NHM_TH1_MSK}, 432 + {R_NHM_TH1, B_NHM_TH2_MSK}, 433 + {R_NHM_TH1, B_NHM_TH3_MSK}, 434 + {R_NHM_TH1, B_NHM_TH4_MSK}, 435 + {R_NHM_TH5, B_NHM_TH5_MSK}, 436 + {R_NHM_TH5, B_NHM_TH6_MSK}, 437 + {R_NHM_TH5, B_NHM_TH7_MSK}, 438 + {R_NHM_TH5, B_NHM_TH8_MSK}, 439 + {R_NHM_TH9, B_NHM_TH9_MSK}, 440 + {R_NHM_TH9, B_NHM_TH10_MSK}, 441 + }; 442 + 443 + static const struct rtw89_reg_def rtw8852a_nhm_rpt[RTW89_NHM_RPT_NUM] = { 444 + {R_NHM_CNT0, B_NHM_CNT0_MSK}, 445 + {R_NHM_CNT0, B_NHM_CNT1_MSK}, 446 + {R_NHM_CNT2, B_NHM_CNT2_MSK}, 447 + {R_NHM_CNT2, B_NHM_CNT3_MSK}, 448 + {R_NHM_CNT4, B_NHM_CNT4_MSK}, 449 + {R_NHM_CNT4, B_NHM_CNT5_MSK}, 450 + {R_NHM_CNT6, B_NHM_CNT6_MSK}, 451 + {R_NHM_CNT6, B_NHM_CNT7_MSK}, 452 + {R_NHM_CNT8, B_NHM_CNT8_MSK}, 453 + {R_NHM_CNT8, B_NHM_CNT9_MSK}, 454 + {R_NHM_CNT10, B_NHM_CNT10_MSK}, 455 + {R_NHM_CNT10, B_NHM_CNT11_MSK}, 456 + }; 457 + 429 458 static const struct rtw89_imr_info rtw8852a_imr_info = { 430 459 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 431 460 .wsec_imr_reg = R_AX_SEC_DEBUG, ··· 2109 2080 { 2110 2081 u8 path; 2111 2082 u8 *rx_power = phy_ppdu->rssi; 2083 + u8 raw; 2112 2084 2113 - if (!status->signal) 2114 - status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], 2115 - rx_power[RF_PATH_B])); 2085 + if (!status->signal) { 2086 + if (phy_ppdu->to_self) 2087 + raw = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 2088 + else 2089 + raw = max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 2090 + 2091 + status->signal = RTW89_RSSI_RAW_TO_DBM(raw); 2092 + } 2093 + 2116 2094 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2117 2095 status->chains |= BIT(path); 2118 2096 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); ··· 2178 2142 .query_rxdesc = rtw89_core_query_rxdesc, 2179 2143 .fill_txdesc = rtw89_core_fill_txdesc, 2180 2144 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2145 + .get_ch_dma = rtw89_core_get_ch_dma, 2181 2146 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2182 2147 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2183 2148 .stop_sch_tx = rtw89_mac_stop_sch_tx, ··· 2257 2220 .support_ant_gain = false, 2258 2221 .support_tas = false, 2259 2222 .support_sar_by_ant = false, 2223 + .support_noise = true, 2260 2224 .ul_tb_waveform_ctrl = false, 2261 2225 .ul_tb_pwr_diff = false, 2262 2226 .rx_freq_frome_ie = true, ··· 2320 2282 .cfo_hw_comp = false, 2321 2283 .dcfo_comp = &rtw8852a_dcfo_comp, 2322 2284 .dcfo_comp_sft = 10, 2285 + .nhm_report = &rtw8852a_nhm_rpt, 2286 + .nhm_th = &rtw8852a_nhm_th, 2323 2287 .imr_info = &rtw8852a_imr_info, 2324 2288 .imr_dmac_table = NULL, 2325 2289 .imr_cmac_table = NULL,

+4

drivers/net/wireless/realtek/rtw89/rtw8852ae.c

··· 11 11 12 12 static const struct rtw89_pci_info rtw8852a_pci_info = { 13 13 .gen_def = &rtw89_pci_gen_ax, 14 + .isr_def = &rtw89_pci_isr_ax, 14 15 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 15 16 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 16 17 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 29 28 .rx_ring_eq_is_full = false, 30 29 .check_rx_tag = false, 31 30 .no_rxbd_fs = false, 31 + .group_bd_addr = false, 32 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 32 33 33 34 .init_cfg_reg = R_AX_PCIE_INIT_CFG1, 34 35 .txhci_en_bit = B_AX_TXHCI_EN, ··· 58 55 59 56 .ltr_set = rtw89_pci_ltr_set, 60 57 .fill_txaddr_info = rtw89_pci_fill_txaddr_info, 58 + .parse_rpp = rtw89_pci_parse_rpp, 61 59 .config_intr_mask = rtw89_pci_config_intr_mask, 62 60 .enable_intr = rtw89_pci_enable_intr, 63 61 .disable_intr = rtw89_pci_disable_intr,

+4

drivers/net/wireless/realtek/rtw89/rtw8852b.c

··· 842 842 .query_rxdesc = rtw89_core_query_rxdesc, 843 843 .fill_txdesc = rtw89_core_fill_txdesc, 844 844 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 845 + .get_ch_dma = rtw89_core_get_ch_dma, 845 846 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 846 847 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 847 848 .stop_sch_tx = rtw89_mac_stop_sch_tx, ··· 940 939 .support_ant_gain = true, 941 940 .support_tas = false, 942 941 .support_sar_by_ant = true, 942 + .support_noise = false, 943 943 .ul_tb_waveform_ctrl = true, 944 944 .ul_tb_pwr_diff = false, 945 945 .rx_freq_frome_ie = true, ··· 1003 1001 .cfo_hw_comp = true, 1004 1002 .dcfo_comp = &rtw8852b_dcfo_comp, 1005 1003 .dcfo_comp_sft = 10, 1004 + .nhm_report = NULL, 1005 + .nhm_th = NULL, 1006 1006 .imr_info = &rtw8852b_imr_info, 1007 1007 .imr_dmac_table = NULL, 1008 1008 .imr_cmac_table = NULL,

+4

drivers/net/wireless/realtek/rtw89/rtw8852be.c

··· 11 11 12 12 static const struct rtw89_pci_info rtw8852b_pci_info = { 13 13 .gen_def = &rtw89_pci_gen_ax, 14 + .isr_def = &rtw89_pci_isr_ax, 14 15 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 15 16 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 16 17 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 29 28 .rx_ring_eq_is_full = false, 30 29 .check_rx_tag = false, 31 30 .no_rxbd_fs = false, 31 + .group_bd_addr = false, 32 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 32 33 33 34 .init_cfg_reg = R_AX_PCIE_INIT_CFG1, 34 35 .txhci_en_bit = B_AX_TXHCI_EN, ··· 60 57 61 58 .ltr_set = rtw89_pci_ltr_set, 62 59 .fill_txaddr_info = rtw89_pci_fill_txaddr_info, 60 + .parse_rpp = rtw89_pci_parse_rpp, 63 61 .config_intr_mask = rtw89_pci_config_intr_mask, 64 62 .enable_intr = rtw89_pci_enable_intr, 65 63 .disable_intr = rtw89_pci_disable_intr,

+1

drivers/net/wireless/realtek/rtw89/rtw8852bt.c

··· 708 708 .query_rxdesc = rtw89_core_query_rxdesc, 709 709 .fill_txdesc = rtw89_core_fill_txdesc, 710 710 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 711 + .get_ch_dma = rtw89_core_get_ch_dma, 711 712 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 712 713 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 713 714 .stop_sch_tx = rtw89_mac_stop_sch_tx,

+3 -11

drivers/net/wireless/realtek/rtw89/rtw8852bt_rfk.c

··· 1799 1799 { 1800 1800 struct rtw89_dpk_info *dpk = &rtwdev->dpk; 1801 1801 u8 val, kidx = dpk->cur_idx[path]; 1802 - bool off_reverse; 1803 1802 1804 1803 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; 1805 - 1806 - if (off) 1807 - off_reverse = false; 1808 - else 1809 - off_reverse = true; 1810 - 1811 - val = dpk->is_dpk_enable & off_reverse & dpk->bp[path][kidx].path_ok; 1812 1804 1813 1805 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), 1814 1806 BIT(24), val); 1815 1807 1816 1808 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, 1817 - kidx, str_enable_disable(dpk->is_dpk_enable & off_reverse)); 1809 + kidx, str_enable_disable(dpk->is_dpk_enable && !off)); 1818 1810 } 1819 1811 1820 1812 static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ··· 1875 1883 rtw89_debug(rtwdev, RTW89_DBG_RFK, 1876 1884 "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n", 1877 1885 path, dpk->cur_idx[path], phy, 1878 - rtwdev->is_tssi_mode[path] ? "on" : "off", 1879 - rtwdev->dbcc_en ? "on" : "off", 1886 + str_on_off(rtwdev->is_tssi_mode[path]), 1887 + str_on_off(rtwdev->dbcc_en), 1880 1888 dpk->bp[path][kidx].band == 0 ? "2G" : 1881 1889 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", 1882 1890 dpk->bp[path][kidx].ch,

+4

drivers/net/wireless/realtek/rtw89/rtw8852bte.c

··· 17 17 18 18 static const struct rtw89_pci_info rtw8852bt_pci_info = { 19 19 .gen_def = &rtw89_pci_gen_ax, 20 + .isr_def = &rtw89_pci_isr_ax, 20 21 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 21 22 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 22 23 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 35 34 .rx_ring_eq_is_full = false, 36 35 .check_rx_tag = false, 37 36 .no_rxbd_fs = false, 37 + .group_bd_addr = false, 38 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 38 39 39 40 .init_cfg_reg = R_AX_PCIE_INIT_CFG1, 40 41 .txhci_en_bit = B_AX_TXHCI_EN, ··· 66 63 67 64 .ltr_set = rtw89_pci_ltr_set, 68 65 .fill_txaddr_info = rtw89_pci_fill_txaddr_info, 66 + .parse_rpp = rtw89_pci_parse_rpp, 69 67 .config_intr_mask = rtw89_pci_config_intr_mask, 70 68 .enable_intr = rtw89_pci_enable_intr, 71 69 .disable_intr = rtw89_pci_disable_intr,

+2

drivers/net/wireless/realtek/rtw89/rtw8852bu.c

··· 30 30 .driver_info = (kernel_ulong_t)&rtw89_8852bu_info }, 31 31 { USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x6931, 0xff, 0xff, 0xff), 32 32 .driver_info = (kernel_ulong_t)&rtw89_8852bu_info }, 33 + { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3327, 0xff, 0xff, 0xff), 34 + .driver_info = (kernel_ulong_t)&rtw89_8852bu_info }, 33 35 { USB_DEVICE_AND_INTERFACE_INFO(0x3574, 0x6121, 0xff, 0xff, 0xff), 34 36 .driver_info = (kernel_ulong_t)&rtw89_8852bu_info }, 35 37 { USB_DEVICE_AND_INTERFACE_INFO(0x35bc, 0x0100, 0xff, 0xff, 0xff),

+4

drivers/net/wireless/realtek/rtw89/rtw8852c.c

··· 2962 2962 .query_rxdesc = rtw89_core_query_rxdesc, 2963 2963 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2964 2964 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2965 + .get_ch_dma = rtw89_core_get_ch_dma, 2965 2966 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2966 2967 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2967 2968 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, ··· 3044 3043 .support_ant_gain = true, 3045 3044 .support_tas = true, 3046 3045 .support_sar_by_ant = true, 3046 + .support_noise = false, 3047 3047 .ul_tb_waveform_ctrl = false, 3048 3048 .ul_tb_pwr_diff = true, 3049 3049 .rx_freq_frome_ie = false, ··· 3108 3106 .cfo_hw_comp = false, 3109 3107 .dcfo_comp = &rtw8852c_dcfo_comp, 3110 3108 .dcfo_comp_sft = 12, 3109 + .nhm_report = NULL, 3110 + .nhm_th = NULL, 3111 3111 .imr_info = &rtw8852c_imr_info, 3112 3112 .imr_dmac_table = NULL, 3113 3113 .imr_cmac_table = NULL,

+4

drivers/net/wireless/realtek/rtw89/rtw8852ce.c

··· 20 20 21 21 static const struct rtw89_pci_info rtw8852c_pci_info = { 22 22 .gen_def = &rtw89_pci_gen_ax, 23 + .isr_def = &rtw89_pci_isr_ax, 23 24 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 24 25 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 25 26 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 38 37 .rx_ring_eq_is_full = false, 39 38 .check_rx_tag = false, 40 39 .no_rxbd_fs = false, 40 + .group_bd_addr = false, 41 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 41 42 42 43 .init_cfg_reg = R_AX_HAXI_INIT_CFG1, 43 44 .txhci_en_bit = B_AX_TXHCI_EN_V1, ··· 67 64 68 65 .ltr_set = rtw89_pci_ltr_set_v1, 69 66 .fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1, 67 + .parse_rpp = rtw89_pci_parse_rpp, 70 68 .config_intr_mask = rtw89_pci_config_intr_mask_v1, 71 69 .enable_intr = rtw89_pci_enable_intr_v1, 72 70 .disable_intr = rtw89_pci_disable_intr_v1,

+10 -1

drivers/net/wireless/realtek/rtw89/rtw8922a.c

··· 2765 2765 return 0; 2766 2766 } 2767 2767 2768 + static const struct rtw89_chanctx_listener rtw8922a_chanctx_listener = { 2769 + .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb, 2770 + }; 2771 + 2768 2772 #ifdef CONFIG_PM 2769 2773 static const struct wiphy_wowlan_support rtw_wowlan_stub_8922a = { 2770 2774 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT | ··· 2821 2817 .query_rxdesc = rtw89_core_query_rxdesc_v2, 2822 2818 .fill_txdesc = rtw89_core_fill_txdesc_v2, 2823 2819 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2, 2820 + .get_ch_dma = rtw89_core_get_ch_dma, 2824 2821 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2, 2825 2822 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v2, 2826 2823 .stop_sch_tx = rtw89_mac_stop_sch_tx_v2, ··· 2880 2875 .nctl_post_table = NULL, 2881 2876 .dflt_parms = NULL, /* load parm from fw */ 2882 2877 .rfe_parms_conf = NULL, /* load parm from fw */ 2878 + .chanctx_listener = &rtw8922a_chanctx_listener, 2883 2879 .txpwr_factor_bb = 3, 2884 2880 .txpwr_factor_rf = 2, 2885 2881 .txpwr_factor_mac = 1, ··· 2900 2894 BIT(NL80211_CHAN_WIDTH_160), 2901 2895 .support_unii4 = true, 2902 2896 .support_ant_gain = true, 2903 - .support_tas = false, 2897 + .support_tas = true, 2904 2898 .support_sar_by_ant = true, 2899 + .support_noise = false, 2905 2900 .ul_tb_waveform_ctrl = false, 2906 2901 .ul_tb_pwr_diff = false, 2907 2902 .rx_freq_frome_ie = false, ··· 2965 2958 .cfo_hw_comp = true, 2966 2959 .dcfo_comp = NULL, 2967 2960 .dcfo_comp_sft = 0, 2961 + .nhm_report = NULL, 2962 + .nhm_th = NULL, 2968 2963 .imr_info = NULL, 2969 2964 .imr_dmac_table = &rtw8922a_imr_dmac_table, 2970 2965 .imr_cmac_table = &rtw8922a_imr_cmac_table,

+4

drivers/net/wireless/realtek/rtw89/rtw8922ae.c

··· 17 17 18 18 static const struct rtw89_pci_info rtw8922a_pci_info = { 19 19 .gen_def = &rtw89_pci_gen_be, 20 + .isr_def = &rtw89_pci_isr_be, 20 21 .txbd_trunc_mode = MAC_AX_BD_TRUNC, 21 22 .rxbd_trunc_mode = MAC_AX_BD_TRUNC, 22 23 .rxbd_mode = MAC_AX_RXBD_PKT, ··· 35 34 .rx_ring_eq_is_full = true, 36 35 .check_rx_tag = true, 37 36 .no_rxbd_fs = true, 37 + .group_bd_addr = false, 38 + .rpp_fmt_size = sizeof(struct rtw89_pci_rpp_fmt), 38 39 39 40 .init_cfg_reg = R_BE_HAXI_INIT_CFG1, 40 41 .txhci_en_bit = B_BE_TXDMA_EN, ··· 64 61 65 62 .ltr_set = rtw89_pci_ltr_set_v2, 66 63 .fill_txaddr_info = rtw89_pci_fill_txaddr_info_v1, 64 + .parse_rpp = rtw89_pci_parse_rpp, 67 65 .config_intr_mask = rtw89_pci_config_intr_mask_v2, 68 66 .enable_intr = rtw89_pci_enable_intr_v2, 69 67 .disable_intr = rtw89_pci_disable_intr_v2,

+15

drivers/net/wireless/realtek/rtw89/sar.c

··· 4 4 5 5 #include "acpi.h" 6 6 #include "debug.h" 7 + #include "fw.h" 7 8 #include "phy.h" 8 9 #include "reg.h" 9 10 #include "sar.h" ··· 843 842 } 844 843 } 845 844 EXPORT_SYMBOL(rtw89_tas_chanctx_cb); 845 + 846 + void rtw89_tas_fw_timer_enable(struct rtw89_dev *rtwdev, bool enable) 847 + { 848 + const struct rtw89_chip_info *chip = rtwdev->chip; 849 + struct rtw89_tas_info *tas = &rtwdev->tas; 850 + 851 + if (!tas->enable) 852 + return; 853 + 854 + if (chip->chip_gen == RTW89_CHIP_AX) 855 + return; 856 + 857 + rtw89_fw_h2c_rf_tas_trigger(rtwdev, enable); 858 + } 846 859 847 860 void rtw89_sar_init(struct rtw89_dev *rtwdev) 848 861 {

+1

drivers/net/wireless/realtek/rtw89/sar.h

··· 37 37 void rtw89_tas_scan(struct rtw89_dev *rtwdev, bool start); 38 38 void rtw89_tas_chanctx_cb(struct rtw89_dev *rtwdev, 39 39 enum rtw89_chanctx_state state); 40 + void rtw89_tas_fw_timer_enable(struct rtw89_dev *rtwdev, bool enable); 40 41 void rtw89_sar_init(struct rtw89_dev *rtwdev); 41 42 void rtw89_sar_track(struct rtw89_dev *rtwdev); 42 43

+3 -2

drivers/net/wireless/realtek/rtw89/ser.c

··· 205 205 206 206 static int ser_send_msg(struct rtw89_ser *ser, u8 event) 207 207 { 208 - struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); 209 208 struct ser_msg *msg = NULL; 210 209 211 210 if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) ··· 220 221 list_add(&msg->list, &ser->msg_q); 221 222 spin_unlock_irq(&ser->msg_q_lock); 222 223 223 - ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work); 224 + schedule_work(&ser->ser_hdl_work); 224 225 return 0; 225 226 } 226 227 ··· 501 502 } 502 503 503 504 drv_stop_rx(ser); 505 + wiphy_lock(wiphy); 504 506 drv_trx_reset(ser); 507 + wiphy_unlock(wiphy); 505 508 506 509 /* wait m3 */ 507 510 hal_send_m2_event(ser);

+1 -37

drivers/net/wireless/realtek/rtw89/txrx.h

··· 572 572 } __packed; 573 573 574 574 #define RTW89_PHY_STS_IE00_W0_RPL GENMASK(15, 7) 575 + #define RTW89_PHY_STS_IE00_W3_RX_PATH_EN GENMASK(31, 28) 575 576 576 577 struct rtw89_phy_sts_ie00_v2 { 577 578 __le32 w0; ··· 731 730 return RTW89_TX_QSEL_B1_MGMT; 732 731 else 733 732 return RTW89_TX_QSEL_B0_MGMT; 734 - } 735 - 736 - static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 737 - { 738 - switch (qsel) { 739 - default: 740 - rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 741 - fallthrough; 742 - case RTW89_TX_QSEL_BE_0: 743 - case RTW89_TX_QSEL_BE_1: 744 - case RTW89_TX_QSEL_BE_2: 745 - case RTW89_TX_QSEL_BE_3: 746 - return RTW89_TXCH_ACH0; 747 - case RTW89_TX_QSEL_BK_0: 748 - case RTW89_TX_QSEL_BK_1: 749 - case RTW89_TX_QSEL_BK_2: 750 - case RTW89_TX_QSEL_BK_3: 751 - return RTW89_TXCH_ACH1; 752 - case RTW89_TX_QSEL_VI_0: 753 - case RTW89_TX_QSEL_VI_1: 754 - case RTW89_TX_QSEL_VI_2: 755 - case RTW89_TX_QSEL_VI_3: 756 - return RTW89_TXCH_ACH2; 757 - case RTW89_TX_QSEL_VO_0: 758 - case RTW89_TX_QSEL_VO_1: 759 - case RTW89_TX_QSEL_VO_2: 760 - case RTW89_TX_QSEL_VO_3: 761 - return RTW89_TXCH_ACH3; 762 - case RTW89_TX_QSEL_B0_MGMT: 763 - return RTW89_TXCH_CH8; 764 - case RTW89_TX_QSEL_B0_HI: 765 - return RTW89_TXCH_CH9; 766 - case RTW89_TX_QSEL_B1_MGMT: 767 - return RTW89_TXCH_CH10; 768 - case RTW89_TX_QSEL_B1_HI: 769 - return RTW89_TXCH_CH11; 770 - } 771 733 } 772 734 773 735 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)

+64 -15

drivers/net/wireless/realtek/rtw89/wow.c

··· 99 99 100 100 ieee80211_get_key_rx_seq(key, 0, &seq); 101 101 102 - /* seq.ccmp.pn[] is BE order array */ 103 - pn = u64_encode_bits(seq.ccmp.pn[0], RTW89_KEY_PN_5) | 104 - u64_encode_bits(seq.ccmp.pn[1], RTW89_KEY_PN_4) | 105 - u64_encode_bits(seq.ccmp.pn[2], RTW89_KEY_PN_3) | 106 - u64_encode_bits(seq.ccmp.pn[3], RTW89_KEY_PN_2) | 107 - u64_encode_bits(seq.ccmp.pn[4], RTW89_KEY_PN_1) | 108 - u64_encode_bits(seq.ccmp.pn[5], RTW89_KEY_PN_0); 102 + switch (key->cipher) { 103 + case WLAN_CIPHER_SUITE_TKIP: 104 + pn = u64_encode_bits(seq.tkip.iv32, RTW89_KEY_TKIP_PN_IV32) | 105 + u64_encode_bits(seq.tkip.iv16, RTW89_KEY_TKIP_PN_IV16); 106 + break; 107 + case WLAN_CIPHER_SUITE_CCMP: 108 + case WLAN_CIPHER_SUITE_GCMP: 109 + case WLAN_CIPHER_SUITE_CCMP_256: 110 + case WLAN_CIPHER_SUITE_GCMP_256: 111 + /* seq.ccmp.pn[] is BE order array */ 112 + pn = u64_encode_bits(seq.ccmp.pn[0], RTW89_KEY_PN_5) | 113 + u64_encode_bits(seq.ccmp.pn[1], RTW89_KEY_PN_4) | 114 + u64_encode_bits(seq.ccmp.pn[2], RTW89_KEY_PN_3) | 115 + u64_encode_bits(seq.ccmp.pn[3], RTW89_KEY_PN_2) | 116 + u64_encode_bits(seq.ccmp.pn[4], RTW89_KEY_PN_1) | 117 + u64_encode_bits(seq.ccmp.pn[5], RTW89_KEY_PN_0); 118 + break; 119 + default: 120 + return -EINVAL; 121 + } 109 122 110 123 err = _pn_to_iv(rtwdev, key, iv, pn, key->keyidx); 111 124 if (err) ··· 190 177 if (err) 191 178 return err; 192 179 193 - /* seq.ccmp.pn[] is BE order array */ 194 - seq.ccmp.pn[0] = u64_get_bits(pn, RTW89_KEY_PN_5); 195 - seq.ccmp.pn[1] = u64_get_bits(pn, RTW89_KEY_PN_4); 196 - seq.ccmp.pn[2] = u64_get_bits(pn, RTW89_KEY_PN_3); 197 - seq.ccmp.pn[3] = u64_get_bits(pn, RTW89_KEY_PN_2); 198 - seq.ccmp.pn[4] = u64_get_bits(pn, RTW89_KEY_PN_1); 199 - seq.ccmp.pn[5] = u64_get_bits(pn, RTW89_KEY_PN_0); 180 + switch (key->cipher) { 181 + case WLAN_CIPHER_SUITE_TKIP: 182 + seq.tkip.iv32 = u64_get_bits(pn, RTW89_KEY_TKIP_PN_IV32); 183 + seq.tkip.iv16 = u64_get_bits(pn, RTW89_KEY_TKIP_PN_IV16); 184 + break; 185 + case WLAN_CIPHER_SUITE_CCMP: 186 + case WLAN_CIPHER_SUITE_GCMP: 187 + case WLAN_CIPHER_SUITE_CCMP_256: 188 + case WLAN_CIPHER_SUITE_GCMP_256: 189 + /* seq.ccmp.pn[] is BE order array */ 190 + seq.ccmp.pn[0] = u64_get_bits(pn, RTW89_KEY_PN_5); 191 + seq.ccmp.pn[1] = u64_get_bits(pn, RTW89_KEY_PN_4); 192 + seq.ccmp.pn[2] = u64_get_bits(pn, RTW89_KEY_PN_3); 193 + seq.ccmp.pn[3] = u64_get_bits(pn, RTW89_KEY_PN_2); 194 + seq.ccmp.pn[4] = u64_get_bits(pn, RTW89_KEY_PN_1); 195 + seq.ccmp.pn[5] = u64_get_bits(pn, RTW89_KEY_PN_0); 196 + break; 197 + default: 198 + return -EINVAL; 199 + } 200 200 201 201 ieee80211_set_key_rx_seq(key, 0, &seq); 202 202 rtw89_debug(rtwdev, RTW89_DBG_WOW, "%s key %d iv-%*ph to pn-%*ph\n", ··· 311 285 312 286 switch (key->cipher) { 313 287 case WLAN_CIPHER_SUITE_TKIP: 288 + if (sta) 289 + memcpy(gtk_info->txmickey, 290 + key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY, 291 + sizeof(gtk_info->txmickey)); 292 + fallthrough; 314 293 case WLAN_CIPHER_SUITE_CCMP: 315 294 case WLAN_CIPHER_SUITE_GCMP: 316 295 case WLAN_CIPHER_SUITE_CCMP_256: ··· 379 348 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 380 349 struct rtw89_set_key_info_iter_data *iter_data = data; 381 350 bool update_tx_key_info = iter_data->rx_ready; 351 + u8 tmp[RTW89_MIC_KEY_LEN]; 382 352 int ret; 383 353 384 354 switch (key->cipher) { 385 355 case WLAN_CIPHER_SUITE_TKIP: 356 + /* 357 + * TX MIC KEY and RX MIC KEY is oppsite in FW, 358 + * need to swap it before sending to mac80211. 359 + */ 360 + if (!sta && update_tx_key_info && aoac_rpt->rekey_ok && 361 + !iter_data->tkip_gtk_swapped) { 362 + memcpy(tmp, &aoac_rpt->gtk[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY], 363 + RTW89_MIC_KEY_LEN); 364 + memcpy(&aoac_rpt->gtk[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY], 365 + &aoac_rpt->gtk[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY], 366 + RTW89_MIC_KEY_LEN); 367 + memcpy(&aoac_rpt->gtk[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY], 368 + tmp, RTW89_MIC_KEY_LEN); 369 + iter_data->tkip_gtk_swapped = true; 370 + } 371 + fallthrough; 386 372 case WLAN_CIPHER_SUITE_CCMP: 387 373 case WLAN_CIPHER_SUITE_GCMP: 388 374 case WLAN_CIPHER_SUITE_CCMP_256: ··· 690 642 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 691 643 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 692 644 struct rtw89_set_key_info_iter_data data = {.error = false, 693 - .rx_ready = rx_ready}; 645 + .rx_ready = rx_ready, 646 + .tkip_gtk_swapped = false}; 694 647 struct ieee80211_bss_conf *bss_conf; 695 648 struct ieee80211_key_conf *key; 696 649

+6

drivers/net/wireless/realtek/rtw89/wow.h

··· 5 5 #ifndef __RTW89_WOW_H__ 6 6 #define __RTW89_WOW_H__ 7 7 8 + #define RTW89_KEY_TKIP_PN_IV16 GENMASK_ULL(15, 0) 9 + #define RTW89_KEY_TKIP_PN_IV32 GENMASK_ULL(47, 16) 10 + 8 11 #define RTW89_KEY_PN_0 GENMASK_ULL(7, 0) 9 12 #define RTW89_KEY_PN_1 GENMASK_ULL(15, 8) 10 13 #define RTW89_KEY_PN_2 GENMASK_ULL(23, 16) ··· 27 24 #define RTW89_WOW_VALID_CHECK 0xDD 28 25 #define RTW89_WOW_SYMBOL_CHK_PTK BIT(0) 29 26 #define RTW89_WOW_SYMBOL_CHK_GTK BIT(1) 27 + 28 + #define RTW89_MIC_KEY_LEN 8 30 29 31 30 enum rtw89_wake_reason { 32 31 RTW89_WOW_RSN_RX_PTK_REKEY = 0x1, ··· 78 73 u32 igtk_cipher; 79 74 bool rx_ready; 80 75 bool error; 76 + bool tkip_gtk_swapped; 81 77 }; 82 78 83 79 static inline int rtw89_wow_get_sec_hdr_len(struct rtw89_dev *rtwdev)

+253 -6

drivers/net/wireless/virtual/mac80211_hwsim.c

··· 645 645 static struct rhashtable hwsim_radios_rht; 646 646 static int hwsim_radio_idx; 647 647 static int hwsim_radios_generation = 1; 648 + static u8 hwsim_nan_cluster_id[ETH_ALEN]; 648 649 649 650 static struct platform_driver mac80211_hwsim_driver = { 650 651 .driver = { ··· 671 670 struct ieee80211_channel channels_s1g[ARRAY_SIZE(hwsim_channels_s1g)]; 672 671 struct ieee80211_rate rates[ARRAY_SIZE(hwsim_rates)]; 673 672 struct ieee80211_iface_combination if_combination; 674 - struct ieee80211_iface_limit if_limits[3]; 673 + struct ieee80211_iface_limit if_limits[4]; 675 674 int n_if_limits; 676 675 677 676 struct ieee80211_iface_combination if_combination_radio; ··· 680 679 681 680 u32 ciphers[ARRAY_SIZE(hwsim_ciphers)]; 682 681 683 - struct mac_address addresses[2]; 682 + struct mac_address addresses[3]; 684 683 int channels, idx; 685 684 bool use_chanctx; 686 685 bool destroy_on_close; ··· 753 752 struct wireless_dev *pmsr_request_wdev; 754 753 755 754 struct mac80211_hwsim_link_data link_data[IEEE80211_MLD_MAX_NUM_LINKS]; 755 + 756 + struct ieee80211_vif *nan_device_vif; 757 + u8 nan_bands; 758 + 759 + enum nl80211_band nan_curr_dw_band; 760 + struct hrtimer nan_timer; 761 + bool notify_dw; 762 + struct ieee80211_vif *nan_vif; 756 763 }; 757 764 758 765 static const struct rhashtable_params hwsim_rht_params = { ··· 935 926 [HWSIM_ATTR_PMSR_SUPPORT] = NLA_POLICY_NESTED(hwsim_pmsr_capa_policy), 936 927 [HWSIM_ATTR_PMSR_RESULT] = NLA_POLICY_NESTED(hwsim_pmsr_peers_result_policy), 937 928 [HWSIM_ATTR_MULTI_RADIO] = { .type = NLA_FLAG }, 929 + [HWSIM_ATTR_SUPPORT_NAN_DEVICE] = { .type = NLA_FLAG }, 938 930 }; 939 931 940 932 #if IS_REACHABLE(CONFIG_VIRTIO) ··· 1654 1644 struct tx_iter_data *data = _data; 1655 1645 int i; 1656 1646 1647 + /* For NAN Device simulation purposes, assume that NAN is always 1648 + * on channel 6 or channel 149. 1649 + */ 1650 + if (vif->type == NL80211_IFTYPE_NAN) { 1651 + data->receive = (data->channel && 1652 + (data->channel->center_freq == 2437 || 1653 + data->channel->center_freq == 5745)); 1654 + return; 1655 + } 1656 + 1657 1657 for (i = 0; i < ARRAY_SIZE(vif->link_conf); i++) { 1658 1658 struct ieee80211_bss_conf *conf; 1659 1659 struct ieee80211_chanctx_conf *chanctx; ··· 1964 1944 struct ieee80211_hdr *hdr = (void *)skb->data; 1965 1945 struct ieee80211_chanctx_conf *chanctx_conf; 1966 1946 struct ieee80211_channel *channel; 1947 + struct ieee80211_vif *vif = txi->control.vif; 1967 1948 bool ack; 1968 1949 enum nl80211_chan_width confbw = NL80211_CHAN_WIDTH_20_NOHT; 1969 1950 u32 _portid, i; ··· 1975 1954 return; 1976 1955 } 1977 1956 1978 - if (!data->use_chanctx) { 1957 + if (vif && vif->type == NL80211_IFTYPE_NAN && !data->tmp_chan) { 1958 + /* For NAN Device simulation purposes, assume that NAN is always 1959 + * on channel 6 or channel 149, unless a ROC is in progress (for 1960 + * USD use cases). 1961 + */ 1962 + if (data->nan_curr_dw_band == NL80211_BAND_2GHZ) 1963 + channel = ieee80211_get_channel(hw->wiphy, 2437); 1964 + else if (data->nan_curr_dw_band == NL80211_BAND_5GHZ) 1965 + channel = ieee80211_get_channel(hw->wiphy, 5745); 1966 + else 1967 + channel = NULL; 1968 + 1969 + if (WARN_ON(!channel)) { 1970 + ieee80211_free_txskb(hw, skb); 1971 + return; 1972 + } 1973 + } else if (!data->use_chanctx) { 1979 1974 channel = data->channel; 1980 1975 confbw = data->bw; 1981 1976 } else if (txi->hw_queue == 4) { ··· 1999 1962 } else { 2000 1963 u8 link = u32_get_bits(IEEE80211_SKB_CB(skb)->control.flags, 2001 1964 IEEE80211_TX_CTRL_MLO_LINK); 2002 - struct ieee80211_vif *vif = txi->control.vif; 2003 1965 struct ieee80211_link_sta *link_sta = NULL; 2004 1966 struct ieee80211_sta *sta = control->sta; 2005 1967 struct ieee80211_bss_conf *bss_conf; ··· 3986 3950 return err; 3987 3951 } 3988 3952 3953 + static enum hrtimer_restart 3954 + mac80211_hwsim_nan_dw_start(struct hrtimer *timer) 3955 + { 3956 + struct mac80211_hwsim_data *data = 3957 + container_of(timer, struct mac80211_hwsim_data, 3958 + nan_timer); 3959 + struct ieee80211_hw *hw = data->hw; 3960 + u64 orig_tsf = mac80211_hwsim_get_tsf(hw, NULL), tsf = orig_tsf; 3961 + u32 dw_int = 512 * 1024; 3962 + u64 until_dw; 3963 + 3964 + if (!data->nan_device_vif) 3965 + return HRTIMER_NORESTART; 3966 + 3967 + if (data->nan_bands & BIT(NL80211_BAND_5GHZ)) { 3968 + if (data->nan_curr_dw_band == NL80211_BAND_2GHZ) { 3969 + dw_int = 128 * 1024; 3970 + data->nan_curr_dw_band = NL80211_BAND_5GHZ; 3971 + } else if (data->nan_curr_dw_band == NL80211_BAND_5GHZ) { 3972 + data->nan_curr_dw_band = NL80211_BAND_2GHZ; 3973 + } 3974 + } 3975 + 3976 + until_dw = dw_int - do_div(tsf, dw_int); 3977 + 3978 + /* The timer might fire just before the actual DW, in which case 3979 + * update the timeout to the actual next DW 3980 + */ 3981 + if (until_dw < dw_int / 2) 3982 + until_dw += dw_int; 3983 + 3984 + /* The above do_div() call directly modifies the 'tsf' variable, thus, 3985 + * use a copy so that the print below would show the original TSF. 3986 + */ 3987 + wiphy_debug(hw->wiphy, 3988 + "%s: tsf=%llx, curr_dw_band=%u, next_dw=%llu\n", 3989 + __func__, orig_tsf, data->nan_curr_dw_band, 3990 + until_dw); 3991 + 3992 + hrtimer_forward_now(&data->nan_timer, 3993 + ns_to_ktime(until_dw * NSEC_PER_USEC)); 3994 + 3995 + if (data->notify_dw) { 3996 + struct ieee80211_channel *ch; 3997 + struct wireless_dev *wdev = 3998 + ieee80211_vif_to_wdev(data->nan_device_vif); 3999 + 4000 + if (data->nan_curr_dw_band == NL80211_BAND_5GHZ) 4001 + ch = ieee80211_get_channel(hw->wiphy, 5475); 4002 + else 4003 + ch = ieee80211_get_channel(hw->wiphy, 2437); 4004 + 4005 + cfg80211_next_nan_dw_notif(wdev, ch, GFP_ATOMIC); 4006 + } 4007 + 4008 + return HRTIMER_RESTART; 4009 + } 4010 + 4011 + static int mac80211_hwsim_start_nan(struct ieee80211_hw *hw, 4012 + struct ieee80211_vif *vif, 4013 + struct cfg80211_nan_conf *conf) 4014 + { 4015 + struct mac80211_hwsim_data *data = hw->priv; 4016 + u64 tsf = mac80211_hwsim_get_tsf(hw, NULL); 4017 + u32 dw_int = 512 * 1000; 4018 + u64 until_dw = dw_int - do_div(tsf, dw_int); 4019 + struct wireless_dev *wdev = ieee80211_vif_to_wdev(vif); 4020 + 4021 + if (vif->type != NL80211_IFTYPE_NAN) 4022 + return -EINVAL; 4023 + 4024 + if (data->nan_device_vif) 4025 + return -EALREADY; 4026 + 4027 + /* set this before starting the timer, as preemption might occur */ 4028 + data->nan_device_vif = vif; 4029 + data->nan_bands = conf->bands; 4030 + data->nan_curr_dw_band = NL80211_BAND_2GHZ; 4031 + 4032 + wiphy_debug(hw->wiphy, "nan_started, next_dw=%llu\n", 4033 + until_dw); 4034 + 4035 + hrtimer_start(&data->nan_timer, 4036 + ns_to_ktime(until_dw * NSEC_PER_USEC), 4037 + HRTIMER_MODE_REL_SOFT); 4038 + 4039 + if (conf->cluster_id && !is_zero_ether_addr(conf->cluster_id) && 4040 + is_zero_ether_addr(hwsim_nan_cluster_id)) { 4041 + memcpy(hwsim_nan_cluster_id, conf->cluster_id, ETH_ALEN); 4042 + } else if (is_zero_ether_addr(hwsim_nan_cluster_id)) { 4043 + hwsim_nan_cluster_id[0] = 0x50; 4044 + hwsim_nan_cluster_id[1] = 0x6f; 4045 + hwsim_nan_cluster_id[2] = 0x9a; 4046 + hwsim_nan_cluster_id[3] = 0x01; 4047 + hwsim_nan_cluster_id[4] = get_random_u8(); 4048 + hwsim_nan_cluster_id[5] = get_random_u8(); 4049 + } 4050 + 4051 + data->notify_dw = conf->enable_dw_notification; 4052 + 4053 + cfg80211_nan_cluster_joined(wdev, hwsim_nan_cluster_id, true, 4054 + GFP_KERNEL); 4055 + 4056 + return 0; 4057 + } 4058 + 4059 + static int mac80211_hwsim_stop_nan(struct ieee80211_hw *hw, 4060 + struct ieee80211_vif *vif) 4061 + { 4062 + struct mac80211_hwsim_data *data = hw->priv; 4063 + struct mac80211_hwsim_data *data2; 4064 + bool nan_cluster_running = false; 4065 + 4066 + if (vif->type != NL80211_IFTYPE_NAN || !data->nan_device_vif || 4067 + data->nan_device_vif != vif) 4068 + return -EINVAL; 4069 + 4070 + hrtimer_cancel(&data->nan_timer); 4071 + data->nan_device_vif = NULL; 4072 + 4073 + spin_lock(&hwsim_radio_lock); 4074 + list_for_each_entry(data2, &hwsim_radios, list) { 4075 + if (data2->nan_device_vif) { 4076 + nan_cluster_running = true; 4077 + break; 4078 + } 4079 + } 4080 + spin_unlock(&hwsim_radio_lock); 4081 + 4082 + if (!nan_cluster_running) 4083 + memset(hwsim_nan_cluster_id, 0, ETH_ALEN); 4084 + 4085 + return 0; 4086 + } 4087 + 4088 + static int mac80211_hwsim_change_nan_config(struct ieee80211_hw *hw, 4089 + struct ieee80211_vif *vif, 4090 + struct cfg80211_nan_conf *conf, 4091 + u32 changes) 4092 + { 4093 + struct mac80211_hwsim_data *data = hw->priv; 4094 + 4095 + if (vif->type != NL80211_IFTYPE_NAN) 4096 + return -EINVAL; 4097 + 4098 + if (!data->nan_device_vif) 4099 + return -EINVAL; 4100 + 4101 + wiphy_debug(hw->wiphy, "nan_config_changed: changes=0x%x\n", changes); 4102 + 4103 + /* Handle only the changes we care about for simulation purposes */ 4104 + if (changes & CFG80211_NAN_CONF_CHANGED_BANDS) { 4105 + data->nan_bands = conf->bands; 4106 + data->nan_curr_dw_band = NL80211_BAND_2GHZ; 4107 + } 4108 + 4109 + if (changes & CFG80211_NAN_CONF_CHANGED_CONFIG) 4110 + data->notify_dw = conf->enable_dw_notification; 4111 + 4112 + return 0; 4113 + } 4114 + 3989 4115 #ifdef CONFIG_MAC80211_DEBUGFS 3990 4116 #define HWSIM_DEBUGFS_OPS \ 3991 4117 .link_add_debugfs = mac80211_hwsim_link_add_debugfs, ··· 4180 3982 .get_et_strings = mac80211_hwsim_get_et_strings, \ 4181 3983 .start_pmsr = mac80211_hwsim_start_pmsr, \ 4182 3984 .abort_pmsr = mac80211_hwsim_abort_pmsr, \ 3985 + .start_nan = mac80211_hwsim_start_nan, \ 3986 + .stop_nan = mac80211_hwsim_stop_nan, \ 3987 + .nan_change_conf = mac80211_hwsim_change_nan_config, \ 4183 3988 HWSIM_DEBUGFS_OPS 4184 3989 4185 3990 #define HWSIM_NON_MLO_OPS \ ··· 4248 4047 u8 n_ciphers; 4249 4048 bool mlo; 4250 4049 const struct cfg80211_pmsr_capabilities *pmsr_capa; 4050 + bool nan_device; 4251 4051 }; 4252 4052 4253 4053 static void hwsim_mcast_config_msg(struct sk_buff *mcast_skb, ··· 4329 4127 return ret; 4330 4128 } 4331 4129 4130 + if (param->nan_device) { 4131 + ret = nla_put_flag(skb, HWSIM_ATTR_SUPPORT_NAN_DEVICE); 4132 + if (ret < 0) 4133 + return ret; 4134 + } 4332 4135 return 0; 4333 4136 } 4334 4137 ··· 5446 5239 /* Why need here second address ? */ 5447 5240 memcpy(data->addresses[1].addr, addr, ETH_ALEN); 5448 5241 data->addresses[1].addr[0] |= 0x40; 5449 - hw->wiphy->n_addresses = 2; 5242 + memcpy(data->addresses[2].addr, addr, ETH_ALEN); 5243 + data->addresses[2].addr[0] |= 0x50; 5244 + 5245 + hw->wiphy->n_addresses = 3; 5450 5246 hw->wiphy->addresses = data->addresses; 5451 5247 /* possible address clash is checked at hash table insertion */ 5452 5248 } else { 5453 5249 memcpy(data->addresses[0].addr, param->perm_addr, ETH_ALEN); 5454 5250 /* compatibility with automatically generated mac addr */ 5455 5251 memcpy(data->addresses[1].addr, param->perm_addr, ETH_ALEN); 5456 - hw->wiphy->n_addresses = 2; 5252 + memcpy(data->addresses[2].addr, param->perm_addr, ETH_ALEN); 5253 + hw->wiphy->n_addresses = 3; 5457 5254 hw->wiphy->addresses = data->addresses; 5458 5255 } 5459 5256 ··· 5492 5281 data->if_limits[n_limits].types = 5493 5282 BIT(NL80211_IFTYPE_P2P_DEVICE); 5494 5283 n_limits++; 5284 + } 5285 + 5286 + if (param->iftypes & BIT(NL80211_IFTYPE_NAN)) { 5287 + data->if_limits[n_limits].max = 1; 5288 + data->if_limits[n_limits].types = BIT(NL80211_IFTYPE_NAN); 5289 + n_limits++; 5290 + 5291 + hw->wiphy->nan_supported_bands = BIT(NL80211_BAND_2GHZ) | 5292 + BIT(NL80211_BAND_5GHZ); 5293 + 5294 + hw->wiphy->nan_capa.flags = WIPHY_NAN_FLAGS_CONFIGURABLE_SYNC | 5295 + WIPHY_NAN_FLAGS_USERSPACE_DE; 5296 + hw->wiphy->nan_capa.op_mode = NAN_OP_MODE_PHY_MODE_MASK | 5297 + NAN_OP_MODE_80P80MHZ | 5298 + NAN_OP_MODE_160MHZ; 5299 + 5300 + hw->wiphy->nan_capa.n_antennas = 0x22; 5301 + hw->wiphy->nan_capa.max_channel_switch_time = 0; 5302 + hw->wiphy->nan_capa.dev_capabilities = 5303 + NAN_DEV_CAPA_EXT_KEY_ID_SUPPORTED | 5304 + NAN_DEV_CAPA_NDPE_SUPPORTED; 5305 + 5306 + hrtimer_setup(&data->nan_timer, mac80211_hwsim_nan_dw_start, 5307 + CLOCK_MONOTONIC, HRTIMER_MODE_ABS_SOFT); 5495 5308 } 5496 5309 5497 5310 data->if_combination.radar_detect_widths = ··· 5936 5701 REGULATORY_STRICT_REG); 5937 5702 param.p2p_device = !!(data->hw->wiphy->interface_modes & 5938 5703 BIT(NL80211_IFTYPE_P2P_DEVICE)); 5704 + param.nan_device = !!(data->hw->wiphy->interface_modes & 5705 + BIT(NL80211_IFTYPE_NAN)); 5939 5706 param.use_chanctx = data->use_chanctx; 5940 5707 param.regd = data->regd; 5941 5708 param.channels = data->channels; ··· 6356 6119 6357 6120 param.reg_strict = info->attrs[HWSIM_ATTR_REG_STRICT_REG]; 6358 6121 param.p2p_device = info->attrs[HWSIM_ATTR_SUPPORT_P2P_DEVICE]; 6122 + param.nan_device = info->attrs[HWSIM_ATTR_SUPPORT_NAN_DEVICE]; 6359 6123 param.channels = channels; 6360 6124 param.destroy_on_close = 6361 6125 info->attrs[HWSIM_ATTR_DESTROY_RADIO_ON_CLOSE]; ··· 6426 6188 param.iftypes & BIT(NL80211_IFTYPE_P2P_DEVICE)) { 6427 6189 param.iftypes |= BIT(NL80211_IFTYPE_P2P_DEVICE); 6428 6190 param.p2p_device = true; 6191 + } 6192 + 6193 + /* ensure both flag and iftype support is honored */ 6194 + if (param.nan_device || 6195 + param.iftypes & BIT(NL80211_IFTYPE_NAN)) { 6196 + param.iftypes |= BIT(NL80211_IFTYPE_NAN); 6197 + param.nan_device = true; 6429 6198 } 6430 6199 6431 6200 if (info->attrs[HWSIM_ATTR_CIPHER_SUPPORT]) { ··· 7155 6910 } 7156 6911 7157 6912 param.p2p_device = support_p2p_device; 6913 + param.nan_device = true; 7158 6914 param.mlo = mlo; 7159 6915 param.multi_radio = multi_radio; 7160 6916 param.use_chanctx = channels > 1 || mlo || multi_radio; 7161 6917 param.iftypes = HWSIM_IFTYPE_SUPPORT_MASK; 7162 6918 if (param.p2p_device) 7163 6919 param.iftypes |= BIT(NL80211_IFTYPE_P2P_DEVICE); 6920 + param.iftypes |= BIT(NL80211_IFTYPE_NAN); 7164 6921 7165 6922 err = mac80211_hwsim_new_radio(NULL, &param); 7166 6923 if (err < 0)

+3 -1

drivers/net/wireless/virtual/mac80211_hwsim.h

··· 3 3 * mac80211_hwsim - software simulator of 802.11 radio(s) for mac80211 4 4 * Copyright (c) 2008, Jouni Malinen <j@w1.fi> 5 5 * Copyright (c) 2011, Javier Lopez <jlopex@gmail.com> 6 - * Copyright (C) 2020, 2022-2024 Intel Corporation 6 + * Copyright (C) 2020, 2022-2025 Intel Corporation 7 7 */ 8 8 9 9 #ifndef __MAC80211_HWSIM_H ··· 160 160 * @HWSIM_ATTR_MULTI_RADIO: Register multiple wiphy radios (flag). 161 161 * Adds one radio for each band. Number of supported channels will be set for 162 162 * each radio instead of for the wiphy. 163 + * @HWSIM_ATTR_SUPPORT_NAN_DEVICE: support NAN Device virtual interface (flag) 163 164 * @__HWSIM_ATTR_MAX: enum limit 164 165 */ 165 166 enum hwsim_attrs { ··· 194 193 HWSIM_ATTR_PMSR_REQUEST, 195 194 HWSIM_ATTR_PMSR_RESULT, 196 195 HWSIM_ATTR_MULTI_RADIO, 196 + HWSIM_ATTR_SUPPORT_NAN_DEVICE, 197 197 __HWSIM_ATTR_MAX, 198 198 }; 199 199 #define HWSIM_ATTR_MAX (__HWSIM_ATTR_MAX - 1)

+34 -1

include/linux/ieee80211.h

··· 1182 1182 IEEE80211_S1G_CHANWIDTH_16MHZ = 15, 1183 1183 }; 1184 1184 1185 + /** 1186 + * enum ieee80211_s1g_pri_chanwidth - S1G primary channel widths 1187 + * described in IEEE80211-2024 Table 10-39. 1188 + * 1189 + * @IEEE80211_S1G_PRI_CHANWIDTH_2MHZ: 2MHz primary channel 1190 + * @IEEE80211_S1G_PRI_CHANWIDTH_1MHZ: 1MHz primary channel 1191 + */ 1192 + enum ieee80211_s1g_pri_chanwidth { 1193 + IEEE80211_S1G_PRI_CHANWIDTH_2MHZ = 0, 1194 + IEEE80211_S1G_PRI_CHANWIDTH_1MHZ = 1, 1195 + }; 1196 + 1185 1197 #define WLAN_SA_QUERY_TR_ID_LEN 2 1186 1198 #define WLAN_MEMBERSHIP_LEN 8 1187 1199 #define WLAN_USER_POSITION_LEN 16 ··· 3182 3170 3183 3171 #define S1G_CAP9_LINK_ADAPT_PER_CONTROL_RESPONSE BIT(0) 3184 3172 3185 - #define S1G_OPER_CH_WIDTH_PRIMARY_1MHZ BIT(0) 3173 + #define S1G_OPER_CH_WIDTH_PRIMARY BIT(0) 3186 3174 #define S1G_OPER_CH_WIDTH_OPER GENMASK(4, 1) 3175 + #define S1G_OPER_CH_PRIMARY_LOCATION BIT(5) 3176 + 3177 + #define S1G_2M_PRIMARY_LOCATION_LOWER 0 3178 + #define S1G_2M_PRIMARY_LOCATION_UPPER 1 3187 3179 3188 3180 /* EHT MAC capabilities as defined in P802.11be_D2.0 section 9.4.2.313.2 */ 3189 3181 #define IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS 0x01 ··· 6080 6064 for_each_element(_elem, \ 6081 6065 _data + ieee80211_mle_common_size(_data),\ 6082 6066 _len - ieee80211_mle_common_size(_data)) 6067 + 6068 + /* NAN operation mode, as defined in Wi-Fi Aware (TM) specification Table 81 */ 6069 + #define NAN_OP_MODE_PHY_MODE_VHT 0x01 6070 + #define NAN_OP_MODE_PHY_MODE_HE 0x10 6071 + #define NAN_OP_MODE_PHY_MODE_MASK 0x11 6072 + #define NAN_OP_MODE_80P80MHZ 0x02 6073 + #define NAN_OP_MODE_160MHZ 0x04 6074 + #define NAN_OP_MODE_PNDL_SUPPRTED 0x08 6075 + 6076 + /* NAN Device capabilities, as defined in Wi-Fi Aware (TM) specification 6077 + * Table 79 6078 + */ 6079 + #define NAN_DEV_CAPA_DFS_OWNER 0x01 6080 + #define NAN_DEV_CAPA_EXT_KEY_ID_SUPPORTED 0x02 6081 + #define NAN_DEV_CAPA_SIM_NDP_RX_SUPPORTED 0x04 6082 + #define NAN_DEV_CAPA_NDPE_SUPPORTED 0x08 6083 + #define NAN_DEV_CAPA_S3_SUPPORTED 0x10 6083 6084 6084 6085 #endif /* LINUX_IEEE80211_H */

+223 -25

include/net/cfg80211.h

··· 101 101 * @IEEE80211_CHAN_NO_10MHZ: 10 MHz bandwidth is not permitted 102 102 * on this channel. 103 103 * @IEEE80211_CHAN_NO_HE: HE operation is not permitted on this channel. 104 - * @IEEE80211_CHAN_1MHZ: 1 MHz bandwidth is permitted 105 - * on this channel. 106 - * @IEEE80211_CHAN_2MHZ: 2 MHz bandwidth is permitted 107 - * on this channel. 108 - * @IEEE80211_CHAN_4MHZ: 4 MHz bandwidth is permitted 109 - * on this channel. 110 - * @IEEE80211_CHAN_8MHZ: 8 MHz bandwidth is permitted 111 - * on this channel. 112 - * @IEEE80211_CHAN_16MHZ: 16 MHz bandwidth is permitted 113 - * on this channel. 114 104 * @IEEE80211_CHAN_NO_320MHZ: If the driver supports 320 MHz on the band, 115 105 * this flag indicates that a 320 MHz channel cannot use this 116 106 * channel as the control or any of the secondary channels. ··· 119 129 * with very low power (VLP), even if otherwise set to NO_IR. 120 130 * @IEEE80211_CHAN_ALLOW_20MHZ_ACTIVITY: Allow activity on a 20 MHz channel, 121 131 * even if otherwise set to NO_IR. 132 + * @IEEE80211_CHAN_S1G_NO_PRIMARY: Prevents the channel for use as an S1G 133 + * primary channel. Does not prevent the wider operating channel 134 + * described by the chandef from being used. In order for a 2MHz primary 135 + * to be used, both 1MHz subchannels shall not contain this flag. 136 + * @IEEE80211_CHAN_NO_4MHZ: 4 MHz bandwidth is not permitted on this channel. 137 + * @IEEE80211_CHAN_NO_8MHZ: 8 MHz bandwidth is not permitted on this channel. 138 + * @IEEE80211_CHAN_NO_16MHZ: 16 MHz bandwidth is not permitted on this channel. 122 139 */ 123 140 enum ieee80211_channel_flags { 124 141 IEEE80211_CHAN_DISABLED = BIT(0), ··· 142 145 IEEE80211_CHAN_NO_20MHZ = BIT(11), 143 146 IEEE80211_CHAN_NO_10MHZ = BIT(12), 144 147 IEEE80211_CHAN_NO_HE = BIT(13), 145 - IEEE80211_CHAN_1MHZ = BIT(14), 146 - IEEE80211_CHAN_2MHZ = BIT(15), 147 - IEEE80211_CHAN_4MHZ = BIT(16), 148 - IEEE80211_CHAN_8MHZ = BIT(17), 149 - IEEE80211_CHAN_16MHZ = BIT(18), 148 + /* can use free bits here */ 150 149 IEEE80211_CHAN_NO_320MHZ = BIT(19), 151 150 IEEE80211_CHAN_NO_EHT = BIT(20), 152 151 IEEE80211_CHAN_DFS_CONCURRENT = BIT(21), ··· 151 158 IEEE80211_CHAN_CAN_MONITOR = BIT(24), 152 159 IEEE80211_CHAN_ALLOW_6GHZ_VLP_AP = BIT(25), 153 160 IEEE80211_CHAN_ALLOW_20MHZ_ACTIVITY = BIT(26), 161 + IEEE80211_CHAN_S1G_NO_PRIMARY = BIT(27), 162 + IEEE80211_CHAN_NO_4MHZ = BIT(28), 163 + IEEE80211_CHAN_NO_8MHZ = BIT(29), 164 + IEEE80211_CHAN_NO_16MHZ = BIT(30), 154 165 }; 155 166 156 167 #define IEEE80211_CHAN_NO_HT40 \ ··· 818 821 * @punctured: mask of the punctured 20 MHz subchannels, with 819 822 * bits turned on being disabled (punctured); numbered 820 823 * from lower to higher frequency (like in the spec) 824 + * @s1g_primary_2mhz: Indicates if the control channel pointed to 825 + * by 'chan' exists as a 1MHz primary subchannel within an 826 + * S1G 2MHz primary channel. 821 827 */ 822 828 struct cfg80211_chan_def { 823 829 struct ieee80211_channel *chan; ··· 830 830 struct ieee80211_edmg edmg; 831 831 u16 freq1_offset; 832 832 u16 punctured; 833 + bool s1g_primary_2mhz; 833 834 }; 834 835 835 836 /* ··· 989 988 cfg80211_chandef_is_edmg(const struct cfg80211_chan_def *chandef) 990 989 { 991 990 return chandef->edmg.channels || chandef->edmg.bw_config; 991 + } 992 + 993 + /** 994 + * cfg80211_chandef_is_s1g - check if chandef represents an S1G channel 995 + * @chandef: the channel definition 996 + * 997 + * Return: %true if S1G. 998 + */ 999 + static inline bool 1000 + cfg80211_chandef_is_s1g(const struct cfg80211_chan_def *chandef) 1001 + { 1002 + return chandef->chan->band == NL80211_BAND_S1GHZ; 992 1003 } 993 1004 994 1005 /** ··· 3926 3913 }; 3927 3914 3928 3915 /** 3916 + * struct cfg80211_nan_band_config - NAN band specific configuration 3917 + * 3918 + * @chan: Pointer to the IEEE 802.11 channel structure. The channel to be used 3919 + * for NAN operations on this band. For 2.4 GHz band, this is always 3920 + * channel 6. For 5 GHz band, the channel is either 44 or 149, according 3921 + * to the regulatory constraints. If chan pointer is NULL the entire band 3922 + * configuration entry is considered invalid and should not be used. 3923 + * @rssi_close: RSSI close threshold used for NAN state transition algorithm 3924 + * as described in chapters 3.3.6 and 3.3.7 "NAN Device Role and State 3925 + * Transition" of Wi-Fi Aware Specification v4.0. If not 3926 + * specified (set to 0), default device value is used. The value should 3927 + * be greater than -60 dBm. 3928 + * @rssi_middle: RSSI middle threshold used for NAN state transition algorithm. 3929 + * as described in chapters 3.3.6 and 3.3.7 "NAN Device Role and State 3930 + * Transition" of Wi-Fi Aware Specification v4.0. If not 3931 + * specified (set to 0), default device value is used. The value should be 3932 + * greater than -75 dBm and less than rssi_close. 3933 + * @awake_dw_interval: Committed DW interval. Valid values range: 0-5. 0 3934 + * indicates no wakeup for DW and can't be used on 2.4GHz band, otherwise 3935 + * 2^(n-1). 3936 + * @disable_scan: If true, the device will not scan this band for cluster 3937 + * merge. Disabling scan on 2.4 GHz band is not allowed. 3938 + */ 3939 + struct cfg80211_nan_band_config { 3940 + struct ieee80211_channel *chan; 3941 + s8 rssi_close; 3942 + s8 rssi_middle; 3943 + u8 awake_dw_interval; 3944 + bool disable_scan; 3945 + }; 3946 + 3947 + /** 3929 3948 * struct cfg80211_nan_conf - NAN configuration 3930 3949 * 3931 3950 * This struct defines NAN configuration parameters ··· 3966 3921 * @bands: operating bands, a bitmap of &enum nl80211_band values. 3967 3922 * For instance, for NL80211_BAND_2GHZ, bit 0 would be set 3968 3923 * (i.e. BIT(NL80211_BAND_2GHZ)). 3924 + * @cluster_id: cluster ID used for NAN synchronization. This is a MAC address 3925 + * that can take a value from 50-6F-9A-01-00-00 to 50-6F-9A-01-FF-FF. 3926 + * If NULL, the device will pick a random Cluster ID. 3927 + * @scan_period: period (in seconds) between NAN scans. 3928 + * @scan_dwell_time: dwell time (in milliseconds) for NAN scans. 3929 + * @discovery_beacon_interval: interval (in TUs) for discovery beacons. 3930 + * @enable_dw_notification: flag to enable/disable discovery window 3931 + * notifications. 3932 + * @band_cfgs: array of band specific configurations, indexed by 3933 + * &enum nl80211_band values. 3934 + * @extra_nan_attrs: pointer to additional NAN attributes. 3935 + * @extra_nan_attrs_len: length of the additional NAN attributes. 3936 + * @vendor_elems: pointer to vendor-specific elements. 3937 + * @vendor_elems_len: length of the vendor-specific elements. 3969 3938 */ 3970 3939 struct cfg80211_nan_conf { 3971 3940 u8 master_pref; 3972 3941 u8 bands; 3942 + const u8 *cluster_id; 3943 + u16 scan_period; 3944 + u16 scan_dwell_time; 3945 + u8 discovery_beacon_interval; 3946 + bool enable_dw_notification; 3947 + struct cfg80211_nan_band_config band_cfgs[NUM_NL80211_BANDS]; 3948 + const u8 *extra_nan_attrs; 3949 + u16 extra_nan_attrs_len; 3950 + const u8 *vendor_elems; 3951 + u16 vendor_elems_len; 3973 3952 }; 3974 3953 3975 3954 /** ··· 4002 3933 * 4003 3934 * @CFG80211_NAN_CONF_CHANGED_PREF: master preference 4004 3935 * @CFG80211_NAN_CONF_CHANGED_BANDS: operating bands 3936 + * @CFG80211_NAN_CONF_CHANGED_CONFIG: changed additional configuration. 3937 + * When this flag is set, it indicates that some additional attribute(s) 3938 + * (other then master_pref and bands) have been changed. In this case, 3939 + * all the unchanged attributes will be properly configured to their 3940 + * previous values. The driver doesn't need to store any 3941 + * previous configuration besides master_pref and bands. 4005 3942 */ 4006 3943 enum cfg80211_nan_conf_changes { 4007 3944 CFG80211_NAN_CONF_CHANGED_PREF = BIT(0), 4008 3945 CFG80211_NAN_CONF_CHANGED_BANDS = BIT(1), 3946 + CFG80211_NAN_CONF_CHANGED_CONFIG = BIT(2), 4009 3947 }; 4010 3948 4011 3949 /** ··· 5724 5648 u32 antenna_mask; 5725 5649 }; 5726 5650 5651 + /** 5652 + * enum wiphy_nan_flags - NAN capabilities 5653 + * 5654 + * @WIPHY_NAN_FLAGS_CONFIGURABLE_SYNC: Device supports NAN configurable 5655 + * synchronization. 5656 + * @WIPHY_NAN_FLAGS_USERSPACE_DE: Device doesn't support DE offload. 5657 + */ 5658 + enum wiphy_nan_flags { 5659 + WIPHY_NAN_FLAGS_CONFIGURABLE_SYNC = BIT(0), 5660 + WIPHY_NAN_FLAGS_USERSPACE_DE = BIT(1), 5661 + }; 5662 + 5663 + /** 5664 + * struct wiphy_nan_capa - NAN capabilities 5665 + * 5666 + * This structure describes the NAN capabilities of a wiphy. 5667 + * 5668 + * @flags: NAN capabilities flags, see &enum wiphy_nan_flags 5669 + * @op_mode: NAN operation mode, as defined in Wi-Fi Aware (TM) specification 5670 + * Table 81. 5671 + * @n_antennas: number of antennas supported by the device for Tx/Rx. Lower 5672 + * nibble indicates the number of TX antennas and upper nibble indicates the 5673 + * number of RX antennas. Value 0 indicates the information is not 5674 + * available. 5675 + * @max_channel_switch_time: maximum channel switch time in milliseconds. 5676 + * @dev_capabilities: NAN device capabilities as defined in Wi-Fi Aware (TM) 5677 + * specification Table 79 (Capabilities field). 5678 + */ 5679 + struct wiphy_nan_capa { 5680 + u32 flags; 5681 + u8 op_mode; 5682 + u8 n_antennas; 5683 + u16 max_channel_switch_time; 5684 + u8 dev_capabilities; 5685 + }; 5686 + 5727 5687 #define CFG80211_HW_TIMESTAMP_ALL_PEERS 0xffff 5728 5688 5729 5689 /** ··· 5933 5821 * bitmap of &enum nl80211_band values. For instance, for 5934 5822 * NL80211_BAND_2GHZ, bit 0 would be set 5935 5823 * (i.e. BIT(NL80211_BAND_2GHZ)). 5824 + * @nan_capa: NAN capabilities 5936 5825 * 5937 5826 * @txq_limit: configuration of internal TX queue frame limit 5938 5827 * @txq_memory_limit: configuration internal TX queue memory limit ··· 6115 6002 u32 bss_select_support; 6116 6003 6117 6004 u8 nan_supported_bands; 6005 + struct wiphy_nan_capa nan_capa; 6118 6006 6119 6007 u32 txq_limit; 6120 6008 u32 txq_memory_limit; ··· 6694 6580 struct { 6695 6581 struct cfg80211_chan_def chandef; 6696 6582 } ocb; 6583 + struct { 6584 + u8 cluster_id[ETH_ALEN] __aligned(2); 6585 + } nan; 6697 6586 } u; 6698 6587 6699 6588 struct { ··· 6803 6686 { 6804 6687 return MHZ_TO_KHZ(chan->center_freq) + chan->freq_offset; 6805 6688 } 6806 - 6807 - /** 6808 - * ieee80211_s1g_channel_width - get allowed channel width from @chan 6809 - * 6810 - * Only allowed for band NL80211_BAND_S1GHZ 6811 - * @chan: channel 6812 - * Return: The allowed channel width for this center_freq 6813 - */ 6814 - enum nl80211_chan_width 6815 - ieee80211_s1g_channel_width(const struct ieee80211_channel *chan); 6816 6689 6817 6690 /** 6818 6691 * ieee80211_channel_to_freq_khz - convert channel number to frequency ··· 10109 10002 */ 10110 10003 void cfg80211_epcs_changed(struct net_device *netdev, bool enabled); 10111 10004 10005 + /** 10006 + * cfg80211_next_nan_dw_notif - Notify about the next NAN Discovery Window (DW) 10007 + * @wdev: Pointer to the wireless device structure 10008 + * @chan: DW channel (6, 44 or 149) 10009 + * @gfp: Memory allocation flags 10010 + */ 10011 + void cfg80211_next_nan_dw_notif(struct wireless_dev *wdev, 10012 + struct ieee80211_channel *chan, gfp_t gfp); 10013 + 10014 + /** 10015 + * cfg80211_nan_cluster_joined - Notify about NAN cluster join 10016 + * @wdev: Pointer to the wireless device structure 10017 + * @cluster_id: Cluster ID of the NAN cluster that was joined or started 10018 + * @new_cluster: Indicates if this is a new cluster or an existing one 10019 + * @gfp: Memory allocation flags 10020 + * 10021 + * This function is used to notify user space when a NAN cluster has been 10022 + * joined, providing the cluster ID and a flag whether it is a new cluster. 10023 + */ 10024 + void cfg80211_nan_cluster_joined(struct wireless_dev *wdev, 10025 + const u8 *cluster_id, bool new_cluster, 10026 + gfp_t gfp); 10027 + 10112 10028 #ifdef CONFIG_CFG80211_DEBUGFS 10113 10029 /** 10114 10030 * wiphy_locked_debugfs_read - do a locked read in debugfs ··· 10181 10051 void *data), 10182 10052 void *data); 10183 10053 #endif 10054 + 10055 + /** 10056 + * cfg80211_s1g_get_start_freq_khz - get S1G chandef start frequency 10057 + * @chandef: the chandef to use 10058 + * 10059 + * Return: the chandefs starting frequency in KHz 10060 + */ 10061 + static inline u32 10062 + cfg80211_s1g_get_start_freq_khz(const struct cfg80211_chan_def *chandef) 10063 + { 10064 + u32 bw_mhz = cfg80211_chandef_get_width(chandef); 10065 + u32 center_khz = 10066 + MHZ_TO_KHZ(chandef->center_freq1) + chandef->freq1_offset; 10067 + return center_khz - bw_mhz * 500 + 500; 10068 + } 10069 + 10070 + /** 10071 + * cfg80211_s1g_get_end_freq_khz - get S1G chandef end frequency 10072 + * @chandef: the chandef to use 10073 + * 10074 + * Return: the chandefs ending frequency in KHz 10075 + */ 10076 + static inline u32 10077 + cfg80211_s1g_get_end_freq_khz(const struct cfg80211_chan_def *chandef) 10078 + { 10079 + u32 bw_mhz = cfg80211_chandef_get_width(chandef); 10080 + u32 center_khz = 10081 + MHZ_TO_KHZ(chandef->center_freq1) + chandef->freq1_offset; 10082 + return center_khz + bw_mhz * 500 - 500; 10083 + } 10084 + 10085 + /** 10086 + * cfg80211_s1g_get_primary_sibling - retrieve the sibling 1MHz subchannel 10087 + * for an S1G chandef using a 2MHz primary channel. 10088 + * @wiphy: wiphy the channel belongs to 10089 + * @chandef: the chandef to use 10090 + * 10091 + * When chandef::s1g_primary_2mhz is set to true, we are operating on a 2MHz 10092 + * primary channel. The 1MHz subchannel designated by the primary channel 10093 + * location exists within chandef::chan, whilst the 'sibling' is denoted as 10094 + * being the other 1MHz subchannel that make up the 2MHz primary channel. 10095 + * 10096 + * Returns: the sibling 1MHz &struct ieee80211_channel, or %NULL on failure. 10097 + */ 10098 + static inline struct ieee80211_channel * 10099 + cfg80211_s1g_get_primary_sibling(struct wiphy *wiphy, 10100 + const struct cfg80211_chan_def *chandef) 10101 + { 10102 + int width_mhz = cfg80211_chandef_get_width(chandef); 10103 + u32 pri_1mhz_khz, sibling_1mhz_khz, op_low_1mhz_khz, pri_index; 10104 + 10105 + if (!chandef->s1g_primary_2mhz || width_mhz < 2) 10106 + return NULL; 10107 + 10108 + pri_1mhz_khz = ieee80211_channel_to_khz(chandef->chan); 10109 + op_low_1mhz_khz = cfg80211_s1g_get_start_freq_khz(chandef); 10110 + 10111 + /* 10112 + * Compute the index of the primary 1 MHz subchannel within the 10113 + * operating channel, relative to the lowest 1 MHz center frequency. 10114 + * Flip the least significant bit to select the even/odd sibling, 10115 + * then translate that index back into a channel frequency. 10116 + */ 10117 + pri_index = (pri_1mhz_khz - op_low_1mhz_khz) / 1000; 10118 + sibling_1mhz_khz = op_low_1mhz_khz + ((pri_index ^ 1) * 1000); 10119 + 10120 + return ieee80211_get_channel_khz(wiphy, sibling_1mhz_khz); 10121 + } 10184 10122 10185 10123 #endif /* __NET_CFG80211_H */

+10

include/net/mac80211.h

··· 3192 3192 { 3193 3193 if (WARN_ON_ONCE(c->control.rates[0].idx < 0)) 3194 3194 return NULL; 3195 + 3196 + if (c->band >= NUM_NL80211_BANDS) 3197 + return NULL; 3198 + 3195 3199 return &hw->wiphy->bands[c->band]->bitrates[c->control.rates[0].idx]; 3196 3200 } 3197 3201 ··· 7838 7834 int n_vifs, 7839 7835 enum ieee80211_chanctx_switch_mode mode); 7840 7836 7837 + /** 7838 + * ieee80211_vif_nan_started - Return whether a NAN vif is started 7839 + * @vif: the vif 7840 + * Return: %true iff the vif is a NAN interface and NAN is started 7841 + */ 7842 + bool ieee80211_vif_nan_started(struct ieee80211_vif *vif); 7841 7843 #endif /* MAC80211_H */

+202 -2

include/uapi/linux/nl80211.h

··· 1085 1085 * %NL80211_ATTR_NAN_MASTER_PREF attribute and optional 1086 1086 * %NL80211_ATTR_BANDS attributes. If %NL80211_ATTR_BANDS is 1087 1087 * omitted or set to 0, it means don't-care and the device will 1088 - * decide what to use. After this command NAN functions can be 1089 - * added. 1088 + * decide what to use. Additional cluster configuration may be 1089 + * optionally provided with %NL80211_ATTR_NAN_CONFIG. 1090 + * After this command NAN functions can be added. 1090 1091 * @NL80211_CMD_STOP_NAN: Stop the NAN operation, identified by 1091 1092 * its %NL80211_ATTR_WDEV interface. 1092 1093 * @NL80211_CMD_ADD_NAN_FUNCTION: Add a NAN function. The function is defined ··· 1116 1115 * current configuration is not changed. If it is present but 1117 1116 * set to zero, the configuration is changed to don't-care 1118 1117 * (i.e. the device can decide what to do). 1118 + * Additional parameters may be provided with 1119 + * %NL80211_ATTR_NAN_CONFIG. User space should provide all previously 1120 + * configured nested attributes under %NL80211_ATTR_NAN_CONFIG, even if 1121 + * only a subset was changed. 1119 1122 * @NL80211_CMD_NAN_MATCH: Notification sent when a match is reported. 1120 1123 * This will contain a %NL80211_ATTR_NAN_MATCH nested attribute and 1121 1124 * %NL80211_ATTR_COOKIE. ··· 1348 1343 * @NL80211_CMD_EPCS_CFG: EPCS configuration for a station. Used by userland to 1349 1344 * control EPCS configuration. Used to notify userland on the current state 1350 1345 * of EPCS. 1346 + * 1347 + * @NL80211_CMD_NAN_NEXT_DW_NOTIFICATION: This command is used to notify 1348 + * user space about the next NAN Discovery Window (DW). User space may use 1349 + * it to prepare frames to be sent in the next DW. 1350 + * %NL80211_ATTR_WIPHY_FREQ is used to indicate the frequency of the next 1351 + * DW. SDF transmission should be requested with %NL80211_CMD_FRAME and 1352 + * the device/driver shall take care of the actual transmission timing. 1353 + * This notification is only sent to the NAN interface owning socket 1354 + * (see %NL80211_ATTR_SOCKET_OWNER flag). 1355 + * @NL80211_CMD_NAN_CLUSTER_JOINED: This command is used to notify 1356 + * user space that the NAN new cluster has been joined. The cluster ID is 1357 + * indicated by %NL80211_ATTR_MAC. 1351 1358 * 1352 1359 * @NL80211_CMD_MAX: highest used command number 1353 1360 * @__NL80211_CMD_AFTER_LAST: internal use ··· 1620 1603 1621 1604 NL80211_CMD_ASSOC_MLO_RECONF, 1622 1605 NL80211_CMD_EPCS_CFG, 1606 + 1607 + NL80211_CMD_NAN_NEXT_DW_NOTIFICATION, 1608 + NL80211_CMD_NAN_CLUSTER_JOINED, 1623 1609 1624 1610 /* add new commands above here */ 1625 1611 ··· 2956 2936 * indicate that it wants strict checking on the BSS parameters to be 2957 2937 * modified. 2958 2938 * 2939 + * @NL80211_ATTR_NAN_CONFIG: Nested attribute for 2940 + * extended NAN cluster configuration. This is used with 2941 + * %NL80211_CMD_START_NAN and %NL80211_CMD_CHANGE_NAN_CONFIG. 2942 + * See &enum nl80211_nan_conf_attributes for details. 2943 + * This attribute is optional. 2944 + * @NL80211_ATTR_NAN_NEW_CLUSTER: Flag attribute indicating that a new 2945 + * NAN cluster has been created. This is used with 2946 + * %NL80211_CMD_NAN_CLUSTER_JOINED 2947 + * @NL80211_ATTR_NAN_CAPABILITIES: Nested attribute for NAN capabilities. 2948 + * This is used with %NL80211_CMD_GET_WIPHY to indicate the NAN 2949 + * capabilities supported by the driver. See &enum nl80211_nan_capabilities 2950 + * for details. 2951 + * 2952 + * @NL80211_ATTR_S1G_PRIMARY_2MHZ: flag attribute indicating that the S1G 2953 + * primary channel is 2 MHz wide, and the control channel designates 2954 + * the 1 MHz primary subchannel within that 2 MHz primary. 2955 + * 2959 2956 * @NUM_NL80211_ATTR: total number of nl80211_attrs available 2960 2957 * @NL80211_ATTR_MAX: highest attribute number currently defined 2961 2958 * @__NL80211_ATTR_AFTER_LAST: internal use ··· 3535 3498 NL80211_ATTR_S1G_LONG_BEACON_PERIOD, 3536 3499 NL80211_ATTR_S1G_SHORT_BEACON, 3537 3500 NL80211_ATTR_BSS_PARAM, 3501 + NL80211_ATTR_NAN_CONFIG, 3502 + NL80211_ATTR_NAN_NEW_CLUSTER, 3503 + NL80211_ATTR_NAN_CAPABILITIES, 3504 + 3505 + NL80211_ATTR_S1G_PRIMARY_2MHZ, 3538 3506 3539 3507 /* add attributes here, update the policy in nl80211.c */ 3540 3508 ··· 4438 4396 * very low power (VLP) AP, despite being NO_IR. 4439 4397 * @NL80211_FREQUENCY_ATTR_ALLOW_20MHZ_ACTIVITY: This channel can be active in 4440 4398 * 20 MHz bandwidth, despite being NO_IR. 4399 + * @NL80211_FREQUENCY_ATTR_NO_4MHZ: 4 MHz operation is not allowed on this 4400 + * channel in current regulatory domain. 4401 + * @NL80211_FREQUENCY_ATTR_NO_8MHZ: 8 MHz operation is not allowed on this 4402 + * channel in current regulatory domain. 4403 + * @NL80211_FREQUENCY_ATTR_NO_16MHZ: 16 MHz operation is not allowed on this 4404 + * channel in current regulatory domain. 4441 4405 * @NL80211_FREQUENCY_ATTR_MAX: highest frequency attribute number 4442 4406 * currently defined 4443 4407 * @__NL80211_FREQUENCY_ATTR_AFTER_LAST: internal use ··· 4489 4441 NL80211_FREQUENCY_ATTR_CAN_MONITOR, 4490 4442 NL80211_FREQUENCY_ATTR_ALLOW_6GHZ_VLP_AP, 4491 4443 NL80211_FREQUENCY_ATTR_ALLOW_20MHZ_ACTIVITY, 4444 + NL80211_FREQUENCY_ATTR_NO_4MHZ, 4445 + NL80211_FREQUENCY_ATTR_NO_8MHZ, 4446 + NL80211_FREQUENCY_ATTR_NO_16MHZ, 4492 4447 4493 4448 /* keep last */ 4494 4449 __NL80211_FREQUENCY_ATTR_AFTER_LAST, ··· 7375 7324 }; 7376 7325 7377 7326 /** 7327 + * enum nl80211_nan_band_conf_attributes - NAN band configuration attributes 7328 + * @__NL80211_NAN_BAND_CONF_INVALID: Invalid. 7329 + * @NL80211_NAN_BAND_CONF_BAND: Band for which the configuration is 7330 + * being set. The value is according to &enum nl80211_band (u8). 7331 + * @NL80211_NAN_BAND_CONF_FREQ: Discovery frequency. This attribute shall not 7332 + * be present on 2.4 GHZ band. On 5 GHz band its presence is optional. 7333 + * The allowed values are 5220 (channel 44) or 5745 (channel 149). 7334 + * If not present, channel 149 is used if allowed, otherwise channel 44 7335 + * will be selected. The value is in MHz (u16). 7336 + * @NL80211_NAN_BAND_CONF_RSSI_CLOSE: RSSI close threshold used for NAN state 7337 + * transition algorithm as described in chapters 3.3.6 and 3.3.7 "NAN 7338 + * Device Role and State Transition" of Wi-Fi Aware (TM) Specification 7339 + * v4.0. If not specified, default device value is used. The value should 7340 + * be greater than -60 dBm (s8). 7341 + * @NL80211_NAN_BAND_CONF_RSSI_MIDDLE: RSSI middle threshold used for NAN state 7342 + * transition algorithm as described in chapters 3.3.6 and 3.3.7 "NAN 7343 + * Device Role and State Transition" of Wi-Fi Aware (TM) Specification 7344 + * v4.0. If not present, default device value is used. The value should be 7345 + * greater than -75 dBm and less than %NL80211_NAN_BAND_CONF_RSSI_CLOSE 7346 + * (s8). 7347 + * @NL80211_NAN_BAND_CONF_WAKE_DW: Committed DW information (values 0-5). 7348 + * Value 0 means that the device will not wake up during the 7349 + * discovery window. Values 1-5 mean that the device will wake up 7350 + * during each 2^(n - 1) discovery window, where n is the value of 7351 + * this attribute. Setting this attribute to 0 is not allowed on 7352 + * 2.4 GHz band (u8). This is an optional parameter (default is 1). 7353 + * @NL80211_NAN_BAND_CONF_DISABLE_SCAN: Optional flag attribute to disable 7354 + * scanning (for cluster merge) on the band. If set, the device will not 7355 + * scan on this band anymore. Disabling scanning on 2.4 GHz band is not 7356 + * allowed. 7357 + * @NUM_NL80211_NAN_BAND_CONF_ATTR: Internal. 7358 + * @NL80211_NAN_BAND_CONF_ATTR_MAX: Highest NAN band configuration attribute. 7359 + * 7360 + * These attributes are used to configure NAN band-specific parameters. Note, 7361 + * that both RSSI attributes should be configured (or both left unset). 7362 + */ 7363 + enum nl80211_nan_band_conf_attributes { 7364 + __NL80211_NAN_BAND_CONF_INVALID, 7365 + NL80211_NAN_BAND_CONF_BAND, 7366 + NL80211_NAN_BAND_CONF_FREQ, 7367 + NL80211_NAN_BAND_CONF_RSSI_CLOSE, 7368 + NL80211_NAN_BAND_CONF_RSSI_MIDDLE, 7369 + NL80211_NAN_BAND_CONF_WAKE_DW, 7370 + NL80211_NAN_BAND_CONF_DISABLE_SCAN, 7371 + 7372 + /* keep last */ 7373 + NUM_NL80211_NAN_BAND_CONF_ATTR, 7374 + NL80211_NAN_BAND_CONF_ATTR_MAX = NUM_NL80211_NAN_BAND_CONF_ATTR - 1, 7375 + }; 7376 + 7377 + /** 7378 + * enum nl80211_nan_conf_attributes - NAN configuration attributes 7379 + * @__NL80211_NAN_CONF_INVALID: Invalid attribute, used for validation. 7380 + * @NL80211_NAN_CONF_CLUSTER_ID: ID for the NAN cluster. This is a MAC 7381 + * address that can take values from 50-6F-9A-01-00-00 to 7382 + * 50-6F-9A-01-FF-FF. This attribute is optional. If not present, 7383 + * a random Cluster ID will be chosen. 7384 + * @NL80211_NAN_CONF_EXTRA_ATTRS: Additional NAN attributes to be 7385 + * published in the beacons. This is an optional byte array. 7386 + * @NL80211_NAN_CONF_VENDOR_ELEMS: Vendor-specific elements that will 7387 + * be published in the beacons. This is an optional byte array. 7388 + * @NL80211_NAN_CONF_BAND_CONFIGS: This is a nested array attribute, 7389 + * containing multiple entries for each supported band. Each band 7390 + * configuration consists of &enum nl80211_nan_band_conf_attributes. 7391 + * @NL80211_NAN_CONF_SCAN_PERIOD: Scan period in seconds. If not configured, 7392 + * device default is used. Zero value will disable scanning. 7393 + * This is u16 (optional). 7394 + * @NL80211_NAN_CONF_SCAN_DWELL_TIME: Scan dwell time in TUs per channel. 7395 + * Only non-zero values are valid. If not configured the device default 7396 + * value is used. This is u16 (optional) 7397 + * @NL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL: Discovery beacon interval 7398 + * in TUs. Valid range is 50-200 TUs. If not configured the device default 7399 + * value is used. This is u8 (optional) 7400 + * @NL80211_NAN_CONF_NOTIFY_DW: If set, the driver will notify userspace about 7401 + * the upcoming discovery window with 7402 + * %NL80211_CMD_NAN_NEXT_DW_NOTIFICATION. 7403 + * This is a flag attribute. 7404 + * @NUM_NL80211_NAN_CONF_ATTR: Internal. 7405 + * @NL80211_NAN_CONF_ATTR_MAX: Highest NAN configuration attribute. 7406 + * 7407 + * These attributes are used to configure NAN-specific parameters. 7408 + */ 7409 + enum nl80211_nan_conf_attributes { 7410 + __NL80211_NAN_CONF_INVALID, 7411 + NL80211_NAN_CONF_CLUSTER_ID, 7412 + NL80211_NAN_CONF_EXTRA_ATTRS, 7413 + NL80211_NAN_CONF_VENDOR_ELEMS, 7414 + NL80211_NAN_CONF_BAND_CONFIGS, 7415 + NL80211_NAN_CONF_SCAN_PERIOD, 7416 + NL80211_NAN_CONF_SCAN_DWELL_TIME, 7417 + NL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL, 7418 + NL80211_NAN_CONF_NOTIFY_DW, 7419 + 7420 + /* keep last */ 7421 + NUM_NL80211_NAN_CONF_ATTR, 7422 + NL80211_NAN_CONF_ATTR_MAX = NUM_NL80211_NAN_CONF_ATTR - 1, 7423 + }; 7424 + 7425 + /** 7378 7426 * enum nl80211_external_auth_action - Action to perform with external 7379 7427 * authentication request. Used by NL80211_ATTR_EXTERNAL_AUTH_ACTION. 7380 7428 * @NL80211_EXTERNAL_AUTH_START: Start the authentication. ··· 8380 8230 __NL80211_S1G_SHORT_BEACON_ATTR_LAST, 8381 8231 NL80211_S1G_SHORT_BEACON_ATTR_MAX = 8382 8232 __NL80211_S1G_SHORT_BEACON_ATTR_LAST - 1 8233 + }; 8234 + 8235 + /** 8236 + * enum nl80211_nan_capabilities - NAN (Neighbor Aware Networking) 8237 + * capabilities. 8238 + * 8239 + * @__NL80211_NAN_CAPABILITIES_INVALID: Invalid. 8240 + * @NL80211_NAN_CAPA_CONFIGURABLE_SYNC: Flag attribute indicating that 8241 + * the device supports configurable synchronization. If set, the device 8242 + * should be able to handle %NL80211_ATTR_NAN_CONFIG 8243 + * attribute in the %NL80211_CMD_START_NAN (and change) command. 8244 + * @NL80211_NAN_CAPA_USERSPACE_DE: Flag attribute indicating that 8245 + * NAN Discovery Engine (DE) is not offloaded and the driver assumes 8246 + * user space DE implementation. When set, %NL80211_CMD_ADD_NAN_FUNCTION, 8247 + * %NL80211_CMD_DEL_NAN_FUNCTION and %NL80211_CMD_NAN_MATCH commands 8248 + * should not be used. In addition, the device/driver should support 8249 + * sending discovery window (DW) notifications using 8250 + * %NL80211_CMD_NAN_NEXT_DW_NOTIFICATION and handling transmission and 8251 + * reception of NAN SDF frames on NAN device interface during DW windows. 8252 + * (%NL80211_CMD_FRAME is used to transmit SDFs) 8253 + * @NL80211_NAN_CAPA_OP_MODE: u8 attribute indicating the supported operation 8254 + * modes as defined in Wi-Fi Aware (TM) specification Table 81 (Operation 8255 + * Mode field format). 8256 + * @NL80211_NAN_CAPA_NUM_ANTENNAS: u8 attribute indicating the number of 8257 + * TX and RX antennas supported by the device. Lower nibble indicates 8258 + * the number of TX antennas and upper nibble indicates the number of RX 8259 + * antennas. Value 0 indicates the information is not available. 8260 + * See table 79 of Wi-Fi Aware (TM) specification (Number of 8261 + * Antennas field). 8262 + * @NL80211_NAN_CAPA_MAX_CHANNEL_SWITCH_TIME: u16 attribute indicating the 8263 + * maximum time in microseconds that the device requires to switch 8264 + * channels. 8265 + * @NL80211_NAN_CAPA_CAPABILITIES: u8 attribute containing the 8266 + * capabilities of the device as defined in Wi-Fi Aware (TM) 8267 + * specification Table 79 (Capabilities field). 8268 + * @__NL80211_NAN_CAPABILITIES_LAST: Internal 8269 + * @NL80211_NAN_CAPABILITIES_MAX: Highest NAN capability attribute. 8270 + */ 8271 + enum nl80211_nan_capabilities { 8272 + __NL80211_NAN_CAPABILITIES_INVALID, 8273 + 8274 + NL80211_NAN_CAPA_CONFIGURABLE_SYNC, 8275 + NL80211_NAN_CAPA_USERSPACE_DE, 8276 + NL80211_NAN_CAPA_OP_MODE, 8277 + NL80211_NAN_CAPA_NUM_ANTENNAS, 8278 + NL80211_NAN_CAPA_MAX_CHANNEL_SWITCH_TIME, 8279 + NL80211_NAN_CAPA_CAPABILITIES, 8280 + /* keep last */ 8281 + __NL80211_NAN_CAPABILITIES_LAST, 8282 + NL80211_NAN_CAPABILITIES_MAX = __NL80211_NAN_CAPABILITIES_LAST - 1, 8383 8283 }; 8384 8284 8385 8285 #endif /* __LINUX_NL80211_H */

+122 -20

net/mac80211/cfg.c

··· 311 311 ieee80211_sdata_stop(IEEE80211_WDEV_TO_SUB_IF(wdev)); 312 312 } 313 313 314 + static void ieee80211_nan_conf_free(struct cfg80211_nan_conf *conf) 315 + { 316 + kfree(conf->cluster_id); 317 + kfree(conf->extra_nan_attrs); 318 + kfree(conf->vendor_elems); 319 + memset(conf, 0, sizeof(*conf)); 320 + } 321 + 322 + static void ieee80211_stop_nan(struct wiphy *wiphy, 323 + struct wireless_dev *wdev) 324 + { 325 + struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); 326 + 327 + if (!sdata->u.nan.started) 328 + return; 329 + 330 + drv_stop_nan(sdata->local, sdata); 331 + sdata->u.nan.started = false; 332 + 333 + ieee80211_nan_conf_free(&sdata->u.nan.conf); 334 + 335 + ieee80211_sdata_stop(sdata); 336 + ieee80211_recalc_idle(sdata->local); 337 + } 338 + 339 + static int ieee80211_nan_conf_copy(struct cfg80211_nan_conf *dst, 340 + struct cfg80211_nan_conf *src, 341 + u32 changes) 342 + { 343 + if (changes & CFG80211_NAN_CONF_CHANGED_PREF) 344 + dst->master_pref = src->master_pref; 345 + 346 + if (changes & CFG80211_NAN_CONF_CHANGED_BANDS) 347 + dst->bands = src->bands; 348 + 349 + if (changes & CFG80211_NAN_CONF_CHANGED_CONFIG) { 350 + dst->scan_period = src->scan_period; 351 + dst->scan_dwell_time = src->scan_dwell_time; 352 + dst->discovery_beacon_interval = 353 + src->discovery_beacon_interval; 354 + dst->enable_dw_notification = src->enable_dw_notification; 355 + memcpy(&dst->band_cfgs, &src->band_cfgs, 356 + sizeof(dst->band_cfgs)); 357 + 358 + kfree(dst->cluster_id); 359 + dst->cluster_id = NULL; 360 + 361 + kfree(dst->extra_nan_attrs); 362 + dst->extra_nan_attrs = NULL; 363 + dst->extra_nan_attrs_len = 0; 364 + 365 + kfree(dst->vendor_elems); 366 + dst->vendor_elems = NULL; 367 + dst->vendor_elems_len = 0; 368 + 369 + if (src->cluster_id) { 370 + dst->cluster_id = kmemdup(src->cluster_id, ETH_ALEN, 371 + GFP_KERNEL); 372 + if (!dst->cluster_id) 373 + goto no_mem; 374 + } 375 + 376 + if (src->extra_nan_attrs && src->extra_nan_attrs_len) { 377 + dst->extra_nan_attrs = kmemdup(src->extra_nan_attrs, 378 + src->extra_nan_attrs_len, 379 + GFP_KERNEL); 380 + if (!dst->extra_nan_attrs) 381 + goto no_mem; 382 + 383 + dst->extra_nan_attrs_len = src->extra_nan_attrs_len; 384 + } 385 + 386 + if (src->vendor_elems && src->vendor_elems_len) { 387 + dst->vendor_elems = kmemdup(src->vendor_elems, 388 + src->vendor_elems_len, 389 + GFP_KERNEL); 390 + if (!dst->vendor_elems) 391 + goto no_mem; 392 + 393 + dst->vendor_elems_len = src->vendor_elems_len; 394 + } 395 + } 396 + 397 + return 0; 398 + 399 + no_mem: 400 + ieee80211_nan_conf_free(dst); 401 + return -ENOMEM; 402 + } 403 + 314 404 static int ieee80211_start_nan(struct wiphy *wiphy, 315 405 struct wireless_dev *wdev, 316 406 struct cfg80211_nan_conf *conf) ··· 409 319 int ret; 410 320 411 321 lockdep_assert_wiphy(sdata->local->hw.wiphy); 322 + 323 + if (sdata->u.nan.started) 324 + return -EALREADY; 412 325 413 326 ret = ieee80211_check_combinations(sdata, NULL, 0, 0, -1); 414 327 if (ret < 0) ··· 422 329 return ret; 423 330 424 331 ret = drv_start_nan(sdata->local, sdata, conf); 425 - if (ret) 332 + if (ret) { 426 333 ieee80211_sdata_stop(sdata); 334 + return ret; 335 + } 427 336 428 - sdata->u.nan.conf = *conf; 337 + sdata->u.nan.started = true; 338 + ieee80211_recalc_idle(sdata->local); 429 339 430 - return ret; 431 - } 340 + ret = ieee80211_nan_conf_copy(&sdata->u.nan.conf, conf, 0xFFFFFFFF); 341 + if (ret) { 342 + ieee80211_stop_nan(wiphy, wdev); 343 + return ret; 344 + } 432 345 433 - static void ieee80211_stop_nan(struct wiphy *wiphy, 434 - struct wireless_dev *wdev) 435 - { 436 - struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); 437 - 438 - drv_stop_nan(sdata->local, sdata); 439 - ieee80211_sdata_stop(sdata); 346 + return 0; 440 347 } 441 348 442 349 static int ieee80211_nan_change_conf(struct wiphy *wiphy, ··· 445 352 u32 changes) 446 353 { 447 354 struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); 448 - struct cfg80211_nan_conf new_conf; 355 + struct cfg80211_nan_conf new_conf = {}; 449 356 int ret = 0; 450 357 451 358 if (sdata->vif.type != NL80211_IFTYPE_NAN) ··· 454 361 if (!ieee80211_sdata_running(sdata)) 455 362 return -ENETDOWN; 456 363 457 - new_conf = sdata->u.nan.conf; 364 + if (!changes) 365 + return 0; 458 366 459 - if (changes & CFG80211_NAN_CONF_CHANGED_PREF) 460 - new_conf.master_pref = conf->master_pref; 367 + /* First make a full copy of the previous configuration and then apply 368 + * the changes. This might be a little wasteful, but it is simpler. 369 + */ 370 + ret = ieee80211_nan_conf_copy(&new_conf, &sdata->u.nan.conf, 371 + 0xFFFFFFFF); 372 + if (ret < 0) 373 + return ret; 461 374 462 - if (changes & CFG80211_NAN_CONF_CHANGED_BANDS) 463 - new_conf.bands = conf->bands; 375 + ret = ieee80211_nan_conf_copy(&new_conf, conf, changes); 376 + if (ret < 0) 377 + return ret; 464 378 465 379 ret = drv_nan_change_conf(sdata->local, sdata, &new_conf, changes); 466 - if (!ret) 380 + if (ret) { 381 + ieee80211_nan_conf_free(&new_conf); 382 + } else { 383 + ieee80211_nan_conf_free(&sdata->u.nan.conf); 467 384 sdata->u.nan.conf = new_conf; 385 + } 468 386 469 387 return ret; 470 388 } ··· 4935 4831 int ret = 0; 4936 4832 4937 4833 spin_lock_bh(&local->fq.lock); 4938 - rcu_read_lock(); 4939 4834 4940 4835 if (wdev) { 4941 4836 sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); ··· 4960 4857 } 4961 4858 4962 4859 out: 4963 - rcu_read_unlock(); 4964 4860 spin_unlock_bh(&local->fq.lock); 4965 4861 4966 4862 return ret;

-3

net/mac80211/debugfs.c

··· 82 82 int len = 0; 83 83 84 84 spin_lock_bh(&local->fq.lock); 85 - rcu_read_lock(); 86 85 87 86 len = scnprintf(buf, sizeof(buf), 88 87 "access name value\n" ··· 104 105 fq->limit, 105 106 fq->quantum); 106 107 107 - rcu_read_unlock(); 108 108 spin_unlock_bh(&local->fq.lock); 109 109 110 110 return simple_read_from_buffer(user_buf, count, ppos, ··· 715 717 DEBUGFS_STATS_ADD(dot11ReceivedFragmentCount); 716 718 DEBUGFS_STATS_ADD(dot11MulticastReceivedFrameCount); 717 719 DEBUGFS_STATS_ADD(dot11TransmittedFrameCount); 718 - DEBUGFS_STATS_ADD(tx_handlers_drop); 719 720 DEBUGFS_STATS_ADD(tx_handlers_queued); 720 721 DEBUGFS_STATS_ADD(tx_handlers_drop_wep); 721 722 DEBUGFS_STATS_ADD(tx_handlers_drop_not_assoc);

-2

net/mac80211/debugfs_netdev.c

··· 625 625 txqi = to_txq_info(sdata->vif.txq); 626 626 627 627 spin_lock_bh(&local->fq.lock); 628 - rcu_read_lock(); 629 628 630 629 len = scnprintf(buf, 631 630 buflen, ··· 641 642 txqi->tin.tx_bytes, 642 643 txqi->tin.tx_packets); 643 644 644 - rcu_read_unlock(); 645 645 spin_unlock_bh(&local->fq.lock); 646 646 647 647 return len;

-2

net/mac80211/debugfs_sta.c

··· 148 148 return -ENOMEM; 149 149 150 150 spin_lock_bh(&local->fq.lock); 151 - rcu_read_lock(); 152 151 153 152 p += scnprintf(p, 154 153 bufsz + buf - p, ··· 177 178 test_bit(IEEE80211_TXQ_DIRTY, &txqi->flags) ? " DIRTY" : ""); 178 179 } 179 180 180 - rcu_read_unlock(); 181 181 spin_unlock_bh(&local->fq.lock); 182 182 183 183 rv = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf);

+4 -4

net/mac80211/ieee80211_i.h

··· 985 985 * struct ieee80211_if_nan - NAN state 986 986 * 987 987 * @conf: current NAN configuration 988 + * @started: true iff NAN is started 988 989 * @func_lock: lock for @func_inst_ids 989 990 * @function_inst_ids: a bitmap of available instance_id's 990 991 */ 991 992 struct ieee80211_if_nan { 992 993 struct cfg80211_nan_conf conf; 994 + bool started; 993 995 994 996 /* protects function_inst_ids */ 995 997 spinlock_t func_lock; ··· 1610 1608 u32 dot11TransmittedFrameCount; 1611 1609 1612 1610 /* TX/RX handler statistics */ 1613 - unsigned int tx_handlers_drop; 1614 1611 unsigned int tx_handlers_queued; 1615 1612 unsigned int tx_handlers_drop_wep; 1616 1613 unsigned int tx_handlers_drop_not_assoc; ··· 1674 1673 1675 1674 struct idr ack_status_frames; 1676 1675 spinlock_t ack_status_lock; 1677 - 1678 - struct ieee80211_sub_if_data __rcu *p2p_sdata; 1679 1676 1680 1677 /* virtual monitor interface */ 1681 1678 struct ieee80211_sub_if_data __rcu *monitor_sdata; ··· 2710 2711 const struct ieee80211_he_operation *he_oper, 2711 2712 const struct ieee80211_eht_operation *eht_oper, 2712 2713 struct cfg80211_chan_def *chandef); 2713 - bool ieee80211_chandef_s1g_oper(const struct ieee80211_s1g_oper_ie *oper, 2714 + bool ieee80211_chandef_s1g_oper(struct ieee80211_local *local, 2715 + const struct ieee80211_s1g_oper_ie *oper, 2714 2716 struct cfg80211_chan_def *chandef); 2715 2717 void ieee80211_chandef_downgrade(struct cfg80211_chan_def *chandef, 2716 2718 struct ieee80211_conn_settings *conn);

+10 -15

net/mac80211/iface.c

··· 107 107 { 108 108 bool working, scanning, active; 109 109 unsigned int led_trig_start = 0, led_trig_stop = 0; 110 + struct ieee80211_sub_if_data *iter; 110 111 111 112 lockdep_assert_wiphy(local->hw.wiphy); 112 113 ··· 117 116 118 117 working = !local->ops->remain_on_channel && 119 118 !list_empty(&local->roc_list); 119 + 120 + list_for_each_entry(iter, &local->interfaces, list) { 121 + if (iter->vif.type == NL80211_IFTYPE_NAN && 122 + iter->u.nan.started) { 123 + working = true; 124 + break; 125 + } 126 + } 120 127 121 128 scanning = test_bit(SCAN_SW_SCANNING, &local->scanning) || 122 129 test_bit(SCAN_ONCHANNEL_SCANNING, &local->scanning); ··· 620 611 621 612 spin_unlock_bh(&sdata->u.nan.func_lock); 622 613 break; 623 - case NL80211_IFTYPE_P2P_DEVICE: 624 - /* relies on synchronize_rcu() below */ 625 - RCU_INIT_POINTER(local->p2p_sdata, NULL); 626 - fallthrough; 627 614 default: 628 615 wiphy_work_cancel(sdata->local->hw.wiphy, &sdata->work); 629 616 /* ··· 1410 1405 ieee80211_recalc_idle(local); 1411 1406 1412 1407 netif_carrier_on(dev); 1408 + list_add_tail_rcu(&sdata->u.mntr.list, &local->mon_list); 1413 1409 break; 1414 1410 default: 1415 1411 if (coming_up) { ··· 1472 1466 */ 1473 1467 ieee80211_set_wmm_default(&sdata->deflink, true, 1474 1468 sdata->vif.type != NL80211_IFTYPE_STATION); 1475 - } 1476 - 1477 - switch (sdata->vif.type) { 1478 - case NL80211_IFTYPE_P2P_DEVICE: 1479 - rcu_assign_pointer(local->p2p_sdata, sdata); 1480 - break; 1481 - case NL80211_IFTYPE_MONITOR: 1482 - list_add_tail_rcu(&sdata->u.mntr.list, &local->mon_list); 1483 - break; 1484 - default: 1485 - break; 1486 1469 } 1487 1470 1488 1471 /*

+9 -2

net/mac80211/main.c

··· 746 746 BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | 747 747 BIT(IEEE80211_STYPE_AUTH >> 4), 748 748 }, 749 + [NL80211_IFTYPE_NAN] = { 750 + .tx = 0xffff, 751 + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | 752 + BIT(IEEE80211_STYPE_AUTH >> 4), 753 + }, 749 754 }; 750 755 751 756 static const struct ieee80211_ht_cap mac80211_ht_capa_mod_mask = { ··· 1249 1244 if (!dflt_chandef.chan) { 1250 1245 /* 1251 1246 * Assign the first enabled channel to dflt_chandef 1252 - * from the list of channels 1247 + * from the list of channels. For S1G interfaces 1248 + * ensure it can be used as a primary. 1253 1249 */ 1254 1250 for (i = 0; i < sband->n_channels; i++) 1255 1251 if (!(sband->channels[i].flags & 1256 - IEEE80211_CHAN_DISABLED)) 1252 + (IEEE80211_CHAN_DISABLED | 1253 + IEEE80211_CHAN_S1G_NO_PRIMARY))) 1257 1254 break; 1258 1255 /* if none found then use the first anyway */ 1259 1256 if (i == sband->n_channels)

+47 -6

net/mac80211/mlme.c

··· 180 180 181 181 /* get special S1G case out of the way */ 182 182 if (sband->band == NL80211_BAND_S1GHZ) { 183 - if (!ieee80211_chandef_s1g_oper(elems->s1g_oper, chandef)) { 184 - sdata_info(sdata, 185 - "Missing S1G Operation Element? Trying operating == primary\n"); 186 - chandef->width = ieee80211_s1g_channel_width(channel); 183 + if (!ieee80211_chandef_s1g_oper(sdata->local, elems->s1g_oper, 184 + chandef)) { 185 + /* Fallback to default 1MHz */ 186 + chandef->width = NL80211_CHAN_WIDTH_1; 187 + chandef->s1g_primary_2mhz = false; 187 188 } 188 189 189 190 return IEEE80211_CONN_MODE_S1G; ··· 1047 1046 ret = -EINVAL; 1048 1047 goto free; 1049 1048 } 1049 + 1050 + chanreq->oper = *ap_chandef; 1051 + if (!cfg80211_chandef_usable(sdata->wdev.wiphy, &chanreq->oper, 1052 + IEEE80211_CHAN_DISABLED)) { 1053 + ret = -EINVAL; 1054 + goto free; 1055 + } 1056 + 1050 1057 return elems; 1051 1058 case NL80211_BAND_6GHZ: 1052 1059 if (ap_mode < IEEE80211_CONN_MODE_HE) { ··· 7301 7292 return memcmp(elems->ssid, cfg->ssid, cfg->ssid_len); 7302 7293 } 7303 7294 7295 + static bool 7296 + ieee80211_rx_beacon_freq_valid(struct ieee80211_local *local, 7297 + struct ieee80211_mgmt *mgmt, 7298 + struct ieee80211_rx_status *rx_status, 7299 + struct ieee80211_chanctx_conf *chanctx) 7300 + { 7301 + u32 pri_2mhz_khz; 7302 + struct ieee80211_channel *s1g_sibling_1mhz; 7303 + u32 pri_khz = ieee80211_channel_to_khz(chanctx->def.chan); 7304 + u32 rx_khz = ieee80211_rx_status_to_khz(rx_status); 7305 + 7306 + if (rx_khz == pri_khz) 7307 + return true; 7308 + 7309 + if (!chanctx->def.s1g_primary_2mhz) 7310 + return false; 7311 + 7312 + /* 7313 + * If we have an S1G interface with a 2MHz primary, beacons are 7314 + * sent on the center frequency of the 2MHz primary. Find the sibling 7315 + * 1MHz channel and calculate the 2MHz primary center frequency. 7316 + */ 7317 + s1g_sibling_1mhz = cfg80211_s1g_get_primary_sibling(local->hw.wiphy, 7318 + &chanctx->def); 7319 + if (!s1g_sibling_1mhz) 7320 + return false; 7321 + 7322 + pri_2mhz_khz = 7323 + (pri_khz + ieee80211_channel_to_khz(s1g_sibling_1mhz)) / 2; 7324 + return rx_khz == pri_2mhz_khz; 7325 + } 7326 + 7304 7327 static void ieee80211_rx_mgmt_beacon(struct ieee80211_link_data *link, 7305 7328 struct ieee80211_hdr *hdr, size_t len, 7306 7329 struct ieee80211_rx_status *rx_status) ··· 7387 7346 return; 7388 7347 } 7389 7348 7390 - if (ieee80211_rx_status_to_khz(rx_status) != 7391 - ieee80211_channel_to_khz(chanctx_conf->def.chan)) { 7349 + if (!ieee80211_rx_beacon_freq_valid(local, mgmt, rx_status, 7350 + chanctx_conf)) { 7392 7351 rcu_read_unlock(); 7393 7352 return; 7394 7353 }

+4 -1

net/mac80211/offchannel.c

··· 8 8 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz> 9 9 * Copyright 2007, Michael Wu <flamingice@sourmilk.net> 10 10 * Copyright 2009 Johannes Berg <johannes@sipsolutions.net> 11 - * Copyright (C) 2019, 2022-2024 Intel Corporation 11 + * Copyright (C) 2019, 2022-2025 Intel Corporation 12 12 */ 13 13 #include <linux/export.h> 14 14 #include <net/mac80211.h> ··· 897 897 need_offchan = true; 898 898 break; 899 899 case NL80211_IFTYPE_NAN: 900 + break; 900 901 default: 901 902 return -EOPNOTSUPP; 902 903 } ··· 911 910 /* Check if the operating channel is the requested channel */ 912 911 if (!params->chan && mlo_sta) { 913 912 need_offchan = false; 913 + } else if (sdata->vif.type == NL80211_IFTYPE_NAN) { 914 + /* Frames can be sent during NAN schedule */ 914 915 } else if (!need_offchan) { 915 916 struct ieee80211_chanctx_conf *chanctx_conf = NULL; 916 917 int i;

+10 -1

net/mac80211/rate.c

··· 4 4 * Copyright 2005-2006, Devicescape Software, Inc. 5 5 * Copyright (c) 2006 Jiri Benc <jbenc@suse.cz> 6 6 * Copyright 2017 Intel Deutschland GmbH 7 - * Copyright (C) 2019, 2022-2024 Intel Corporation 7 + * Copyright (C) 2019, 2022-2025 Intel Corporation 8 8 */ 9 9 10 10 #include <linux/kernel.h> ··· 96 96 struct ieee80211_supported_band *sband; 97 97 98 98 if (!ref || !test_sta_flag(sta, WLAN_STA_RATE_CONTROL)) 99 + return; 100 + 101 + if (st->info->band >= NUM_NL80211_BANDS) 99 102 return; 100 103 101 104 sband = local->hw.wiphy->bands[st->info->band]; ··· 421 418 struct sta_info *sta; 422 419 int mcast_rate; 423 420 bool use_basicrate = false; 421 + 422 + if (!sband) 423 + return false; 424 424 425 425 if (!pubsta || rc_no_data_or_no_ack_use_min(txrc)) { 426 426 __rate_control_send_low(txrc->hw, sband, pubsta, info, ··· 904 898 return; 905 899 906 900 sdata = vif_to_sdata(vif); 901 + if (info->band >= NUM_NL80211_BANDS) 902 + return; 903 + 907 904 sband = sdata->local->hw.wiphy->bands[info->band]; 908 905 909 906 if (ieee80211_is_tx_data(skb))

+32 -8

net/mac80211/rx.c

··· 4502 4502 (ieee80211_is_auth(hdr->frame_control) && 4503 4503 ether_addr_equal(sdata->vif.addr, hdr->addr1)); 4504 4504 case NL80211_IFTYPE_NAN: 4505 - /* Currently no frames on NAN interface are allowed */ 4506 - return false; 4505 + /* Accept only frames that are addressed to the NAN cluster 4506 + * (based on the Cluster ID). From these frames, accept only 4507 + * action frames or authentication frames that are addressed to 4508 + * the local NAN interface. 4509 + */ 4510 + return memcmp(sdata->wdev.u.nan.cluster_id, 4511 + hdr->addr3, ETH_ALEN) == 0 && 4512 + (ieee80211_is_public_action(hdr, skb->len) || 4513 + (ieee80211_is_auth(hdr->frame_control) && 4514 + ether_addr_equal(sdata->vif.addr, hdr->addr1))); 4507 4515 default: 4508 4516 break; 4509 4517 } ··· 5238 5230 } 5239 5231 5240 5232 rx.sdata = prev_sta->sdata; 5233 + if (!status->link_valid && prev_sta->sta.mlo) { 5234 + struct link_sta_info *link_sta; 5235 + 5236 + link_sta = link_sta_info_get_bss(rx.sdata, 5237 + hdr->addr2); 5238 + if (!link_sta) 5239 + continue; 5240 + 5241 + link_id = link_sta->link_id; 5242 + } 5243 + 5241 5244 if (!ieee80211_rx_data_set_sta(&rx, prev_sta, link_id)) 5242 5245 goto out; 5243 - 5244 - if (!status->link_valid && prev_sta->sta.mlo) 5245 - continue; 5246 5246 5247 5247 ieee80211_prepare_and_rx_handle(&rx, skb, false); 5248 5248 ··· 5259 5243 5260 5244 if (prev_sta) { 5261 5245 rx.sdata = prev_sta->sdata; 5262 - if (!ieee80211_rx_data_set_sta(&rx, prev_sta, link_id)) 5263 - goto out; 5246 + if (!status->link_valid && prev_sta->sta.mlo) { 5247 + struct link_sta_info *link_sta; 5264 5248 5265 - if (!status->link_valid && prev_sta->sta.mlo) 5249 + link_sta = link_sta_info_get_bss(rx.sdata, 5250 + hdr->addr2); 5251 + if (!link_sta) 5252 + goto out; 5253 + 5254 + link_id = link_sta->link_id; 5255 + } 5256 + 5257 + if (!ieee80211_rx_data_set_sta(&rx, prev_sta, link_id)) 5266 5258 goto out; 5267 5259 5268 5260 if (ieee80211_prepare_and_rx_handle(&rx, skb, true))

+7 -6

net/mac80211/scan.c

··· 996 996 local->scan_chandef.freq1_offset = chan->freq_offset; 997 997 local->scan_chandef.center_freq2 = 0; 998 998 999 - /* For scanning on the S1G band, detect the channel width according to 1000 - * the channel being scanned. 1001 - */ 999 + /* For S1G, only scan the 1MHz primaries. */ 1002 1000 if (chan->band == NL80211_BAND_S1GHZ) { 1003 - local->scan_chandef.width = ieee80211_s1g_channel_width(chan); 1001 + local->scan_chandef.width = NL80211_CHAN_WIDTH_1; 1002 + local->scan_chandef.s1g_primary_2mhz = false; 1004 1003 goto set_channel; 1005 1004 } 1006 1005 1007 - /* If scanning on oper channel, use whatever channel-type 1006 + /* 1007 + * If scanning on oper channel, use whatever channel-type 1008 1008 * is currently in use. 1009 1009 */ 1010 1010 if (chan == local->hw.conf.chandef.chan) ··· 1213 1213 1214 1214 for (band = 0; band < NUM_NL80211_BANDS; band++) { 1215 1215 if (!local->hw.wiphy->bands[band] || 1216 - band == NL80211_BAND_6GHZ) 1216 + band == NL80211_BAND_6GHZ || 1217 + band == NL80211_BAND_S1GHZ) 1217 1218 continue; 1218 1219 1219 1220 max_n = local->hw.wiphy->bands[band]->n_channels;

-2

net/mac80211/sta_info.c

··· 2637 2637 2638 2638 if (link_id < 0 && tid < IEEE80211_NUM_TIDS) { 2639 2639 spin_lock_bh(&local->fq.lock); 2640 - rcu_read_lock(); 2641 2640 2642 2641 tidstats->filled |= BIT(NL80211_TID_STATS_TXQ_STATS); 2643 2642 ieee80211_fill_txq_stats(&tidstats->txq_stats, 2644 2643 to_txq_info(sta->sta.txq[tid])); 2645 2644 2646 - rcu_read_unlock(); 2647 2645 spin_unlock_bh(&local->fq.lock); 2648 2646 } 2649 2647 }

+19 -2

net/mac80211/status.c

··· 5 5 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz> 6 6 * Copyright 2008-2010 Johannes Berg <johannes@sipsolutions.net> 7 7 * Copyright 2013-2014 Intel Mobile Communications GmbH 8 - * Copyright 2021-2024 Intel Corporation 8 + * Copyright 2021-2025 Intel Corporation 9 9 */ 10 10 11 11 #include <linux/export.h> ··· 572 572 ieee80211_sdata_from_skb(struct ieee80211_local *local, struct sk_buff *skb) 573 573 { 574 574 struct ieee80211_sub_if_data *sdata; 575 + struct ieee80211_hdr *hdr = (void *)skb->data; 575 576 576 577 if (skb->dev) { 577 578 list_for_each_entry_rcu(sdata, &local->interfaces, list) { ··· 586 585 return NULL; 587 586 } 588 587 589 - return rcu_dereference(local->p2p_sdata); 588 + list_for_each_entry_rcu(sdata, &local->interfaces, list) { 589 + switch (sdata->vif.type) { 590 + case NL80211_IFTYPE_P2P_DEVICE: 591 + break; 592 + case NL80211_IFTYPE_NAN: 593 + if (sdata->u.nan.started) 594 + break; 595 + fallthrough; 596 + default: 597 + continue; 598 + } 599 + 600 + if (ether_addr_equal(sdata->vif.addr, hdr->addr2)) 601 + return sdata; 602 + } 603 + 604 + return NULL; 590 605 } 591 606 592 607 static void ieee80211_report_ack_skb(struct ieee80211_local *local,

+10 -4

net/mac80211/tx.c

··· 59 59 if (WARN_ON_ONCE(tx->rate.idx < 0)) 60 60 return 0; 61 61 62 + if (info->band >= NUM_NL80211_BANDS) 63 + return 0; 64 + 62 65 sband = local->hw.wiphy->bands[info->band]; 63 66 txrate = &sband->bitrates[tx->rate.idx]; 64 67 ··· 686 683 687 684 memset(&txrc, 0, sizeof(txrc)); 688 685 689 - sband = tx->local->hw.wiphy->bands[info->band]; 686 + if (info->band < NUM_NL80211_BANDS) 687 + sband = tx->local->hw.wiphy->bands[info->band]; 688 + else 689 + return TX_CONTINUE; 690 690 691 691 len = min_t(u32, tx->skb->len + FCS_LEN, 692 692 tx->local->hw.wiphy->frag_threshold); ··· 1821 1815 txh_done: 1822 1816 if (unlikely(res == TX_DROP)) { 1823 1817 tx->sdata->tx_handlers_drop++; 1824 - I802_DEBUG_INC(tx->local->tx_handlers_drop); 1825 1818 if (tx->skb) 1826 1819 ieee80211_free_txskb(&tx->local->hw, tx->skb); 1827 1820 else ··· 1865 1860 txh_done: 1866 1861 if (unlikely(res == TX_DROP)) { 1867 1862 tx->sdata->tx_handlers_drop++; 1868 - I802_DEBUG_INC(tx->local->tx_handlers_drop); 1869 1863 if (tx->skb) 1870 1864 ieee80211_free_txskb(&tx->local->hw, tx->skb); 1871 1865 else ··· 6292 6288 enum nl80211_band band; 6293 6289 6294 6290 rcu_read_lock(); 6295 - if (!ieee80211_vif_is_mld(&sdata->vif)) { 6291 + if (sdata->vif.type == NL80211_IFTYPE_NAN) { 6292 + band = NUM_NL80211_BANDS; 6293 + } else if (!ieee80211_vif_is_mld(&sdata->vif)) { 6296 6294 WARN_ON(link_id >= 0); 6297 6295 chanctx_conf = 6298 6296 rcu_dereference(sdata->vif.bss_conf.chanctx_conf);

+40 -7

net/mac80211/util.c

··· 3199 3199 return true; 3200 3200 } 3201 3201 3202 - bool ieee80211_chandef_s1g_oper(const struct ieee80211_s1g_oper_ie *oper, 3202 + bool ieee80211_chandef_s1g_oper(struct ieee80211_local *local, 3203 + const struct ieee80211_s1g_oper_ie *oper, 3203 3204 struct cfg80211_chan_def *chandef) 3204 3205 { 3205 - u32 oper_freq; 3206 + u32 oper_khz, pri_1mhz_khz, pri_2mhz_khz; 3206 3207 3207 3208 if (!oper) 3208 3209 return false; ··· 3228 3227 return false; 3229 3228 } 3230 3229 3231 - oper_freq = ieee80211_channel_to_freq_khz(oper->oper_ch, 3232 - NL80211_BAND_S1GHZ); 3233 - chandef->center_freq1 = KHZ_TO_MHZ(oper_freq); 3234 - chandef->freq1_offset = oper_freq % 1000; 3230 + chandef->s1g_primary_2mhz = false; 3235 3231 3236 - return true; 3232 + switch (u8_get_bits(oper->ch_width, S1G_OPER_CH_WIDTH_PRIMARY)) { 3233 + case IEEE80211_S1G_PRI_CHANWIDTH_1MHZ: 3234 + pri_1mhz_khz = ieee80211_channel_to_freq_khz( 3235 + oper->primary_ch, NL80211_BAND_S1GHZ); 3236 + break; 3237 + case IEEE80211_S1G_PRI_CHANWIDTH_2MHZ: 3238 + chandef->s1g_primary_2mhz = true; 3239 + pri_2mhz_khz = ieee80211_channel_to_freq_khz( 3240 + oper->primary_ch, NL80211_BAND_S1GHZ); 3241 + 3242 + if (u8_get_bits(oper->ch_width, S1G_OPER_CH_PRIMARY_LOCATION) == 3243 + S1G_2M_PRIMARY_LOCATION_LOWER) 3244 + pri_1mhz_khz = pri_2mhz_khz - 500; 3245 + else 3246 + pri_1mhz_khz = pri_2mhz_khz + 500; 3247 + break; 3248 + default: 3249 + return false; 3250 + } 3251 + 3252 + oper_khz = ieee80211_channel_to_freq_khz(oper->oper_ch, 3253 + NL80211_BAND_S1GHZ); 3254 + chandef->center_freq1 = KHZ_TO_MHZ(oper_khz); 3255 + chandef->freq1_offset = oper_khz % 1000; 3256 + chandef->chan = 3257 + ieee80211_get_channel_khz(local->hw.wiphy, pri_1mhz_khz); 3258 + 3259 + return chandef->chan; 3237 3260 } 3238 3261 3239 3262 int ieee80211_put_srates_elem(struct sk_buff *skb, ··· 4537 4512 sizeof(tpe->psd_reg_client[i].power)); 4538 4513 } 4539 4514 } 4515 + 4516 + bool ieee80211_vif_nan_started(struct ieee80211_vif *vif) 4517 + { 4518 + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); 4519 + 4520 + return vif->type == NL80211_IFTYPE_NAN && sdata->u.nan.started; 4521 + } 4522 + EXPORT_SYMBOL_GPL(ieee80211_vif_nan_started);

+70 -33

net/wireless/chan.c

··· 100 100 punctured = 0) : (punctured >>= 1))) \ 101 101 if (!(punctured & 1)) 102 102 103 + #define for_each_s1g_subchan(chandef, freq_khz) \ 104 + for (freq_khz = cfg80211_s1g_get_start_freq_khz(chandef); \ 105 + freq_khz <= cfg80211_s1g_get_end_freq_khz(chandef); \ 106 + freq_khz += MHZ_TO_KHZ(1)) 107 + 103 108 struct cfg80211_per_bw_puncturing_values { 104 109 u8 len; 105 110 const u16 *valid_values; ··· 341 336 342 337 bool cfg80211_chandef_valid(const struct cfg80211_chan_def *chandef) 343 338 { 344 - u32 control_freq, oper_freq; 345 - int oper_width, control_width; 339 + u32 control_freq, control_freq_khz, start_khz, end_khz; 346 340 347 341 if (!chandef->chan) 348 342 return false; ··· 367 363 case NL80211_CHAN_WIDTH_4: 368 364 case NL80211_CHAN_WIDTH_8: 369 365 case NL80211_CHAN_WIDTH_16: 370 - if (chandef->chan->band != NL80211_BAND_S1GHZ) 371 - return false; 372 - 373 - control_freq = ieee80211_channel_to_khz(chandef->chan); 374 - oper_freq = ieee80211_chandef_to_khz(chandef); 375 - control_width = nl80211_chan_width_to_mhz( 376 - ieee80211_s1g_channel_width( 377 - chandef->chan)); 378 - oper_width = cfg80211_chandef_get_width(chandef); 379 - 380 - if (oper_width < 0 || control_width < 0) 366 + if (!cfg80211_chandef_is_s1g(chandef)) 381 367 return false; 382 368 if (chandef->center_freq2) 383 369 return false; 384 370 385 - if (control_freq + MHZ_TO_KHZ(control_width) / 2 > 386 - oper_freq + MHZ_TO_KHZ(oper_width) / 2) 387 - return false; 371 + control_freq_khz = ieee80211_channel_to_khz(chandef->chan); 372 + start_khz = cfg80211_s1g_get_start_freq_khz(chandef); 373 + end_khz = cfg80211_s1g_get_end_freq_khz(chandef); 388 374 389 - if (control_freq - MHZ_TO_KHZ(control_width) / 2 < 390 - oper_freq - MHZ_TO_KHZ(oper_width) / 2) 375 + if (control_freq_khz < start_khz || control_freq_khz > end_khz) 391 376 return false; 392 377 break; 393 378 case NL80211_CHAN_WIDTH_80P80: ··· 452 459 453 460 if (cfg80211_chandef_is_edmg(chandef) && 454 461 !cfg80211_edmg_chandef_valid(chandef)) 462 + return false; 463 + 464 + if (!cfg80211_chandef_is_s1g(chandef) && chandef->s1g_primary_2mhz) 455 465 return false; 456 466 457 467 return valid_puncturing_bitmap(chandef); ··· 720 724 enum nl80211_iftype iftype) 721 725 { 722 726 struct ieee80211_channel *c; 727 + 728 + /* DFS is not required for S1G */ 729 + if (cfg80211_chandef_is_s1g(chandef)) 730 + return 0; 723 731 724 732 for_each_subchan(chandef, freq, cf) { 725 733 c = ieee80211_get_channel_khz(wiphy, freq); ··· 1130 1130 return true; 1131 1131 } 1132 1132 1133 + static bool cfg80211_s1g_usable(struct wiphy *wiphy, 1134 + const struct cfg80211_chan_def *chandef) 1135 + { 1136 + u32 freq_khz; 1137 + const struct ieee80211_channel *chan; 1138 + u32 pri_khz = ieee80211_channel_to_khz(chandef->chan); 1139 + u32 end_khz = cfg80211_s1g_get_end_freq_khz(chandef); 1140 + u32 start_khz = cfg80211_s1g_get_start_freq_khz(chandef); 1141 + int width_mhz = cfg80211_chandef_get_width(chandef); 1142 + u32 prohibited_flags = IEEE80211_CHAN_DISABLED; 1143 + 1144 + if (width_mhz >= 16) 1145 + prohibited_flags |= IEEE80211_CHAN_NO_16MHZ; 1146 + if (width_mhz >= 8) 1147 + prohibited_flags |= IEEE80211_CHAN_NO_8MHZ; 1148 + if (width_mhz >= 4) 1149 + prohibited_flags |= IEEE80211_CHAN_NO_4MHZ; 1150 + 1151 + if (chandef->chan->flags & IEEE80211_CHAN_S1G_NO_PRIMARY) 1152 + return false; 1153 + 1154 + if (pri_khz < start_khz || pri_khz > end_khz) 1155 + return false; 1156 + 1157 + for_each_s1g_subchan(chandef, freq_khz) { 1158 + chan = ieee80211_get_channel_khz(wiphy, freq_khz); 1159 + if (!chan || (chan->flags & prohibited_flags)) 1160 + return false; 1161 + } 1162 + 1163 + if (chandef->s1g_primary_2mhz) { 1164 + u32 sib_khz; 1165 + const struct ieee80211_channel *sibling; 1166 + 1167 + sibling = cfg80211_s1g_get_primary_sibling(wiphy, chandef); 1168 + if (!sibling) 1169 + return false; 1170 + 1171 + if (sibling->flags & IEEE80211_CHAN_S1G_NO_PRIMARY) 1172 + return false; 1173 + 1174 + sib_khz = ieee80211_channel_to_khz(sibling); 1175 + if (sib_khz < start_khz || sib_khz > end_khz) 1176 + return false; 1177 + } 1178 + 1179 + return true; 1180 + } 1181 + 1133 1182 bool _cfg80211_chandef_usable(struct wiphy *wiphy, 1134 1183 const struct cfg80211_chan_def *chandef, 1135 1184 u32 prohibited_flags, ··· 1203 1154 ext_nss_cap = __le16_to_cpu(vht_cap->vht_mcs.tx_highest) & 1204 1155 IEEE80211_VHT_EXT_NSS_BW_CAPABLE; 1205 1156 1157 + if (cfg80211_chandef_is_s1g(chandef)) 1158 + return cfg80211_s1g_usable(wiphy, chandef); 1159 + 1206 1160 if (edmg_cap->channels && 1207 1161 !cfg80211_edmg_usable(wiphy, 1208 1162 chandef->edmg.channels, ··· 1217 1165 control_freq = chandef->chan->center_freq; 1218 1166 1219 1167 switch (chandef->width) { 1220 - case NL80211_CHAN_WIDTH_1: 1221 - width = 1; 1222 - break; 1223 - case NL80211_CHAN_WIDTH_2: 1224 - width = 2; 1225 - break; 1226 - case NL80211_CHAN_WIDTH_4: 1227 - width = 4; 1228 - break; 1229 - case NL80211_CHAN_WIDTH_8: 1230 - width = 8; 1231 - break; 1232 - case NL80211_CHAN_WIDTH_16: 1233 - width = 16; 1234 - break; 1235 1168 case NL80211_CHAN_WIDTH_5: 1236 1169 width = 5; 1237 1170 break;

+420 -67

net/wireless/nl80211.c

··· 312 312 return 0; 313 313 } 314 314 315 + static int validate_nan_cluster_id(const struct nlattr *attr, 316 + struct netlink_ext_ack *extack) 317 + { 318 + const u8 *data = nla_data(attr); 319 + unsigned int len = nla_len(attr); 320 + static const u8 cluster_id_prefix[4] = {0x50, 0x6f, 0x9a, 0x1}; 321 + 322 + if (len != ETH_ALEN) { 323 + NL_SET_ERR_MSG_ATTR(extack, attr, "bad cluster id length"); 324 + return -EINVAL; 325 + } 326 + 327 + if (memcmp(data, cluster_id_prefix, sizeof(cluster_id_prefix))) { 328 + NL_SET_ERR_MSG_ATTR(extack, attr, "invalid cluster id prefix"); 329 + return -EINVAL; 330 + } 331 + 332 + return 0; 333 + } 334 + 315 335 /* policy for the attributes */ 316 336 static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR]; 317 337 ··· 518 498 [NL80211_S1G_SHORT_BEACON_ATTR_TAIL] = 519 499 NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_ie_attr, 520 500 IEEE80211_MAX_DATA_LEN), 501 + }; 502 + 503 + static const struct nla_policy 504 + nl80211_nan_band_conf_policy[NL80211_NAN_BAND_CONF_ATTR_MAX + 1] = { 505 + [NL80211_NAN_BAND_CONF_BAND] = NLA_POLICY_MAX(NLA_U8, 506 + NUM_NL80211_BANDS - 1), 507 + [NL80211_NAN_BAND_CONF_FREQ] = { .type = NLA_U16 }, 508 + [NL80211_NAN_BAND_CONF_RSSI_CLOSE] = NLA_POLICY_MIN(NLA_S8, -59), 509 + [NL80211_NAN_BAND_CONF_RSSI_MIDDLE] = NLA_POLICY_MIN(NLA_S8, -74), 510 + [NL80211_NAN_BAND_CONF_WAKE_DW] = NLA_POLICY_MAX(NLA_U8, 5), 511 + [NL80211_NAN_BAND_CONF_DISABLE_SCAN] = { .type = NLA_FLAG }, 512 + }; 513 + 514 + static const struct nla_policy 515 + nl80211_nan_conf_policy[NL80211_NAN_CONF_ATTR_MAX + 1] = { 516 + [NL80211_NAN_CONF_CLUSTER_ID] = 517 + NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_nan_cluster_id, 518 + ETH_ALEN), 519 + [NL80211_NAN_CONF_EXTRA_ATTRS] = { .type = NLA_BINARY, 520 + .len = IEEE80211_MAX_DATA_LEN}, 521 + [NL80211_NAN_CONF_VENDOR_ELEMS] = 522 + NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_ie_attr, 523 + IEEE80211_MAX_DATA_LEN), 524 + [NL80211_NAN_CONF_BAND_CONFIGS] = 525 + NLA_POLICY_NESTED_ARRAY(nl80211_nan_band_conf_policy), 526 + [NL80211_NAN_CONF_SCAN_PERIOD] = { .type = NLA_U16 }, 527 + [NL80211_NAN_CONF_SCAN_DWELL_TIME] = NLA_POLICY_RANGE(NLA_U16, 50, 512), 528 + [NL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL] = 529 + NLA_POLICY_RANGE(NLA_U8, 50, 200), 530 + [NL80211_NAN_CONF_NOTIFY_DW] = { .type = NLA_FLAG }, 521 531 }; 522 532 523 533 static const struct netlink_range_validation nl80211_punct_bitmap_range = { ··· 819 769 [NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR] = NLA_POLICY_EXACT_LEN_WARN(ETH_ALEN), 820 770 [NL80211_ATTR_NAN_MASTER_PREF] = NLA_POLICY_MIN(NLA_U8, 1), 821 771 [NL80211_ATTR_BANDS] = { .type = NLA_U32 }, 772 + [NL80211_ATTR_NAN_CONFIG] = NLA_POLICY_NESTED(nl80211_nan_conf_policy), 822 773 [NL80211_ATTR_NAN_FUNC] = { .type = NLA_NESTED }, 823 774 [NL80211_ATTR_FILS_KEK] = { .type = NLA_BINARY, 824 775 .len = FILS_MAX_KEK_LEN }, ··· 931 880 [NL80211_ATTR_S1G_SHORT_BEACON] = 932 881 NLA_POLICY_NESTED(nl80211_s1g_short_beacon), 933 882 [NL80211_ATTR_BSS_PARAM] = { .type = NLA_FLAG }, 883 + [NL80211_ATTR_S1G_PRIMARY_2MHZ] = { .type = NLA_FLAG }, 934 884 }; 935 885 936 886 /* policy for the key attributes */ ··· 1280 1228 if ((chan->flags & IEEE80211_CHAN_NO_HE) && 1281 1229 nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_HE)) 1282 1230 goto nla_put_failure; 1283 - if ((chan->flags & IEEE80211_CHAN_1MHZ) && 1284 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_1MHZ)) 1285 - goto nla_put_failure; 1286 - if ((chan->flags & IEEE80211_CHAN_2MHZ) && 1287 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_2MHZ)) 1288 - goto nla_put_failure; 1289 - if ((chan->flags & IEEE80211_CHAN_4MHZ) && 1290 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_4MHZ)) 1291 - goto nla_put_failure; 1292 - if ((chan->flags & IEEE80211_CHAN_8MHZ) && 1293 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_8MHZ)) 1294 - goto nla_put_failure; 1295 - if ((chan->flags & IEEE80211_CHAN_16MHZ) && 1296 - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_16MHZ)) 1297 - goto nla_put_failure; 1298 1231 if ((chan->flags & IEEE80211_CHAN_NO_320MHZ) && 1299 1232 nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_320MHZ)) 1300 1233 goto nla_put_failure; ··· 1304 1267 if ((chan->flags & IEEE80211_CHAN_ALLOW_20MHZ_ACTIVITY) && 1305 1268 nla_put_flag(msg, 1306 1269 NL80211_FREQUENCY_ATTR_ALLOW_20MHZ_ACTIVITY)) 1270 + goto nla_put_failure; 1271 + if ((chan->flags & IEEE80211_CHAN_NO_4MHZ) && 1272 + nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_4MHZ)) 1273 + goto nla_put_failure; 1274 + if ((chan->flags & IEEE80211_CHAN_NO_8MHZ) && 1275 + nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_8MHZ)) 1276 + goto nla_put_failure; 1277 + if ((chan->flags & IEEE80211_CHAN_NO_16MHZ) && 1278 + nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_16MHZ)) 1307 1279 goto nla_put_failure; 1308 1280 } 1309 1281 ··· 2600 2554 return -ENOBUFS; 2601 2555 } 2602 2556 2557 + static int nl80211_put_nan_capa(struct wiphy *wiphy, struct sk_buff *msg) 2558 + { 2559 + struct nlattr *nan_caps; 2560 + 2561 + nan_caps = nla_nest_start(msg, NL80211_ATTR_NAN_CAPABILITIES); 2562 + if (!nan_caps) 2563 + return -ENOBUFS; 2564 + 2565 + if (wiphy->nan_capa.flags & WIPHY_NAN_FLAGS_CONFIGURABLE_SYNC && 2566 + nla_put_flag(msg, NL80211_NAN_CAPA_CONFIGURABLE_SYNC)) 2567 + goto fail; 2568 + 2569 + if ((wiphy->nan_capa.flags & WIPHY_NAN_FLAGS_USERSPACE_DE) && 2570 + nla_put_flag(msg, NL80211_NAN_CAPA_USERSPACE_DE)) 2571 + goto fail; 2572 + 2573 + if (nla_put_u8(msg, NL80211_NAN_CAPA_OP_MODE, 2574 + wiphy->nan_capa.op_mode) || 2575 + nla_put_u8(msg, NL80211_NAN_CAPA_NUM_ANTENNAS, 2576 + wiphy->nan_capa.n_antennas) || 2577 + nla_put_u16(msg, NL80211_NAN_CAPA_MAX_CHANNEL_SWITCH_TIME, 2578 + wiphy->nan_capa.max_channel_switch_time) || 2579 + nla_put_u8(msg, NL80211_NAN_CAPA_CAPABILITIES, 2580 + wiphy->nan_capa.dev_capabilities)) 2581 + goto fail; 2582 + 2583 + nla_nest_end(msg, nan_caps); 2584 + 2585 + return 0; 2586 + 2587 + fail: 2588 + nla_nest_cancel(msg, nan_caps); 2589 + return -ENOBUFS; 2590 + } 2591 + 2603 2592 struct nl80211_dump_wiphy_state { 2604 2593 s64 filter_wiphy; 2605 2594 long start; ··· 3287 3206 if (nl80211_put_radios(&rdev->wiphy, msg)) 3288 3207 goto nla_put_failure; 3289 3208 3209 + state->split_start++; 3210 + break; 3211 + case 18: 3212 + if (nl80211_put_nan_capa(&rdev->wiphy, msg)) 3213 + goto nla_put_failure; 3214 + 3290 3215 /* done */ 3291 3216 state->split_start = 0; 3292 3217 break; ··· 3536 3449 chandef->center_freq1 = KHZ_TO_MHZ(control_freq); 3537 3450 chandef->freq1_offset = control_freq % 1000; 3538 3451 chandef->center_freq2 = 0; 3452 + chandef->s1g_primary_2mhz = false; 3539 3453 3540 3454 if (!chandef->chan) { 3541 3455 NL_SET_ERR_MSG_ATTR(extack, attrs[NL80211_ATTR_WIPHY_FREQ], ··· 3580 3492 return -EINVAL; 3581 3493 } 3582 3494 } else if (attrs[NL80211_ATTR_CHANNEL_WIDTH]) { 3583 - chandef->width = 3584 - nla_get_u32(attrs[NL80211_ATTR_CHANNEL_WIDTH]); 3585 - if (chandef->chan->band == NL80211_BAND_S1GHZ) { 3586 - /* User input error for channel width doesn't match channel */ 3587 - if (chandef->width != ieee80211_s1g_channel_width(chandef->chan)) { 3588 - NL_SET_ERR_MSG_ATTR(extack, 3589 - attrs[NL80211_ATTR_CHANNEL_WIDTH], 3590 - "bad channel width"); 3591 - return -EINVAL; 3592 - } 3593 - } 3495 + chandef->width = nla_get_u32(attrs[NL80211_ATTR_CHANNEL_WIDTH]); 3594 3496 if (attrs[NL80211_ATTR_CENTER_FREQ1]) { 3595 3497 chandef->center_freq1 = 3596 3498 nla_get_u32(attrs[NL80211_ATTR_CENTER_FREQ1]); 3597 - chandef->freq1_offset = 3598 - nla_get_u32_default(attrs[NL80211_ATTR_CENTER_FREQ1_OFFSET], 3599 - 0); 3499 + chandef->freq1_offset = nla_get_u32_default( 3500 + attrs[NL80211_ATTR_CENTER_FREQ1_OFFSET], 0); 3600 3501 } 3502 + 3601 3503 if (attrs[NL80211_ATTR_CENTER_FREQ2]) 3602 3504 chandef->center_freq2 = 3603 3505 nla_get_u32(attrs[NL80211_ATTR_CENTER_FREQ2]); 3506 + 3507 + chandef->s1g_primary_2mhz = nla_get_flag( 3508 + attrs[NL80211_ATTR_S1G_PRIMARY_2MHZ]); 3604 3509 } 3605 3510 3606 3511 if (info->attrs[NL80211_ATTR_WIPHY_EDMG_CHANNELS]) { ··· 10444 10363 goto out_free; 10445 10364 } 10446 10365 10447 - /* ignore disabled channels */ 10366 + /* Ignore disabled / no primary channels */ 10448 10367 if (chan->flags & IEEE80211_CHAN_DISABLED || 10368 + chan->flags & IEEE80211_CHAN_S1G_NO_PRIMARY || 10449 10369 !cfg80211_wdev_channel_allowed(wdev, chan)) 10450 10370 continue; 10451 10371 ··· 10468 10386 chan = &wiphy->bands[band]->channels[j]; 10469 10387 10470 10388 if (chan->flags & IEEE80211_CHAN_DISABLED || 10389 + chan->flags & 10390 + IEEE80211_CHAN_S1G_NO_PRIMARY || 10471 10391 !cfg80211_wdev_channel_allowed(wdev, chan)) 10472 10392 continue; 10473 10393 ··· 13774 13690 break; 13775 13691 case NL80211_IFTYPE_NAN: 13776 13692 if (!wiphy_ext_feature_isset(wdev->wiphy, 13777 - NL80211_EXT_FEATURE_SECURE_NAN)) 13693 + NL80211_EXT_FEATURE_SECURE_NAN) && 13694 + !(wdev->wiphy->nan_capa.flags & 13695 + WIPHY_NAN_FLAGS_USERSPACE_DE)) 13778 13696 return -EOPNOTSUPP; 13779 13697 break; 13780 13698 default: ··· 13837 13751 break; 13838 13752 case NL80211_IFTYPE_NAN: 13839 13753 if (!wiphy_ext_feature_isset(wdev->wiphy, 13840 - NL80211_EXT_FEATURE_SECURE_NAN)) 13754 + NL80211_EXT_FEATURE_SECURE_NAN) && 13755 + !(wdev->wiphy->nan_capa.flags & 13756 + WIPHY_NAN_FLAGS_USERSPACE_DE)) 13841 13757 return -EOPNOTSUPP; 13842 13758 break; 13843 13759 default: ··· 15486 15398 return 0; 15487 15399 } 15488 15400 15401 + static struct ieee80211_channel *nl80211_get_nan_channel(struct wiphy *wiphy, 15402 + int freq) 15403 + { 15404 + struct ieee80211_channel *chan; 15405 + struct cfg80211_chan_def def; 15406 + 15407 + /* Check if the frequency is valid for NAN */ 15408 + if (freq != 5220 && freq != 5745 && freq != 2437) 15409 + return NULL; 15410 + 15411 + chan = ieee80211_get_channel(wiphy, freq); 15412 + if (!chan) 15413 + return NULL; 15414 + 15415 + cfg80211_chandef_create(&def, chan, NL80211_CHAN_NO_HT); 15416 + 15417 + /* Check if the channel is allowed */ 15418 + if (cfg80211_reg_can_beacon(wiphy, &def, NL80211_IFTYPE_NAN)) 15419 + return chan; 15420 + 15421 + return NULL; 15422 + } 15423 + 15424 + static int nl80211_parse_nan_band_config(struct wiphy *wiphy, 15425 + struct nlattr **tb, 15426 + struct cfg80211_nan_band_config *cfg, 15427 + enum nl80211_band band) 15428 + { 15429 + if (BIT(band) & ~(u32)wiphy->nan_supported_bands) 15430 + return -EINVAL; 15431 + 15432 + if (tb[NL80211_NAN_BAND_CONF_FREQ]) { 15433 + u16 freq = nla_get_u16(tb[NL80211_NAN_BAND_CONF_FREQ]); 15434 + 15435 + if (band != NL80211_BAND_5GHZ) 15436 + return -EINVAL; 15437 + 15438 + cfg->chan = nl80211_get_nan_channel(wiphy, freq); 15439 + if (!cfg->chan) 15440 + return -EINVAL; 15441 + } 15442 + 15443 + if (tb[NL80211_NAN_BAND_CONF_RSSI_CLOSE]) { 15444 + cfg->rssi_close = 15445 + nla_get_s8(tb[NL80211_NAN_BAND_CONF_RSSI_CLOSE]); 15446 + if (!tb[NL80211_NAN_BAND_CONF_RSSI_MIDDLE]) 15447 + return -EINVAL; 15448 + } 15449 + 15450 + if (tb[NL80211_NAN_BAND_CONF_RSSI_MIDDLE]) { 15451 + cfg->rssi_middle = 15452 + nla_get_s8(tb[NL80211_NAN_BAND_CONF_RSSI_MIDDLE]); 15453 + if (!cfg->rssi_close || cfg->rssi_middle >= cfg->rssi_close) 15454 + return -EINVAL; 15455 + } 15456 + 15457 + if (tb[NL80211_NAN_BAND_CONF_WAKE_DW]) { 15458 + cfg->awake_dw_interval = 15459 + nla_get_u8(tb[NL80211_NAN_BAND_CONF_WAKE_DW]); 15460 + 15461 + if (band == NL80211_BAND_2GHZ && cfg->awake_dw_interval == 0) 15462 + return -EINVAL; 15463 + } 15464 + 15465 + cfg->disable_scan = 15466 + nla_get_flag(tb[NL80211_NAN_BAND_CONF_DISABLE_SCAN]); 15467 + return 0; 15468 + } 15469 + 15470 + static int nl80211_parse_nan_conf(struct wiphy *wiphy, 15471 + struct genl_info *info, 15472 + struct cfg80211_nan_conf *conf, 15473 + u32 *changed_flags) 15474 + { 15475 + struct nlattr *attrs[NL80211_NAN_CONF_ATTR_MAX + 1]; 15476 + int err, rem; 15477 + u32 changed = 0; 15478 + struct nlattr *band_config; 15479 + 15480 + if (info->attrs[NL80211_ATTR_NAN_MASTER_PREF]) { 15481 + conf->master_pref = 15482 + nla_get_u8(info->attrs[NL80211_ATTR_NAN_MASTER_PREF]); 15483 + 15484 + changed |= CFG80211_NAN_CONF_CHANGED_PREF; 15485 + } 15486 + 15487 + if (info->attrs[NL80211_ATTR_BANDS]) { 15488 + u32 bands = nla_get_u32(info->attrs[NL80211_ATTR_BANDS]); 15489 + 15490 + if (bands & ~(u32)wiphy->nan_supported_bands) 15491 + return -EOPNOTSUPP; 15492 + 15493 + if (bands && !(bands & BIT(NL80211_BAND_2GHZ))) 15494 + return -EINVAL; 15495 + 15496 + conf->bands = bands; 15497 + changed |= CFG80211_NAN_CONF_CHANGED_BANDS; 15498 + } 15499 + 15500 + conf->band_cfgs[NL80211_BAND_2GHZ].awake_dw_interval = 1; 15501 + if (conf->bands & BIT(NL80211_BAND_5GHZ) || !conf->bands) 15502 + conf->band_cfgs[NL80211_BAND_5GHZ].awake_dw_interval = 1; 15503 + 15504 + /* On 2.4 GHz band use channel 6 */ 15505 + conf->band_cfgs[NL80211_BAND_2GHZ].chan = 15506 + nl80211_get_nan_channel(wiphy, 2437); 15507 + if (!conf->band_cfgs[NL80211_BAND_2GHZ].chan) 15508 + return -EINVAL; 15509 + 15510 + if (!info->attrs[NL80211_ATTR_NAN_CONFIG]) 15511 + goto out; 15512 + 15513 + err = nla_parse_nested(attrs, NL80211_NAN_CONF_ATTR_MAX, 15514 + info->attrs[NL80211_ATTR_NAN_CONFIG], NULL, 15515 + info->extack); 15516 + if (err) 15517 + return err; 15518 + 15519 + changed |= CFG80211_NAN_CONF_CHANGED_CONFIG; 15520 + if (attrs[NL80211_NAN_CONF_CLUSTER_ID]) 15521 + conf->cluster_id = 15522 + nla_data(attrs[NL80211_NAN_CONF_CLUSTER_ID]); 15523 + 15524 + if (attrs[NL80211_NAN_CONF_EXTRA_ATTRS]) { 15525 + conf->extra_nan_attrs = 15526 + nla_data(attrs[NL80211_NAN_CONF_EXTRA_ATTRS]); 15527 + conf->extra_nan_attrs_len = 15528 + nla_len(attrs[NL80211_NAN_CONF_EXTRA_ATTRS]); 15529 + } 15530 + 15531 + if (attrs[NL80211_NAN_CONF_VENDOR_ELEMS]) { 15532 + conf->vendor_elems = 15533 + nla_data(attrs[NL80211_NAN_CONF_VENDOR_ELEMS]); 15534 + conf->vendor_elems_len = 15535 + nla_len(attrs[NL80211_NAN_CONF_VENDOR_ELEMS]); 15536 + } 15537 + 15538 + if (attrs[NL80211_NAN_CONF_BAND_CONFIGS]) { 15539 + nla_for_each_nested(band_config, 15540 + attrs[NL80211_NAN_CONF_BAND_CONFIGS], 15541 + rem) { 15542 + enum nl80211_band band; 15543 + struct cfg80211_nan_band_config *cfg; 15544 + struct nlattr *tb[NL80211_NAN_BAND_CONF_ATTR_MAX + 1]; 15545 + 15546 + err = nla_parse_nested(tb, 15547 + NL80211_NAN_BAND_CONF_ATTR_MAX, 15548 + band_config, NULL, 15549 + info->extack); 15550 + if (err) 15551 + return err; 15552 + 15553 + if (!tb[NL80211_NAN_BAND_CONF_BAND]) 15554 + return -EINVAL; 15555 + 15556 + band = nla_get_u8(tb[NL80211_NAN_BAND_CONF_BAND]); 15557 + if (conf->bands && !(conf->bands & BIT(band))) 15558 + return -EINVAL; 15559 + 15560 + cfg = &conf->band_cfgs[band]; 15561 + 15562 + err = nl80211_parse_nan_band_config(wiphy, tb, cfg, 15563 + band); 15564 + if (err) 15565 + return err; 15566 + } 15567 + } 15568 + 15569 + if (attrs[NL80211_NAN_CONF_SCAN_PERIOD]) 15570 + conf->scan_period = 15571 + nla_get_u16(attrs[NL80211_NAN_CONF_SCAN_PERIOD]); 15572 + 15573 + if (attrs[NL80211_NAN_CONF_SCAN_DWELL_TIME]) 15574 + conf->scan_dwell_time = 15575 + nla_get_u16(attrs[NL80211_NAN_CONF_SCAN_DWELL_TIME]); 15576 + 15577 + if (attrs[NL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL]) 15578 + conf->discovery_beacon_interval = 15579 + nla_get_u8(attrs[NL80211_NAN_CONF_DISCOVERY_BEACON_INTERVAL]); 15580 + 15581 + if (attrs[NL80211_NAN_CONF_NOTIFY_DW]) 15582 + conf->enable_dw_notification = 15583 + nla_get_flag(attrs[NL80211_NAN_CONF_NOTIFY_DW]); 15584 + 15585 + out: 15586 + if (!conf->band_cfgs[NL80211_BAND_5GHZ].chan && 15587 + (!conf->bands || conf->bands & BIT(NL80211_BAND_5GHZ))) { 15588 + /* If no 5GHz channel is specified use default, if possible */ 15589 + conf->band_cfgs[NL80211_BAND_5GHZ].chan = 15590 + nl80211_get_nan_channel(wiphy, 5745); 15591 + if (!conf->band_cfgs[NL80211_BAND_5GHZ].chan) 15592 + conf->band_cfgs[NL80211_BAND_5GHZ].chan = 15593 + nl80211_get_nan_channel(wiphy, 5220); 15594 + 15595 + /* Return error if user space asked explicitly for 5 GHz */ 15596 + if (!conf->band_cfgs[NL80211_BAND_5GHZ].chan && 15597 + conf->bands & BIT(NL80211_BAND_5GHZ)) { 15598 + NL_SET_ERR_MSG_ATTR(info->extack, 15599 + info->attrs[NL80211_ATTR_BANDS], 15600 + "5 GHz band operation is not allowed"); 15601 + return -EINVAL; 15602 + } 15603 + } 15604 + 15605 + if (changed_flags) 15606 + *changed_flags = changed; 15607 + 15608 + return 0; 15609 + } 15610 + 15489 15611 static int nl80211_start_nan(struct sk_buff *skb, struct genl_info *info) 15490 15612 { 15491 15613 struct cfg80211_registered_device *rdev = info->user_ptr[0]; ··· 15712 15414 if (rfkill_blocked(rdev->wiphy.rfkill)) 15713 15415 return -ERFKILL; 15714 15416 15417 + /* Master preference is mandatory for START_NAN */ 15715 15418 if (!info->attrs[NL80211_ATTR_NAN_MASTER_PREF]) 15716 15419 return -EINVAL; 15717 15420 15718 - conf.master_pref = 15719 - nla_get_u8(info->attrs[NL80211_ATTR_NAN_MASTER_PREF]); 15720 - 15721 - if (info->attrs[NL80211_ATTR_BANDS]) { 15722 - u32 bands = nla_get_u32(info->attrs[NL80211_ATTR_BANDS]); 15723 - 15724 - if (bands & ~(u32)wdev->wiphy->nan_supported_bands) 15725 - return -EOPNOTSUPP; 15726 - 15727 - if (bands && !(bands & BIT(NL80211_BAND_2GHZ))) 15728 - return -EINVAL; 15729 - 15730 - conf.bands = bands; 15731 - } 15421 + err = nl80211_parse_nan_conf(&rdev->wiphy, info, &conf, NULL); 15422 + if (err) 15423 + return err; 15732 15424 15733 15425 err = rdev_start_nan(rdev, wdev, &conf); 15734 15426 if (err) ··· 16074 15786 struct wireless_dev *wdev = info->user_ptr[1]; 16075 15787 struct cfg80211_nan_conf conf = {}; 16076 15788 u32 changed = 0; 15789 + int err; 16077 15790 16078 15791 if (wdev->iftype != NL80211_IFTYPE_NAN) 16079 15792 return -EOPNOTSUPP; ··· 16082 15793 if (!wdev_running(wdev)) 16083 15794 return -ENOTCONN; 16084 15795 16085 - if (info->attrs[NL80211_ATTR_NAN_MASTER_PREF]) { 16086 - conf.master_pref = 16087 - nla_get_u8(info->attrs[NL80211_ATTR_NAN_MASTER_PREF]); 16088 - if (conf.master_pref <= 1 || conf.master_pref == 255) 16089 - return -EINVAL; 16090 - 16091 - changed |= CFG80211_NAN_CONF_CHANGED_PREF; 16092 - } 16093 - 16094 - if (info->attrs[NL80211_ATTR_BANDS]) { 16095 - u32 bands = nla_get_u32(info->attrs[NL80211_ATTR_BANDS]); 16096 - 16097 - if (bands & ~(u32)wdev->wiphy->nan_supported_bands) 16098 - return -EOPNOTSUPP; 16099 - 16100 - if (bands && !(bands & BIT(NL80211_BAND_2GHZ))) 16101 - return -EINVAL; 16102 - 16103 - conf.bands = bands; 16104 - changed |= CFG80211_NAN_CONF_CHANGED_BANDS; 16105 - } 15796 + err = nl80211_parse_nan_conf(&rdev->wiphy, info, &conf, &changed); 15797 + if (err) 15798 + return err; 16106 15799 16107 15800 if (!changed) 16108 15801 return -EINVAL; ··· 21806 21535 nlmsg_free(msg); 21807 21536 } 21808 21537 EXPORT_SYMBOL(cfg80211_epcs_changed); 21538 + 21539 + void cfg80211_next_nan_dw_notif(struct wireless_dev *wdev, 21540 + struct ieee80211_channel *chan, gfp_t gfp) 21541 + { 21542 + struct wiphy *wiphy = wdev->wiphy; 21543 + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); 21544 + struct sk_buff *msg; 21545 + void *hdr; 21546 + 21547 + trace_cfg80211_next_nan_dw_notif(wdev, chan); 21548 + 21549 + if (!wdev->owner_nlportid) 21550 + return; 21551 + 21552 + msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); 21553 + if (!msg) 21554 + return; 21555 + 21556 + hdr = nl80211hdr_put(msg, 0, 0, 0, 21557 + NL80211_CMD_NAN_NEXT_DW_NOTIFICATION); 21558 + if (!hdr) 21559 + goto nla_put_failure; 21560 + 21561 + if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || 21562 + nla_put_u64_64bit(msg, NL80211_ATTR_WDEV, wdev_id(wdev), 21563 + NL80211_ATTR_PAD) || 21564 + nla_put_u32(msg, NL80211_ATTR_WIPHY_FREQ, chan->center_freq)) 21565 + goto nla_put_failure; 21566 + 21567 + genlmsg_end(msg, hdr); 21568 + 21569 + genlmsg_unicast(wiphy_net(wiphy), msg, wdev->owner_nlportid); 21570 + 21571 + return; 21572 + 21573 + nla_put_failure: 21574 + nlmsg_free(msg); 21575 + } 21576 + EXPORT_SYMBOL(cfg80211_next_nan_dw_notif); 21577 + 21578 + void cfg80211_nan_cluster_joined(struct wireless_dev *wdev, 21579 + const u8 *cluster_id, bool new_cluster, 21580 + gfp_t gfp) 21581 + { 21582 + struct wiphy *wiphy = wdev->wiphy; 21583 + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); 21584 + struct sk_buff *msg; 21585 + void *hdr; 21586 + 21587 + trace_cfg80211_nan_cluster_joined(wdev, cluster_id, new_cluster); 21588 + 21589 + memcpy(wdev->u.nan.cluster_id, cluster_id, ETH_ALEN); 21590 + 21591 + msg = nlmsg_new(NLMSG_DEFAULT_SIZE, gfp); 21592 + if (!msg) 21593 + return; 21594 + 21595 + hdr = nl80211hdr_put(msg, 0, 0, 0, NL80211_CMD_NAN_CLUSTER_JOINED); 21596 + if (!hdr) 21597 + goto nla_put_failure; 21598 + 21599 + if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || 21600 + nla_put_u64_64bit(msg, NL80211_ATTR_WDEV, wdev_id(wdev), 21601 + NL80211_ATTR_PAD) || 21602 + nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, cluster_id) || 21603 + (new_cluster && nla_put_flag(msg, NL80211_ATTR_NAN_NEW_CLUSTER))) 21604 + goto nla_put_failure; 21605 + 21606 + genlmsg_end(msg, hdr); 21607 + 21608 + if (!wdev->owner_nlportid) 21609 + genlmsg_multicast_netns(&nl80211_fam, wiphy_net(wiphy), 21610 + msg, 0, NL80211_MCGRP_NAN, gfp); 21611 + else 21612 + genlmsg_unicast(wiphy_net(wiphy), msg, 21613 + wdev->owner_nlportid); 21614 + return; 21615 + 21616 + nla_put_failure: 21617 + nlmsg_free(msg); 21618 + } 21619 + EXPORT_SYMBOL(cfg80211_nan_cluster_joined); 21809 21620 21810 21621 /* initialisation/exit functions */ 21811 21622

+22 -52

net/wireless/reg.c

··· 1707 1707 if (reg_rule->flags & NL80211_RRF_AUTO_BW) 1708 1708 max_bandwidth_khz = reg_get_max_bandwidth(regd, reg_rule); 1709 1709 1710 + if (is_s1g) { 1711 + if (max_bandwidth_khz < MHZ_TO_KHZ(16)) 1712 + bw_flags |= IEEE80211_CHAN_NO_16MHZ; 1713 + if (max_bandwidth_khz < MHZ_TO_KHZ(8)) 1714 + bw_flags |= IEEE80211_CHAN_NO_8MHZ; 1715 + if (max_bandwidth_khz < MHZ_TO_KHZ(4)) 1716 + bw_flags |= IEEE80211_CHAN_NO_4MHZ; 1717 + return bw_flags; 1718 + } 1719 + 1710 1720 /* If we get a reg_rule we can assume that at least 5Mhz fit */ 1711 1721 if (!cfg80211_does_bw_fit_range(freq_range, 1712 1722 center_freq_khz, ··· 1727 1717 MHZ_TO_KHZ(20))) 1728 1718 bw_flags |= IEEE80211_CHAN_NO_20MHZ; 1729 1719 1730 - if (is_s1g) { 1731 - /* S1G is strict about non overlapping channels. We can 1732 - * calculate which bandwidth is allowed per channel by finding 1733 - * the largest bandwidth which cleanly divides the freq_range. 1734 - */ 1735 - int edge_offset; 1736 - int ch_bw = max_bandwidth_khz; 1720 + if (max_bandwidth_khz < MHZ_TO_KHZ(10)) 1721 + bw_flags |= IEEE80211_CHAN_NO_10MHZ; 1722 + if (max_bandwidth_khz < MHZ_TO_KHZ(20)) 1723 + bw_flags |= IEEE80211_CHAN_NO_20MHZ; 1724 + if (max_bandwidth_khz < MHZ_TO_KHZ(40)) 1725 + bw_flags |= IEEE80211_CHAN_NO_HT40; 1726 + if (max_bandwidth_khz < MHZ_TO_KHZ(80)) 1727 + bw_flags |= IEEE80211_CHAN_NO_80MHZ; 1728 + if (max_bandwidth_khz < MHZ_TO_KHZ(160)) 1729 + bw_flags |= IEEE80211_CHAN_NO_160MHZ; 1730 + if (max_bandwidth_khz < MHZ_TO_KHZ(320)) 1731 + bw_flags |= IEEE80211_CHAN_NO_320MHZ; 1737 1732 1738 - while (ch_bw) { 1739 - edge_offset = (center_freq_khz - ch_bw / 2) - 1740 - freq_range->start_freq_khz; 1741 - if (edge_offset % ch_bw == 0) { 1742 - switch (KHZ_TO_MHZ(ch_bw)) { 1743 - case 1: 1744 - bw_flags |= IEEE80211_CHAN_1MHZ; 1745 - break; 1746 - case 2: 1747 - bw_flags |= IEEE80211_CHAN_2MHZ; 1748 - break; 1749 - case 4: 1750 - bw_flags |= IEEE80211_CHAN_4MHZ; 1751 - break; 1752 - case 8: 1753 - bw_flags |= IEEE80211_CHAN_8MHZ; 1754 - break; 1755 - case 16: 1756 - bw_flags |= IEEE80211_CHAN_16MHZ; 1757 - break; 1758 - default: 1759 - /* If we got here, no bandwidths fit on 1760 - * this frequency, ie. band edge. 1761 - */ 1762 - bw_flags |= IEEE80211_CHAN_DISABLED; 1763 - break; 1764 - } 1765 - break; 1766 - } 1767 - ch_bw /= 2; 1768 - } 1769 - } else { 1770 - if (max_bandwidth_khz < MHZ_TO_KHZ(10)) 1771 - bw_flags |= IEEE80211_CHAN_NO_10MHZ; 1772 - if (max_bandwidth_khz < MHZ_TO_KHZ(20)) 1773 - bw_flags |= IEEE80211_CHAN_NO_20MHZ; 1774 - if (max_bandwidth_khz < MHZ_TO_KHZ(40)) 1775 - bw_flags |= IEEE80211_CHAN_NO_HT40; 1776 - if (max_bandwidth_khz < MHZ_TO_KHZ(80)) 1777 - bw_flags |= IEEE80211_CHAN_NO_80MHZ; 1778 - if (max_bandwidth_khz < MHZ_TO_KHZ(160)) 1779 - bw_flags |= IEEE80211_CHAN_NO_160MHZ; 1780 - if (max_bandwidth_khz < MHZ_TO_KHZ(320)) 1781 - bw_flags |= IEEE80211_CHAN_NO_320MHZ; 1782 - } 1783 1733 return bw_flags; 1784 1734 } 1785 1735

+35

net/wireless/trace.h

··· 4166 4166 WDEV_PR_ARG, __entry->enabled) 4167 4167 ); 4168 4168 4169 + TRACE_EVENT(cfg80211_next_nan_dw_notif, 4170 + TP_PROTO(struct wireless_dev *wdev, 4171 + struct ieee80211_channel *chan), 4172 + TP_ARGS(wdev, chan), 4173 + TP_STRUCT__entry( 4174 + WDEV_ENTRY 4175 + CHAN_ENTRY 4176 + ), 4177 + TP_fast_assign( 4178 + WDEV_ASSIGN; 4179 + CHAN_ASSIGN(chan); 4180 + ), 4181 + TP_printk(WDEV_PR_FMT " " CHAN_PR_FMT, 4182 + WDEV_PR_ARG, CHAN_PR_ARG) 4183 + ); 4184 + 4185 + TRACE_EVENT(cfg80211_nan_cluster_joined, 4186 + TP_PROTO(struct wireless_dev *wdev, 4187 + const u8 *cluster_id, 4188 + bool new_cluster), 4189 + TP_ARGS(wdev, cluster_id, new_cluster), 4190 + TP_STRUCT__entry( 4191 + WDEV_ENTRY 4192 + MAC_ENTRY(cluster_id) 4193 + __field(bool, new_cluster) 4194 + ), 4195 + TP_fast_assign( 4196 + WDEV_ASSIGN; 4197 + MAC_ASSIGN(cluster_id, cluster_id); 4198 + __entry->new_cluster = new_cluster; 4199 + ), 4200 + TP_printk(WDEV_PR_FMT " cluster_id %pMF%s", 4201 + WDEV_PR_ARG, __entry->cluster_id, 4202 + __entry->new_cluster ? " [new]" : "") 4203 + ); 4169 4204 #endif /* !__RDEV_OPS_TRACE || TRACE_HEADER_MULTI_READ */ 4170 4205 4171 4206 #undef TRACE_INCLUDE_PATH

+1 -28

net/wireless/util.c

··· 106 106 } 107 107 EXPORT_SYMBOL(ieee80211_channel_to_freq_khz); 108 108 109 - enum nl80211_chan_width 110 - ieee80211_s1g_channel_width(const struct ieee80211_channel *chan) 111 - { 112 - if (WARN_ON(!chan || chan->band != NL80211_BAND_S1GHZ)) 113 - return NL80211_CHAN_WIDTH_20_NOHT; 114 - 115 - /*S1G defines a single allowed channel width per channel. 116 - * Extract that width here. 117 - */ 118 - if (chan->flags & IEEE80211_CHAN_1MHZ) 119 - return NL80211_CHAN_WIDTH_1; 120 - else if (chan->flags & IEEE80211_CHAN_2MHZ) 121 - return NL80211_CHAN_WIDTH_2; 122 - else if (chan->flags & IEEE80211_CHAN_4MHZ) 123 - return NL80211_CHAN_WIDTH_4; 124 - else if (chan->flags & IEEE80211_CHAN_8MHZ) 125 - return NL80211_CHAN_WIDTH_8; 126 - else if (chan->flags & IEEE80211_CHAN_16MHZ) 127 - return NL80211_CHAN_WIDTH_16; 128 - 129 - pr_err("unknown channel width for channel at %dKHz?\n", 130 - ieee80211_channel_to_khz(chan)); 131 - 132 - return NL80211_CHAN_WIDTH_1; 133 - } 134 - EXPORT_SYMBOL(ieee80211_s1g_channel_width); 135 - 136 109 int ieee80211_freq_khz_to_channel(u32 freq) 137 110 { 138 111 /* TODO: just handle MHz for now */ ··· 2965 2992 u32 freq, width; 2966 2993 2967 2994 freq = ieee80211_chandef_to_khz(chandef); 2968 - width = cfg80211_chandef_get_width(chandef); 2995 + width = MHZ_TO_KHZ(cfg80211_chandef_get_width(chandef)); 2969 2996 if (!ieee80211_radio_freq_range_valid(radio, freq, width)) 2970 2997 return false; 2971 2998

Configure Feed

Configure Feed