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drm/i915/display: Avoid use of VTOTAL.Vtotal bits

For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
bits are not required. Since the support for these bits is going to
be deprecated in upcoming platforms, avoid writing these bits for the
platforms that do not use legacy Timing Generator.

Since for these platforms vrr.vmin is always filled with crtc_vtotal,
use TRAN_VRR_VMIN to get the vtotal for adjusted_mode.

v2: Avoid having a helper for manipulating VTOTAL register, and instead
just make the change where required. (Ville)
v3: Set crtc_vtotal instead of working with the bits directly (Ville).
Use intel_vrr_vmin_vtotal() to set the vtotal during readout. (Ville)
v4: Keep the reading part unchanged, and let it get overwritten for
cases where we use vrr.vmin. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250327144629.648306-3-ankit.k.nautiyal@intel.com

Ankit Nautiyal 94f60899 7a6bf54c

+28
+18
drivers/gpu/drm/i915/display/intel_display.c
··· 2698 2698 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2699 2699 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2700 2700 2701 + /* 2702 + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2703 + * bits are not required. Since the support for these bits is going to 2704 + * be deprecated in upcoming platforms, avoid writing these bits for the 2705 + * platforms that do not use legacy Timing Generator. 2706 + */ 2707 + if (intel_vrr_always_use_vrr_tg(display)) 2708 + crtc_vtotal = 1; 2709 + 2701 2710 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 2702 2711 VACTIVE(crtc_vdisplay - 1) | 2703 2712 VTOTAL(crtc_vtotal - 1)); ··· 2767 2758 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 2768 2759 VBLANK_START(crtc_vblank_start - 1) | 2769 2760 VBLANK_END(crtc_vblank_end - 1)); 2761 + /* 2762 + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2763 + * bits are not required. Since the support for these bits is going to 2764 + * be deprecated in upcoming platforms, avoid writing these bits for the 2765 + * platforms that do not use legacy Timing Generator. 2766 + */ 2767 + if (intel_vrr_always_use_vrr_tg(display)) 2768 + crtc_vtotal = 1; 2769 + 2770 2770 /* 2771 2771 * The double buffer latch point for TRANS_VTOTAL 2772 2772 * is the transcoder's undelayed vblank.
+10
drivers/gpu/drm/i915/display/intel_vrr.c
··· 708 708 crtc_state->vrr.vmin = intel_de_read(display, 709 709 TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; 710 710 711 + /* 712 + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 713 + * bits are not filled. Since for these platforms TRAN_VMIN is always 714 + * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for 715 + * adjusted_mode. 716 + */ 717 + if (intel_vrr_always_use_vrr_tg(display)) 718 + crtc_state->hw.adjusted_mode.crtc_vtotal = 719 + intel_vrr_vmin_vtotal(crtc_state); 720 + 711 721 if (HAS_AS_SDP(display)) { 712 722 trans_vrr_vsync = 713 723 intel_de_read(display,