Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
perf vendor events: Add/update sierraforest events/metrics
Update events from v1.02 to v1.04.
Add TMA metrics v4.8.
Bring in the event updates v1.04:
https://github.com/intel/perfmon/commit/0a9546cdf63c8b07f5c33ebf6fe49e6ebec89f86
v1.03:
https://github.com/intel/perfmon/commit/c7dd26ce67ca4477d40fb4b55b6baa0584b3e5d6
The TMA 4.8 information was added in:
https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9a5736
Add counter information. The most recent RFC patch set using this
information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
New events are:
FP_INST_RETIRED.128B_DP,
FP_INST_RETIRED.128B_SP,
FP_INST_RETIRED.256B_DP,
FP_INST_RETIRED.32B_SP,
FP_INST_RETIRED.64B_DP,
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM,
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD,
OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM,
OCR.STREAMING_WR.ANY_RESPONSE,
UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL,
UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE,
UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL,
UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE,
UNC_CHA_TOR_INSERTS.IO_MISS,
UNC_CHA_TOR_INSERTS.IO_MISS_ITOM,
UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR,
UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL,
UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE,
UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA,
UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-30-irogers@google.com
authored by
Ian Rogers
Weilin Wang
Caleb Biggers
and committed by
Namhyung Kim
951bf72a
5ecf682e
+2414
-102
+1
-1
tools/perf/pmu-events/arch/x86/mapfile.csv
+1
-1
tools/perf/pmu-events/arch/x86/mapfile.csv
···
27
27
GenuineIntel-6-A7,v1.03,rocketlake,core
28
28
GenuineIntel-6-2A,v19,sandybridge,core
29
29
GenuineIntel-6-8F,v1.23,sapphirerapids,core
30
-
GenuineIntel-6-AF,v1.02,sierraforest,core
30
+
GenuineIntel-6-AF,v1.04,sierraforest,core
31
31
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
32
32
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core
33
33
GenuineIntel-6-55-[01234],v1.33,skylakex,core
+71
-26
tools/perf/pmu-events/arch/x86/sierraforest/cache.json
+71
-26
tools/perf/pmu-events/arch/x86/sierraforest/cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"EventCode": "0x2e",
5
6
"EventName": "LONGEST_LAT_CACHE.MISS",
6
-
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
7
+
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
7
8
"SampleAfterValue": "200003",
8
9
"UMask": "0x41"
9
10
},
10
11
{
11
12
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
13
+
"Counter": "0,1,2,3,4,5,6,7",
12
14
"EventCode": "0x2e",
13
15
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
14
-
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
16
+
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
15
17
"SampleAfterValue": "200003",
16
18
"UMask": "0x4f"
17
19
},
18
20
{
19
21
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.",
22
+
"Counter": "0,1,2,3,4,5,6,7",
20
23
"EventCode": "0x35",
21
24
"EventName": "MEM_BOUND_STALLS_IFETCH.ALL",
22
25
"SampleAfterValue": "1000003",
···
27
24
},
28
25
{
29
26
"BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
27
+
"Counter": "0,1,2,3,4,5,6,7",
30
28
"EventCode": "0x35",
31
29
"EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT",
32
30
"PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
···
36
32
},
37
33
{
38
34
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC.",
35
+
"Counter": "0,1,2,3,4,5,6,7",
39
36
"EventCode": "0x35",
40
37
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT",
41
38
"SampleAfterValue": "1000003",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.",
42
+
"Counter": "0,1,2,3,4,5,6,7",
47
43
"EventCode": "0x35",
48
44
"EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS",
49
45
"SampleAfterValue": "1000003",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
49
+
"Counter": "0,1,2,3,4,5,6,7",
55
50
"EventCode": "0x34",
56
51
"EventName": "MEM_BOUND_STALLS_LOAD.ALL",
57
52
"SampleAfterValue": "1000003",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
56
+
"Counter": "0,1,2,3,4,5,6,7",
63
57
"EventCode": "0x34",
64
58
"EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT",
65
59
"PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
···
69
61
},
70
62
{
71
63
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.",
64
+
"Counter": "0,1,2,3,4,5,6,7",
72
65
"EventCode": "0x34",
73
66
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT",
74
67
"SampleAfterValue": "1000003",
···
77
68
},
78
69
{
79
70
"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.",
71
+
"Counter": "0,1,2,3,4,5,6,7",
80
72
"EventCode": "0x34",
81
73
"EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS",
82
74
"SampleAfterValue": "1000003",
···
85
75
},
86
76
{
87
77
"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
78
+
"Counter": "0,1,2,3,4,5,6,7",
88
79
"EventCode": "0xd3",
89
80
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
90
-
"PEBS": "1",
91
81
"SampleAfterValue": "1000003",
92
82
"UMask": "0x1"
93
83
},
94
84
{
95
85
"BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
86
+
"Counter": "0,1,2,3,4,5,6,7",
96
87
"EventCode": "0xd1",
97
88
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
98
-
"PEBS": "1",
99
89
"SampleAfterValue": "200003",
100
90
"UMask": "0x1"
101
91
},
102
92
{
103
93
"BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
94
+
"Counter": "0,1,2,3,4,5,6,7",
104
95
"EventCode": "0xd1",
105
96
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
106
-
"PEBS": "1",
107
97
"SampleAfterValue": "200003",
108
98
"UMask": "0x40"
109
99
},
110
100
{
111
101
"BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
102
+
"Counter": "0,1,2,3,4,5,6,7",
112
103
"EventCode": "0xd1",
113
104
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
114
-
"PEBS": "1",
115
105
"SampleAfterValue": "200003",
116
106
"UMask": "0x2"
117
107
},
118
108
{
119
109
"BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.",
110
+
"Counter": "0,1,2,3,4,5,6,7",
120
111
"EventCode": "0xd1",
121
112
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
122
-
"PEBS": "1",
123
113
"SampleAfterValue": "200003",
124
114
"UMask": "0x80"
125
115
},
126
116
{
127
117
"BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
118
+
"Counter": "0,1,2,3,4,5,6,7",
128
119
"EventCode": "0xd1",
129
120
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
130
-
"PEBS": "1",
131
121
"SampleAfterValue": "200003",
132
122
"UMask": "0x1c"
133
123
},
134
124
{
135
125
"BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.",
126
+
"Counter": "0,1,2,3,4,5,6,7",
136
127
"EventCode": "0xd1",
137
128
"EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
138
-
"PEBS": "1",
139
129
"SampleAfterValue": "200003",
140
130
"UMask": "0x20"
141
131
},
142
132
{
143
133
"BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
134
+
"Counter": "0,1,2,3,4,5,6,7",
144
135
"EventCode": "0x04",
145
136
"EventName": "MEM_SCHEDULER_BLOCK.ALL",
146
137
"SampleAfterValue": "20003",
···
149
138
},
150
139
{
151
140
"BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
141
+
"Counter": "0,1,2,3,4,5,6,7",
152
142
"EventCode": "0x04",
153
143
"EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
154
144
"SampleAfterValue": "20003",
···
157
145
},
158
146
{
159
147
"BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
148
+
"Counter": "0,1,2,3,4,5,6,7",
160
149
"EventCode": "0x04",
161
150
"EventName": "MEM_SCHEDULER_BLOCK.RSV",
162
151
"SampleAfterValue": "20003",
···
165
152
},
166
153
{
167
154
"BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
155
+
"Counter": "0,1,2,3,4,5,6,7",
168
156
"EventCode": "0x04",
169
157
"EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
170
158
"SampleAfterValue": "20003",
···
173
159
},
174
160
{
175
161
"BriefDescription": "Counts the number of load ops retired.",
162
+
"Counter": "0,1,2,3,4,5,6,7",
176
163
"Data_LA": "1",
177
164
"EventCode": "0xd0",
178
165
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
179
-
"PEBS": "1",
180
166
"SampleAfterValue": "200003",
181
167
"UMask": "0x81"
182
168
},
183
169
{
184
170
"BriefDescription": "Counts the number of store ops retired.",
171
+
"Counter": "0,1,2,3,4,5,6,7",
185
172
"Data_LA": "1",
186
173
"EventCode": "0xd0",
187
174
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
188
-
"PEBS": "1",
189
175
"SampleAfterValue": "200003",
190
176
"UMask": "0x82"
191
177
},
192
178
{
193
179
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
180
+
"Counter": "0,1",
194
181
"Data_LA": "1",
195
182
"EventCode": "0xd0",
196
183
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
197
184
"MSRIndex": "0x3F6",
198
185
"MSRValue": "0x400",
199
-
"PEBS": "2",
200
186
"SampleAfterValue": "1000003",
201
187
"UMask": "0x5"
202
188
},
203
189
{
204
190
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
191
+
"Counter": "0,1",
205
192
"Data_LA": "1",
206
193
"EventCode": "0xd0",
207
194
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
208
195
"MSRIndex": "0x3F6",
209
196
"MSRValue": "0x80",
210
-
"PEBS": "2",
211
197
"SampleAfterValue": "1000003",
212
198
"UMask": "0x5"
213
199
},
214
200
{
215
201
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
202
+
"Counter": "0,1",
216
203
"Data_LA": "1",
217
204
"EventCode": "0xd0",
218
205
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
219
206
"MSRIndex": "0x3F6",
220
207
"MSRValue": "0x10",
221
-
"PEBS": "2",
222
208
"SampleAfterValue": "1000003",
223
209
"UMask": "0x5"
224
210
},
225
211
{
226
212
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
213
+
"Counter": "0,1",
227
214
"Data_LA": "1",
228
215
"EventCode": "0xd0",
229
216
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
230
217
"MSRIndex": "0x3F6",
231
218
"MSRValue": "0x800",
232
-
"PEBS": "2",
233
219
"SampleAfterValue": "1000003",
234
220
"UMask": "0x5"
235
221
},
236
222
{
237
223
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
224
+
"Counter": "0,1",
238
225
"Data_LA": "1",
239
226
"EventCode": "0xd0",
240
227
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
241
228
"MSRIndex": "0x3F6",
242
229
"MSRValue": "0x100",
243
-
"PEBS": "2",
244
230
"SampleAfterValue": "1000003",
245
231
"UMask": "0x5"
246
232
},
247
233
{
248
234
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
235
+
"Counter": "0,1",
249
236
"Data_LA": "1",
250
237
"EventCode": "0xd0",
251
238
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
252
239
"MSRIndex": "0x3F6",
253
240
"MSRValue": "0x20",
254
-
"PEBS": "2",
255
241
"SampleAfterValue": "1000003",
256
242
"UMask": "0x5"
257
243
},
258
244
{
259
245
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
246
+
"Counter": "0,1",
260
247
"Data_LA": "1",
261
248
"EventCode": "0xd0",
262
249
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
263
250
"MSRIndex": "0x3F6",
264
251
"MSRValue": "0x4",
265
-
"PEBS": "2",
266
252
"SampleAfterValue": "1000003",
267
253
"UMask": "0x5"
268
254
},
269
255
{
270
256
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
257
+
"Counter": "0,1",
271
258
"Data_LA": "1",
272
259
"EventCode": "0xd0",
273
260
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
274
261
"MSRIndex": "0x3F6",
275
262
"MSRValue": "0x200",
276
-
"PEBS": "2",
277
263
"SampleAfterValue": "1000003",
278
264
"UMask": "0x5"
279
265
},
280
266
{
281
267
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
268
+
"Counter": "0,1",
282
269
"Data_LA": "1",
283
270
"EventCode": "0xd0",
284
271
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
285
272
"MSRIndex": "0x3F6",
286
273
"MSRValue": "0x40",
287
-
"PEBS": "2",
288
274
"SampleAfterValue": "1000003",
289
275
"UMask": "0x5"
290
276
},
291
277
{
292
278
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
279
+
"Counter": "0,1",
293
280
"Data_LA": "1",
294
281
"EventCode": "0xd0",
295
282
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
296
283
"MSRIndex": "0x3F6",
297
284
"MSRValue": "0x8",
298
-
"PEBS": "2",
299
285
"SampleAfterValue": "1000003",
300
286
"UMask": "0x5"
301
287
},
302
288
{
303
289
"BriefDescription": "Counts the number of load uops retired that performed one or more locks",
290
+
"Counter": "0,1,2,3,4,5,6,7",
304
291
"Data_LA": "1",
305
292
"EventCode": "0xd0",
306
293
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
307
-
"PEBS": "1",
308
294
"SampleAfterValue": "200003",
309
295
"UMask": "0x21"
310
296
},
311
297
{
312
298
"BriefDescription": "Counts the number of memory uops retired that were splits.",
299
+
"Counter": "0,1,2,3,4,5,6,7",
313
300
"Data_LA": "1",
314
301
"EventCode": "0xd0",
315
302
"EventName": "MEM_UOPS_RETIRED.SPLIT",
316
-
"PEBS": "1",
317
303
"SampleAfterValue": "200003",
318
304
"UMask": "0x43"
319
305
},
320
306
{
321
307
"BriefDescription": "Counts the number of retired split load uops.",
308
+
"Counter": "0,1,2,3,4,5,6,7",
322
309
"Data_LA": "1",
323
310
"EventCode": "0xd0",
324
311
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
325
-
"PEBS": "1",
326
312
"SampleAfterValue": "200003",
327
313
"UMask": "0x41"
328
314
},
329
315
{
330
316
"BriefDescription": "Counts the number of retired split store uops.",
317
+
"Counter": "0,1,2,3,4,5,6,7",
331
318
"Data_LA": "1",
332
319
"EventCode": "0xd0",
333
320
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
334
-
"PEBS": "1",
335
321
"SampleAfterValue": "200003",
336
322
"UMask": "0x42"
337
323
},
338
324
{
339
325
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
326
+
"Counter": "0,1,2,3,4,5,6,7",
340
327
"Data_LA": "1",
341
328
"EventCode": "0xd0",
342
329
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
343
-
"PEBS": "2",
344
330
"SampleAfterValue": "1000003",
345
331
"UMask": "0x6"
346
332
},
347
333
{
334
+
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
335
+
"Counter": "0,1,2,3,4,5,6,7",
336
+
"EventCode": "0xB7",
337
+
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
338
+
"MSRIndex": "0x1a6,0x1a7",
339
+
"MSRValue": "0x10003C0001",
340
+
"SampleAfterValue": "100003",
341
+
"UMask": "0x1"
342
+
},
343
+
{
344
+
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",
345
+
"Counter": "0,1,2,3,4,5,6,7",
346
+
"EventCode": "0xB7",
347
+
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
348
+
"MSRIndex": "0x1a6,0x1a7",
349
+
"MSRValue": "0x8003C0001",
350
+
"SampleAfterValue": "100003",
351
+
"UMask": "0x1"
352
+
},
353
+
{
354
+
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
355
+
"Counter": "0,1,2,3,4,5,6,7",
356
+
"EventCode": "0xB7",
357
+
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
358
+
"MSRIndex": "0x1a6,0x1a7",
359
+
"MSRValue": "0x10003C0002",
360
+
"SampleAfterValue": "100003",
361
+
"UMask": "0x1"
362
+
},
363
+
{
348
364
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss",
365
+
"Counter": "0,1,2,3,4,5,6,7",
349
366
"EventCode": "0x71",
350
367
"EventName": "TOPDOWN_FE_BOUND.ICACHE",
351
368
"SampleAfterValue": "1000003",
+77
tools/perf/pmu-events/arch/x86/sierraforest/counter.json
+77
tools/perf/pmu-events/arch/x86/sierraforest/counter.json
···
1
+
[
2
+
{
3
+
"Unit": "core",
4
+
"CountersNumFixed": "3",
5
+
"CountersNumGeneric": "8"
6
+
},
7
+
{
8
+
"Unit": "B2CMI",
9
+
"CountersNumFixed": "0",
10
+
"CountersNumGeneric": "4"
11
+
},
12
+
{
13
+
"Unit": "CHA",
14
+
"CountersNumFixed": "0",
15
+
"CountersNumGeneric": "4"
16
+
},
17
+
{
18
+
"Unit": "IMC",
19
+
"CountersNumFixed": "0",
20
+
"CountersNumGeneric": "4"
21
+
},
22
+
{
23
+
"Unit": "B2HOT",
24
+
"CountersNumFixed": "0",
25
+
"CountersNumGeneric": 4
26
+
},
27
+
{
28
+
"Unit": "IIO",
29
+
"CountersNumFixed": "0",
30
+
"CountersNumGeneric": "4"
31
+
},
32
+
{
33
+
"Unit": "IRP",
34
+
"CountersNumFixed": "0",
35
+
"CountersNumGeneric": "4"
36
+
},
37
+
{
38
+
"Unit": "UPI",
39
+
"CountersNumFixed": "0",
40
+
"CountersNumGeneric": "4"
41
+
},
42
+
{
43
+
"Unit": "B2UPI",
44
+
"CountersNumFixed": "0",
45
+
"CountersNumGeneric": 4
46
+
},
47
+
{
48
+
"Unit": "B2CXL",
49
+
"CountersNumFixed": "0",
50
+
"CountersNumGeneric": 4
51
+
},
52
+
{
53
+
"Unit": "PCU",
54
+
"CountersNumFixed": "0",
55
+
"CountersNumGeneric": 4
56
+
},
57
+
{
58
+
"Unit": "CHACMS",
59
+
"CountersNumFixed": "0",
60
+
"CountersNumGeneric": 4
61
+
},
62
+
{
63
+
"Unit": "MDF",
64
+
"CountersNumFixed": "0",
65
+
"CountersNumGeneric": 4
66
+
},
67
+
{
68
+
"Unit": "CXLCM",
69
+
"CountersNumFixed": "0",
70
+
"CountersNumGeneric": 8
71
+
},
72
+
{
73
+
"Unit": "CXLDP",
74
+
"CountersNumFixed": "0",
75
+
"CountersNumGeneric": 4
76
+
}
77
+
]
+48
-6
tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json
+48
-6
tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"CounterMask": "1",
5
6
"EventCode": "0xcd",
6
7
"EventName": "ARITH.FPDIV_ACTIVE",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting",
12
+
"Counter": "0,1,2,3,4,5,6,7",
13
13
"EventCode": "0xc8",
14
14
"EventName": "FP_FLOPS_RETIRED.ALL",
15
-
"PEBS": "1",
16
15
"SampleAfterValue": "1000003",
17
16
"UMask": "0x3"
18
17
},
19
18
{
20
19
"BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]",
20
+
"Counter": "0,1,2,3,4,5,6,7",
21
21
"Deprecated": "1",
22
22
"EventCode": "0xc8",
23
23
"EventName": "FP_FLOPS_RETIRED.DP",
24
-
"PEBS": "1",
25
24
"SampleAfterValue": "1000003",
26
25
"UMask": "0x1"
27
26
},
28
27
{
29
28
"BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]",
29
+
"Counter": "0,1,2,3,4,5,6,7",
30
30
"EventCode": "0xc8",
31
31
"EventName": "FP_FLOPS_RETIRED.FP32",
32
-
"PEBS": "1",
33
32
"SampleAfterValue": "1000003",
34
33
"UMask": "0x2"
35
34
},
36
35
{
37
36
"BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]",
37
+
"Counter": "0,1,2,3,4,5,6,7",
38
38
"EventCode": "0xc8",
39
39
"EventName": "FP_FLOPS_RETIRED.FP64",
40
-
"PEBS": "1",
41
40
"SampleAfterValue": "1000003",
42
41
"UMask": "0x1"
43
42
},
44
43
{
45
44
"BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]",
45
+
"Counter": "0,1,2,3,4,5,6,7",
46
46
"Deprecated": "1",
47
47
"EventCode": "0xc8",
48
48
"EventName": "FP_FLOPS_RETIRED.SP",
49
-
"PEBS": "1",
49
+
"SampleAfterValue": "1000003",
50
+
"UMask": "0x2"
51
+
},
52
+
{
53
+
"BriefDescription": "Counts the total number of floating point retired instructions.",
54
+
"Counter": "0,1,2,3,4,5,6,7",
55
+
"EventCode": "0xc7",
56
+
"EventName": "FP_INST_RETIRED.128B_DP",
57
+
"SampleAfterValue": "1000003",
58
+
"UMask": "0x8"
59
+
},
60
+
{
61
+
"BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.",
62
+
"Counter": "0,1,2,3,4,5,6,7",
63
+
"EventCode": "0xc7",
64
+
"EventName": "FP_INST_RETIRED.128B_SP",
65
+
"SampleAfterValue": "1000003",
66
+
"UMask": "0x4"
67
+
},
68
+
{
69
+
"BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.",
70
+
"Counter": "0,1,2,3,4,5,6,7",
71
+
"EventCode": "0xc7",
72
+
"EventName": "FP_INST_RETIRED.256B_DP",
73
+
"SampleAfterValue": "1000003",
74
+
"UMask": "0x20"
75
+
},
76
+
{
77
+
"BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.",
78
+
"Counter": "0,1,2,3,4,5,6,7",
79
+
"EventCode": "0xc7",
80
+
"EventName": "FP_INST_RETIRED.32B_SP",
81
+
"SampleAfterValue": "1000003",
82
+
"UMask": "0x1"
83
+
},
84
+
{
85
+
"BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.",
86
+
"Counter": "0,1,2,3,4,5,6,7",
87
+
"EventCode": "0xc7",
88
+
"EventName": "FP_INST_RETIRED.64B_DP",
50
89
"SampleAfterValue": "1000003",
51
90
"UMask": "0x2"
52
91
},
53
92
{
54
93
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
94
+
"Counter": "0,1,2,3,4,5,6,7",
55
95
"EventCode": "0xc3",
56
96
"EventName": "MACHINE_CLEARS.FP_ASSIST",
57
97
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
···
101
59
},
102
60
{
103
61
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
62
+
"Counter": "0,1,2,3,4,5,6,7",
104
63
"EventCode": "0xc2",
105
64
"EventName": "UOPS_RETIRED.FPDIV",
106
-
"PEBS": "1",
107
65
"SampleAfterValue": "2000003",
108
66
"UMask": "0x8"
109
67
}
+4
-1
tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
+4
-1
tools/perf/pmu-events/arch/x86/sierraforest/frontend.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"EventCode": "0xe6",
5
6
"EventName": "BACLEARS.ANY",
6
7
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
12
+
"Counter": "0,1,2,3,4,5,6,7",
13
13
"EventCode": "0xc6",
14
14
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
15
-
"PEBS": "1",
16
15
"SampleAfterValue": "1000003",
17
16
"UMask": "0x10"
18
17
},
19
18
{
20
19
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
20
+
"Counter": "0,1,2,3,4,5,6,7",
21
21
"EventCode": "0x80",
22
22
"EventName": "ICACHE.ACCESSES",
23
23
"SampleAfterValue": "200003",
···
26
24
},
27
25
{
28
26
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
27
+
"Counter": "0,1,2,3,4,5,6,7",
29
28
"EventCode": "0x80",
30
29
"EventName": "ICACHE.MISSES",
31
30
"SampleAfterValue": "200003",
+11
-2
tools/perf/pmu-events/arch/x86/sierraforest/memory.json
+11
-2
tools/perf/pmu-events/arch/x86/sierraforest/memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"EventCode": "0x05",
5
6
"EventName": "LD_HEAD.ANY_AT_RET",
6
7
"SampleAfterValue": "1000003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
11
+
"Counter": "0,1,2,3,4,5,6,7",
12
12
"EventCode": "0x05",
13
13
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
14
14
"SampleAfterValue": "1000003",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
18
+
"Counter": "0,1,2,3,4,5,6,7",
20
19
"EventCode": "0x05",
21
20
"EventName": "LD_HEAD.L1_MISS_AT_RET",
22
21
"SampleAfterValue": "1000003",
···
25
22
},
26
23
{
27
24
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
25
+
"Counter": "0,1,2,3,4,5,6,7",
28
26
"EventCode": "0x05",
29
27
"EventName": "LD_HEAD.OTHER_AT_RET",
30
28
"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
···
34
30
},
35
31
{
36
32
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
33
+
"Counter": "0,1,2,3,4,5,6,7",
37
34
"EventCode": "0x05",
38
35
"EventName": "LD_HEAD.PGWALK_AT_RET",
39
36
"SampleAfterValue": "1000003",
···
42
37
},
43
38
{
44
39
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
40
+
"Counter": "0,1,2,3,4,5,6,7",
45
41
"EventCode": "0x05",
46
42
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
47
43
"SampleAfterValue": "1000003",
···
50
44
},
51
45
{
52
46
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
47
+
"Counter": "0,1,2,3,4,5,6,7",
53
48
"EventCode": "0xc3",
54
49
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
55
50
"SampleAfterValue": "20003",
···
58
51
},
59
52
{
60
53
"BriefDescription": "Counts misaligned loads that are 4K page splits.",
54
+
"Counter": "0,1,2,3,4,5,6,7",
61
55
"EventCode": "0x13",
62
56
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
63
-
"PEBS": "1",
64
57
"SampleAfterValue": "200003",
65
58
"UMask": "0x2"
66
59
},
67
60
{
68
61
"BriefDescription": "Counts misaligned stores that are 4K page splits.",
62
+
"Counter": "0,1,2,3,4,5,6,7",
69
63
"EventCode": "0x13",
70
64
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
71
-
"PEBS": "1",
72
65
"SampleAfterValue": "200003",
73
66
"UMask": "0x4"
74
67
},
75
68
{
76
69
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
70
+
"Counter": "0,1,2,3,4,5,6,7",
77
71
"EventCode": "0xB7",
78
72
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
79
73
"MSRIndex": "0x1a6,0x1a7",
···
84
76
},
85
77
{
86
78
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
79
+
"Counter": "0,1,2,3,4,5,6,7",
87
80
"EventCode": "0xB7",
88
81
"EventName": "OCR.DEMAND_RFO.L3_MISS",
89
82
"MSRIndex": "0x1a6,0x1a7",
+23
tools/perf/pmu-events/arch/x86/sierraforest/metricgroups.json
+23
tools/perf/pmu-events/arch/x86/sierraforest/metricgroups.json
···
1
+
{
2
+
"Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
3
+
"Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
4
+
"Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
5
+
"Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
6
+
"Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
7
+
"Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
8
+
"TopdownL1": "Metrics for top-down breakdown at level 1",
9
+
"TopdownL2": "Metrics for top-down breakdown at level 2",
10
+
"TopdownL3": "Metrics for top-down breakdown at level 3",
11
+
"load_store_bound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
12
+
"tma_L1_group": "Metrics for top-down breakdown at level 1",
13
+
"tma_L2_group": "Metrics for top-down breakdown at level 2",
14
+
"tma_L3_group": "Metrics for top-down breakdown at level 3",
15
+
"tma_backend_bound_group": "Metrics contributing to tma_backend_bound category",
16
+
"tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",
17
+
"tma_core_bound_group": "Metrics contributing to tma_core_bound category",
18
+
"tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",
19
+
"tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_bandwidth category",
20
+
"tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latency category",
21
+
"tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",
22
+
"tma_resource_bound_group": "Metrics contributing to tma_resource_bound category"
23
+
}
+14
-1
tools/perf/pmu-events/arch/x86/sierraforest/other.json
+14
-1
tools/perf/pmu-events/arch/x86/sierraforest/other.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"Deprecated": "1",
5
6
"EventCode": "0xe4",
6
7
"EventName": "LBR_INSERTS.ANY",
7
-
"PEBS": "1",
8
8
"SampleAfterValue": "1000003",
9
9
"UMask": "0x1"
10
10
},
11
11
{
12
12
"BriefDescription": "Counts demand data reads that have any type of response.",
13
+
"Counter": "0,1,2,3,4,5,6,7",
13
14
"EventCode": "0xB7",
14
15
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
15
16
"MSRIndex": "0x1a6,0x1a7",
···
20
19
},
21
20
{
22
21
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
22
+
"Counter": "0,1,2,3,4,5,6,7",
23
23
"EventCode": "0xB7",
24
24
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
25
25
"MSRIndex": "0x1a6,0x1a7",
···
29
27
"UMask": "0x1"
30
28
},
31
29
{
30
+
"BriefDescription": "Counts streaming stores that have any type of response.",
31
+
"Counter": "0,1,2,3,4,5,6,7",
32
+
"EventCode": "0xB7",
33
+
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
34
+
"MSRIndex": "0x1a6,0x1a7",
35
+
"MSRValue": "0x10800",
36
+
"SampleAfterValue": "100003",
37
+
"UMask": "0x1"
38
+
},
39
+
{
32
40
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
41
+
"Counter": "0,1,2,3,4,5,6,7",
33
42
"EventCode": "0x75",
34
43
"EventName": "SERIALIZATION.C01_MS_SCB",
35
44
"SampleAfterValue": "200003",
+68
-29
tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
+68
-29
tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of cycles when any of the dividers are active.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"CounterMask": "1",
5
6
"EventCode": "0xcd",
6
7
"EventName": "ARITH.DIV_ACTIVE",
···
10
9
},
11
10
{
12
11
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
12
+
"Counter": "0,1,2,3,4,5,6,7",
13
13
"EventCode": "0xc4",
14
14
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
15
-
"PEBS": "1",
16
15
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
17
16
"SampleAfterValue": "200003"
18
17
},
19
18
{
20
19
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
20
+
"Counter": "0,1,2,3,4,5,6,7",
21
21
"EventCode": "0xc4",
22
22
"EventName": "BR_INST_RETIRED.COND",
23
-
"PEBS": "1",
24
23
"SampleAfterValue": "200003",
25
24
"UMask": "0x7e"
26
25
},
27
26
{
28
27
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
28
+
"Counter": "0,1,2,3,4,5,6,7",
29
29
"EventCode": "0xc4",
30
30
"EventName": "BR_INST_RETIRED.COND_TAKEN",
31
-
"PEBS": "1",
32
31
"SampleAfterValue": "200003",
33
32
"UMask": "0xfe"
34
33
},
35
34
{
36
35
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
36
+
"Counter": "0,1,2,3,4,5,6,7",
37
37
"EventCode": "0xc4",
38
38
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
39
-
"PEBS": "1",
40
39
"SampleAfterValue": "200003",
41
40
"UMask": "0xbf"
42
41
},
43
42
{
44
43
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
44
+
"Counter": "0,1,2,3,4,5,6,7",
45
45
"EventCode": "0xc4",
46
46
"EventName": "BR_INST_RETIRED.INDIRECT",
47
-
"PEBS": "1",
48
47
"SampleAfterValue": "200003",
49
48
"UMask": "0xeb"
50
49
},
51
50
{
52
51
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
52
+
"Counter": "0,1,2,3,4,5,6,7",
53
53
"EventCode": "0xc4",
54
54
"EventName": "BR_INST_RETIRED.INDIRECT_CALL",
55
-
"PEBS": "1",
56
55
"SampleAfterValue": "200003",
57
56
"UMask": "0xfb"
58
57
},
59
58
{
60
59
"BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL",
60
+
"Counter": "0,1,2,3,4,5,6,7",
61
61
"Deprecated": "1",
62
62
"EventCode": "0xc4",
63
63
"EventName": "BR_INST_RETIRED.IND_CALL",
64
-
"PEBS": "1",
65
64
"SampleAfterValue": "200003",
66
65
"UMask": "0xfb"
67
66
},
68
67
{
69
68
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
69
+
"Counter": "0,1,2,3,4,5,6,7",
70
70
"EventCode": "0xc4",
71
71
"EventName": "BR_INST_RETIRED.NEAR_CALL",
72
-
"PEBS": "1",
73
72
"SampleAfterValue": "200003",
74
73
"UMask": "0xf9"
75
74
},
76
75
{
77
76
"BriefDescription": "Counts the number of near RET branch instructions retired.",
77
+
"Counter": "0,1,2,3,4,5,6,7",
78
78
"EventCode": "0xc4",
79
79
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
80
-
"PEBS": "1",
81
80
"SampleAfterValue": "200003",
82
81
"UMask": "0xf7"
83
82
},
84
83
{
85
84
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
85
+
"Counter": "0,1,2,3,4,5,6,7",
86
86
"EventCode": "0xc5",
87
87
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
88
-
"PEBS": "1",
89
88
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
90
89
"SampleAfterValue": "200003"
91
90
},
92
91
{
93
92
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
93
+
"Counter": "0,1,2,3,4,5,6,7",
94
94
"EventCode": "0xc5",
95
95
"EventName": "BR_MISP_RETIRED.COND",
96
-
"PEBS": "1",
97
96
"SampleAfterValue": "200003",
98
97
"UMask": "0x7e"
99
98
},
100
99
{
101
100
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
101
+
"Counter": "0,1,2,3,4,5,6,7",
102
102
"EventCode": "0xc5",
103
103
"EventName": "BR_MISP_RETIRED.COND_TAKEN",
104
-
"PEBS": "1",
105
104
"SampleAfterValue": "200003",
106
105
"UMask": "0xfe"
107
106
},
108
107
{
109
108
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
109
+
"Counter": "0,1,2,3,4,5,6,7",
110
110
"EventCode": "0xc5",
111
111
"EventName": "BR_MISP_RETIRED.INDIRECT",
112
-
"PEBS": "1",
113
112
"SampleAfterValue": "200003",
114
113
"UMask": "0xeb"
115
114
},
116
115
{
117
116
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
117
+
"Counter": "0,1,2,3,4,5,6,7",
118
118
"EventCode": "0xc5",
119
119
"EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
120
-
"PEBS": "1",
121
120
"SampleAfterValue": "200003",
122
121
"UMask": "0xfb"
123
122
},
124
123
{
125
124
"BriefDescription": "Counts the number of mispredicted near taken branch instructions retired.",
125
+
"Counter": "0,1,2,3,4,5,6,7",
126
126
"EventCode": "0xc5",
127
127
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
128
-
"PEBS": "1",
129
128
"SampleAfterValue": "200003",
130
129
"UMask": "0x80"
131
130
},
132
131
{
133
132
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
133
+
"Counter": "0,1,2,3,4,5,6,7",
134
134
"EventCode": "0xc5",
135
135
"EventName": "BR_MISP_RETIRED.RETURN",
136
-
"PEBS": "1",
137
136
"SampleAfterValue": "200003",
138
137
"UMask": "0xf7"
139
138
},
140
139
{
141
140
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
141
+
"Counter": "Fixed counter 1",
142
142
"EventName": "CPU_CLK_UNHALTED.CORE",
143
143
"SampleAfterValue": "2000003",
144
144
"UMask": "0x2"
145
145
},
146
146
{
147
147
"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
148
+
"Counter": "0,1,2,3,4,5,6,7",
148
149
"EventCode": "0x3c",
149
150
"EventName": "CPU_CLK_UNHALTED.CORE_P",
150
151
"SampleAfterValue": "2000003"
151
152
},
152
153
{
153
154
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
155
+
"Counter": "Fixed counter 2",
154
156
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
155
157
"SampleAfterValue": "2000003",
156
158
"UMask": "0x3"
157
159
},
158
160
{
159
161
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
162
+
"Counter": "0,1,2,3,4,5,6,7",
160
163
"EventCode": "0x3c",
161
164
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
162
165
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
···
169
164
},
170
165
{
171
166
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
167
+
"Counter": "Fixed counter 1",
172
168
"EventName": "CPU_CLK_UNHALTED.THREAD",
173
169
"SampleAfterValue": "2000003",
174
170
"UMask": "0x2"
175
171
},
176
172
{
177
173
"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
174
+
"Counter": "0,1,2,3,4,5,6,7",
178
175
"EventCode": "0x3c",
179
176
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
180
177
"SampleAfterValue": "2000003"
181
178
},
182
179
{
183
180
"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
181
+
"Counter": "Fixed counter 0",
184
182
"EventName": "INST_RETIRED.ANY",
185
183
"PEBS": "1",
186
184
"SampleAfterValue": "2000003",
···
191
183
},
192
184
{
193
185
"BriefDescription": "Counts the number of instructions retired",
186
+
"Counter": "0,1,2,3,4,5,6,7",
194
187
"EventCode": "0xc0",
195
188
"EventName": "INST_RETIRED.ANY_P",
196
-
"PEBS": "1",
197
189
"SampleAfterValue": "2000003"
198
190
},
199
191
{
200
192
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
193
+
"Counter": "0,1,2,3,4,5,6,7",
201
194
"EventCode": "0x03",
202
195
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
203
-
"PEBS": "1",
204
196
"SampleAfterValue": "1000003",
205
197
"UMask": "0x4"
206
198
},
207
199
{
208
200
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
201
+
"Counter": "0,1,2,3,4,5,6,7",
209
202
"EventCode": "0x03",
210
203
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
211
-
"PEBS": "1",
212
204
"SampleAfterValue": "1000003",
213
205
"UMask": "0x1"
214
206
},
215
207
{
216
208
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
209
+
"Counter": "0,1,2,3,4,5,6,7",
217
210
"EventCode": "0x03",
218
211
"EventName": "LD_BLOCKS.STORE_FORWARD",
219
-
"PEBS": "1",
220
212
"SampleAfterValue": "1000003",
221
213
"UMask": "0x2"
222
214
},
223
215
{
224
216
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
217
+
"Counter": "0,1,2,3,4,5,6,7",
225
218
"EventCode": "0xc3",
226
219
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
227
220
"SampleAfterValue": "20003",
···
230
221
},
231
222
{
232
223
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
224
+
"Counter": "0,1,2,3,4,5,6,7",
233
225
"EventCode": "0xc3",
234
226
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
235
227
"SampleAfterValue": "20003",
···
238
228
},
239
229
{
240
230
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
231
+
"Counter": "0,1,2,3,4,5,6,7",
241
232
"EventCode": "0xc3",
242
233
"EventName": "MACHINE_CLEARS.SLOW",
243
234
"SampleAfterValue": "20003",
···
246
235
},
247
236
{
248
237
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
238
+
"Counter": "0,1,2,3,4,5,6,7",
249
239
"EventCode": "0xc3",
250
240
"EventName": "MACHINE_CLEARS.SMC",
251
241
"SampleAfterValue": "20003",
···
254
242
},
255
243
{
256
244
"BriefDescription": "Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This event is alias to LBR_INSERTS.ANY]",
245
+
"Counter": "0,1,2,3,4,5,6,7",
257
246
"EventCode": "0xe4",
258
247
"EventName": "MISC_RETIRED.LBR_INSERTS",
259
-
"PEBS": "1",
260
248
"SampleAfterValue": "1000003",
261
249
"UMask": "0x1"
262
250
},
263
251
{
264
252
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]",
253
+
"Counter": "0,1,2,3,4,5,6,7",
265
254
"EventCode": "0x73",
266
255
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
267
256
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]",
···
270
257
},
271
258
{
272
259
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]",
260
+
"Counter": "0,1,2,3,4,5,6,7",
273
261
"EventCode": "0x73",
274
262
"EventName": "TOPDOWN_BAD_SPECULATION.ALL_P",
275
263
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]",
···
278
264
},
279
265
{
280
266
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes",
267
+
"Counter": "0,1,2,3,4,5,6,7",
281
268
"EventCode": "0x73",
282
269
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
283
270
"SampleAfterValue": "1000003",
···
286
271
},
287
272
{
288
273
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
274
+
"Counter": "0,1,2,3,4,5,6,7",
289
275
"EventCode": "0x73",
290
276
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
291
277
"SampleAfterValue": "1000003",
···
294
278
},
295
279
{
296
280
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict",
281
+
"Counter": "0,1,2,3,4,5,6,7",
297
282
"EventCode": "0x73",
298
283
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
299
284
"SampleAfterValue": "1000003",
···
302
285
},
303
286
{
304
287
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).",
288
+
"Counter": "0,1,2,3,4,5,6,7",
305
289
"EventCode": "0x73",
306
290
"EventName": "TOPDOWN_BAD_SPECULATION.NUKE",
307
291
"SampleAfterValue": "1000003",
···
310
292
},
311
293
{
312
294
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]",
295
+
"Counter": "0,1,2,3,4,5,6,7",
313
296
"EventCode": "0x74",
314
297
"EventName": "TOPDOWN_BE_BOUND.ALL",
315
298
"SampleAfterValue": "1000003"
316
299
},
317
300
{
318
301
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions",
302
+
"Counter": "0,1,2,3,4,5,6,7",
319
303
"EventCode": "0x74",
320
304
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
321
305
"SampleAfterValue": "1000003",
···
325
305
},
326
306
{
327
307
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]",
308
+
"Counter": "0,1,2,3,4,5,6,7",
328
309
"EventCode": "0x74",
329
310
"EventName": "TOPDOWN_BE_BOUND.ALL_P",
330
311
"SampleAfterValue": "1000003"
331
312
},
332
313
{
333
314
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.",
315
+
"Counter": "0,1,2,3,4,5,6,7",
334
316
"EventCode": "0x74",
335
317
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
336
318
"SampleAfterValue": "1000003",
···
340
318
},
341
319
{
342
320
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. )",
321
+
"Counter": "0,1,2,3,4,5,6,7",
343
322
"EventCode": "0x74",
344
323
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
345
324
"SampleAfterValue": "1000003",
···
348
325
},
349
326
{
350
327
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).",
328
+
"Counter": "0,1,2,3,4,5,6,7",
351
329
"EventCode": "0x74",
352
330
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
353
331
"SampleAfterValue": "1000003",
···
356
332
},
357
333
{
358
334
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
335
+
"Counter": "0,1,2,3,4,5,6,7",
359
336
"EventCode": "0x74",
360
337
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
361
338
"SampleAfterValue": "1000003",
···
364
339
},
365
340
{
366
341
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
342
+
"Counter": "0,1,2,3,4,5,6,7",
367
343
"EventCode": "0x74",
368
344
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
369
345
"SampleAfterValue": "1000003",
···
372
346
},
373
347
{
374
348
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_P]",
349
+
"Counter": "0,1,2,3,4,5,6,7",
375
350
"EventCode": "0x71",
376
351
"EventName": "TOPDOWN_FE_BOUND.ALL",
377
352
"SampleAfterValue": "1000003"
378
353
},
379
354
{
380
355
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]",
356
+
"Counter": "0,1,2,3,4,5,6,7",
381
357
"EventCode": "0x71",
382
358
"EventName": "TOPDOWN_FE_BOUND.ALL_P",
383
359
"SampleAfterValue": "1000003"
384
360
},
385
361
{
386
362
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear",
363
+
"Counter": "0,1,2,3,4,5,6,7",
387
364
"EventCode": "0x71",
388
365
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
389
366
"SampleAfterValue": "1000003",
···
394
365
},
395
366
{
396
367
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear",
368
+
"Counter": "0,1,2,3,4,5,6,7",
397
369
"EventCode": "0x71",
398
370
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
399
371
"SampleAfterValue": "1000003",
···
402
372
},
403
373
{
404
374
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms",
375
+
"Counter": "0,1,2,3,4,5,6,7",
405
376
"EventCode": "0x71",
406
377
"EventName": "TOPDOWN_FE_BOUND.CISC",
407
378
"SampleAfterValue": "1000003",
···
410
379
},
411
380
{
412
381
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall",
382
+
"Counter": "0,1,2,3,4,5,6,7",
413
383
"EventCode": "0x71",
414
384
"EventName": "TOPDOWN_FE_BOUND.DECODE",
415
385
"SampleAfterValue": "1000003",
···
418
386
},
419
387
{
420
388
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
389
+
"Counter": "0,1,2,3,4,5,6,7",
421
390
"EventCode": "0x71",
422
391
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH",
423
392
"SampleAfterValue": "1000003",
···
426
393
},
427
394
{
428
395
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
396
+
"Counter": "0,1,2,3,4,5,6,7",
429
397
"EventCode": "0x71",
430
398
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
431
399
"SampleAfterValue": "1000003",
···
434
400
},
435
401
{
436
402
"BriefDescription": "This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]",
403
+
"Counter": "0,1,2,3,4,5,6,7",
437
404
"Deprecated": "1",
438
405
"EventCode": "0x71",
439
406
"EventName": "TOPDOWN_FE_BOUND.ITLB",
···
443
408
},
444
409
{
445
410
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]",
411
+
"Counter": "0,1,2,3,4,5,6,7",
446
412
"EventCode": "0x71",
447
413
"EventName": "TOPDOWN_FE_BOUND.ITLB_MISS",
448
414
"SampleAfterValue": "1000003",
···
451
415
},
452
416
{
453
417
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall",
418
+
"Counter": "0,1,2,3,4,5,6,7",
454
419
"EventCode": "0x71",
455
420
"EventName": "TOPDOWN_FE_BOUND.OTHER",
456
421
"SampleAfterValue": "1000003",
···
459
422
},
460
423
{
461
424
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong",
425
+
"Counter": "0,1,2,3,4,5,6,7",
462
426
"EventCode": "0x71",
463
427
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
464
428
"SampleAfterValue": "1000003",
465
429
"UMask": "0x4"
466
430
},
467
431
{
468
-
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.ALL_P]",
432
+
"BriefDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL_P]",
433
+
"Counter": "0,1,2,3,4,5,6,7",
469
434
"EventCode": "0x72",
470
435
"EventName": "TOPDOWN_RETIRING.ALL",
471
-
"PEBS": "1",
472
436
"SampleAfterValue": "1000003"
473
437
},
474
438
{
475
-
"BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.ALL]",
439
+
"BriefDescription": "Counts the number of consumed retirement slots. [This event is alias to TOPDOWN_RETIRING.ALL]",
440
+
"Counter": "0,1,2,3,4,5,6,7",
476
441
"EventCode": "0x72",
477
442
"EventName": "TOPDOWN_RETIRING.ALL_P",
478
-
"PEBS": "1",
479
443
"SampleAfterValue": "1000003"
480
444
},
481
445
{
482
446
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
447
+
"Counter": "0,1,2,3,4,5,6,7",
483
448
"EventCode": "0x0e",
484
449
"EventName": "UOPS_ISSUED.ANY",
485
450
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
···
489
450
},
490
451
{
491
452
"BriefDescription": "Counts the total number of uops retired.",
453
+
"Counter": "0,1,2,3,4,5,6,7",
492
454
"EventCode": "0xc2",
493
455
"EventName": "UOPS_RETIRED.ALL",
494
-
"PEBS": "1",
495
456
"SampleAfterValue": "2000003"
496
457
},
497
458
{
498
459
"BriefDescription": "Counts the number of integer divide uops retired.",
460
+
"Counter": "0,1,2,3,4,5,6,7",
499
461
"EventCode": "0xc2",
500
462
"EventName": "UOPS_RETIRED.IDIV",
501
-
"PEBS": "1",
502
463
"SampleAfterValue": "2000003",
503
464
"UMask": "0x10"
504
465
},
505
466
{
506
467
"BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
468
+
"Counter": "0,1,2,3,4,5,6,7",
507
469
"EventCode": "0xc2",
508
470
"EventName": "UOPS_RETIRED.MS",
509
-
"PEBS": "1",
510
471
"SampleAfterValue": "2000003",
511
472
"UMask": "0x1"
512
473
},
513
474
{
514
475
"BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows",
476
+
"Counter": "0,1,2,3,4,5,6,7",
515
477
"EventCode": "0xc2",
516
478
"EventName": "UOPS_RETIRED.X87",
517
-
"PEBS": "1",
518
479
"SampleAfterValue": "2000003",
519
480
"UMask": "0x2"
520
481
}
+927
tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics.json
+927
tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics.json
···
1
+
[
2
+
{
3
+
"BriefDescription": "C1 residency percent per core",
4
+
"MetricExpr": "cstate_core@c1\\-residency@ / TSC",
5
+
"MetricGroup": "Power",
6
+
"MetricName": "C1_Core_Residency",
7
+
"ScaleUnit": "100%"
8
+
},
9
+
{
10
+
"BriefDescription": "C6 residency percent per core",
11
+
"MetricExpr": "cstate_core@c6\\-residency@ / TSC",
12
+
"MetricGroup": "Power",
13
+
"MetricName": "C6_Core_Residency",
14
+
"ScaleUnit": "100%"
15
+
},
16
+
{
17
+
"BriefDescription": "C6 residency percent per module",
18
+
"MetricExpr": "cstate_module@c6\\-residency@ / TSC",
19
+
"MetricGroup": "Power",
20
+
"MetricName": "C6_Module_Residency",
21
+
"ScaleUnit": "100%"
22
+
},
23
+
{
24
+
"BriefDescription": "C6 residency percent per package",
25
+
"MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
26
+
"MetricGroup": "Power",
27
+
"MetricName": "C6_Pkg_Residency",
28
+
"ScaleUnit": "100%"
29
+
},
30
+
{
31
+
"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
32
+
"MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
33
+
"MetricName": "cpi",
34
+
"ScaleUnit": "1per_instr"
35
+
},
36
+
{
37
+
"BriefDescription": "CPU operating frequency (in GHz)",
38
+
"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9",
39
+
"MetricName": "cpu_operating_frequency",
40
+
"ScaleUnit": "1GHz"
41
+
},
42
+
{
43
+
"BriefDescription": "Percentage of time spent in the active CPU power state C0",
44
+
"MetricExpr": "tma_info_system_cpu_utilization",
45
+
"MetricName": "cpu_utilization",
46
+
"ScaleUnit": "100%"
47
+
},
48
+
{
49
+
"BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
50
+
"MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
51
+
"MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi",
52
+
"PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
53
+
"ScaleUnit": "1per_instr"
54
+
},
55
+
{
56
+
"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
57
+
"MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
58
+
"MetricName": "dtlb_2nd_level_load_mpi",
59
+
"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
60
+
"ScaleUnit": "1per_instr"
61
+
},
62
+
{
63
+
"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
64
+
"MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
65
+
"MetricName": "dtlb_2nd_level_store_mpi",
66
+
"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
67
+
"ScaleUnit": "1per_instr"
68
+
},
69
+
{
70
+
"BriefDescription": "Bandwidth observed by the integrated I/O traffic contoller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
71
+
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time",
72
+
"MetricName": "iio_bandwidth_read",
73
+
"ScaleUnit": "1MB/s"
74
+
},
75
+
{
76
+
"BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
77
+
"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1e6 / duration_time",
78
+
"MetricName": "iio_bandwidth_write",
79
+
"ScaleUnit": "1MB/s"
80
+
},
81
+
{
82
+
"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
83
+
"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time",
84
+
"MetricName": "io_bandwidth_read",
85
+
"ScaleUnit": "1MB/s"
86
+
},
87
+
{
88
+
"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket.",
89
+
"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time",
90
+
"MetricName": "io_bandwidth_read_local",
91
+
"ScaleUnit": "1MB/s"
92
+
},
93
+
{
94
+
"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket.",
95
+
"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time",
96
+
"MetricName": "io_bandwidth_read_remote",
97
+
"ScaleUnit": "1MB/s"
98
+
},
99
+
{
100
+
"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
101
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
102
+
"MetricName": "io_bandwidth_write",
103
+
"ScaleUnit": "1MB/s"
104
+
},
105
+
{
106
+
"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket.",
107
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time",
108
+
"MetricName": "io_bandwidth_write_local",
109
+
"ScaleUnit": "1MB/s"
110
+
},
111
+
{
112
+
"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket.",
113
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time",
114
+
"MetricName": "io_bandwidth_write_remote",
115
+
"ScaleUnit": "1MB/s"
116
+
},
117
+
{
118
+
"BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
119
+
"MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
120
+
"MetricName": "itlb_2nd_level_large_page_mpi",
121
+
"PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
122
+
"ScaleUnit": "1per_instr"
123
+
},
124
+
{
125
+
"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
126
+
"MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
127
+
"MetricName": "itlb_2nd_level_mpi",
128
+
"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
129
+
"ScaleUnit": "1per_instr"
130
+
},
131
+
{
132
+
"BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
133
+
"MetricExpr": "ICACHE.MISSES / INST_RETIRED.ANY",
134
+
"MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
135
+
"ScaleUnit": "1per_instr"
136
+
},
137
+
{
138
+
"BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
139
+
"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
140
+
"MetricName": "l1d_demand_data_read_hits_per_instr",
141
+
"ScaleUnit": "1per_instr"
142
+
},
143
+
{
144
+
"BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
145
+
"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
146
+
"MetricName": "l2_demand_data_read_hits_per_instr",
147
+
"ScaleUnit": "1per_instr"
148
+
},
149
+
{
150
+
"BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
151
+
"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
152
+
"MetricName": "l2_demand_data_read_mpi",
153
+
"ScaleUnit": "1per_instr"
154
+
},
155
+
{
156
+
"BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
157
+
"MetricExpr": "LONGEST_LAT_CACHE.REFERENCE / INST_RETIRED.ANY",
158
+
"MetricName": "l2_mpi",
159
+
"ScaleUnit": "1per_instr"
160
+
},
161
+
{
162
+
"BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
163
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY",
164
+
"MetricName": "llc_code_read_mpi_demand_plus_prefetch",
165
+
"ScaleUnit": "1per_instr"
166
+
},
167
+
{
168
+
"BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
169
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / INST_RETIRED.ANY",
170
+
"MetricName": "llc_data_read_mpi_demand_plus_prefetch",
171
+
"ScaleUnit": "1per_instr"
172
+
},
173
+
{
174
+
"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
175
+
"MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time",
176
+
"MetricName": "llc_demand_data_read_miss_latency",
177
+
"ScaleUnit": "1ns"
178
+
},
179
+
{
180
+
"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
181
+
"MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
182
+
"MetricName": "llc_miss_local_memory_bandwidth_read",
183
+
"ScaleUnit": "1MB/s"
184
+
},
185
+
{
186
+
"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
187
+
"MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
188
+
"MetricName": "llc_miss_local_memory_bandwidth_write",
189
+
"ScaleUnit": "1MB/s"
190
+
},
191
+
{
192
+
"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
193
+
"MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
194
+
"MetricName": "llc_miss_remote_memory_bandwidth_read",
195
+
"ScaleUnit": "1MB/s"
196
+
},
197
+
{
198
+
"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.",
199
+
"MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
200
+
"MetricName": "llc_miss_remote_memory_bandwidth_write",
201
+
"ScaleUnit": "1MB/s"
202
+
},
203
+
{
204
+
"BriefDescription": "Load operations retired per instruction",
205
+
"MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
206
+
"MetricName": "loads_retired_per_instr",
207
+
"ScaleUnit": "1per_instr"
208
+
},
209
+
{
210
+
"BriefDescription": "DDR memory read bandwidth (MB/sec)",
211
+
"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD) * 64 / 1e6 / duration_time",
212
+
"MetricName": "memory_bandwidth_read",
213
+
"ScaleUnit": "1MB/s"
214
+
},
215
+
{
216
+
"BriefDescription": "DDR memory bandwidth (MB/sec)",
217
+
"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time",
218
+
"MetricName": "memory_bandwidth_total",
219
+
"ScaleUnit": "1MB/s"
220
+
},
221
+
{
222
+
"BriefDescription": "DDR memory write bandwidth (MB/sec)",
223
+
"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time",
224
+
"MetricName": "memory_bandwidth_write",
225
+
"ScaleUnit": "1MB/s"
226
+
},
227
+
{
228
+
"BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
229
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)",
230
+
"MetricName": "numa_reads_addressed_to_local_dram",
231
+
"ScaleUnit": "100%"
232
+
},
233
+
{
234
+
"BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
235
+
"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)",
236
+
"MetricName": "numa_reads_addressed_to_remote_dram",
237
+
"ScaleUnit": "100%"
238
+
},
239
+
{
240
+
"BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
241
+
"MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
242
+
"MetricGroup": "smi",
243
+
"MetricName": "smi_cycles",
244
+
"MetricThreshold": "smi_cycles > 0.1",
245
+
"ScaleUnit": "100%"
246
+
},
247
+
{
248
+
"BriefDescription": "Number of SMI interrupts.",
249
+
"MetricExpr": "msr@smi@",
250
+
"MetricGroup": "smi",
251
+
"MetricName": "smi_num",
252
+
"ScaleUnit": "1SMI#"
253
+
},
254
+
{
255
+
"BriefDescription": "Store operations retired per instruction",
256
+
"MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
257
+
"MetricName": "stores_retired_per_instr",
258
+
"ScaleUnit": "1per_instr"
259
+
},
260
+
{
261
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
262
+
"MetricExpr": "tma_core_bound",
263
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
264
+
"MetricName": "tma_allocation_restriction",
265
+
"MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1)",
266
+
"ScaleUnit": "100%"
267
+
},
268
+
{
269
+
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
270
+
"MetricExpr": "TOPDOWN_BE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE)",
271
+
"MetricGroup": "TopdownL1;tma_L1_group",
272
+
"MetricName": "tma_backend_bound",
273
+
"MetricThreshold": "tma_backend_bound > 0.1",
274
+
"MetricgroupNoGroup": "TopdownL1",
275
+
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
276
+
"ScaleUnit": "100%"
277
+
},
278
+
{
279
+
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
280
+
"MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL_P / (6 * CPU_CLK_UNHALTED.CORE)",
281
+
"MetricGroup": "TopdownL1;tma_L1_group",
282
+
"MetricName": "tma_bad_speculation",
283
+
"MetricThreshold": "tma_bad_speculation > 0.15",
284
+
"MetricgroupNoGroup": "TopdownL1",
285
+
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
286
+
"ScaleUnit": "100%"
287
+
},
288
+
{
289
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
290
+
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (6 * CPU_CLK_UNHALTED.CORE)",
291
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
292
+
"MetricName": "tma_branch_detect",
293
+
"MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
294
+
"PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
295
+
"ScaleUnit": "100%"
296
+
},
297
+
{
298
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts",
299
+
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (6 * CPU_CLK_UNHALTED.CORE)",
300
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
301
+
"MetricName": "tma_branch_mispredicts",
302
+
"MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15",
303
+
"MetricgroupNoGroup": "TopdownL2",
304
+
"ScaleUnit": "100%"
305
+
},
306
+
{
307
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
308
+
"MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (6 * CPU_CLK_UNHALTED.CORE)",
309
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
310
+
"MetricName": "tma_branch_resteer",
311
+
"MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
312
+
"ScaleUnit": "100%"
313
+
},
314
+
{
315
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).",
316
+
"MetricExpr": "TOPDOWN_FE_BOUND.CISC / (6 * CPU_CLK_UNHALTED.CORE)",
317
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
318
+
"MetricName": "tma_cisc",
319
+
"MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
320
+
"ScaleUnit": "100%"
321
+
},
322
+
{
323
+
"BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation",
324
+
"MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (6 * CPU_CLK_UNHALTED.CORE)",
325
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
326
+
"MetricName": "tma_core_bound",
327
+
"MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1",
328
+
"MetricgroupNoGroup": "TopdownL2",
329
+
"ScaleUnit": "100%"
330
+
},
331
+
{
332
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
333
+
"MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (6 * CPU_CLK_UNHALTED.CORE)",
334
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
335
+
"MetricName": "tma_decode",
336
+
"MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
337
+
"ScaleUnit": "100%"
338
+
},
339
+
{
340
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming",
341
+
"MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (6 * CPU_CLK_UNHALTED.CORE)",
342
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
343
+
"MetricName": "tma_fast_nuke",
344
+
"MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
345
+
"ScaleUnit": "100%"
346
+
},
347
+
{
348
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
349
+
"MetricExpr": "TOPDOWN_FE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE)",
350
+
"MetricGroup": "TopdownL1;tma_L1_group",
351
+
"MetricName": "tma_frontend_bound",
352
+
"MetricThreshold": "tma_frontend_bound > 0.2",
353
+
"MetricgroupNoGroup": "TopdownL1",
354
+
"ScaleUnit": "100%"
355
+
},
356
+
{
357
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.",
358
+
"MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (6 * CPU_CLK_UNHALTED.CORE)",
359
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
360
+
"MetricName": "tma_icache_misses",
361
+
"MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
362
+
"ScaleUnit": "100%"
363
+
},
364
+
{
365
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
366
+
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (6 * CPU_CLK_UNHALTED.CORE)",
367
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
368
+
"MetricName": "tma_ifetch_bandwidth",
369
+
"MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2",
370
+
"MetricgroupNoGroup": "TopdownL2",
371
+
"ScaleUnit": "100%"
372
+
},
373
+
{
374
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.",
375
+
"MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (6 * CPU_CLK_UNHALTED.CORE)",
376
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
377
+
"MetricName": "tma_ifetch_latency",
378
+
"MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2",
379
+
"MetricgroupNoGroup": "TopdownL2",
380
+
"ScaleUnit": "100%"
381
+
},
382
+
{
383
+
"BriefDescription": "Instructions per Floating Point (FP) Operation",
384
+
"MetricExpr": "INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL",
385
+
"MetricGroup": "Flops",
386
+
"MetricName": "tma_info_arith_inst_mix_ipflop"
387
+
},
388
+
{
389
+
"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction",
390
+
"MetricExpr": "INST_RETIRED.ANY / (FP_INST_RETIRED.128B_DP + FP_INST_RETIRED.128B_SP)",
391
+
"MetricGroup": "Flops",
392
+
"MetricName": "tma_info_arith_inst_mix_ipfparith_avx128"
393
+
},
394
+
{
395
+
"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction",
396
+
"MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP",
397
+
"MetricGroup": "Flops",
398
+
"MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp"
399
+
},
400
+
{
401
+
"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction",
402
+
"MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP",
403
+
"MetricGroup": "Flops",
404
+
"MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp"
405
+
},
406
+
{
407
+
"BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss",
408
+
"MetricExpr": "tma_info_bottleneck_dtlb_miss_bound_cycles",
409
+
"MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles"
410
+
},
411
+
{
412
+
"BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss",
413
+
"MetricExpr": "tma_info_bottleneck_ifetch_miss_bound_cycles",
414
+
"MetricGroup": "Ifetch",
415
+
"MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles",
416
+
"PublicDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound"
417
+
},
418
+
{
419
+
"BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
420
+
"MetricExpr": "tma_info_bottleneck_load_miss_bound_cycles",
421
+
"MetricGroup": "Load_Store_Miss",
422
+
"MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles",
423
+
"PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound"
424
+
},
425
+
{
426
+
"BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall",
427
+
"MetricExpr": "tma_info_bottleneck_mem_exec_bound_cycles",
428
+
"MetricGroup": "Mem_Exec",
429
+
"MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles",
430
+
"PublicDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound"
431
+
},
432
+
{
433
+
"BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss",
434
+
"MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT_RET) / CPU_CLK_UNHALTED.CORE",
435
+
"MetricGroup": "Cycles",
436
+
"MetricName": "tma_info_bottleneck_dtlb_miss_bound_cycles",
437
+
"ScaleUnit": "100%"
438
+
},
439
+
{
440
+
"BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss",
441
+
"MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.ALL / CPU_CLK_UNHALTED.CORE",
442
+
"MetricGroup": "Cycles;Ifetch",
443
+
"MetricName": "tma_info_bottleneck_ifetch_miss_bound_cycles",
444
+
"PublicDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound",
445
+
"ScaleUnit": "100%"
446
+
},
447
+
{
448
+
"BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
449
+
"MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.ALL / CPU_CLK_UNHALTED.CORE",
450
+
"MetricGroup": "Cycles;Load_Store_Miss",
451
+
"MetricName": "tma_info_bottleneck_load_miss_bound_cycles",
452
+
"PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound",
453
+
"ScaleUnit": "100%"
454
+
},
455
+
{
456
+
"BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall",
457
+
"MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE",
458
+
"MetricGroup": "Cycles;Mem_Exec",
459
+
"MetricName": "tma_info_bottleneck_mem_exec_bound_cycles",
460
+
"PublicDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound",
461
+
"ScaleUnit": "100%"
462
+
},
463
+
{
464
+
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
465
+
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
466
+
"MetricName": "tma_info_br_inst_mix_ipbranch"
467
+
},
468
+
{
469
+
"BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
470
+
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
471
+
"MetricName": "tma_info_br_inst_mix_ipcall"
472
+
},
473
+
{
474
+
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
475
+
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
476
+
"MetricName": "tma_info_br_inst_mix_ipfarbranch"
477
+
},
478
+
{
479
+
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken",
480
+
"MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)",
481
+
"MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken"
482
+
},
483
+
{
484
+
"BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken",
485
+
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN",
486
+
"MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken"
487
+
},
488
+
{
489
+
"BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction",
490
+
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT",
491
+
"MetricName": "tma_info_br_inst_mix_ipmisp_indirect"
492
+
},
493
+
{
494
+
"BriefDescription": "Instructions per retired return Branch Misprediction",
495
+
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN",
496
+
"MetricName": "tma_info_br_inst_mix_ipmisp_ret"
497
+
},
498
+
{
499
+
"BriefDescription": "Instructions per retired Branch Misprediction",
500
+
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
501
+
"MetricName": "tma_info_br_inst_mix_ipmispredict"
502
+
},
503
+
{
504
+
"BriefDescription": "Ratio of all branches which mispredict",
505
+
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES",
506
+
"MetricName": "tma_info_br_mispredict_bound_branch_mispredict_ratio"
507
+
},
508
+
{
509
+
"BriefDescription": "Ratio between Mispredicted branches and unknown branches",
510
+
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY",
511
+
"MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio"
512
+
},
513
+
{
514
+
"BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
515
+
"MetricExpr": "tma_info_buffer_stalls_load_buffer_stall_cycles",
516
+
"MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles"
517
+
},
518
+
{
519
+
"BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full",
520
+
"MetricExpr": "tma_info_buffer_stalls_mem_rsv_stall_cycles",
521
+
"MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles"
522
+
},
523
+
{
524
+
"BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
525
+
"MetricExpr": "tma_info_buffer_stalls_store_buffer_stall_cycles",
526
+
"MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles"
527
+
},
528
+
{
529
+
"BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
530
+
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED.CORE",
531
+
"MetricName": "tma_info_buffer_stalls_load_buffer_stall_cycles",
532
+
"ScaleUnit": "100%"
533
+
},
534
+
{
535
+
"BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full",
536
+
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CORE",
537
+
"MetricName": "tma_info_buffer_stalls_mem_rsv_stall_cycles",
538
+
"ScaleUnit": "100%"
539
+
},
540
+
{
541
+
"BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
542
+
"MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED.CORE",
543
+
"MetricName": "tma_info_buffer_stalls_store_buffer_stall_cycles",
544
+
"ScaleUnit": "100%"
545
+
},
546
+
{
547
+
"BriefDescription": "Cycles Per Instruction",
548
+
"MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY",
549
+
"MetricName": "tma_info_core_cpi"
550
+
},
551
+
{
552
+
"BriefDescription": "Floating Point Operations Per Cycle",
553
+
"MetricExpr": "FP_FLOPS_RETIRED.ALL / CPU_CLK_UNHALTED.CORE",
554
+
"MetricGroup": "Flops",
555
+
"MetricName": "tma_info_core_flopc"
556
+
},
557
+
{
558
+
"BriefDescription": "Instructions Per Cycle",
559
+
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE",
560
+
"MetricName": "tma_info_core_ipc"
561
+
},
562
+
{
563
+
"BriefDescription": "Uops Per Instruction",
564
+
"MetricExpr": "TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY",
565
+
"MetricName": "tma_info_core_upi"
566
+
},
567
+
{
568
+
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2",
569
+
"MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit",
570
+
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit"
571
+
},
572
+
{
573
+
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3",
574
+
"MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit",
575
+
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3hit"
576
+
},
577
+
{
578
+
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss subsequently misses in the L3",
579
+
"MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_MISS / MEM_BOUND_STALLS_IFETCH.ALL",
580
+
"MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l3miss"
581
+
},
582
+
{
583
+
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2",
584
+
"MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / MEM_BOUND_STALLS_IFETCH.ALL",
585
+
"MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2hit",
586
+
"ScaleUnit": "100%"
587
+
},
588
+
{
589
+
"BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L3",
590
+
"MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / MEM_BOUND_STALLS_IFETCH.ALL",
591
+
"MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3hit",
592
+
"ScaleUnit": "100%"
593
+
},
594
+
{
595
+
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2",
596
+
"MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l2hit",
597
+
"MetricGroup": "load_store_bound",
598
+
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit"
599
+
},
600
+
{
601
+
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3",
602
+
"MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l3hit",
603
+
"MetricGroup": "load_store_bound",
604
+
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit"
605
+
},
606
+
{
607
+
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses the L3",
608
+
"MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_MISS / MEM_BOUND_STALLS_LOAD.ALL",
609
+
"MetricGroup": "load_store_bound",
610
+
"MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3miss"
611
+
},
612
+
{
613
+
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2",
614
+
"MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STALLS_LOAD.ALL",
615
+
"MetricGroup": "load_store_bound",
616
+
"MetricName": "tma_info_load_miss_bound_loadmissbound_with_l2hit",
617
+
"ScaleUnit": "100%"
618
+
},
619
+
{
620
+
"BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L3",
621
+
"MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STALLS_LOAD.ALL",
622
+
"MetricGroup": "load_store_bound",
623
+
"MetricName": "tma_info_load_miss_bound_loadmissbound_with_l3hit",
624
+
"ScaleUnit": "100%"
625
+
},
626
+
{
627
+
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block",
628
+
"MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CORE",
629
+
"MetricGroup": "load_store_bound",
630
+
"MetricName": "tma_info_load_store_bound_l1_bound"
631
+
},
632
+
{
633
+
"BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement",
634
+
"MetricExpr": "100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_LOAD.ALL) / CPU_CLK_UNHALTED.CORE",
635
+
"MetricGroup": "load_store_bound",
636
+
"MetricName": "tma_info_load_store_bound_load_bound"
637
+
},
638
+
{
639
+
"BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full",
640
+
"MetricExpr": "100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL) * tma_mem_scheduler",
641
+
"MetricGroup": "load_store_bound",
642
+
"MetricName": "tma_info_load_store_bound_store_bound"
643
+
},
644
+
{
645
+
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists",
646
+
"MetricExpr": "1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY",
647
+
"MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assist_pki"
648
+
},
649
+
{
650
+
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults",
651
+
"MetricExpr": "1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY",
652
+
"MetricName": "tma_info_machine_clear_bound_machine_clears_page_fault_pki"
653
+
},
654
+
{
655
+
"BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to self-modifying code",
656
+
"MetricExpr": "1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY",
657
+
"MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki"
658
+
},
659
+
{
660
+
"BriefDescription": "Percentage of total non-speculative loads with an address aliasing block",
661
+
"MetricExpr": "tma_info_mem_exec_blocks_loads_with_adressaliasing",
662
+
"MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasing"
663
+
},
664
+
{
665
+
"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
666
+
"MetricExpr": "tma_info_mem_exec_blocks_loads_with_storefwdblk",
667
+
"MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk"
668
+
},
669
+
{
670
+
"BriefDescription": "Percentage of total non-speculative loads with an address aliasing block",
671
+
"MetricExpr": "100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS",
672
+
"MetricName": "tma_info_mem_exec_blocks_loads_with_adressaliasing",
673
+
"ScaleUnit": "100%"
674
+
},
675
+
{
676
+
"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
677
+
"MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS",
678
+
"MetricName": "tma_info_mem_exec_blocks_loads_with_storefwdblk",
679
+
"ScaleUnit": "100%"
680
+
},
681
+
{
682
+
"BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
683
+
"MetricExpr": "tma_info_mem_exec_bound_loadhead_with_l1miss",
684
+
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss"
685
+
},
686
+
{
687
+
"BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc",
688
+
"MetricExpr": "tma_info_mem_exec_bound_loadhead_with_otherpipelineblks",
689
+
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks"
690
+
},
691
+
{
692
+
"BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
693
+
"MetricExpr": "tma_info_mem_exec_bound_loadhead_with_pagewalk",
694
+
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk"
695
+
},
696
+
{
697
+
"BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
698
+
"MetricExpr": "tma_info_mem_exec_bound_loadhead_with_stlbhit",
699
+
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit"
700
+
},
701
+
{
702
+
"BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
703
+
"MetricExpr": "tma_info_mem_exec_bound_loadhead_with_storefwding",
704
+
"MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding"
705
+
},
706
+
{
707
+
"BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
708
+
"MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET",
709
+
"MetricName": "tma_info_mem_exec_bound_loadhead_with_l1miss",
710
+
"ScaleUnit": "100%"
711
+
},
712
+
{
713
+
"BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc",
714
+
"MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET",
715
+
"MetricName": "tma_info_mem_exec_bound_loadhead_with_otherpipelineblks",
716
+
"ScaleUnit": "100%"
717
+
},
718
+
{
719
+
"BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
720
+
"MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET",
721
+
"MetricName": "tma_info_mem_exec_bound_loadhead_with_pagewalk",
722
+
"ScaleUnit": "100%"
723
+
},
724
+
{
725
+
"BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
726
+
"MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET",
727
+
"MetricName": "tma_info_mem_exec_bound_loadhead_with_stlbhit",
728
+
"ScaleUnit": "100%"
729
+
},
730
+
{
731
+
"BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
732
+
"MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET",
733
+
"MetricName": "tma_info_mem_exec_bound_loadhead_with_storefwding",
734
+
"ScaleUnit": "100%"
735
+
},
736
+
{
737
+
"BriefDescription": "Instructions per Load",
738
+
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
739
+
"MetricName": "tma_info_mem_mix_ipload"
740
+
},
741
+
{
742
+
"BriefDescription": "Instructions per Store",
743
+
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
744
+
"MetricName": "tma_info_mem_mix_ipstore"
745
+
},
746
+
{
747
+
"BriefDescription": "Percentage of total non-speculative loads that perform one or more locks",
748
+
"MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
749
+
"MetricName": "tma_info_mem_mix_load_locks_ratio"
750
+
},
751
+
{
752
+
"BriefDescription": "Percentage of total non-speculative loads that are splits",
753
+
"MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
754
+
"MetricName": "tma_info_mem_mix_load_splits_ratio"
755
+
},
756
+
{
757
+
"BriefDescription": "Ratio of mem load uops to all uops",
758
+
"MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING.ALL_P",
759
+
"MetricName": "tma_info_mem_mix_memload_ratio"
760
+
},
761
+
{
762
+
"BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction",
763
+
"MetricExpr": "tma_info_serialization_tpause_cycles",
764
+
"MetricName": "tma_info_serialization _%_tpause_cycles"
765
+
},
766
+
{
767
+
"BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction",
768
+
"MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / (6 * CPU_CLK_UNHALTED.CORE)",
769
+
"MetricName": "tma_info_serialization_tpause_cycles",
770
+
"ScaleUnit": "100%"
771
+
},
772
+
{
773
+
"BriefDescription": "Average CPU Utilization",
774
+
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
775
+
"MetricName": "tma_info_system_cpu_utilization"
776
+
},
777
+
{
778
+
"BriefDescription": "Giga Floating Point Operations Per Second",
779
+
"MetricExpr": "FP_FLOPS_RETIRED.ALL / (duration_time * 1e9)",
780
+
"MetricGroup": "Flops",
781
+
"MetricName": "tma_info_system_gflops",
782
+
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width"
783
+
},
784
+
{
785
+
"BriefDescription": "Fraction of cycles spent in Kernel mode",
786
+
"MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CORE",
787
+
"MetricGroup": "Summary",
788
+
"MetricName": "tma_info_system_kernel_utilization"
789
+
},
790
+
{
791
+
"BriefDescription": "Average Frequency Utilization relative nominal frequency",
792
+
"MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC",
793
+
"MetricGroup": "Power",
794
+
"MetricName": "tma_info_system_turbo_utilization"
795
+
},
796
+
{
797
+
"BriefDescription": "Percentage of all uops which are FPDiv uops",
798
+
"MetricExpr": "100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P",
799
+
"MetricName": "tma_info_uop_mix_fpdiv_uop_ratio"
800
+
},
801
+
{
802
+
"BriefDescription": "Percentage of all uops which are IDiv uops",
803
+
"MetricExpr": "100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P",
804
+
"MetricName": "tma_info_uop_mix_idiv_uop_ratio"
805
+
},
806
+
{
807
+
"BriefDescription": "Percentage of all uops which are microcode ops",
808
+
"MetricExpr": "100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P",
809
+
"MetricName": "tma_info_uop_mix_microcode_uop_ratio"
810
+
},
811
+
{
812
+
"BriefDescription": "Percentage of all uops which are x87 uops",
813
+
"MetricExpr": "100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P",
814
+
"MetricName": "tma_info_uop_mix_x87_uop_ratio"
815
+
},
816
+
{
817
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
818
+
"MetricExpr": "TOPDOWN_FE_BOUND.ITLB_MISS / (6 * CPU_CLK_UNHALTED.CORE)",
819
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
820
+
"MetricName": "tma_itlb_misses",
821
+
"MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
822
+
"ScaleUnit": "100%"
823
+
},
824
+
{
825
+
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation",
826
+
"MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (6 * CPU_CLK_UNHALTED.CORE)",
827
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
828
+
"MetricName": "tma_machine_clears",
829
+
"MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculation > 0.15",
830
+
"MetricgroupNoGroup": "TopdownL2",
831
+
"ScaleUnit": "100%"
832
+
},
833
+
{
834
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops",
835
+
"MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE)",
836
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
837
+
"MetricName": "tma_mem_scheduler",
838
+
"MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
839
+
"ScaleUnit": "100%"
840
+
},
841
+
{
842
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops",
843
+
"MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (6 * CPU_CLK_UNHALTED.CORE)",
844
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
845
+
"MetricName": "tma_non_mem_scheduler",
846
+
"MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
847
+
"ScaleUnit": "100%"
848
+
},
849
+
{
850
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)",
851
+
"MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / (6 * CPU_CLK_UNHALTED.CORE)",
852
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
853
+
"MetricName": "tma_nuke",
854
+
"MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
855
+
"ScaleUnit": "100%"
856
+
},
857
+
{
858
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.",
859
+
"MetricExpr": "TOPDOWN_FE_BOUND.OTHER / (6 * CPU_CLK_UNHALTED.CORE)",
860
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
861
+
"MetricName": "tma_other_fb",
862
+
"MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
863
+
"ScaleUnit": "100%"
864
+
},
865
+
{
866
+
"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.",
867
+
"MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / (6 * CPU_CLK_UNHALTED.CORE)",
868
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
869
+
"MetricName": "tma_predecode",
870
+
"MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
871
+
"ScaleUnit": "100%"
872
+
},
873
+
{
874
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)",
875
+
"MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / (6 * CPU_CLK_UNHALTED.CORE)",
876
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
877
+
"MetricName": "tma_register",
878
+
"MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
879
+
"ScaleUnit": "100%"
880
+
},
881
+
{
882
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)",
883
+
"MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / (6 * CPU_CLK_UNHALTED.CORE)",
884
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
885
+
"MetricName": "tma_reorder_buffer",
886
+
"MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
887
+
"ScaleUnit": "100%"
888
+
},
889
+
{
890
+
"BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation",
891
+
"MetricExpr": "tma_backend_bound - tma_core_bound",
892
+
"MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
893
+
"MetricName": "tma_resource_bound",
894
+
"MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound > 0.1",
895
+
"MetricgroupNoGroup": "TopdownL2",
896
+
"ScaleUnit": "100%"
897
+
},
898
+
{
899
+
"BriefDescription": "Counts the number of issue slots that result in retirement slots",
900
+
"MetricExpr": "TOPDOWN_RETIRING.ALL_P / (6 * CPU_CLK_UNHALTED.CORE)",
901
+
"MetricGroup": "TopdownL1;tma_L1_group",
902
+
"MetricName": "tma_retiring",
903
+
"MetricThreshold": "tma_retiring > 0.75",
904
+
"MetricgroupNoGroup": "TopdownL1",
905
+
"ScaleUnit": "100%"
906
+
},
907
+
{
908
+
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)",
909
+
"MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / (6 * CPU_CLK_UNHALTED.CORE)",
910
+
"MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
911
+
"MetricName": "tma_serialization",
912
+
"MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
913
+
"ScaleUnit": "100%"
914
+
},
915
+
{
916
+
"BriefDescription": "Uncore operating frequency in GHz",
917
+
"MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
918
+
"MetricName": "uncore_frequency",
919
+
"ScaleUnit": "1GHz"
920
+
},
921
+
{
922
+
"BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
923
+
"MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
924
+
"MetricName": "upi_data_transmit_bw",
925
+
"ScaleUnit": "1MB/s"
926
+
}
927
+
]
+531
-36
tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json
+531
-36
tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Clockticks for CMS units attached to CHA",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x01",
5
6
"EventName": "UNC_CHACMS_CLOCKTICKS",
6
7
"PerPkg": "1",
···
11
10
},
12
11
{
13
12
"BriefDescription": "Number of CHA clock cycles while the event is enabled",
13
+
"Counter": "0,1,2,3",
14
14
"EventCode": "0x01",
15
15
"EventName": "UNC_CHA_CLOCKTICKS",
16
16
"PerPkg": "1",
···
20
18
},
21
19
{
22
20
"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.",
21
+
"Counter": "0,1,2,3",
23
22
"EventCode": "0x53",
24
23
"EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
24
+
"Experimental": "1",
25
25
"PerPkg": "1",
26
26
"UMask": "0x2",
27
27
"Unit": "CHA"
28
28
},
29
29
{
30
30
"BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.",
31
+
"Counter": "0,1,2,3",
31
32
"EventCode": "0x53",
32
33
"EventName": "UNC_CHA_DIR_LOOKUP.SNP",
34
+
"Experimental": "1",
33
35
"PerPkg": "1",
34
36
"UMask": "0x1",
35
37
"Unit": "CHA"
36
38
},
37
39
{
38
40
"BriefDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
41
+
"Counter": "0,1,2,3",
39
42
"EventCode": "0x54",
40
43
"EventName": "UNC_CHA_DIR_UPDATE.HA",
44
+
"Experimental": "1",
41
45
"PerPkg": "1",
42
46
"UMask": "0x1",
43
47
"Unit": "CHA"
44
48
},
45
49
{
46
50
"BriefDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
51
+
"Counter": "0,1,2,3",
47
52
"EventCode": "0x54",
48
53
"EventName": "UNC_CHA_DIR_UPDATE.TOR",
54
+
"Experimental": "1",
49
55
"PerPkg": "1",
50
56
"UMask": "0x2",
51
57
"Unit": "CHA"
52
58
},
53
59
{
54
60
"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).",
61
+
"Counter": "0,1,2,3",
55
62
"EventCode": "0x59",
56
63
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY",
57
64
"PerPkg": "1",
···
70
59
},
71
60
{
72
61
"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).",
62
+
"Counter": "0,1,2,3",
73
63
"EventCode": "0x59",
74
64
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ",
75
65
"PerPkg": "1",
···
79
67
},
80
68
{
81
69
"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).",
70
+
"Counter": "0,1,2,3",
82
71
"EventCode": "0x59",
83
72
"EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR",
84
73
"PerPkg": "1",
···
88
75
},
89
76
{
90
77
"BriefDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
78
+
"Counter": "0,1,2,3",
91
79
"EventCode": "0x5b",
92
80
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
81
+
"Experimental": "1",
93
82
"PerPkg": "1",
94
83
"UMask": "0x1",
95
84
"Unit": "CHA"
96
85
},
97
86
{
98
87
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
88
+
"Counter": "0,1,2,3",
99
89
"EventCode": "0x5b",
100
90
"EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
91
+
"Experimental": "1",
101
92
"PerPkg": "1",
102
93
"UMask": "0x4",
103
94
"Unit": "CHA"
104
95
},
105
96
{
106
97
"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
98
+
"Counter": "0,1,2,3",
107
99
"EventCode": "0x5b",
108
100
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
101
+
"Experimental": "1",
109
102
"PerPkg": "1",
110
103
"UMask": "0x2",
111
104
"Unit": "CHA"
112
105
},
113
106
{
114
107
"BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
108
+
"Counter": "0,1,2,3",
115
109
"EventCode": "0x5b",
116
110
"EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
111
+
"Experimental": "1",
117
112
"PerPkg": "1",
118
113
"UMask": "0x8",
119
114
"Unit": "CHA"
120
115
},
121
116
{
122
117
"BriefDescription": "Cache Lookups: All Requests to Remotely Homed Memory",
118
+
"Counter": "0,1,2,3",
123
119
"EventCode": "0x34",
124
120
"EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
121
+
"Experimental": "1",
125
122
"PerPkg": "1",
126
123
"PublicDescription": "Cache Lookups : All transactions from Remote Agents",
127
124
"UMask": "0x17e0ff",
···
139
116
},
140
117
{
141
118
"BriefDescription": "Cache Lookups: CRd Requests",
119
+
"Counter": "0,1,2,3",
142
120
"EventCode": "0x34",
143
121
"EventName": "UNC_CHA_LLC_LOOKUP.CODE",
122
+
"Experimental": "1",
144
123
"PerPkg": "1",
145
124
"PublicDescription": "Cache Lookups : CRd Requests",
146
125
"UMask": "0x1bd0ff",
···
150
125
},
151
126
{
152
127
"BriefDescription": "Cache Lookups: Read Requests and Read Prefetches",
128
+
"Counter": "0,1,2,3",
153
129
"EventCode": "0x34",
154
130
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
131
+
"Experimental": "1",
155
132
"PerPkg": "1",
156
133
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
157
134
"UMask": "0x1bc1ff",
···
161
134
},
162
135
{
163
136
"BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops",
137
+
"Counter": "0,1,2,3",
164
138
"EventCode": "0x34",
165
139
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
140
+
"Experimental": "1",
166
141
"PerPkg": "1",
167
142
"PublicDescription": "Cache Lookups : Data Reads",
168
143
"UMask": "0x1fc1ff",
···
172
143
},
173
144
{
174
145
"BriefDescription": "Cache Lookups: Read Requests to Locally Homed Memory",
146
+
"Counter": "0,1,2,3",
175
147
"EventCode": "0x34",
176
148
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
149
+
"Experimental": "1",
177
150
"PerPkg": "1",
178
151
"PublicDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches",
179
152
"UMask": "0x841ff",
···
183
152
},
184
153
{
185
154
"BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cache",
155
+
"Counter": "0,1,2,3",
186
156
"EventCode": "0x34",
187
157
"EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
158
+
"Experimental": "1",
188
159
"PerPkg": "1",
189
160
"PublicDescription": "Cache Lookups : Data Read Misses",
190
161
"UMask": "0x1fc101",
···
194
161
},
195
162
{
196
163
"BriefDescription": "Cache Lookups: All Requests to Locally Homed Memory",
164
+
"Counter": "0,1,2,3",
197
165
"EventCode": "0x34",
198
166
"EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
167
+
"Experimental": "1",
199
168
"PerPkg": "1",
200
169
"PublicDescription": "Cache Lookups : Transactions homed locally",
201
170
"UMask": "0xbdfff",
···
205
170
},
206
171
{
207
172
"BriefDescription": "Cache Lookups: Code Read Requests and Code Read Prefetches to Locally Homed Memory",
173
+
"Counter": "0,1,2,3",
208
174
"EventCode": "0x34",
209
175
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE",
176
+
"Experimental": "1",
210
177
"PerPkg": "1",
211
178
"PublicDescription": "Cache Lookups : CRd Requests",
212
179
"UMask": "0x19d0ff",
···
216
179
},
217
180
{
218
181
"BriefDescription": "Cache Lookups: Read Requests and Read Prefetches to Locally Homed Memory",
182
+
"Counter": "0,1,2,3",
219
183
"EventCode": "0x34",
220
184
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD",
185
+
"Experimental": "1",
221
186
"PerPkg": "1",
222
187
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
223
188
"UMask": "0x19c1ff",
···
227
188
},
228
189
{
229
190
"BriefDescription": "Cache Lookups: Code Read Requests to Locally Homed Memory",
191
+
"Counter": "0,1,2,3",
230
192
"EventCode": "0x34",
231
193
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE",
194
+
"Experimental": "1",
232
195
"PerPkg": "1",
233
196
"PublicDescription": "Cache Lookups : CRd Requests",
234
197
"UMask": "0x1850ff",
···
238
197
},
239
198
{
240
199
"BriefDescription": "Cache Lookups: Read Requests to Locally Homed Memory",
200
+
"Counter": "0,1,2,3",
241
201
"EventCode": "0x34",
242
202
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD",
203
+
"Experimental": "1",
243
204
"PerPkg": "1",
244
205
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
245
206
"UMask": "0x1841ff",
···
249
206
},
250
207
{
251
208
"BriefDescription": "Cache Lookups: RFO Requests to Locally Homed Memory",
209
+
"Counter": "0,1,2,3",
252
210
"EventCode": "0x34",
253
211
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO",
212
+
"Experimental": "1",
254
213
"PerPkg": "1",
255
214
"PublicDescription": "Cache Lookups : RFO Requests",
256
215
"UMask": "0x1848ff",
···
260
215
},
261
216
{
262
217
"BriefDescription": "Cache Lookups: LLC Prefetch Requests to Locally Homed Memory",
218
+
"Counter": "0,1,2,3",
263
219
"EventCode": "0x34",
264
220
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF",
221
+
"Experimental": "1",
265
222
"PerPkg": "1",
266
223
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
267
224
"UMask": "0x189dff",
···
271
224
},
272
225
{
273
226
"BriefDescription": "Cache Lookups: All Prefetches to Locally Homed Memory",
227
+
"Counter": "0,1,2,3",
274
228
"EventCode": "0x34",
275
229
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF",
230
+
"Experimental": "1",
276
231
"PerPkg": "1",
277
232
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
278
233
"UMask": "0x199dff",
···
282
233
},
283
234
{
284
235
"BriefDescription": "Cache Lookups: Code Prefetches to Locally Homed Memory",
236
+
"Counter": "0,1,2,3",
285
237
"EventCode": "0x34",
286
238
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE",
239
+
"Experimental": "1",
287
240
"PerPkg": "1",
288
241
"PublicDescription": "Cache Lookups : CRd Requests",
289
242
"UMask": "0x1910ff",
···
293
242
},
294
243
{
295
244
"BriefDescription": "Cache Lookups: Read Prefetches to Locally Homed Memory",
245
+
"Counter": "0,1,2,3",
296
246
"EventCode": "0x34",
297
247
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD",
248
+
"Experimental": "1",
298
249
"PerPkg": "1",
299
250
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
300
251
"UMask": "0x1981ff",
···
304
251
},
305
252
{
306
253
"BriefDescription": "Cache Lookups: RFO Prefetches to Locally Homed Memory",
254
+
"Counter": "0,1,2,3",
307
255
"EventCode": "0x34",
308
256
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO",
257
+
"Experimental": "1",
309
258
"PerPkg": "1",
310
259
"PublicDescription": "Cache Lookups : RFO Requests",
311
260
"UMask": "0x1908ff",
···
315
260
},
316
261
{
317
262
"BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory",
263
+
"Counter": "0,1,2,3",
318
264
"EventCode": "0x34",
319
265
"EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO",
266
+
"Experimental": "1",
320
267
"PerPkg": "1",
321
268
"PublicDescription": "Cache Lookups : RFO Requests",
322
269
"UMask": "0x19c8ff",
···
326
269
},
327
270
{
328
271
"BriefDescription": "Cache Lookups: All Requests to Remotely Homed Memory",
272
+
"Counter": "0,1,2,3",
329
273
"EventCode": "0x34",
330
274
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
275
+
"Experimental": "1",
331
276
"PerPkg": "1",
332
277
"PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
333
278
"UMask": "0x15dfff",
···
337
278
},
338
279
{
339
280
"BriefDescription": "Cache Lookups: Code Read/Prefetch Requests from a Remote Socket",
281
+
"Counter": "0,1,2,3",
340
282
"EventCode": "0x34",
341
283
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE",
284
+
"Experimental": "1",
342
285
"PerPkg": "1",
343
286
"PublicDescription": "Cache Lookups : CRd Requests",
344
287
"UMask": "0x1a10ff",
···
348
287
},
349
288
{
350
289
"BriefDescription": "Cache Lookups: Data Read/Prefetch Requests from a Remote Socket",
290
+
"Counter": "0,1,2,3",
351
291
"EventCode": "0x34",
352
292
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD",
293
+
"Experimental": "1",
353
294
"PerPkg": "1",
354
295
"PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
355
296
"UMask": "0x1a01ff",
···
359
296
},
360
297
{
361
298
"BriefDescription": "Cache Lookups: RFO Requests/Prefetches from a Remote Socket",
299
+
"Counter": "0,1,2,3",
362
300
"EventCode": "0x34",
363
301
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO",
302
+
"Experimental": "1",
364
303
"PerPkg": "1",
365
304
"PublicDescription": "Cache Lookups : RFO Requests",
366
305
"UMask": "0x1a08ff",
···
370
305
},
371
306
{
372
307
"BriefDescription": "Cache Lookups: Snoop Requests from a Remote Socket",
308
+
"Counter": "0,1,2,3",
373
309
"EventCode": "0x34",
374
310
"EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
311
+
"Experimental": "1",
375
312
"PerPkg": "1",
376
313
"PublicDescription": "Counts the number of times the LLC was accessed",
377
314
"UMask": "0x1c19ff",
···
381
314
},
382
315
{
383
316
"BriefDescription": "Cache Lookups: All RFO and RFO Prefetches",
317
+
"Counter": "0,1,2,3",
384
318
"EventCode": "0x34",
385
319
"EventName": "UNC_CHA_LLC_LOOKUP.RFO",
320
+
"Experimental": "1",
386
321
"PerPkg": "1",
387
322
"PublicDescription": "Cache Lookups : All RFOs - Demand and Prefetches",
388
323
"UMask": "0x1bc8ff",
···
392
323
},
393
324
{
394
325
"BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory",
326
+
"Counter": "0,1,2,3",
395
327
"EventCode": "0x34",
396
328
"EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
329
+
"Experimental": "1",
397
330
"PerPkg": "1",
398
331
"PublicDescription": "Cache Lookups : Locally HOMed RFOs - Demand and Prefetches",
399
332
"UMask": "0x9c8ff",
···
403
332
},
404
333
{
405
334
"BriefDescription": "Cache Lookups: Writes to Locally Homed Memory (includes writebacks from L1/L2)",
335
+
"Counter": "0,1,2,3",
406
336
"EventCode": "0x34",
407
337
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
338
+
"Experimental": "1",
408
339
"PerPkg": "1",
409
340
"PublicDescription": "Cache Lookups : Writes",
410
341
"UMask": "0x842ff",
···
414
341
},
415
342
{
416
343
"BriefDescription": "Cache Lookups: Writes to Remotely Homed Memory (includes writebacks from L1/L2)",
344
+
"Counter": "0,1,2,3",
417
345
"EventCode": "0x34",
418
346
"EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
347
+
"Experimental": "1",
419
348
"PerPkg": "1",
420
349
"PublicDescription": "Cache Lookups : Remote Writes",
421
350
"UMask": "0x17c2ff",
···
425
350
},
426
351
{
427
352
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
353
+
"Counter": "0,1,2,3",
428
354
"EventCode": "0x37",
429
355
"EventName": "UNC_CHA_LLC_VICTIMS.ALL",
356
+
"Experimental": "1",
430
357
"PerPkg": "1",
431
358
"PublicDescription": "Lines Victimized : All Lines Victimized",
432
359
"UMask": "0xf",
···
436
359
},
437
360
{
438
361
"BriefDescription": "Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
362
+
"Counter": "0,1,2,3",
439
363
"EventCode": "0x37",
440
364
"EventName": "UNC_CHA_LLC_VICTIMS.IA",
365
+
"Experimental": "1",
441
366
"PerPkg": "1",
442
367
"UMask": "0x20",
443
368
"Unit": "CHA"
444
369
},
445
370
{
446
371
"BriefDescription": "Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
372
+
"Counter": "0,1,2,3",
447
373
"EventCode": "0x37",
448
374
"EventName": "UNC_CHA_LLC_VICTIMS.IO",
375
+
"Experimental": "1",
449
376
"PerPkg": "1",
450
377
"UMask": "0x10",
451
378
"Unit": "CHA"
452
379
},
453
380
{
454
381
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
382
+
"Counter": "0,1,2,3",
455
383
"EventCode": "0x37",
456
384
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
385
+
"Experimental": "1",
457
386
"PerPkg": "1",
458
387
"PublicDescription": "Lines Victimized : Local - All Lines",
459
388
"UMask": "0x200f",
···
467
384
},
468
385
{
469
386
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
387
+
"Counter": "0,1,2,3",
470
388
"EventCode": "0x37",
471
389
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
390
+
"Experimental": "1",
472
391
"PerPkg": "1",
473
392
"PublicDescription": "Lines Victimized : Local - Lines in E State",
474
393
"UMask": "0x2002",
···
478
393
},
479
394
{
480
395
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
396
+
"Counter": "0,1,2,3",
481
397
"EventCode": "0x37",
482
398
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
399
+
"Experimental": "1",
483
400
"PerPkg": "1",
484
401
"PublicDescription": "Lines Victimized : Local - Lines in F State",
485
402
"UMask": "0x2008",
···
489
402
},
490
403
{
491
404
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
405
+
"Counter": "0,1,2,3",
492
406
"EventCode": "0x37",
493
407
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
408
+
"Experimental": "1",
494
409
"PerPkg": "1",
495
410
"PublicDescription": "Lines Victimized : Local - Lines in M State",
496
411
"UMask": "0x2001",
···
500
411
},
501
412
{
502
413
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
414
+
"Counter": "0,1,2,3",
503
415
"EventCode": "0x37",
504
416
"EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
417
+
"Experimental": "1",
505
418
"PerPkg": "1",
506
419
"PublicDescription": "Lines Victimized : Local - Lines in S State",
507
420
"UMask": "0x2004",
···
511
420
},
512
421
{
513
422
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
423
+
"Counter": "0,1,2,3",
514
424
"EventCode": "0x37",
515
425
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
426
+
"Experimental": "1",
516
427
"PerPkg": "1",
517
428
"PublicDescription": "Lines Victimized : Remote - All Lines",
518
429
"UMask": "0x800f",
···
522
429
},
523
430
{
524
431
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
432
+
"Counter": "0,1,2,3",
525
433
"EventCode": "0x37",
526
434
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
435
+
"Experimental": "1",
527
436
"PerPkg": "1",
528
437
"PublicDescription": "Lines Victimized : Remote - Lines in E State",
529
438
"UMask": "0x8002",
···
533
438
},
534
439
{
535
440
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
441
+
"Counter": "0,1,2,3",
536
442
"EventCode": "0x37",
537
443
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
444
+
"Experimental": "1",
538
445
"PerPkg": "1",
539
446
"PublicDescription": "Lines Victimized : Remote - Lines in M State",
540
447
"UMask": "0x8001",
···
544
447
},
545
448
{
546
449
"BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
450
+
"Counter": "0,1,2,3",
547
451
"EventCode": "0x37",
548
452
"EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
453
+
"Experimental": "1",
549
454
"PerPkg": "1",
550
455
"PublicDescription": "Lines Victimized : Remote - Lines in S State",
551
456
"UMask": "0x8004",
···
555
456
},
556
457
{
557
458
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
459
+
"Counter": "0,1,2,3",
558
460
"EventCode": "0x37",
559
461
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
462
+
"Experimental": "1",
560
463
"PerPkg": "1",
561
464
"PublicDescription": "Lines Victimized : Lines in E state",
562
465
"UMask": "0x2",
···
566
465
},
567
466
{
568
467
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
468
+
"Counter": "0,1,2,3",
569
469
"EventCode": "0x37",
570
470
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
471
+
"Experimental": "1",
571
472
"PerPkg": "1",
572
473
"PublicDescription": "Lines Victimized : Lines in M state",
573
474
"UMask": "0x1",
···
577
474
},
578
475
{
579
476
"BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
477
+
"Counter": "0,1,2,3",
580
478
"EventCode": "0x37",
581
479
"EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
480
+
"Experimental": "1",
582
481
"PerPkg": "1",
583
482
"PublicDescription": "Lines Victimized : Lines in S State",
584
483
"UMask": "0x4",
···
588
483
},
589
484
{
590
485
"BriefDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
486
+
"Counter": "0,1,2,3",
591
487
"EventCode": "0x39",
592
488
"EventName": "UNC_CHA_MISC.RFO_HIT_S",
593
489
"PerPkg": "1",
···
598
492
},
599
493
{
600
494
"BriefDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
495
+
"Counter": "0,1,2,3",
601
496
"EventCode": "0x55",
602
497
"EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
498
+
"Experimental": "1",
603
499
"PerPkg": "1",
604
500
"UMask": "0x1",
605
501
"Unit": "CHA"
606
502
},
607
503
{
608
504
"BriefDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
505
+
"Counter": "0,1,2,3",
609
506
"EventCode": "0x55",
610
507
"EventName": "UNC_CHA_OSB.LOCAL_READ",
508
+
"Experimental": "1",
611
509
"PerPkg": "1",
612
510
"UMask": "0x2",
613
511
"Unit": "CHA"
614
512
},
615
513
{
616
514
"BriefDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
515
+
"Counter": "0,1,2,3",
617
516
"EventCode": "0x55",
618
517
"EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
518
+
"Experimental": "1",
619
519
"PerPkg": "1",
620
520
"UMask": "0x20",
621
521
"Unit": "CHA"
622
522
},
623
523
{
624
524
"BriefDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
525
+
"Counter": "0,1,2,3",
625
526
"EventCode": "0x55",
626
527
"EventName": "UNC_CHA_OSB.REMOTE_READ",
528
+
"Experimental": "1",
627
529
"PerPkg": "1",
628
530
"UMask": "0x4",
629
531
"Unit": "CHA"
630
532
},
631
533
{
632
534
"BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
535
+
"Counter": "0,1,2,3",
633
536
"EventCode": "0x55",
634
537
"EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
635
538
"PerPkg": "1",
···
647
532
},
648
533
{
649
534
"BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE",
535
+
"Counter": "0,1,2,3",
650
536
"EventCode": "0x69",
651
537
"EventName": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE",
538
+
"Experimental": "1",
652
539
"PerPkg": "1",
653
540
"UMask": "0x10",
654
541
"Unit": "CHA"
655
542
},
656
543
{
657
544
"BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_SHARED",
545
+
"Counter": "0,1,2,3",
658
546
"EventCode": "0x69",
659
547
"EventName": "UNC_CHA_REMOTE_SF.ALLOC_SHARED",
548
+
"Experimental": "1",
660
549
"PerPkg": "1",
661
550
"UMask": "0x8",
662
551
"Unit": "CHA"
663
552
},
664
553
{
665
554
"BriefDescription": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN",
555
+
"Counter": "0,1,2,3",
666
556
"EventCode": "0x69",
667
557
"EventName": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN",
558
+
"Experimental": "1",
668
559
"PerPkg": "1",
669
560
"UMask": "0x40",
670
561
"Unit": "CHA"
671
562
},
672
563
{
673
564
"BriefDescription": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY",
565
+
"Counter": "0,1,2,3",
674
566
"EventCode": "0x69",
675
567
"EventName": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY",
568
+
"Experimental": "1",
676
569
"PerPkg": "1",
677
570
"Unit": "CHA"
678
571
},
679
572
{
680
573
"BriefDescription": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE",
574
+
"Counter": "0,1,2,3",
681
575
"EventCode": "0x69",
682
576
"EventName": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE",
577
+
"Experimental": "1",
683
578
"PerPkg": "1",
684
579
"UMask": "0x2",
685
580
"Unit": "CHA"
686
581
},
687
582
{
688
583
"BriefDescription": "UNC_CHA_REMOTE_SF.HIT_SHARED",
584
+
"Counter": "0,1,2,3",
689
585
"EventCode": "0x69",
690
586
"EventName": "UNC_CHA_REMOTE_SF.HIT_SHARED",
587
+
"Experimental": "1",
691
588
"PerPkg": "1",
692
589
"UMask": "0x1",
693
590
"Unit": "CHA"
694
591
},
695
592
{
696
593
"BriefDescription": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY",
594
+
"Counter": "0,1,2,3",
697
595
"EventCode": "0x69",
698
596
"EventName": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY",
597
+
"Experimental": "1",
699
598
"PerPkg": "1",
700
599
"Unit": "CHA"
701
600
},
702
601
{
703
602
"BriefDescription": "UNC_CHA_REMOTE_SF.MISS",
603
+
"Counter": "0,1,2,3",
704
604
"EventCode": "0x69",
705
605
"EventName": "UNC_CHA_REMOTE_SF.MISS",
706
606
"PerPkg": "1",
···
724
594
},
725
595
{
726
596
"BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE",
597
+
"Counter": "0,1,2,3",
727
598
"EventCode": "0x69",
728
599
"EventName": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE",
600
+
"Experimental": "1",
729
601
"PerPkg": "1",
730
602
"Unit": "CHA"
731
603
},
732
604
{
733
605
"BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_SHARED",
606
+
"Counter": "0,1,2,3",
734
607
"EventCode": "0x69",
735
608
"EventName": "UNC_CHA_REMOTE_SF.UPDATE_SHARED",
609
+
"Experimental": "1",
736
610
"PerPkg": "1",
737
611
"UMask": "0x80",
738
612
"Unit": "CHA"
739
613
},
740
614
{
741
615
"BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE",
616
+
"Counter": "0,1,2,3",
742
617
"EventCode": "0x69",
743
618
"EventName": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE",
619
+
"Experimental": "1",
744
620
"PerPkg": "1",
745
621
"Unit": "CHA"
746
622
},
747
623
{
748
624
"BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_SHARED",
625
+
"Counter": "0,1,2,3",
749
626
"EventCode": "0x69",
750
627
"EventName": "UNC_CHA_REMOTE_SF.VICTIM_SHARED",
628
+
"Experimental": "1",
751
629
"PerPkg": "1",
752
630
"Unit": "CHA"
753
631
},
754
632
{
755
633
"BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
634
+
"Counter": "0,1,2,3",
756
635
"EventCode": "0x50",
757
636
"EventName": "UNC_CHA_REQUESTS.INVITOE",
758
637
"PerPkg": "1",
···
771
632
},
772
633
{
773
634
"BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
635
+
"Counter": "0,1,2,3",
774
636
"EventCode": "0x50",
775
637
"EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
776
638
"PerPkg": "1",
···
780
640
},
781
641
{
782
642
"BriefDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
643
+
"Counter": "0,1,2,3",
783
644
"EventCode": "0x50",
784
645
"EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
785
646
"PerPkg": "1",
···
789
648
},
790
649
{
791
650
"BriefDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
651
+
"Counter": "0,1,2,3",
792
652
"EventCode": "0x50",
793
653
"EventName": "UNC_CHA_REQUESTS.READS",
794
654
"PerPkg": "1",
···
799
657
},
800
658
{
801
659
"BriefDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
660
+
"Counter": "0,1,2,3",
802
661
"EventCode": "0x50",
803
662
"EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
804
663
"PerPkg": "1",
···
808
665
},
809
666
{
810
667
"BriefDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
668
+
"Counter": "0,1,2,3",
811
669
"EventCode": "0x50",
812
670
"EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
813
671
"PerPkg": "1",
···
817
673
},
818
674
{
819
675
"BriefDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
676
+
"Counter": "0,1,2,3",
820
677
"EventCode": "0x50",
821
678
"EventName": "UNC_CHA_REQUESTS.WRITES",
822
679
"PerPkg": "1",
···
827
682
},
828
683
{
829
684
"BriefDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
685
+
"Counter": "0,1,2,3",
830
686
"EventCode": "0x50",
831
687
"EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
832
688
"PerPkg": "1",
···
836
690
},
837
691
{
838
692
"BriefDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
693
+
"Counter": "0,1,2,3",
839
694
"EventCode": "0x50",
840
695
"EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
841
696
"PerPkg": "1",
···
845
698
},
846
699
{
847
700
"BriefDescription": "All TOR Inserts",
701
+
"Counter": "0,1,2,3",
848
702
"EventCode": "0x35",
849
703
"EventName": "UNC_CHA_TOR_INSERTS.ALL",
704
+
"Experimental": "1",
850
705
"PerPkg": "1",
851
706
"PublicDescription": "TOR Inserts : All",
852
707
"UMask": "0xc001ffff",
···
856
707
},
857
708
{
858
709
"BriefDescription": "CLFlush transactions from a CXL device which hit in the L3.",
710
+
"Counter": "0,1,2,3",
859
711
"EventCode": "0x35",
860
712
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_CLFLUSH",
713
+
"Experimental": "1",
861
714
"PerPkg": "1",
862
715
"UMask": "0x78c8c7fd20",
863
716
"Unit": "CHA"
864
717
},
865
718
{
866
719
"BriefDescription": "FsRdCur transactions from a CXL device which hit in the L3.",
720
+
"Counter": "0,1,2,3",
867
721
"EventCode": "0x35",
868
722
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCUR",
723
+
"Experimental": "1",
869
724
"PerPkg": "1",
870
725
"UMask": "0x78c8effd20",
871
726
"Unit": "CHA"
872
727
},
873
728
{
874
729
"BriefDescription": "FsRdCurPtl transactions from a CXL device which hit in the L3.",
730
+
"Counter": "0,1,2,3",
875
731
"EventCode": "0x35",
876
732
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCURPTL",
733
+
"Experimental": "1",
877
734
"PerPkg": "1",
878
735
"UMask": "0x78c9effd20",
879
736
"Unit": "CHA"
880
737
},
881
738
{
882
739
"BriefDescription": "ItoM transactions from a CXL device which hit in the L3.",
740
+
"Counter": "0,1,2,3",
883
741
"EventCode": "0x35",
884
742
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOM",
743
+
"Experimental": "1",
885
744
"PerPkg": "1",
886
745
"UMask": "0x78cc47fd20",
887
746
"Unit": "CHA"
888
747
},
889
748
{
890
749
"BriefDescription": "ItoMWr transactions from a CXL device which hit in the L3.",
750
+
"Counter": "0,1,2,3",
891
751
"EventCode": "0x35",
892
752
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOMWR",
753
+
"Experimental": "1",
893
754
"PerPkg": "1",
894
755
"UMask": "0x78cc4ffd20",
895
756
"Unit": "CHA"
896
757
},
897
758
{
898
759
"BriefDescription": "MemPushWr transactions from a CXL device which hit in the L3.",
760
+
"Counter": "0,1,2,3",
899
761
"EventCode": "0x35",
900
762
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_MEMPUSHWR",
763
+
"Experimental": "1",
901
764
"PerPkg": "1",
902
765
"UMask": "0x78cc6ffd20",
903
766
"Unit": "CHA"
904
767
},
905
768
{
906
769
"BriefDescription": "WCiL transactions from a CXL device which hit in the L3.",
770
+
"Counter": "0,1,2,3",
907
771
"EventCode": "0x35",
908
772
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCIL",
773
+
"Experimental": "1",
909
774
"PerPkg": "1",
910
775
"UMask": "0x78c86ffd20",
911
776
"Unit": "CHA"
912
777
},
913
778
{
914
779
"BriefDescription": "WcilF transactions from a CXL device which hit in the L3.",
780
+
"Counter": "0,1,2,3",
915
781
"EventCode": "0x35",
916
782
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCILF",
783
+
"Experimental": "1",
917
784
"PerPkg": "1",
918
785
"UMask": "0x78c867fd20",
919
786
"Unit": "CHA"
920
787
},
921
788
{
922
789
"BriefDescription": "WiL transactions from a CXL device which hit in the L3.",
790
+
"Counter": "0,1,2,3",
923
791
"EventCode": "0x35",
924
792
"EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WIL",
793
+
"Experimental": "1",
925
794
"PerPkg": "1",
926
795
"UMask": "0x78c87ffd20",
927
796
"Unit": "CHA"
928
797
},
929
798
{
930
799
"BriefDescription": "CLFlush transactions from a CXL device which miss the L3.",
800
+
"Counter": "0,1,2,3",
931
801
"EventCode": "0x35",
932
802
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_CLFLUSH",
803
+
"Experimental": "1",
933
804
"PerPkg": "1",
934
805
"UMask": "0x78c8c7fe20",
935
806
"Unit": "CHA"
936
807
},
937
808
{
938
809
"BriefDescription": "FsRdCur transactions from a CXL device which miss the L3.",
810
+
"Counter": "0,1,2,3",
939
811
"EventCode": "0x35",
940
812
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCUR",
813
+
"Experimental": "1",
941
814
"PerPkg": "1",
942
815
"UMask": "0x78c8effe20",
943
816
"Unit": "CHA"
944
817
},
945
818
{
946
819
"BriefDescription": "FsRdCurPtl transactions from a CXL device which miss the L3.",
820
+
"Counter": "0,1,2,3",
947
821
"EventCode": "0x35",
948
822
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCURPTL",
823
+
"Experimental": "1",
949
824
"PerPkg": "1",
950
825
"UMask": "0x78c9effe20",
951
826
"Unit": "CHA"
952
827
},
953
828
{
954
829
"BriefDescription": "ItoM transactions from a CXL device which miss the L3.",
830
+
"Counter": "0,1,2,3",
955
831
"EventCode": "0x35",
956
832
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOM",
833
+
"Experimental": "1",
957
834
"PerPkg": "1",
958
835
"UMask": "0x78cc47fe20",
959
836
"Unit": "CHA"
960
837
},
961
838
{
962
839
"BriefDescription": "ItoMWr transactions from a CXL device which miss the L3.",
840
+
"Counter": "0,1,2,3",
963
841
"EventCode": "0x35",
964
842
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOMWR",
843
+
"Experimental": "1",
965
844
"PerPkg": "1",
966
845
"UMask": "0x78cc4ffe20",
967
846
"Unit": "CHA"
968
847
},
969
848
{
970
849
"BriefDescription": "MemPushWr transactions from a CXL device which miss the L3.",
850
+
"Counter": "0,1,2,3",
971
851
"EventCode": "0x35",
972
852
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_MEMPUSHWR",
853
+
"Experimental": "1",
973
854
"PerPkg": "1",
974
855
"UMask": "0x78cc6ffe20",
975
856
"Unit": "CHA"
976
857
},
977
858
{
978
859
"BriefDescription": "WCiL transactions from a CXL device which miss the L3.",
860
+
"Counter": "0,1,2,3",
979
861
"EventCode": "0x35",
980
862
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCIL",
863
+
"Experimental": "1",
981
864
"PerPkg": "1",
982
865
"UMask": "0x78c86ffe20",
983
866
"Unit": "CHA"
984
867
},
985
868
{
986
869
"BriefDescription": "WcilF transactions from a CXL device which miss the L3.",
870
+
"Counter": "0,1,2,3",
987
871
"EventCode": "0x35",
988
872
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCILF",
873
+
"Experimental": "1",
989
874
"PerPkg": "1",
990
875
"UMask": "0x78c867fe20",
991
876
"Unit": "CHA"
992
877
},
993
878
{
994
879
"BriefDescription": "WiL transactions from a CXL device which miss the L3.",
880
+
"Counter": "0,1,2,3",
995
881
"EventCode": "0x35",
996
882
"EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WIL",
883
+
"Experimental": "1",
997
884
"PerPkg": "1",
998
885
"UMask": "0x78c87ffe20",
999
886
"Unit": "CHA"
1000
887
},
1001
888
{
1002
889
"BriefDescription": "All locally initiated requests from IA Cores",
890
+
"Counter": "0,1,2,3",
1003
891
"EventCode": "0x35",
1004
892
"EventName": "UNC_CHA_TOR_INSERTS.IA",
893
+
"Experimental": "1",
1005
894
"PerPkg": "1",
1006
895
"PublicDescription": "TOR Inserts : All requests from iA Cores",
1007
896
"UMask": "0xc001ff01",
···
1047
860
},
1048
861
{
1049
862
"BriefDescription": "CLFlush events that are initiated from the Core",
863
+
"Counter": "0,1,2,3",
1050
864
"EventCode": "0x35",
1051
865
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
1052
866
"PerPkg": "1",
···
1057
869
},
1058
870
{
1059
871
"BriefDescription": "CLFlushOpt events that are initiated from the Core",
872
+
"Counter": "0,1,2,3",
1060
873
"EventCode": "0x35",
1061
874
"EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT",
1062
875
"PerPkg": "1",
···
1067
878
},
1068
879
{
1069
880
"BriefDescription": "Code read from local IA that miss the cache",
881
+
"Counter": "0,1,2,3",
1070
882
"EventCode": "0x35",
1071
883
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
1072
884
"PerPkg": "1",
···
1077
887
},
1078
888
{
1079
889
"BriefDescription": "Code read prefetch from local IA that miss the cache",
890
+
"Counter": "0,1,2,3",
1080
891
"EventCode": "0x35",
1081
892
"EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
1082
893
"PerPkg": "1",
···
1087
896
},
1088
897
{
1089
898
"BriefDescription": "Data read opt from local IA that miss the cache",
899
+
"Counter": "0,1,2,3",
1090
900
"EventCode": "0x35",
1091
901
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT",
1092
902
"PerPkg": "1",
···
1097
905
},
1098
906
{
1099
907
"BriefDescription": "Data read opt prefetch from local IA that miss the cache",
908
+
"Counter": "0,1,2,3",
1100
909
"EventCode": "0x35",
1101
910
"EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF",
1102
911
"PerPkg": "1",
···
1107
914
},
1108
915
{
1109
916
"BriefDescription": "All locally initiated requests from IA Cores which hit the cache",
917
+
"Counter": "0,1,2,3",
1110
918
"EventCode": "0x35",
1111
919
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
920
+
"Experimental": "1",
1112
921
"PerPkg": "1",
1113
922
"PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
1114
923
"UMask": "0xc001fd01",
···
1118
923
},
1119
924
{
1120
925
"BriefDescription": "Code read from local IA that hit the cache",
926
+
"Counter": "0,1,2,3",
1121
927
"EventCode": "0x35",
1122
928
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
1123
929
"PerPkg": "1",
···
1128
932
},
1129
933
{
1130
934
"BriefDescription": "Code read prefetch from local IA that hit the cache",
935
+
"Counter": "0,1,2,3",
1131
936
"EventCode": "0x35",
1132
937
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
1133
938
"PerPkg": "1",
···
1138
941
},
1139
942
{
1140
943
"BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
944
+
"Counter": "0,1,2,3",
1141
945
"EventCode": "0x35",
1142
946
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC",
1143
947
"PerPkg": "1",
···
1147
949
},
1148
950
{
1149
951
"BriefDescription": "Data read opt from local IA that hit the cache",
952
+
"Counter": "0,1,2,3",
1150
953
"EventCode": "0x35",
1151
954
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT",
1152
955
"PerPkg": "1",
···
1157
958
},
1158
959
{
1159
960
"BriefDescription": "Data read opt prefetch from local IA that hit the cache",
961
+
"Counter": "0,1,2,3",
1160
962
"EventCode": "0x35",
1161
963
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF",
1162
964
"PerPkg": "1",
···
1167
967
},
1168
968
{
1169
969
"BriefDescription": "ItoM requests from local IA cores that hit the cache",
970
+
"Counter": "0,1,2,3",
1170
971
"EventCode": "0x35",
1171
972
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
1172
973
"PerPkg": "1",
···
1177
976
},
1178
977
{
1179
978
"BriefDescription": "Last level cache prefetch code read from local IA that hit the cache",
979
+
"Counter": "0,1,2,3",
1180
980
"EventCode": "0x35",
1181
981
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
1182
982
"PerPkg": "1",
···
1187
985
},
1188
986
{
1189
987
"BriefDescription": "Last level cache prefetch data read from local IA that hit the cache",
988
+
"Counter": "0,1,2,3",
1190
989
"EventCode": "0x35",
1191
990
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
1192
991
"PerPkg": "1",
···
1197
994
},
1198
995
{
1199
996
"BriefDescription": "Last level cache prefetch read for ownership from local IA that hit the cache",
997
+
"Counter": "0,1,2,3",
1200
998
"EventCode": "0x35",
1201
999
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
1202
1000
"PerPkg": "1",
···
1207
1003
},
1208
1004
{
1209
1005
"BriefDescription": "Read for ownership from local IA that hit the cache",
1006
+
"Counter": "0,1,2,3",
1210
1007
"EventCode": "0x35",
1211
1008
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
1212
1009
"PerPkg": "1",
···
1217
1012
},
1218
1013
{
1219
1014
"BriefDescription": "Read for ownership prefetch from local IA that hit the cache",
1015
+
"Counter": "0,1,2,3",
1220
1016
"EventCode": "0x35",
1221
1017
"EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
1222
1018
"PerPkg": "1",
···
1227
1021
},
1228
1022
{
1229
1023
"BriefDescription": "ItoM events that are initiated from the Core",
1024
+
"Counter": "0,1,2,3",
1230
1025
"EventCode": "0x35",
1231
1026
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
1232
1027
"PerPkg": "1",
···
1237
1030
},
1238
1031
{
1239
1032
"BriefDescription": "ItoMCacheNear requests from local IA cores",
1033
+
"Counter": "0,1,2,3",
1240
1034
"EventCode": "0x35",
1241
1035
"EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
1242
1036
"PerPkg": "1",
···
1247
1039
},
1248
1040
{
1249
1041
"BriefDescription": "Last level cache prefetch code read from local IA.",
1042
+
"Counter": "0,1,2,3",
1250
1043
"EventCode": "0x35",
1251
1044
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
1252
1045
"PerPkg": "1",
···
1257
1048
},
1258
1049
{
1259
1050
"BriefDescription": "Last level cache prefetch data read from local IA.",
1051
+
"Counter": "0,1,2,3",
1260
1052
"EventCode": "0x35",
1261
1053
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
1262
1054
"PerPkg": "1",
···
1267
1057
},
1268
1058
{
1269
1059
"BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache",
1060
+
"Counter": "0,1,2,3",
1270
1061
"EventCode": "0x35",
1271
1062
"EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
1272
1063
"PerPkg": "1",
···
1277
1066
},
1278
1067
{
1279
1068
"BriefDescription": "All locally initiated requests from IA Cores which miss the cache",
1069
+
"Counter": "0,1,2,3",
1280
1070
"EventCode": "0x35",
1281
1071
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
1282
1072
"PerPkg": "1",
···
1287
1075
},
1288
1076
{
1289
1077
"BriefDescription": "Code read from local IA that miss the cache",
1078
+
"Counter": "0,1,2,3",
1290
1079
"EventCode": "0x35",
1291
1080
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
1292
1081
"PerPkg": "1",
···
1297
1084
},
1298
1085
{
1299
1086
"BriefDescription": "CRDs from local IA cores to locally homed memory",
1087
+
"Counter": "0,1,2,3",
1300
1088
"EventCode": "0x35",
1301
1089
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
1302
1090
"PerPkg": "1",
···
1307
1093
},
1308
1094
{
1309
1095
"BriefDescription": "Code read prefetch from local IA that miss the cache",
1096
+
"Counter": "0,1,2,3",
1310
1097
"EventCode": "0x35",
1311
1098
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
1312
1099
"PerPkg": "1",
···
1317
1102
},
1318
1103
{
1319
1104
"BriefDescription": "CRD Prefetches from local IA cores to locally homed memory",
1105
+
"Counter": "0,1,2,3",
1320
1106
"EventCode": "0x35",
1321
1107
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
1322
1108
"PerPkg": "1",
···
1327
1111
},
1328
1112
{
1329
1113
"BriefDescription": "CRD Prefetches from local IA cores to remotely homed memory",
1114
+
"Counter": "0,1,2,3",
1330
1115
"EventCode": "0x35",
1331
1116
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
1332
1117
"PerPkg": "1",
···
1337
1120
},
1338
1121
{
1339
1122
"BriefDescription": "CRDs from local IA cores to remotely homed memory",
1123
+
"Counter": "0,1,2,3",
1340
1124
"EventCode": "0x35",
1341
1125
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
1342
1126
"PerPkg": "1",
···
1347
1129
},
1348
1130
{
1349
1131
"BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
1132
+
"Counter": "0,1,2,3",
1350
1133
"EventCode": "0x35",
1351
1134
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC",
1352
1135
"PerPkg": "1",
···
1356
1137
},
1357
1138
{
1358
1139
"BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
1140
+
"Counter": "0,1,2,3",
1359
1141
"EventCode": "0x35",
1360
1142
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC",
1361
1143
"PerPkg": "1",
···
1366
1146
},
1367
1147
{
1368
1148
"BriefDescription": "Data read opt from local IA that miss the cache",
1149
+
"Counter": "0,1,2,3",
1369
1150
"EventCode": "0x35",
1370
1151
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT",
1371
1152
"PerPkg": "1",
···
1376
1155
},
1377
1156
{
1378
1157
"BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and which target local memory",
1158
+
"Counter": "0,1,2,3",
1379
1159
"EventCode": "0x35",
1380
1160
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL",
1381
1161
"PerPkg": "1",
···
1386
1164
},
1387
1165
{
1388
1166
"BriefDescription": "Data read opt prefetch from local IA that miss the cache",
1167
+
"Counter": "0,1,2,3",
1389
1168
"EventCode": "0x35",
1390
1169
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF",
1391
1170
"PerPkg": "1",
···
1396
1173
},
1397
1174
{
1398
1175
"BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target local memory",
1176
+
"Counter": "0,1,2,3",
1399
1177
"EventCode": "0x35",
1400
1178
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL",
1401
1179
"PerPkg": "1",
···
1406
1182
},
1407
1183
{
1408
1184
"BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target remote memory",
1185
+
"Counter": "0,1,2,3",
1409
1186
"EventCode": "0x35",
1410
1187
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE",
1411
1188
"PerPkg": "1",
···
1416
1191
},
1417
1192
{
1418
1193
"BriefDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd_Opt, and target remote memory",
1194
+
"Counter": "0,1,2,3",
1419
1195
"EventCode": "0x35",
1420
1196
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE",
1421
1197
"PerPkg": "1",
···
1426
1200
},
1427
1201
{
1428
1202
"BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
1203
+
"Counter": "0,1,2,3",
1429
1204
"EventCode": "0x35",
1430
1205
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC",
1431
1206
"PerPkg": "1",
···
1435
1208
},
1436
1209
{
1437
1210
"BriefDescription": "ItoM requests from local IA cores that miss the cache",
1211
+
"Counter": "0,1,2,3",
1438
1212
"EventCode": "0x35",
1439
1213
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
1440
1214
"PerPkg": "1",
···
1445
1217
},
1446
1218
{
1447
1219
"BriefDescription": "Last level cache prefetch code read from local IA that miss the cache",
1220
+
"Counter": "0,1,2,3",
1448
1221
"EventCode": "0x35",
1449
1222
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
1450
1223
"PerPkg": "1",
···
1455
1226
},
1456
1227
{
1457
1228
"BriefDescription": "Last level cache prefetch data read from local IA that miss the cache",
1229
+
"Counter": "0,1,2,3",
1458
1230
"EventCode": "0x35",
1459
1231
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
1460
1232
"PerPkg": "1",
···
1465
1235
},
1466
1236
{
1467
1237
"BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
1238
+
"Counter": "0,1,2,3",
1468
1239
"EventCode": "0x35",
1469
1240
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC",
1470
1241
"PerPkg": "1",
···
1474
1243
},
1475
1244
{
1476
1245
"BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache",
1246
+
"Counter": "0,1,2,3",
1477
1247
"EventCode": "0x35",
1478
1248
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
1479
1249
"PerPkg": "1",
···
1484
1252
},
1485
1253
{
1486
1254
"BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
1255
+
"Counter": "0,1,2,3",
1487
1256
"EventCode": "0x35",
1488
1257
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC",
1489
1258
"PerPkg": "1",
···
1493
1260
},
1494
1261
{
1495
1262
"BriefDescription": "WCILF requests from local IA cores to locally homed DDR addresses that miss the cache",
1263
+
"Counter": "0,1,2,3",
1496
1264
"EventCode": "0x35",
1497
1265
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
1498
1266
"PerPkg": "1",
···
1503
1269
},
1504
1270
{
1505
1271
"BriefDescription": "WCILF requests from local IA cores to locally homed PMM addresses which miss the cache",
1272
+
"Counter": "0,1,2,3",
1506
1273
"EventCode": "0x35",
1507
1274
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
1275
+
"Experimental": "1",
1508
1276
"PerPkg": "1",
1509
1277
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
1510
1278
"UMask": "0xc8668a01",
···
1514
1278
},
1515
1279
{
1516
1280
"BriefDescription": "WCIL requests from local IA cores to locally homed DDR addresses that miss the cache",
1281
+
"Counter": "0,1,2,3",
1517
1282
"EventCode": "0x35",
1518
1283
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
1519
1284
"PerPkg": "1",
···
1524
1287
},
1525
1288
{
1526
1289
"BriefDescription": "WCIL requests from local IA cores to locally homed PMM addresses which miss the cache",
1290
+
"Counter": "0,1,2,3",
1527
1291
"EventCode": "0x35",
1528
1292
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
1293
+
"Experimental": "1",
1529
1294
"PerPkg": "1",
1530
1295
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
1531
1296
"UMask": "0xc86e8a01",
···
1535
1296
},
1536
1297
{
1537
1298
"BriefDescription": "WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache",
1299
+
"Counter": "0,1,2,3",
1538
1300
"EventCode": "0x35",
1539
1301
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
1540
1302
"PerPkg": "1",
···
1545
1305
},
1546
1306
{
1547
1307
"BriefDescription": "WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache",
1308
+
"Counter": "0,1,2,3",
1548
1309
"EventCode": "0x35",
1549
1310
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
1311
+
"Experimental": "1",
1550
1312
"PerPkg": "1",
1551
1313
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
1552
1314
"UMask": "0xc8670a01",
···
1556
1314
},
1557
1315
{
1558
1316
"BriefDescription": "WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache",
1317
+
"Counter": "0,1,2,3",
1559
1318
"EventCode": "0x35",
1560
1319
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
1561
1320
"PerPkg": "1",
···
1566
1323
},
1567
1324
{
1568
1325
"BriefDescription": "WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache",
1326
+
"Counter": "0,1,2,3",
1569
1327
"EventCode": "0x35",
1570
1328
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
1329
+
"Experimental": "1",
1571
1330
"PerPkg": "1",
1572
1331
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
1573
1332
"UMask": "0xc86f0a01",
···
1577
1332
},
1578
1333
{
1579
1334
"BriefDescription": "Read for ownership from local IA that miss the cache",
1335
+
"Counter": "0,1,2,3",
1580
1336
"EventCode": "0x35",
1581
1337
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
1582
1338
"PerPkg": "1",
···
1587
1341
},
1588
1342
{
1589
1343
"BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
1344
+
"Counter": "0,1,2,3",
1590
1345
"EventCode": "0x35",
1591
1346
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC",
1592
1347
"PerPkg": "1",
···
1596
1349
},
1597
1350
{
1598
1351
"BriefDescription": "Read for ownership from local IA that miss the cache",
1352
+
"Counter": "0,1,2,3",
1599
1353
"EventCode": "0x35",
1600
1354
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
1601
1355
"PerPkg": "1",
···
1606
1358
},
1607
1359
{
1608
1360
"BriefDescription": "Read for ownership prefetch from local IA that miss the cache",
1361
+
"Counter": "0,1,2,3",
1609
1362
"EventCode": "0x35",
1610
1363
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
1611
1364
"PerPkg": "1",
···
1616
1367
},
1617
1368
{
1618
1369
"BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
1370
+
"Counter": "0,1,2,3",
1619
1371
"EventCode": "0x35",
1620
1372
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC",
1621
1373
"PerPkg": "1",
···
1625
1375
},
1626
1376
{
1627
1377
"BriefDescription": "Read for ownership prefetch from local IA that miss the cache",
1378
+
"Counter": "0,1,2,3",
1628
1379
"EventCode": "0x35",
1629
1380
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
1630
1381
"PerPkg": "1",
···
1635
1384
},
1636
1385
{
1637
1386
"BriefDescription": "Read for ownership prefetch from local IA that miss the cache",
1387
+
"Counter": "0,1,2,3",
1638
1388
"EventCode": "0x35",
1639
1389
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
1640
1390
"PerPkg": "1",
···
1645
1393
},
1646
1394
{
1647
1395
"BriefDescription": "Read for ownership from local IA that miss the cache",
1396
+
"Counter": "0,1,2,3",
1648
1397
"EventCode": "0x35",
1649
1398
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
1650
1399
"PerPkg": "1",
···
1655
1402
},
1656
1403
{
1657
1404
"BriefDescription": "UCRDF requests from local IA cores that miss the cache",
1405
+
"Counter": "0,1,2,3",
1658
1406
"EventCode": "0x35",
1659
1407
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
1660
1408
"PerPkg": "1",
···
1665
1411
},
1666
1412
{
1667
1413
"BriefDescription": "WCIL requests from a local IA core that miss the cache",
1414
+
"Counter": "0,1,2,3",
1668
1415
"EventCode": "0x35",
1669
1416
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
1670
1417
"PerPkg": "1",
···
1675
1420
},
1676
1421
{
1677
1422
"BriefDescription": "WCILF requests from local IA core that miss the cache",
1423
+
"Counter": "0,1,2,3",
1678
1424
"EventCode": "0x35",
1679
1425
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
1680
1426
"PerPkg": "1",
···
1685
1429
},
1686
1430
{
1687
1431
"BriefDescription": "WCILF requests from local IA cores to DDR homed addresses which miss the cache",
1432
+
"Counter": "0,1,2,3",
1688
1433
"EventCode": "0x35",
1689
1434
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
1690
1435
"PerPkg": "1",
···
1695
1438
},
1696
1439
{
1697
1440
"BriefDescription": "WCILF requests from local IA cores to PMM homed addresses which miss the cache",
1441
+
"Counter": "0,1,2,3",
1698
1442
"EventCode": "0x35",
1699
1443
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
1444
+
"Experimental": "1",
1700
1445
"PerPkg": "1",
1701
1446
"PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
1702
1447
"UMask": "0xc8678a01",
···
1706
1447
},
1707
1448
{
1708
1449
"BriefDescription": "WCIL requests from local IA cores to DDR homed addresses which miss the cache",
1450
+
"Counter": "0,1,2,3",
1709
1451
"EventCode": "0x35",
1710
1452
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
1711
1453
"PerPkg": "1",
···
1716
1456
},
1717
1457
{
1718
1458
"BriefDescription": "WCIL requests from a local IA core to PMM homed addresses that miss the cache",
1459
+
"Counter": "0,1,2,3",
1719
1460
"EventCode": "0x35",
1720
1461
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
1462
+
"Experimental": "1",
1721
1463
"PerPkg": "1",
1722
1464
"PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
1723
1465
"UMask": "0xc86f8a01",
···
1727
1465
},
1728
1466
{
1729
1467
"BriefDescription": "WIL requests from local IA cores that miss the cache",
1468
+
"Counter": "0,1,2,3",
1730
1469
"EventCode": "0x35",
1731
1470
"EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
1732
1471
"PerPkg": "1",
···
1737
1474
},
1738
1475
{
1739
1476
"BriefDescription": "Read for ownership from local IA that miss the cache",
1477
+
"Counter": "0,1,2,3",
1740
1478
"EventCode": "0x35",
1741
1479
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
1742
1480
"PerPkg": "1",
···
1747
1483
},
1748
1484
{
1749
1485
"BriefDescription": "Read for ownership prefetch from local IA that miss the cache",
1486
+
"Counter": "0,1,2,3",
1750
1487
"EventCode": "0x35",
1751
1488
"EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
1752
1489
"PerPkg": "1",
···
1757
1492
},
1758
1493
{
1759
1494
"BriefDescription": "SpecItoM events that are initiated from the Core",
1495
+
"Counter": "0,1,2,3",
1760
1496
"EventCode": "0x35",
1761
1497
"EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
1762
1498
"PerPkg": "1",
···
1767
1501
},
1768
1502
{
1769
1503
"BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified Write Backs)",
1504
+
"Counter": "0,1,2,3",
1770
1505
"EventCode": "0x35",
1771
1506
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
1772
1507
"PerPkg": "1",
···
1777
1510
},
1778
1511
{
1779
1512
"BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs)",
1513
+
"Counter": "0,1,2,3",
1780
1514
"EventCode": "0x35",
1781
1515
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
1782
1516
"PerPkg": "1",
···
1787
1519
},
1788
1520
{
1789
1521
"BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write Backs)",
1522
+
"Counter": "0,1,2,3",
1790
1523
"EventCode": "0x35",
1791
1524
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
1792
1525
"PerPkg": "1",
···
1797
1528
},
1798
1529
{
1799
1530
"BriefDescription": "WbMtoI requests from local IA cores",
1531
+
"Counter": "0,1,2,3",
1800
1532
"EventCode": "0x35",
1801
1533
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
1802
1534
"PerPkg": "1",
···
1807
1537
},
1808
1538
{
1809
1539
"BriefDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs)",
1540
+
"Counter": "0,1,2,3",
1810
1541
"EventCode": "0x35",
1811
1542
"EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
1812
1543
"PerPkg": "1",
···
1817
1546
},
1818
1547
{
1819
1548
"BriefDescription": "WCIL requests from a local IA core",
1549
+
"Counter": "0,1,2,3",
1820
1550
"EventCode": "0x35",
1821
1551
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
1822
1552
"PerPkg": "1",
···
1827
1555
},
1828
1556
{
1829
1557
"BriefDescription": "WCILF requests from local IA core",
1558
+
"Counter": "0,1,2,3",
1830
1559
"EventCode": "0x35",
1831
1560
"EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
1832
1561
"PerPkg": "1",
···
1837
1564
},
1838
1565
{
1839
1566
"BriefDescription": "All TOR inserts from local IO devices",
1567
+
"Counter": "0,1,2,3",
1840
1568
"EventCode": "0x35",
1841
1569
"EventName": "UNC_CHA_TOR_INSERTS.IO",
1570
+
"Experimental": "1",
1842
1571
"PerPkg": "1",
1843
1572
"PublicDescription": "TOR Inserts : All requests from IO Devices",
1844
1573
"UMask": "0xc001ff04",
···
1848
1573
},
1849
1574
{
1850
1575
"BriefDescription": "CLFlush requests from IO devices",
1576
+
"Counter": "0,1,2,3",
1851
1577
"EventCode": "0x35",
1852
1578
"EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
1853
1579
"PerPkg": "1",
···
1858
1582
},
1859
1583
{
1860
1584
"BriefDescription": "All TOR inserts from local IO devices which hit the cache",
1585
+
"Counter": "0,1,2,3",
1861
1586
"EventCode": "0x35",
1862
1587
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
1588
+
"Experimental": "1",
1863
1589
"PerPkg": "1",
1864
1590
"PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
1865
1591
"UMask": "0xc001fd04",
···
1869
1591
},
1870
1592
{
1871
1593
"BriefDescription": "ItoMs from local IO devices which hit the cache",
1594
+
"Counter": "0,1,2,3",
1872
1595
"EventCode": "0x35",
1873
1596
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
1874
1597
"PerPkg": "1",
···
1879
1600
},
1880
1601
{
1881
1602
"BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
1603
+
"Counter": "0,1,2,3",
1882
1604
"EventCode": "0x35",
1883
1605
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
1884
1606
"PerPkg": "1",
···
1889
1609
},
1890
1610
{
1891
1611
"BriefDescription": "PCIRDCURs issued by IO devices which hit the LLC",
1612
+
"Counter": "0,1,2,3",
1892
1613
"EventCode": "0x35",
1893
1614
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
1894
1615
"PerPkg": "1",
···
1899
1618
},
1900
1619
{
1901
1620
"BriefDescription": "RFOs from local IO devices which hit the cache",
1621
+
"Counter": "0,1,2,3",
1902
1622
"EventCode": "0x35",
1903
1623
"EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
1904
1624
"PerPkg": "1",
···
1909
1627
},
1910
1628
{
1911
1629
"BriefDescription": "All TOR ItoM inserts from local IO devices",
1630
+
"Counter": "0,1,2,3",
1912
1631
"EventCode": "0x35",
1913
1632
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
1914
1633
"PerPkg": "1",
···
1919
1636
},
1920
1637
{
1921
1638
"BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices",
1639
+
"Counter": "0,1,2,3",
1922
1640
"EventCode": "0x35",
1923
1641
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
1924
1642
"PerPkg": "1",
···
1928
1644
"Unit": "CHA"
1929
1645
},
1930
1646
{
1647
+
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket",
1648
+
"Counter": "0,1,2,3",
1649
+
"EventCode": "0x35",
1650
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
1651
+
"PerPkg": "1",
1652
+
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket",
1653
+
"UMask": "0xcd42ff04",
1654
+
"Unit": "CHA"
1655
+
},
1656
+
{
1657
+
"BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket",
1658
+
"Counter": "0,1,2,3",
1659
+
"EventCode": "0x35",
1660
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
1661
+
"PerPkg": "1",
1662
+
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket",
1663
+
"UMask": "0xcd437f04",
1664
+
"Unit": "CHA"
1665
+
},
1666
+
{
1667
+
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket",
1668
+
"Counter": "0,1,2,3",
1669
+
"EventCode": "0x35",
1670
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
1671
+
"PerPkg": "1",
1672
+
"PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket",
1673
+
"UMask": "0xcc42ff04",
1674
+
"Unit": "CHA"
1675
+
},
1676
+
{
1677
+
"BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket",
1678
+
"Counter": "0,1,2,3",
1679
+
"EventCode": "0x35",
1680
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
1681
+
"PerPkg": "1",
1682
+
"PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket",
1683
+
"UMask": "0xcc437f04",
1684
+
"Unit": "CHA"
1685
+
},
1686
+
{
1931
1687
"BriefDescription": "All TOR inserts from local IO devices which miss the cache",
1688
+
"Counter": "0,1,2,3",
1932
1689
"EventCode": "0x35",
1933
1690
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
1691
+
"Experimental": "1",
1934
1692
"PerPkg": "1",
1935
1693
"PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
1936
1694
"UMask": "0xc001fe04",
···
1980
1654
},
1981
1655
{
1982
1656
"BriefDescription": "All TOR ItoM inserts from local IO devices which miss the cache",
1657
+
"Counter": "0,1,2,3",
1983
1658
"EventCode": "0x35",
1984
1659
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
1985
1660
"PerPkg": "1",
···
1990
1663
},
1991
1664
{
1992
1665
"BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
1666
+
"Counter": "0,1,2,3",
1993
1667
"EventCode": "0x35",
1994
1668
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
1995
1669
"PerPkg": "1",
···
1999
1671
"Unit": "CHA"
2000
1672
},
2001
1673
{
2002
-
"BriefDescription": "ItoMCacheNear transactions from an IO device on the local socket that miss the cache",
2003
-
"EventCode": "0x35",
2004
-
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR_LOCAL",
2005
-
"PerPkg": "1",
2006
-
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
2007
-
"UMask": "0xcd42fe04",
2008
-
"Unit": "CHA"
2009
-
},
2010
-
{
2011
-
"BriefDescription": "ItoMCacheNear transactions from an IO device on a remote socket that miss the cache",
2012
-
"EventCode": "0x35",
2013
-
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR_REMOTE",
2014
-
"PerPkg": "1",
2015
-
"PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
2016
-
"UMask": "0xcd437e04",
2017
-
"Unit": "CHA"
2018
-
},
2019
-
{
2020
-
"BriefDescription": "ItoM transactions from an IO device on the local socket that miss the cache",
2021
-
"EventCode": "0x35",
2022
-
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM_LOCAL",
2023
-
"PerPkg": "1",
2024
-
"PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
2025
-
"UMask": "0xcc42fe04",
2026
-
"Unit": "CHA"
2027
-
},
2028
-
{
2029
-
"BriefDescription": "ItoM transactions from an IO device on a remote socket that miss the cache",
2030
-
"EventCode": "0x35",
2031
-
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM_REMOTE",
2032
-
"PerPkg": "1",
2033
-
"PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
2034
-
"UMask": "0xcc437e04",
2035
-
"Unit": "CHA"
2036
-
},
2037
-
{
2038
1674
"BriefDescription": "PCIRDCURs issued by IO devices which miss the LLC",
1675
+
"Counter": "0,1,2,3",
2039
1676
"EventCode": "0x35",
2040
1677
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
2041
1678
"PerPkg": "1",
···
2010
1717
},
2011
1718
{
2012
1719
"BriefDescription": "All TOR RFO inserts from local IO devices which miss the cache",
1720
+
"Counter": "0,1,2,3",
2013
1721
"EventCode": "0x35",
2014
1722
"EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
2015
1723
"PerPkg": "1",
···
2020
1726
},
2021
1727
{
2022
1728
"BriefDescription": "PCIRDCURs issued by IO devices",
1729
+
"Counter": "0,1,2,3",
2023
1730
"EventCode": "0x35",
2024
1731
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
2025
1732
"PerPkg": "1",
···
2029
1734
"Unit": "CHA"
2030
1735
},
2031
1736
{
1737
+
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
1738
+
"Counter": "0,1,2,3",
1739
+
"EventCode": "0x35",
1740
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
1741
+
"PerPkg": "1",
1742
+
"PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket",
1743
+
"UMask": "0xc8f2ff04",
1744
+
"Unit": "CHA"
1745
+
},
1746
+
{
1747
+
"BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
1748
+
"Counter": "0,1,2,3",
1749
+
"EventCode": "0x35",
1750
+
"EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
1751
+
"PerPkg": "1",
1752
+
"PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket",
1753
+
"UMask": "0xc8f37f04",
1754
+
"Unit": "CHA"
1755
+
},
1756
+
{
2032
1757
"BriefDescription": "RFOs from local IO devices",
1758
+
"Counter": "0,1,2,3",
2033
1759
"EventCode": "0x35",
2034
1760
"EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
2035
1761
"PerPkg": "1",
···
2060
1744
},
2061
1745
{
2062
1746
"BriefDescription": "WBMtoI requests from IO devices",
1747
+
"Counter": "0,1,2,3",
2063
1748
"EventCode": "0x35",
2064
1749
"EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
2065
1750
"PerPkg": "1",
···
2070
1753
},
2071
1754
{
2072
1755
"BriefDescription": "TOR Inserts for SF or LLC Evictions",
1756
+
"Counter": "0,1,2,3",
2073
1757
"EventCode": "0x35",
2074
1758
"EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS",
2075
1759
"PerPkg": "1",
···
2080
1762
},
2081
1763
{
2082
1764
"BriefDescription": "All locally initiated requests",
1765
+
"Counter": "0,1,2,3",
2083
1766
"EventCode": "0x35",
2084
1767
"EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
1768
+
"Experimental": "1",
2085
1769
"PerPkg": "1",
2086
1770
"PublicDescription": "TOR Inserts : All from Local iA and IO",
2087
1771
"UMask": "0xc000ff05",
···
2091
1771
},
2092
1772
{
2093
1773
"BriefDescription": "All from Local iA",
1774
+
"Counter": "0,1,2,3",
2094
1775
"EventCode": "0x35",
2095
1776
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
1777
+
"Experimental": "1",
2096
1778
"PerPkg": "1",
2097
1779
"PublicDescription": "TOR Inserts : All from Local iA",
2098
1780
"UMask": "0xc000ff01",
···
2102
1780
},
2103
1781
{
2104
1782
"BriefDescription": "All from Local IO",
1783
+
"Counter": "0,1,2,3",
2105
1784
"EventCode": "0x35",
2106
1785
"EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
1786
+
"Experimental": "1",
2107
1787
"PerPkg": "1",
2108
1788
"PublicDescription": "TOR Inserts : All from Local IO",
2109
1789
"UMask": "0xc000ff04",
···
2113
1789
},
2114
1790
{
2115
1791
"BriefDescription": "All remote requests (e.g. snoops, writebacks) that came from remote sockets",
1792
+
"Counter": "0,1,2,3",
2116
1793
"EventCode": "0x35",
2117
1794
"EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
1795
+
"Experimental": "1",
2118
1796
"PerPkg": "1",
2119
1797
"PublicDescription": "TOR Inserts : All Remote Requests",
2120
1798
"UMask": "0xc001ffc8",
···
2124
1798
},
2125
1799
{
2126
1800
"BriefDescription": "All snoops to this LLC that came from remote sockets",
1801
+
"Counter": "0,1,2,3",
2127
1802
"EventCode": "0x35",
2128
1803
"EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
1804
+
"Experimental": "1",
2129
1805
"PerPkg": "1",
2130
1806
"PublicDescription": "TOR Inserts : All Snoops from Remote",
2131
1807
"UMask": "0xc001ff08",
···
2135
1807
},
2136
1808
{
2137
1809
"BriefDescription": "Occupancy for all TOR entries",
1810
+
"Counter": "0",
2138
1811
"EventCode": "0x36",
2139
1812
"EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
1813
+
"Experimental": "1",
2140
1814
"PerPkg": "1",
2141
1815
"PublicDescription": "TOR Occupancy : All",
2142
1816
"UMask": "0xc001ffff",
···
2146
1816
},
2147
1817
{
2148
1818
"BriefDescription": "TOR Occupancy for CLFlush transactions from a CXL device which hit in the L3.",
1819
+
"Counter": "0",
2149
1820
"EventCode": "0x36",
2150
1821
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_CLFLUSH",
1822
+
"Experimental": "1",
2151
1823
"PerPkg": "1",
2152
1824
"UMask": "0x78c8c7fd20",
2153
1825
"Unit": "CHA"
2154
1826
},
2155
1827
{
2156
1828
"BriefDescription": "TOR Occupancy for FsRdCur transactions from a CXL device which hit in the L3.",
1829
+
"Counter": "0",
2157
1830
"EventCode": "0x36",
2158
1831
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCUR",
1832
+
"Experimental": "1",
2159
1833
"PerPkg": "1",
2160
1834
"UMask": "0x78c8effd20",
2161
1835
"Unit": "CHA"
2162
1836
},
2163
1837
{
2164
1838
"BriefDescription": "TOR Occupancy for FsRdCurPtl transactions from a CXL device which hit in the L3.",
1839
+
"Counter": "0",
2165
1840
"EventCode": "0x36",
2166
1841
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCURPTL",
1842
+
"Experimental": "1",
2167
1843
"PerPkg": "1",
2168
1844
"UMask": "0x78c9effd20",
2169
1845
"Unit": "CHA"
2170
1846
},
2171
1847
{
2172
1848
"BriefDescription": "TOR Occupancy for ItoM transactions from a CXL device which hit in the L3.",
1849
+
"Counter": "0",
2173
1850
"EventCode": "0x36",
2174
1851
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOM",
1852
+
"Experimental": "1",
2175
1853
"PerPkg": "1",
2176
1854
"UMask": "0x78cc47fd20",
2177
1855
"Unit": "CHA"
2178
1856
},
2179
1857
{
2180
1858
"BriefDescription": "TOR Occupancy for ItoMWr transactions from a CXL device which hit in the L3.",
1859
+
"Counter": "0",
2181
1860
"EventCode": "0x36",
2182
1861
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOMWR",
1862
+
"Experimental": "1",
2183
1863
"PerPkg": "1",
2184
1864
"UMask": "0x78cc4ffd20",
2185
1865
"Unit": "CHA"
2186
1866
},
2187
1867
{
2188
1868
"BriefDescription": "TOR Occupancy for MemPushWr transactions from a CXL device which hit in the L3.",
1869
+
"Counter": "0",
2189
1870
"EventCode": "0x36",
2190
1871
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_MEMPUSHWR",
1872
+
"Experimental": "1",
2191
1873
"PerPkg": "1",
2192
1874
"UMask": "0x78cc6ffd20",
2193
1875
"Unit": "CHA"
2194
1876
},
2195
1877
{
2196
1878
"BriefDescription": "TOR Occupancy for WCiL transactions from a CXL device which hit in the L3.",
1879
+
"Counter": "0",
2197
1880
"EventCode": "0x36",
2198
1881
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCIL",
1882
+
"Experimental": "1",
2199
1883
"PerPkg": "1",
2200
1884
"UMask": "0x78c86ffd20",
2201
1885
"Unit": "CHA"
2202
1886
},
2203
1887
{
2204
1888
"BriefDescription": "TOR Occupancy for WcilF transactions from a CXL device which hit in the L3.",
1889
+
"Counter": "0",
2205
1890
"EventCode": "0x36",
2206
1891
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCILF",
1892
+
"Experimental": "1",
2207
1893
"PerPkg": "1",
2208
1894
"UMask": "0x78c867fd20",
2209
1895
"Unit": "CHA"
2210
1896
},
2211
1897
{
2212
1898
"BriefDescription": "TOR Occupancy for WiL transactions from a CXL device which hit in the L3.",
1899
+
"Counter": "0",
2213
1900
"EventCode": "0x36",
2214
1901
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WIL",
1902
+
"Experimental": "1",
2215
1903
"PerPkg": "1",
2216
1904
"UMask": "0x78c87ffd20",
2217
1905
"Unit": "CHA"
2218
1906
},
2219
1907
{
2220
1908
"BriefDescription": "TOR Occupancy for CLFlush transactions from a CXL device which miss the L3.",
1909
+
"Counter": "0",
2221
1910
"EventCode": "0x36",
2222
1911
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_CLFLUSH",
1912
+
"Experimental": "1",
2223
1913
"PerPkg": "1",
2224
1914
"UMask": "0x78c8c7fe20",
2225
1915
"Unit": "CHA"
2226
1916
},
2227
1917
{
2228
1918
"BriefDescription": "TOR Occupancy for FsRdCur transactions from a CXL device which miss the L3.",
1919
+
"Counter": "0",
2229
1920
"EventCode": "0x36",
2230
1921
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCUR",
1922
+
"Experimental": "1",
2231
1923
"PerPkg": "1",
2232
1924
"UMask": "0x78c8effe20",
2233
1925
"Unit": "CHA"
2234
1926
},
2235
1927
{
2236
1928
"BriefDescription": "TOR Occupancy for FsRdCurPtl transactions from a CXL device which miss the L3.",
1929
+
"Counter": "0",
2237
1930
"EventCode": "0x36",
2238
1931
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCURPTL",
1932
+
"Experimental": "1",
2239
1933
"PerPkg": "1",
2240
1934
"UMask": "0x78c9effe20",
2241
1935
"Unit": "CHA"
2242
1936
},
2243
1937
{
2244
1938
"BriefDescription": "TOR Occupancy for ItoM transactions from a CXL device which miss the L3.",
1939
+
"Counter": "0",
2245
1940
"EventCode": "0x36",
2246
1941
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOM",
1942
+
"Experimental": "1",
2247
1943
"PerPkg": "1",
2248
1944
"UMask": "0x78cc47fe20",
2249
1945
"Unit": "CHA"
2250
1946
},
2251
1947
{
2252
1948
"BriefDescription": "TOR Occupancy for ItoMWr transactions from a CXL device which miss the L3.",
1949
+
"Counter": "0",
2253
1950
"EventCode": "0x36",
2254
1951
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOMWR",
1952
+
"Experimental": "1",
2255
1953
"PerPkg": "1",
2256
1954
"UMask": "0x78cc4ffe20",
2257
1955
"Unit": "CHA"
2258
1956
},
2259
1957
{
2260
1958
"BriefDescription": "TOR Occupancy for MemPushWr transactions from a CXL device which miss the L3.",
1959
+
"Counter": "0",
2261
1960
"EventCode": "0x36",
2262
1961
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_MEMPUSHWR",
1962
+
"Experimental": "1",
2263
1963
"PerPkg": "1",
2264
1964
"UMask": "0x78cc6ffe20",
2265
1965
"Unit": "CHA"
2266
1966
},
2267
1967
{
2268
1968
"BriefDescription": "TOR Occupancy for WCiL transactions from a CXL device which miss the L3.",
1969
+
"Counter": "0",
2269
1970
"EventCode": "0x36",
2270
1971
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCIL",
1972
+
"Experimental": "1",
2271
1973
"PerPkg": "1",
2272
1974
"UMask": "0x78c86ffe20",
2273
1975
"Unit": "CHA"
2274
1976
},
2275
1977
{
2276
1978
"BriefDescription": "TOR Occupancy for WcilF transactions from a CXL device which miss the L3.",
1979
+
"Counter": "0",
2277
1980
"EventCode": "0x36",
2278
1981
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCILF",
1982
+
"Experimental": "1",
2279
1983
"PerPkg": "1",
2280
1984
"UMask": "0x78c867fe20",
2281
1985
"Unit": "CHA"
2282
1986
},
2283
1987
{
2284
1988
"BriefDescription": "TOR Occupancy for WiL transactions from a CXL device which miss the L3.",
1989
+
"Counter": "0",
2285
1990
"EventCode": "0x36",
2286
1991
"EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WIL",
1992
+
"Experimental": "1",
2287
1993
"PerPkg": "1",
2288
1994
"UMask": "0x78c87ffe20",
2289
1995
"Unit": "CHA"
2290
1996
},
2291
1997
{
2292
1998
"BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores",
1999
+
"Counter": "0",
2293
2000
"EventCode": "0x36",
2294
2001
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
2002
+
"Experimental": "1",
2295
2003
"PerPkg": "1",
2296
2004
"PublicDescription": "TOR Occupancy : All requests from iA Cores",
2297
2005
"UMask": "0xc001ff01",
···
2337
1969
},
2338
1970
{
2339
1971
"BriefDescription": "TOR Occupancy for CLFlush events that are initiated from the Core",
1972
+
"Counter": "0",
2340
1973
"EventCode": "0x36",
2341
1974
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
2342
1975
"PerPkg": "1",
···
2347
1978
},
2348
1979
{
2349
1980
"BriefDescription": "TOR Occupancy for CLFlushOpt events that are initiated from the Core",
1981
+
"Counter": "0",
2350
1982
"EventCode": "0x36",
2351
1983
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT",
2352
1984
"PerPkg": "1",
···
2357
1987
},
2358
1988
{
2359
1989
"BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache",
1990
+
"Counter": "0",
2360
1991
"EventCode": "0x36",
2361
1992
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
2362
1993
"PerPkg": "1",
···
2367
1996
},
2368
1997
{
2369
1998
"BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache",
1999
+
"Counter": "0",
2370
2000
"EventCode": "0x36",
2371
2001
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
2372
2002
"PerPkg": "1",
···
2377
2005
},
2378
2006
{
2379
2007
"BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache",
2008
+
"Counter": "0",
2380
2009
"EventCode": "0x36",
2381
2010
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT",
2011
+
"Experimental": "1",
2382
2012
"PerPkg": "1",
2383
2013
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores",
2384
2014
"UMask": "0xc827ff01",
···
2388
2014
},
2389
2015
{
2390
2016
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache",
2017
+
"Counter": "0",
2391
2018
"EventCode": "0x36",
2392
2019
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF",
2020
+
"Experimental": "1",
2393
2021
"PerPkg": "1",
2394
2022
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores",
2395
2023
"UMask": "0xc8a7ff01",
···
2399
2023
},
2400
2024
{
2401
2025
"BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores which hit the cache",
2026
+
"Counter": "0",
2402
2027
"EventCode": "0x36",
2403
2028
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
2029
+
"Experimental": "1",
2404
2030
"PerPkg": "1",
2405
2031
"PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
2406
2032
"UMask": "0xc001fd01",
···
2410
2032
},
2411
2033
{
2412
2034
"BriefDescription": "TOR Occupancy for Code read from local IA that hit the cache",
2035
+
"Counter": "0",
2413
2036
"EventCode": "0x36",
2414
2037
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
2415
2038
"PerPkg": "1",
···
2420
2041
},
2421
2042
{
2422
2043
"BriefDescription": "TOR Occupancy for Code read prefetch from local IA that hit the cache",
2044
+
"Counter": "0",
2423
2045
"EventCode": "0x36",
2424
2046
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
2425
2047
"PerPkg": "1",
···
2430
2050
},
2431
2051
{
2432
2052
"BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
2053
+
"Counter": "0",
2433
2054
"EventCode": "0x36",
2434
2055
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC",
2435
2056
"PerPkg": "1",
···
2439
2058
},
2440
2059
{
2441
2060
"BriefDescription": "TOR Occupancy for Data read opt from local IA that hit the cache",
2061
+
"Counter": "0",
2442
2062
"EventCode": "0x36",
2443
2063
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT",
2064
+
"Experimental": "1",
2444
2065
"PerPkg": "1",
2445
2066
"PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC",
2446
2067
"UMask": "0xc827fd01",
···
2450
2067
},
2451
2068
{
2452
2069
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that hit the cache",
2070
+
"Counter": "0",
2453
2071
"EventCode": "0x36",
2454
2072
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF",
2073
+
"Experimental": "1",
2455
2074
"PerPkg": "1",
2456
2075
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC",
2457
2076
"UMask": "0xc8a7fd01",
···
2461
2076
},
2462
2077
{
2463
2078
"BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that hit the cache",
2079
+
"Counter": "0",
2464
2080
"EventCode": "0x36",
2465
2081
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
2466
2082
"PerPkg": "1",
···
2471
2085
},
2472
2086
{
2473
2087
"BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache",
2088
+
"Counter": "0",
2474
2089
"EventCode": "0x36",
2475
2090
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
2476
2091
"PerPkg": "1",
···
2481
2094
},
2482
2095
{
2483
2096
"BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache",
2097
+
"Counter": "0",
2484
2098
"EventCode": "0x36",
2485
2099
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
2486
2100
"PerPkg": "1",
···
2491
2103
},
2492
2104
{
2493
2105
"BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache",
2106
+
"Counter": "0",
2494
2107
"EventCode": "0x36",
2495
2108
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
2496
2109
"PerPkg": "1",
···
2501
2112
},
2502
2113
{
2503
2114
"BriefDescription": "TOR Occupancy for Read for ownership from local IA that hit the cache",
2115
+
"Counter": "0",
2504
2116
"EventCode": "0x36",
2505
2117
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
2506
2118
"PerPkg": "1",
···
2511
2121
},
2512
2122
{
2513
2123
"BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that hit the cache",
2124
+
"Counter": "0",
2514
2125
"EventCode": "0x36",
2515
2126
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
2516
2127
"PerPkg": "1",
···
2521
2130
},
2522
2131
{
2523
2132
"BriefDescription": "TOR Occupancy for ItoM events that are initiated from the Core",
2133
+
"Counter": "0",
2524
2134
"EventCode": "0x36",
2525
2135
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
2526
2136
"PerPkg": "1",
···
2531
2139
},
2532
2140
{
2533
2141
"BriefDescription": "TOR Occupancy for ItoMCacheNear requests from local IA cores",
2142
+
"Counter": "0",
2534
2143
"EventCode": "0x36",
2535
2144
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
2536
2145
"PerPkg": "1",
···
2541
2148
},
2542
2149
{
2543
2150
"BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA.",
2151
+
"Counter": "0",
2544
2152
"EventCode": "0x36",
2545
2153
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
2546
2154
"PerPkg": "1",
···
2551
2157
},
2552
2158
{
2553
2159
"BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA.",
2160
+
"Counter": "0",
2554
2161
"EventCode": "0x36",
2555
2162
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
2556
2163
"PerPkg": "1",
···
2561
2166
},
2562
2167
{
2563
2168
"BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache",
2169
+
"Counter": "0",
2564
2170
"EventCode": "0x36",
2565
2171
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
2566
2172
"PerPkg": "1",
···
2571
2175
},
2572
2176
{
2573
2177
"BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores which miss the cache",
2178
+
"Counter": "0",
2574
2179
"EventCode": "0x36",
2575
2180
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
2181
+
"Experimental": "1",
2576
2182
"PerPkg": "1",
2577
2183
"PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
2578
2184
"UMask": "0xc001fe01",
···
2582
2184
},
2583
2185
{
2584
2186
"BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache",
2187
+
"Counter": "0",
2585
2188
"EventCode": "0x36",
2586
2189
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
2587
2190
"PerPkg": "1",
···
2592
2193
},
2593
2194
{
2594
2195
"BriefDescription": "TOR Occupancy for CRDs from local IA cores to locally homed memory",
2196
+
"Counter": "0",
2595
2197
"EventCode": "0x36",
2596
2198
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
2597
2199
"PerPkg": "1",
···
2602
2202
},
2603
2203
{
2604
2204
"BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache",
2205
+
"Counter": "0",
2605
2206
"EventCode": "0x36",
2606
2207
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
2607
2208
"PerPkg": "1",
···
2612
2211
},
2613
2212
{
2614
2213
"BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory",
2214
+
"Counter": "0",
2615
2215
"EventCode": "0x36",
2616
2216
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
2617
2217
"PerPkg": "1",
···
2622
2220
},
2623
2221
{
2624
2222
"BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory",
2223
+
"Counter": "0",
2625
2224
"EventCode": "0x36",
2626
2225
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
2627
2226
"PerPkg": "1",
···
2632
2229
},
2633
2230
{
2634
2231
"BriefDescription": "TOR Occupancy for CRDs from local IA cores to remotely homed memory",
2232
+
"Counter": "0",
2635
2233
"EventCode": "0x36",
2636
2234
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
2637
2235
"PerPkg": "1",
···
2642
2238
},
2643
2239
{
2644
2240
"BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
2241
+
"Counter": "0",
2645
2242
"EventCode": "0x36",
2646
2243
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC",
2647
2244
"PerPkg": "1",
···
2651
2246
},
2652
2247
{
2653
2248
"BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
2249
+
"Counter": "0",
2654
2250
"EventCode": "0x36",
2655
2251
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC",
2656
2252
"PerPkg": "1",
···
2660
2254
},
2661
2255
{
2662
2256
"BriefDescription": "TOR Occupancy for Data read opt from local IA that miss the cache",
2257
+
"Counter": "0",
2663
2258
"EventCode": "0x36",
2664
2259
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT",
2260
+
"Experimental": "1",
2665
2261
"PerPkg": "1",
2666
2262
"PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC",
2667
2263
"UMask": "0xc827fe01",
···
2671
2263
},
2672
2264
{
2673
2265
"BriefDescription": "TOR Occupancy for Data read opt prefetch from local IA that miss the cache",
2266
+
"Counter": "0",
2674
2267
"EventCode": "0x36",
2675
2268
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF",
2269
+
"Experimental": "1",
2676
2270
"PerPkg": "1",
2677
2271
"PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC",
2678
2272
"UMask": "0xc8a7fe01",
···
2682
2272
},
2683
2273
{
2684
2274
"BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
2275
+
"Counter": "0",
2685
2276
"EventCode": "0x36",
2686
2277
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC",
2687
2278
"PerPkg": "1",
···
2691
2280
},
2692
2281
{
2693
2282
"BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that miss the cache",
2283
+
"Counter": "0",
2694
2284
"EventCode": "0x36",
2695
2285
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
2696
2286
"PerPkg": "1",
···
2701
2289
},
2702
2290
{
2703
2291
"BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache",
2292
+
"Counter": "0",
2704
2293
"EventCode": "0x36",
2705
2294
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
2706
2295
"PerPkg": "1",
···
2711
2298
},
2712
2299
{
2713
2300
"BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache",
2301
+
"Counter": "0",
2714
2302
"EventCode": "0x36",
2715
2303
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
2716
2304
"PerPkg": "1",
···
2721
2307
},
2722
2308
{
2723
2309
"BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
2310
+
"Counter": "0",
2724
2311
"EventCode": "0x36",
2725
2312
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC",
2726
2313
"PerPkg": "1",
···
2730
2315
},
2731
2316
{
2732
2317
"BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache",
2318
+
"Counter": "0",
2733
2319
"EventCode": "0x36",
2734
2320
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
2735
2321
"PerPkg": "1",
···
2740
2324
},
2741
2325
{
2742
2326
"BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
2327
+
"Counter": "0",
2743
2328
"EventCode": "0x36",
2744
2329
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC",
2745
2330
"PerPkg": "1",
···
2749
2332
},
2750
2333
{
2751
2334
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache",
2335
+
"Counter": "0",
2752
2336
"EventCode": "0x36",
2753
2337
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
2754
2338
"PerPkg": "1",
···
2759
2341
},
2760
2342
{
2761
2343
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed PMM addresses which miss the cache",
2344
+
"Counter": "0",
2762
2345
"EventCode": "0x36",
2763
2346
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
2347
+
"Experimental": "1",
2764
2348
"PerPkg": "1",
2765
2349
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
2766
2350
"UMask": "0xc8668a01",
···
2770
2350
},
2771
2351
{
2772
2352
"BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache",
2353
+
"Counter": "0",
2773
2354
"EventCode": "0x36",
2774
2355
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
2775
2356
"PerPkg": "1",
···
2780
2359
},
2781
2360
{
2782
2361
"BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed PMM addresses which miss the cache",
2362
+
"Counter": "0",
2783
2363
"EventCode": "0x36",
2784
2364
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
2365
+
"Experimental": "1",
2785
2366
"PerPkg": "1",
2786
2367
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
2787
2368
"UMask": "0xc86e8a01",
···
2791
2368
},
2792
2369
{
2793
2370
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache",
2371
+
"Counter": "0",
2794
2372
"EventCode": "0x36",
2795
2373
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
2796
2374
"PerPkg": "1",
···
2801
2377
},
2802
2378
{
2803
2379
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache",
2380
+
"Counter": "0",
2804
2381
"EventCode": "0x36",
2805
2382
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
2383
+
"Experimental": "1",
2806
2384
"PerPkg": "1",
2807
2385
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
2808
2386
"UMask": "0xc8670a01",
···
2812
2386
},
2813
2387
{
2814
2388
"BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache",
2389
+
"Counter": "0",
2815
2390
"EventCode": "0x36",
2816
2391
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
2817
2392
"PerPkg": "1",
···
2822
2395
},
2823
2396
{
2824
2397
"BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache",
2398
+
"Counter": "0",
2825
2399
"EventCode": "0x36",
2826
2400
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
2401
+
"Experimental": "1",
2827
2402
"PerPkg": "1",
2828
2403
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
2829
2404
"UMask": "0xc86f0a01",
···
2833
2404
},
2834
2405
{
2835
2406
"BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
2407
+
"Counter": "0",
2836
2408
"EventCode": "0x36",
2837
2409
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
2838
2410
"PerPkg": "1",
···
2843
2413
},
2844
2414
{
2845
2415
"BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
2416
+
"Counter": "0",
2846
2417
"EventCode": "0x36",
2847
2418
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC",
2848
2419
"PerPkg": "1",
···
2852
2421
},
2853
2422
{
2854
2423
"BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
2424
+
"Counter": "0",
2855
2425
"EventCode": "0x36",
2856
2426
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
2857
2427
"PerPkg": "1",
···
2862
2430
},
2863
2431
{
2864
2432
"BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
2433
+
"Counter": "0",
2865
2434
"EventCode": "0x36",
2866
2435
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
2867
2436
"PerPkg": "1",
···
2872
2439
},
2873
2440
{
2874
2441
"BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
2442
+
"Counter": "0",
2875
2443
"EventCode": "0x36",
2876
2444
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC",
2877
2445
"PerPkg": "1",
···
2881
2447
},
2882
2448
{
2883
2449
"BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
2450
+
"Counter": "0",
2884
2451
"EventCode": "0x36",
2885
2452
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
2886
2453
"PerPkg": "1",
···
2891
2456
},
2892
2457
{
2893
2458
"BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
2459
+
"Counter": "0",
2894
2460
"EventCode": "0x36",
2895
2461
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
2896
2462
"PerPkg": "1",
···
2901
2465
},
2902
2466
{
2903
2467
"BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
2468
+
"Counter": "0",
2904
2469
"EventCode": "0x36",
2905
2470
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
2906
2471
"PerPkg": "1",
···
2911
2474
},
2912
2475
{
2913
2476
"BriefDescription": "TOR Occupancy for UCRDF requests from local IA cores that miss the cache",
2477
+
"Counter": "0",
2914
2478
"EventCode": "0x36",
2915
2479
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
2916
2480
"PerPkg": "1",
···
2921
2483
},
2922
2484
{
2923
2485
"BriefDescription": "TOR Occupancy for WCIL requests from a local IA core that miss the cache",
2486
+
"Counter": "0",
2924
2487
"EventCode": "0x36",
2925
2488
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
2926
2489
"PerPkg": "1",
···
2931
2492
},
2932
2493
{
2933
2494
"BriefDescription": "TOR Occupancy for WCILF requests from local IA core that miss the cache",
2495
+
"Counter": "0",
2934
2496
"EventCode": "0x36",
2935
2497
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
2936
2498
"PerPkg": "1",
···
2941
2501
},
2942
2502
{
2943
2503
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache",
2504
+
"Counter": "0",
2944
2505
"EventCode": "0x36",
2945
2506
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
2946
2507
"PerPkg": "1",
···
2951
2510
},
2952
2511
{
2953
2512
"BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to PMM homed addresses which miss the cache",
2513
+
"Counter": "0",
2954
2514
"EventCode": "0x36",
2955
2515
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
2516
+
"Experimental": "1",
2956
2517
"PerPkg": "1",
2957
2518
"PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
2958
2519
"UMask": "0xc8678a01",
···
2962
2519
},
2963
2520
{
2964
2521
"BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache",
2522
+
"Counter": "0",
2965
2523
"EventCode": "0x36",
2966
2524
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
2967
2525
"PerPkg": "1",
···
2972
2528
},
2973
2529
{
2974
2530
"BriefDescription": "TOR Occupancy for WCIL requests from a local IA core to PMM homed addresses that miss the cache",
2531
+
"Counter": "0",
2975
2532
"EventCode": "0x36",
2976
2533
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
2534
+
"Experimental": "1",
2977
2535
"PerPkg": "1",
2978
2536
"PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
2979
2537
"UMask": "0xc86f8a01",
···
2983
2537
},
2984
2538
{
2985
2539
"BriefDescription": "TOR Occupancy for WIL requests from local IA cores that miss the cache",
2540
+
"Counter": "0",
2986
2541
"EventCode": "0x36",
2987
2542
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
2988
2543
"PerPkg": "1",
···
2993
2546
},
2994
2547
{
2995
2548
"BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
2549
+
"Counter": "0",
2996
2550
"EventCode": "0x36",
2997
2551
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
2998
2552
"PerPkg": "1",
···
3003
2555
},
3004
2556
{
3005
2557
"BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
2558
+
"Counter": "0",
3006
2559
"EventCode": "0x36",
3007
2560
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
3008
2561
"PerPkg": "1",
···
3013
2564
},
3014
2565
{
3015
2566
"BriefDescription": "TOR Occupancy for SpecItoM events that are initiated from the Core",
2567
+
"Counter": "0",
3016
2568
"EventCode": "0x36",
3017
2569
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
3018
2570
"PerPkg": "1",
···
3023
2573
},
3024
2574
{
3025
2575
"BriefDescription": "TOR Occupancy for WbMtoI requests from local IA cores",
2576
+
"Counter": "0",
3026
2577
"EventCode": "0x36",
3027
2578
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
3028
2579
"PerPkg": "1",
···
3033
2582
},
3034
2583
{
3035
2584
"BriefDescription": "TOR Occupancy for WCIL requests from a local IA core",
2585
+
"Counter": "0",
3036
2586
"EventCode": "0x36",
3037
2587
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
3038
2588
"PerPkg": "1",
···
3043
2591
},
3044
2592
{
3045
2593
"BriefDescription": "TOR Occupancy for WCILF requests from local IA core",
2594
+
"Counter": "0",
3046
2595
"EventCode": "0x36",
3047
2596
"EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
3048
2597
"PerPkg": "1",
···
3053
2600
},
3054
2601
{
3055
2602
"BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices",
2603
+
"Counter": "0",
3056
2604
"EventCode": "0x36",
3057
2605
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
2606
+
"Experimental": "1",
3058
2607
"PerPkg": "1",
3059
2608
"PublicDescription": "TOR Occupancy : All requests from IO Devices",
3060
2609
"UMask": "0xc001ff04",
···
3064
2609
},
3065
2610
{
3066
2611
"BriefDescription": "TOR Occupancy for CLFlush requests from IO devices",
2612
+
"Counter": "0",
3067
2613
"EventCode": "0x36",
3068
2614
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
3069
2615
"PerPkg": "1",
···
3074
2618
},
3075
2619
{
3076
2620
"BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices which hit the cache",
2621
+
"Counter": "0",
3077
2622
"EventCode": "0x36",
3078
2623
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
2624
+
"Experimental": "1",
3079
2625
"PerPkg": "1",
3080
2626
"PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
3081
2627
"UMask": "0xc001fd04",
···
3085
2627
},
3086
2628
{
3087
2629
"BriefDescription": "TOR Occupancy for ItoMs from local IO devices which hit the cache",
2630
+
"Counter": "0",
3088
2631
"EventCode": "0x36",
3089
2632
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
3090
2633
"PerPkg": "1",
···
3095
2636
},
3096
2637
{
3097
2638
"BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
2639
+
"Counter": "0",
3098
2640
"EventCode": "0x36",
3099
2641
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
3100
2642
"PerPkg": "1",
···
3105
2645
},
3106
2646
{
3107
2647
"BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC",
2648
+
"Counter": "0",
3108
2649
"EventCode": "0x36",
3109
2650
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
3110
2651
"PerPkg": "1",
···
3115
2654
},
3116
2655
{
3117
2656
"BriefDescription": "TOR Occupancy for RFOs from local IO devices which hit the cache",
2657
+
"Counter": "0",
3118
2658
"EventCode": "0x36",
3119
2659
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
3120
2660
"PerPkg": "1",
···
3125
2663
},
3126
2664
{
3127
2665
"BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices",
2666
+
"Counter": "0",
3128
2667
"EventCode": "0x36",
3129
2668
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
3130
2669
"PerPkg": "1",
···
3135
2672
},
3136
2673
{
3137
2674
"BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices",
2675
+
"Counter": "0",
3138
2676
"EventCode": "0x36",
3139
2677
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
3140
2678
"PerPkg": "1",
···
3145
2681
},
3146
2682
{
3147
2683
"BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices which miss the cache",
2684
+
"Counter": "0",
3148
2685
"EventCode": "0x36",
3149
2686
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
2687
+
"Experimental": "1",
3150
2688
"PerPkg": "1",
3151
2689
"PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
3152
2690
"UMask": "0xc001fe04",
···
3156
2690
},
3157
2691
{
3158
2692
"BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache",
2693
+
"Counter": "0",
3159
2694
"EventCode": "0x36",
3160
2695
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
3161
2696
"PerPkg": "1",
···
3166
2699
},
3167
2700
{
3168
2701
"BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
2702
+
"Counter": "0",
3169
2703
"EventCode": "0x36",
3170
2704
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
3171
2705
"PerPkg": "1",
···
3176
2708
},
3177
2709
{
3178
2710
"BriefDescription": "TOR Occupancy for ItoMCacheNear transactions from an IO device on the local socket that miss the cache",
2711
+
"Counter": "0",
3179
2712
"EventCode": "0x36",
3180
2713
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL",
2714
+
"Experimental": "1",
3181
2715
"PerPkg": "1",
3182
2716
"PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
3183
2717
"UMask": "0xcd42fe04",
···
3187
2717
},
3188
2718
{
3189
2719
"BriefDescription": "TOR Occupancy for ItoMCacheNear transactions from an IO device on a remote socket that miss the cache",
2720
+
"Counter": "0",
3190
2721
"EventCode": "0x36",
3191
2722
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE",
2723
+
"Experimental": "1",
3192
2724
"PerPkg": "1",
3193
2725
"PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
3194
2726
"UMask": "0xcd437e04",
···
3198
2726
},
3199
2727
{
3200
2728
"BriefDescription": "TOR Occupancy for ItoM transactions from an IO device on the local socket that miss the cache",
2729
+
"Counter": "0",
3201
2730
"EventCode": "0x36",
3202
2731
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL",
2732
+
"Experimental": "1",
3203
2733
"PerPkg": "1",
3204
2734
"PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
3205
2735
"UMask": "0xcc42fe04",
···
3209
2735
},
3210
2736
{
3211
2737
"BriefDescription": "TOR Occupancy for ItoM transactions from an IO device on a remote socket that miss the cache",
2738
+
"Counter": "0",
3212
2739
"EventCode": "0x36",
3213
2740
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE",
2741
+
"Experimental": "1",
3214
2742
"PerPkg": "1",
3215
2743
"PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
3216
2744
"UMask": "0xcc437e04",
···
3220
2744
},
3221
2745
{
3222
2746
"BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC",
2747
+
"Counter": "0",
3223
2748
"EventCode": "0x36",
3224
2749
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
3225
2750
"PerPkg": "1",
···
3230
2753
},
3231
2754
{
3232
2755
"BriefDescription": "TOR Occupancy for PCIRDCUR transactions from an IO device on the local socket that miss the cache",
2756
+
"Counter": "0",
3233
2757
"EventCode": "0x36",
3234
2758
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL",
2759
+
"Experimental": "1",
3235
2760
"PerPkg": "1",
3236
2761
"PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
3237
2762
"UMask": "0xc8f2fe04",
···
3241
2762
},
3242
2763
{
3243
2764
"BriefDescription": "TOR Occupancy for PCIRDCUR transactions from an IO device on a remote socket that miss the cache",
2765
+
"Counter": "0",
3244
2766
"EventCode": "0x36",
3245
2767
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE",
2768
+
"Experimental": "1",
3246
2769
"PerPkg": "1",
3247
2770
"PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
3248
2771
"UMask": "0xc8f37e04",
···
3252
2771
},
3253
2772
{
3254
2773
"BriefDescription": "TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache",
2774
+
"Counter": "0",
3255
2775
"EventCode": "0x36",
3256
2776
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
3257
2777
"PerPkg": "1",
···
3262
2780
},
3263
2781
{
3264
2782
"BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices",
2783
+
"Counter": "0",
3265
2784
"EventCode": "0x36",
3266
2785
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
3267
2786
"PerPkg": "1",
···
3272
2789
},
3273
2790
{
3274
2791
"BriefDescription": "TOR Occupancy for RFOs from local IO devices",
2792
+
"Counter": "0",
3275
2793
"EventCode": "0x36",
3276
2794
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
3277
2795
"PerPkg": "1",
···
3282
2798
},
3283
2799
{
3284
2800
"BriefDescription": "TOR Occupancy for WBMtoI requests from IO devices",
2801
+
"Counter": "0",
3285
2802
"EventCode": "0x36",
3286
2803
"EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
3287
2804
"PerPkg": "1",
···
3292
2807
},
3293
2808
{
3294
2809
"BriefDescription": "TOR Occupancy for All locally initiated requests",
2810
+
"Counter": "0",
3295
2811
"EventCode": "0x36",
3296
2812
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
2813
+
"Experimental": "1",
3297
2814
"PerPkg": "1",
3298
2815
"PublicDescription": "TOR Occupancy : All from Local iA and IO",
3299
2816
"UMask": "0xc000ff05",
···
3303
2816
},
3304
2817
{
3305
2818
"BriefDescription": "TOR Occupancy for All from Local iA",
2819
+
"Counter": "0",
3306
2820
"EventCode": "0x36",
3307
2821
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
2822
+
"Experimental": "1",
3308
2823
"PerPkg": "1",
3309
2824
"PublicDescription": "TOR Occupancy : All from Local iA",
3310
2825
"UMask": "0xc000ff01",
···
3314
2825
},
3315
2826
{
3316
2827
"BriefDescription": "TOR Occupancy for All from Local IO",
2828
+
"Counter": "0",
3317
2829
"EventCode": "0x36",
3318
2830
"EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
2831
+
"Experimental": "1",
3319
2832
"PerPkg": "1",
3320
2833
"PublicDescription": "TOR Occupancy : All from Local IO",
3321
2834
"UMask": "0xc000ff04",
···
3325
2834
},
3326
2835
{
3327
2836
"BriefDescription": "TOR Occupancy for All remote requests (e.g. snoops, writebacks) that came from remote sockets",
2837
+
"Counter": "0",
3328
2838
"EventCode": "0x36",
3329
2839
"EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
2840
+
"Experimental": "1",
3330
2841
"PerPkg": "1",
3331
2842
"PublicDescription": "TOR Occupancy : All Remote Requests",
3332
2843
"UMask": "0xc001ffc8",
···
3336
2843
},
3337
2844
{
3338
2845
"BriefDescription": "TOR Occupancy for All snoops to this LLC that came from remote sockets",
2846
+
"Counter": "0",
3339
2847
"EventCode": "0x36",
3340
2848
"EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
2849
+
"Experimental": "1",
3341
2850
"PerPkg": "1",
3342
2851
"PublicDescription": "TOR Occupancy : All Snoops from Remote",
3343
2852
"UMask": "0xc001ff08",
+21
tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json
+21
tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "B2CXL Clockticks",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x01",
5
6
"EventName": "UNC_B2CXL_CLOCKTICKS",
6
7
"PerPkg": "1",
7
8
"PortMask": "0x000",
8
9
"Unit": "B2CXL"
10
+
},
11
+
{
12
+
"BriefDescription": "Number of Allocation to Mem Data Packing buffer",
13
+
"Counter": "4,5,6,7",
14
+
"EventCode": "0x41",
15
+
"EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
16
+
"Experimental": "1",
17
+
"PerPkg": "1",
18
+
"UMask": "0x10",
19
+
"Unit": "CXLCM"
20
+
},
21
+
{
22
+
"BriefDescription": "Number of Allocation to M2S Data AGF",
23
+
"Counter": "0,1,2,3",
24
+
"EventCode": "0x02",
25
+
"EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
26
+
"Experimental": "1",
27
+
"PerPkg": "1",
28
+
"UMask": "0x20",
29
+
"Unit": "CXLDP"
9
30
}
10
31
]
+267
tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnect.json
+267
tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnect.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Clockticks of the mesh to memory (B2CMI)",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x01",
5
6
"EventName": "UNC_B2CMI_CLOCKTICKS",
6
7
"PerPkg": "1",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Counts the number of time D2C was not honoured by egress due to directory state constraints",
11
+
"Counter": "0,1,2,3",
12
12
"EventCode": "0x17",
13
13
"EventName": "UNC_B2CMI_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
14
+
"Experimental": "1",
14
15
"PerPkg": "1",
15
16
"UMask": "0x1",
16
17
"Unit": "B2CMI"
17
18
},
18
19
{
19
20
"BriefDescription": "Counts the number of times B2CMI egress did D2C (direct to core)",
21
+
"Counter": "0,1,2,3",
20
22
"EventCode": "0x16",
21
23
"EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN",
22
24
"PerPkg": "1",
···
28
24
},
29
25
{
30
26
"BriefDescription": "Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn",
27
+
"Counter": "0,1,2,3",
31
28
"EventCode": "0x18",
32
29
"EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE",
30
+
"Experimental": "1",
33
31
"PerPkg": "1",
34
32
"UMask": "0x1",
35
33
"Unit": "B2CMI"
36
34
},
37
35
{
38
36
"BriefDescription": "Counts the number of d2k wasn't done due to credit constraints",
37
+
"Counter": "0,1,2,3",
39
38
"EventCode": "0x1B",
40
39
"EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS",
41
40
"PerPkg": "1",
···
47
40
},
48
41
{
49
42
"BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints",
43
+
"Counter": "0,1,2,3",
50
44
"EventCode": "0x1B",
51
45
"EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS",
52
46
"PerPkg": "1",
···
56
48
},
57
49
{
58
50
"BriefDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints",
51
+
"Counter": "0,1,2,3",
59
52
"EventCode": "0x1A",
60
53
"EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
61
54
"PerPkg": "1",
···
65
56
},
66
57
{
67
58
"BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints",
59
+
"Counter": "0,1,2,3",
68
60
"EventCode": "0x1A",
69
61
"EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS",
70
62
"PerPkg": "1",
···
74
64
},
75
65
{
76
66
"BriefDescription": "Counts the number of times egress did D2K (Direct to KTI)",
67
+
"Counter": "0,1,2,3",
77
68
"EventCode": "0x19",
78
69
"EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN",
79
70
"PerPkg": "1",
···
83
72
},
84
73
{
85
74
"BriefDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn",
75
+
"Counter": "0,1,2,3",
86
76
"EventCode": "0x1C",
87
77
"EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE",
88
78
"PerPkg": "1",
···
92
80
},
93
81
{
94
82
"BriefDescription": "Directory Hit Clean",
83
+
"Counter": "0,1,2,3",
95
84
"EventCode": "0x1D",
96
85
"EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN",
86
+
"Experimental": "1",
97
87
"PerPkg": "1",
98
88
"UMask": "0x38",
99
89
"Unit": "B2CMI"
100
90
},
101
91
{
102
92
"BriefDescription": "Directory Hit : On NonDirty Line in A State",
93
+
"Counter": "0,1,2,3",
103
94
"EventCode": "0x1D",
104
95
"EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_A",
96
+
"Experimental": "1",
105
97
"PerPkg": "1",
106
98
"UMask": "0x20",
107
99
"Unit": "B2CMI"
108
100
},
109
101
{
110
102
"BriefDescription": "Directory Hit : On NonDirty Line in I State",
103
+
"Counter": "0,1,2,3",
111
104
"EventCode": "0x1D",
112
105
"EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_I",
106
+
"Experimental": "1",
113
107
"PerPkg": "1",
114
108
"UMask": "0x8",
115
109
"Unit": "B2CMI"
116
110
},
117
111
{
118
112
"BriefDescription": "Directory Hit : On NonDirty Line in S State",
113
+
"Counter": "0,1,2,3",
119
114
"EventCode": "0x1D",
120
115
"EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_S",
116
+
"Experimental": "1",
121
117
"PerPkg": "1",
122
118
"UMask": "0x10",
123
119
"Unit": "B2CMI"
124
120
},
125
121
{
126
122
"BriefDescription": "Directory Hit Dirty (modified)",
123
+
"Counter": "0,1,2,3",
127
124
"EventCode": "0x1D",
128
125
"EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY",
126
+
"Experimental": "1",
129
127
"PerPkg": "1",
130
128
"UMask": "0x7",
131
129
"Unit": "B2CMI"
132
130
},
133
131
{
134
132
"BriefDescription": "Directory Hit : On Dirty Line in A State",
133
+
"Counter": "0,1,2,3",
135
134
"EventCode": "0x1D",
136
135
"EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_A",
136
+
"Experimental": "1",
137
137
"PerPkg": "1",
138
138
"UMask": "0x4",
139
139
"Unit": "B2CMI"
140
140
},
141
141
{
142
142
"BriefDescription": "Directory Hit : On Dirty Line in I State",
143
+
"Counter": "0,1,2,3",
143
144
"EventCode": "0x1D",
144
145
"EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_I",
146
+
"Experimental": "1",
145
147
"PerPkg": "1",
146
148
"UMask": "0x1",
147
149
"Unit": "B2CMI"
148
150
},
149
151
{
150
152
"BriefDescription": "Directory Hit : On Dirty Line in S State",
153
+
"Counter": "0,1,2,3",
151
154
"EventCode": "0x1D",
152
155
"EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_S",
156
+
"Experimental": "1",
153
157
"PerPkg": "1",
154
158
"UMask": "0x2",
155
159
"Unit": "B2CMI"
156
160
},
157
161
{
158
162
"BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory",
163
+
"Counter": "0,1,2,3",
159
164
"EventCode": "0x20",
160
165
"EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY",
161
166
"PerPkg": "1",
···
181
152
},
182
153
{
183
154
"BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory",
155
+
"Counter": "0,1,2,3",
184
156
"EventCode": "0x20",
185
157
"EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A",
186
158
"PerPkg": "1",
···
190
160
},
191
161
{
192
162
"BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory",
163
+
"Counter": "0,1,2,3",
193
164
"EventCode": "0x20",
194
165
"EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I",
195
166
"PerPkg": "1",
···
199
168
},
200
169
{
201
170
"BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory",
171
+
"Counter": "0,1,2,3",
202
172
"EventCode": "0x20",
203
173
"EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S",
204
174
"PerPkg": "1",
···
209
177
},
210
178
{
211
179
"BriefDescription": "Directory Miss Clean",
180
+
"Counter": "0,1,2,3",
212
181
"EventCode": "0x1E",
213
182
"EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN",
183
+
"Experimental": "1",
214
184
"PerPkg": "1",
215
185
"UMask": "0x38",
216
186
"Unit": "B2CMI"
217
187
},
218
188
{
219
189
"BriefDescription": "Directory Miss : On NonDirty Line in A State",
190
+
"Counter": "0,1,2,3",
220
191
"EventCode": "0x1E",
221
192
"EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_A",
193
+
"Experimental": "1",
222
194
"PerPkg": "1",
223
195
"UMask": "0x20",
224
196
"Unit": "B2CMI"
225
197
},
226
198
{
227
199
"BriefDescription": "Directory Miss : On NonDirty Line in I State",
200
+
"Counter": "0,1,2,3",
228
201
"EventCode": "0x1E",
229
202
"EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_I",
203
+
"Experimental": "1",
230
204
"PerPkg": "1",
231
205
"UMask": "0x8",
232
206
"Unit": "B2CMI"
233
207
},
234
208
{
235
209
"BriefDescription": "Directory Miss : On NonDirty Line in S State",
210
+
"Counter": "0,1,2,3",
236
211
"EventCode": "0x1E",
237
212
"EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_S",
213
+
"Experimental": "1",
238
214
"PerPkg": "1",
239
215
"UMask": "0x10",
240
216
"Unit": "B2CMI"
241
217
},
242
218
{
243
219
"BriefDescription": "Directory Miss Dirty (modified)",
220
+
"Counter": "0,1,2,3",
244
221
"EventCode": "0x1E",
245
222
"EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY",
223
+
"Experimental": "1",
246
224
"PerPkg": "1",
247
225
"UMask": "0x7",
248
226
"Unit": "B2CMI"
249
227
},
250
228
{
251
229
"BriefDescription": "Directory Miss : On Dirty Line in A State",
230
+
"Counter": "0,1,2,3",
252
231
"EventCode": "0x1E",
253
232
"EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_A",
233
+
"Experimental": "1",
254
234
"PerPkg": "1",
255
235
"UMask": "0x4",
256
236
"Unit": "B2CMI"
257
237
},
258
238
{
259
239
"BriefDescription": "Directory Miss : On Dirty Line in I State",
240
+
"Counter": "0,1,2,3",
260
241
"EventCode": "0x1E",
261
242
"EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_I",
243
+
"Experimental": "1",
262
244
"PerPkg": "1",
263
245
"UMask": "0x1",
264
246
"Unit": "B2CMI"
265
247
},
266
248
{
267
249
"BriefDescription": "Directory Miss : On Dirty Line in S State",
250
+
"Counter": "0,1,2,3",
268
251
"EventCode": "0x1E",
269
252
"EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_S",
253
+
"Experimental": "1",
270
254
"PerPkg": "1",
271
255
"UMask": "0x2",
272
256
"Unit": "B2CMI"
273
257
},
274
258
{
275
259
"BriefDescription": "Any A2I Transition",
260
+
"Counter": "0,1,2,3",
276
261
"EventCode": "0x21",
277
262
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I",
278
263
"PerPkg": "1",
···
298
249
},
299
250
{
300
251
"BriefDescription": "Any A2S Transition",
252
+
"Counter": "0,1,2,3",
301
253
"EventCode": "0x21",
302
254
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S",
303
255
"PerPkg": "1",
···
307
257
},
308
258
{
309
259
"BriefDescription": "Counts cisgress directory updates",
260
+
"Counter": "0,1,2,3",
310
261
"EventCode": "0x21",
311
262
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY",
312
263
"PerPkg": "1",
···
316
265
},
317
266
{
318
267
"BriefDescription": "Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM)",
268
+
"Counter": "0,1,2,3",
319
269
"EventCode": "0x21",
320
270
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_ANY",
271
+
"Experimental": "1",
321
272
"PerPkg": "1",
322
273
"UMask": "0x101",
323
274
"Unit": "B2CMI"
324
275
},
325
276
{
326
277
"BriefDescription": "Directory update in near memory to the A state",
278
+
"Counter": "0,1,2,3",
327
279
"EventCode": "0x21",
328
280
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2A",
281
+
"Experimental": "1",
329
282
"PerPkg": "1",
330
283
"UMask": "0x114",
331
284
"Unit": "B2CMI"
332
285
},
333
286
{
334
287
"BriefDescription": "Directory update in near memory to the I state",
288
+
"Counter": "0,1,2,3",
335
289
"EventCode": "0x21",
336
290
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2I",
291
+
"Experimental": "1",
337
292
"PerPkg": "1",
338
293
"UMask": "0x128",
339
294
"Unit": "B2CMI"
340
295
},
341
296
{
342
297
"BriefDescription": "Directory update in near memory to the S state",
298
+
"Counter": "0,1,2,3",
343
299
"EventCode": "0x21",
344
300
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2S",
301
+
"Experimental": "1",
345
302
"PerPkg": "1",
346
303
"UMask": "0x142",
347
304
"Unit": "B2CMI"
348
305
},
349
306
{
350
307
"BriefDescription": "Any I2A Transition",
308
+
"Counter": "0,1,2,3",
351
309
"EventCode": "0x21",
352
310
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A",
353
311
"PerPkg": "1",
···
365
305
},
366
306
{
367
307
"BriefDescription": "Any I2S Transition",
308
+
"Counter": "0,1,2,3",
368
309
"EventCode": "0x21",
369
310
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S",
370
311
"PerPkg": "1",
···
374
313
},
375
314
{
376
315
"BriefDescription": "Directory update in far memory to the A state",
316
+
"Counter": "0,1,2,3",
377
317
"EventCode": "0x21",
378
318
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2A",
319
+
"Experimental": "1",
379
320
"PerPkg": "1",
380
321
"UMask": "0x214",
381
322
"Unit": "B2CMI"
382
323
},
383
324
{
384
325
"BriefDescription": "Directory update in far memory to the I state",
326
+
"Counter": "0,1,2,3",
385
327
"EventCode": "0x21",
386
328
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2I",
329
+
"Experimental": "1",
387
330
"PerPkg": "1",
388
331
"UMask": "0x228",
389
332
"Unit": "B2CMI"
390
333
},
391
334
{
392
335
"BriefDescription": "Directory update in far memory to the S state",
336
+
"Counter": "0,1,2,3",
393
337
"EventCode": "0x21",
394
338
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2S",
339
+
"Experimental": "1",
395
340
"PerPkg": "1",
396
341
"UMask": "0x242",
397
342
"Unit": "B2CMI"
398
343
},
399
344
{
400
345
"BriefDescription": "Any S2A Transition",
346
+
"Counter": "0,1,2,3",
401
347
"EventCode": "0x21",
402
348
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2A",
349
+
"Experimental": "1",
403
350
"PerPkg": "1",
404
351
"UMask": "0x310",
405
352
"Unit": "B2CMI"
406
353
},
407
354
{
408
355
"BriefDescription": "Any S2I Transition",
356
+
"Counter": "0,1,2,3",
409
357
"EventCode": "0x21",
410
358
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2I",
359
+
"Experimental": "1",
411
360
"PerPkg": "1",
412
361
"UMask": "0x308",
413
362
"Unit": "B2CMI"
414
363
},
415
364
{
416
365
"BriefDescription": "Directory update to the A state",
366
+
"Counter": "0,1,2,3",
417
367
"EventCode": "0x21",
418
368
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2A",
369
+
"Experimental": "1",
419
370
"PerPkg": "1",
420
371
"UMask": "0x314",
421
372
"Unit": "B2CMI"
422
373
},
423
374
{
424
375
"BriefDescription": "Directory update to the I state",
376
+
"Counter": "0,1,2,3",
425
377
"EventCode": "0x21",
426
378
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2I",
379
+
"Experimental": "1",
427
380
"PerPkg": "1",
428
381
"UMask": "0x328",
429
382
"Unit": "B2CMI"
430
383
},
431
384
{
432
385
"BriefDescription": "Directory update to the S state",
386
+
"Counter": "0,1,2,3",
433
387
"EventCode": "0x21",
434
388
"EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2S",
389
+
"Experimental": "1",
435
390
"PerPkg": "1",
436
391
"UMask": "0x342",
437
392
"Unit": "B2CMI"
438
393
},
439
394
{
440
395
"BriefDescription": "Counts any read",
396
+
"Counter": "0,1,2,3",
441
397
"EventCode": "0x24",
442
398
"EventName": "UNC_B2CMI_IMC_READS.ALL",
443
399
"PerPkg": "1",
···
463
385
},
464
386
{
465
387
"BriefDescription": "Counts normal reads issue to CMI",
388
+
"Counter": "0,1,2,3",
466
389
"EventCode": "0x24",
467
390
"EventName": "UNC_B2CMI_IMC_READS.NORMAL",
468
391
"PerPkg": "1",
···
472
393
},
473
394
{
474
395
"BriefDescription": "Count reads to NM region",
396
+
"Counter": "0,1,2,3",
475
397
"EventCode": "0x24",
476
398
"EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_CACHE",
399
+
"Experimental": "1",
477
400
"PerPkg": "1",
478
401
"UMask": "0x110",
479
402
"Unit": "B2CMI"
480
403
},
481
404
{
482
405
"BriefDescription": "Counts reads to 1lm non persistent memory regions",
406
+
"Counter": "0,1,2,3",
483
407
"EventCode": "0x24",
484
408
"EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_MEM",
409
+
"Experimental": "1",
485
410
"PerPkg": "1",
486
411
"UMask": "0x108",
487
412
"Unit": "B2CMI"
488
413
},
489
414
{
490
415
"BriefDescription": "All Writes - All Channels",
416
+
"Counter": "0,1,2,3",
491
417
"EventCode": "0x25",
492
418
"EventName": "UNC_B2CMI_IMC_WRITES.ALL",
493
419
"PerPkg": "1",
···
501
417
},
502
418
{
503
419
"BriefDescription": "Full Non-ISOCH - All Channels",
420
+
"Counter": "0,1,2,3",
504
421
"EventCode": "0x25",
505
422
"EventName": "UNC_B2CMI_IMC_WRITES.FULL",
506
423
"PerPkg": "1",
···
510
425
},
511
426
{
512
427
"BriefDescription": "Non-Inclusive - All Channels",
428
+
"Counter": "0,1,2,3",
513
429
"EventCode": "0x25",
514
430
"EventName": "UNC_B2CMI_IMC_WRITES.NI",
431
+
"Experimental": "1",
515
432
"PerPkg": "1",
516
433
"Unit": "B2CMI"
517
434
},
518
435
{
519
436
"BriefDescription": "Non-Inclusive Miss - All Channels",
437
+
"Counter": "0,1,2,3",
520
438
"EventCode": "0x25",
521
439
"EventName": "UNC_B2CMI_IMC_WRITES.NI_MISS",
440
+
"Experimental": "1",
522
441
"PerPkg": "1",
523
442
"Unit": "B2CMI"
524
443
},
525
444
{
526
445
"BriefDescription": "Partial Non-ISOCH - All Channels",
446
+
"Counter": "0,1,2,3",
527
447
"EventCode": "0x25",
528
448
"EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL",
529
449
"PerPkg": "1",
···
537
447
},
538
448
{
539
449
"BriefDescription": "DDR, acting as Cache - All Channels",
450
+
"Counter": "0,1,2,3",
540
451
"EventCode": "0x25",
541
452
"EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_CACHE",
453
+
"Experimental": "1",
542
454
"PerPkg": "1",
543
455
"UMask": "0x140",
544
456
"Unit": "B2CMI"
545
457
},
546
458
{
547
459
"BriefDescription": "DDR - All Channels",
460
+
"Counter": "0,1,2,3",
548
461
"EventCode": "0x25",
549
462
"EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_MEM",
463
+
"Experimental": "1",
550
464
"PerPkg": "1",
551
465
"UMask": "0x120",
552
466
"Unit": "B2CMI"
553
467
},
554
468
{
555
469
"BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
470
+
"Counter": "0,1,2,3",
556
471
"EventCode": "0x56",
557
472
"EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_UPI",
473
+
"Experimental": "1",
558
474
"PerPkg": "1",
559
475
"UMask": "0x2",
560
476
"Unit": "B2CMI"
561
477
},
562
478
{
563
479
"BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
480
+
"Counter": "0,1,2,3",
564
481
"EventCode": "0x56",
565
482
"EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_XPT",
483
+
"Experimental": "1",
566
484
"PerPkg": "1",
567
485
"UMask": "0x1",
568
486
"Unit": "B2CMI"
569
487
},
570
488
{
571
489
"BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
490
+
"Counter": "0,1,2,3",
572
491
"EventCode": "0x56",
573
492
"EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH",
574
493
"PerPkg": "1",
···
586
487
},
587
488
{
588
489
"BriefDescription": "Prefetch CAM Inserts : XPT -All Channels",
490
+
"Counter": "0,1,2,3",
589
491
"EventCode": "0x56",
590
492
"EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH",
591
493
"PerPkg": "1",
···
596
496
},
597
497
{
598
498
"BriefDescription": "Prefetch CAM Occupancy : Channel 0",
499
+
"Counter": "0,1,2,3",
599
500
"EventCode": "0x54",
600
501
"EventName": "UNC_B2CMI_PREFCAM_OCCUPANCY.CH0",
502
+
"Experimental": "1",
601
503
"PerPkg": "1",
602
504
"UMask": "0x1",
603
505
"Unit": "B2CMI"
604
506
},
605
507
{
606
508
"BriefDescription": "Counts the 2lm reads and WRNI which were a hit",
509
+
"Counter": "0,1,2,3",
607
510
"EventCode": "0x1F",
608
511
"EventName": "UNC_B2CMI_TAG_HIT.ALL",
512
+
"Experimental": "1",
609
513
"PerPkg": "1",
610
514
"UMask": "0xf",
611
515
"Unit": "B2CMI"
612
516
},
613
517
{
614
518
"BriefDescription": "Counts the 2lm reads which were a hit clean",
519
+
"Counter": "0,1,2,3",
615
520
"EventCode": "0x1F",
616
521
"EventName": "UNC_B2CMI_TAG_HIT.RD_CLEAN",
522
+
"Experimental": "1",
617
523
"PerPkg": "1",
618
524
"UMask": "0x1",
619
525
"Unit": "B2CMI"
620
526
},
621
527
{
622
528
"BriefDescription": "Counts the 2lm reads which were a hit dirty",
529
+
"Counter": "0,1,2,3",
623
530
"EventCode": "0x1F",
624
531
"EventName": "UNC_B2CMI_TAG_HIT.RD_DIRTY",
532
+
"Experimental": "1",
625
533
"PerPkg": "1",
626
534
"UMask": "0x2",
627
535
"Unit": "B2CMI"
628
536
},
629
537
{
630
538
"BriefDescription": "Counts the 2lm WRNI which were a hit clean",
539
+
"Counter": "0,1,2,3",
631
540
"EventCode": "0x1F",
632
541
"EventName": "UNC_B2CMI_TAG_HIT.WR_CLEAN",
542
+
"Experimental": "1",
633
543
"PerPkg": "1",
634
544
"UMask": "0x4",
635
545
"Unit": "B2CMI"
636
546
},
637
547
{
638
548
"BriefDescription": "Counts the 2lm WRNI which were a hit dirty",
549
+
"Counter": "0,1,2,3",
639
550
"EventCode": "0x1F",
640
551
"EventName": "UNC_B2CMI_TAG_HIT.WR_DIRTY",
552
+
"Experimental": "1",
641
553
"PerPkg": "1",
642
554
"UMask": "0x8",
643
555
"Unit": "B2CMI"
644
556
},
645
557
{
646
558
"BriefDescription": "Counts the 2lm second way read miss for a WrNI",
559
+
"Counter": "0,1,2,3",
647
560
"EventCode": "0x4B",
648
561
"EventName": "UNC_B2CMI_TAG_MISS.CLEAN",
562
+
"Experimental": "1",
649
563
"PerPkg": "1",
650
564
"UMask": "0x5",
651
565
"Unit": "B2CMI"
652
566
},
653
567
{
654
568
"BriefDescription": "Counts the 2lm second way read miss for a WrNI",
569
+
"Counter": "0,1,2,3",
655
570
"EventCode": "0x4B",
656
571
"EventName": "UNC_B2CMI_TAG_MISS.DIRTY",
572
+
"Experimental": "1",
657
573
"PerPkg": "1",
658
574
"UMask": "0xa",
659
575
"Unit": "B2CMI"
660
576
},
661
577
{
662
578
"BriefDescription": "Counts the 2lm second way read miss for a Rd",
579
+
"Counter": "0,1,2,3",
663
580
"EventCode": "0x4B",
664
581
"EventName": "UNC_B2CMI_TAG_MISS.RD_2WAY",
582
+
"Experimental": "1",
665
583
"PerPkg": "1",
666
584
"UMask": "0x10",
667
585
"Unit": "B2CMI"
668
586
},
669
587
{
670
588
"BriefDescription": "Counts the 2lm reads which were a miss and the cache line is unmodified",
589
+
"Counter": "0,1,2,3",
671
590
"EventCode": "0x4B",
672
591
"EventName": "UNC_B2CMI_TAG_MISS.RD_CLEAN",
592
+
"Experimental": "1",
673
593
"PerPkg": "1",
674
594
"UMask": "0x1",
675
595
"Unit": "B2CMI"
676
596
},
677
597
{
678
598
"BriefDescription": "Counts the 2lm reads which were a miss and the cache line is modified",
599
+
"Counter": "0,1,2,3",
679
600
"EventCode": "0x4B",
680
601
"EventName": "UNC_B2CMI_TAG_MISS.RD_DIRTY",
602
+
"Experimental": "1",
681
603
"PerPkg": "1",
682
604
"UMask": "0x2",
683
605
"Unit": "B2CMI"
684
606
},
685
607
{
686
608
"BriefDescription": "Counts the 2lm second way read miss for a WrNI",
609
+
"Counter": "0,1,2,3",
687
610
"EventCode": "0x4B",
688
611
"EventName": "UNC_B2CMI_TAG_MISS.WR_2WAY",
612
+
"Experimental": "1",
689
613
"PerPkg": "1",
690
614
"UMask": "0x20",
691
615
"Unit": "B2CMI"
692
616
},
693
617
{
694
618
"BriefDescription": "Counts the 2lm WRNI which were a miss and the cache line is unmodified",
619
+
"Counter": "0,1,2,3",
695
620
"EventCode": "0x4B",
696
621
"EventName": "UNC_B2CMI_TAG_MISS.WR_CLEAN",
622
+
"Experimental": "1",
697
623
"PerPkg": "1",
698
624
"UMask": "0x4",
699
625
"Unit": "B2CMI"
700
626
},
701
627
{
702
628
"BriefDescription": "Counts the 2lm WRNI which were a miss and the cache line is modified",
629
+
"Counter": "0,1,2,3",
703
630
"EventCode": "0x4B",
704
631
"EventName": "UNC_B2CMI_TAG_MISS.WR_DIRTY",
632
+
"Experimental": "1",
705
633
"PerPkg": "1",
706
634
"UMask": "0x8",
707
635
"Unit": "B2CMI"
708
636
},
709
637
{
710
638
"BriefDescription": "Tracker Inserts : Channel 0",
639
+
"Counter": "0,1,2,3",
711
640
"EventCode": "0x32",
712
641
"EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0",
713
642
"PerPkg": "1",
···
745
616
},
746
617
{
747
618
"BriefDescription": "Tracker Occupancy : Channel 0",
619
+
"Counter": "0,1,2,3",
748
620
"EventCode": "0x33",
749
621
"EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0",
750
622
"PerPkg": "1",
···
754
624
},
755
625
{
756
626
"BriefDescription": "Write Tracker Inserts : Channel 0",
627
+
"Counter": "0,1,2,3",
757
628
"EventCode": "0x40",
758
629
"EventName": "UNC_B2CMI_WR_TRACKER_INSERTS.CH0",
630
+
"Experimental": "1",
759
631
"PerPkg": "1",
760
632
"UMask": "0x1",
761
633
"Unit": "B2CMI"
762
634
},
763
635
{
764
636
"BriefDescription": "UNC_B2HOT_CLOCKTICKS",
637
+
"Counter": "0,1,2,3",
765
638
"EventCode": "0x01",
766
639
"EventName": "UNC_B2HOT_CLOCKTICKS",
767
640
"PerPkg": "1",
···
773
640
},
774
641
{
775
642
"BriefDescription": "Number of uclks in domain",
643
+
"Counter": "0,1,2,3",
776
644
"EventCode": "0x01",
777
645
"EventName": "UNC_B2UPI_CLOCKTICKS",
778
646
"PerPkg": "1",
···
781
647
},
782
648
{
783
649
"BriefDescription": "Total Write Cache Occupancy : Mem",
650
+
"Counter": "0,1,2,3",
784
651
"EventCode": "0x0F",
785
652
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
653
+
"Experimental": "1",
786
654
"PerPkg": "1",
787
655
"UMask": "0x4",
788
656
"Unit": "IRP"
789
657
},
790
658
{
791
659
"BriefDescription": "IRP Clockticks",
660
+
"Counter": "0,1,2,3",
792
661
"EventCode": "0x01",
793
662
"EventName": "UNC_I_CLOCKTICKS",
794
663
"PerPkg": "1",
···
799
662
},
800
663
{
801
664
"BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
665
+
"Counter": "0,1,2,3",
802
666
"EventCode": "0x18",
803
667
"EventName": "UNC_I_FAF_INSERTS",
804
668
"PerPkg": "1",
···
807
669
},
808
670
{
809
671
"BriefDescription": "FAF occupancy",
672
+
"Counter": "0,1,2,3",
810
673
"EventCode": "0x19",
811
674
"EventName": "UNC_I_FAF_OCCUPANCY",
675
+
"Experimental": "1",
812
676
"PerPkg": "1",
813
677
"Unit": "IRP"
814
678
},
815
679
{
816
680
"BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
681
+
"Counter": "0,1,2,3",
817
682
"EventCode": "0x1F",
818
683
"EventName": "UNC_I_MISC1.LOST_FWD",
684
+
"Experimental": "1",
819
685
"PerPkg": "1",
820
686
"UMask": "0x10",
821
687
"Unit": "IRP"
822
688
},
823
689
{
824
690
"BriefDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
691
+
"Counter": "0,1,2,3",
825
692
"EventCode": "0x11",
826
693
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
827
694
"PerPkg": "1",
···
835
692
},
836
693
{
837
694
"BriefDescription": "MDF Clockticks",
695
+
"Counter": "0,1,2,3",
838
696
"EventCode": "0x01",
839
697
"EventName": "UNC_MDF_CLOCKTICKS",
840
698
"PerPkg": "1",
···
843
699
},
844
700
{
845
701
"BriefDescription": "Number of UPI LL clock cycles while the event is enabled",
702
+
"Counter": "0,1,2,3",
846
703
"EventCode": "0x01",
847
704
"EventName": "UNC_UPI_CLOCKTICKS",
848
705
"PerPkg": "1",
···
852
707
},
853
708
{
854
709
"BriefDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
710
+
"Counter": "0,1,2,3",
855
711
"EventCode": "0x21",
856
712
"EventName": "UNC_UPI_L1_POWER_CYCLES",
713
+
"Experimental": "1",
857
714
"PerPkg": "1",
858
715
"Unit": "UPI"
859
716
},
860
717
{
861
718
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
719
+
"Counter": "0,1,2,3",
862
720
"EventCode": "0x05",
863
721
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
722
+
"Experimental": "1",
864
723
"PerPkg": "1",
865
724
"UMask": "0xe",
866
725
"Unit": "UPI"
867
726
},
868
727
{
869
728
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
729
+
"Counter": "0,1,2,3",
870
730
"EventCode": "0x05",
871
731
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
732
+
"Experimental": "1",
872
733
"PerPkg": "1",
873
734
"UMask": "0x10e",
874
735
"Unit": "UPI"
875
736
},
876
737
{
877
738
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
739
+
"Counter": "0,1,2,3",
878
740
"EventCode": "0x05",
879
741
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
742
+
"Experimental": "1",
880
743
"PerPkg": "1",
881
744
"UMask": "0xf",
882
745
"Unit": "UPI"
883
746
},
884
747
{
885
748
"BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
749
+
"Counter": "0,1,2,3",
886
750
"EventCode": "0x05",
887
751
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
752
+
"Experimental": "1",
888
753
"PerPkg": "1",
889
754
"UMask": "0x10f",
890
755
"Unit": "UPI"
891
756
},
892
757
{
893
758
"BriefDescription": "Matches on Receive path of a UPI Port : Request",
759
+
"Counter": "0,1,2,3",
894
760
"EventCode": "0x05",
895
761
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
896
762
"PerPkg": "1",
···
910
754
},
911
755
{
912
756
"BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
757
+
"Counter": "0,1,2,3",
913
758
"EventCode": "0x05",
914
759
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
760
+
"Experimental": "1",
915
761
"PerPkg": "1",
916
762
"UMask": "0x108",
917
763
"Unit": "UPI"
918
764
},
919
765
{
920
766
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
767
+
"Counter": "0,1,2,3",
921
768
"EventCode": "0x05",
922
769
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
770
+
"Experimental": "1",
923
771
"PerPkg": "1",
924
772
"UMask": "0x1aa",
925
773
"Unit": "UPI"
926
774
},
927
775
{
928
776
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
777
+
"Counter": "0,1,2,3",
929
778
"EventCode": "0x05",
930
779
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
780
+
"Experimental": "1",
931
781
"PerPkg": "1",
932
782
"UMask": "0x12a",
933
783
"Unit": "UPI"
934
784
},
935
785
{
936
786
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
787
+
"Counter": "0,1,2,3",
937
788
"EventCode": "0x05",
938
789
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
790
+
"Experimental": "1",
939
791
"PerPkg": "1",
940
792
"UMask": "0xc",
941
793
"Unit": "UPI"
942
794
},
943
795
{
944
796
"BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
797
+
"Counter": "0,1,2,3",
945
798
"EventCode": "0x05",
946
799
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
800
+
"Experimental": "1",
947
801
"PerPkg": "1",
948
802
"UMask": "0x10c",
949
803
"Unit": "UPI"
950
804
},
951
805
{
952
806
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
807
+
"Counter": "0,1,2,3",
953
808
"EventCode": "0x05",
954
809
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
810
+
"Experimental": "1",
955
811
"PerPkg": "1",
956
812
"UMask": "0xa",
957
813
"Unit": "UPI"
958
814
},
959
815
{
960
816
"BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
817
+
"Counter": "0,1,2,3",
961
818
"EventCode": "0x05",
962
819
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
820
+
"Experimental": "1",
963
821
"PerPkg": "1",
964
822
"UMask": "0x10a",
965
823
"Unit": "UPI"
966
824
},
967
825
{
968
826
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
827
+
"Counter": "0,1,2,3",
969
828
"EventCode": "0x05",
970
829
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
830
+
"Experimental": "1",
971
831
"PerPkg": "1",
972
832
"UMask": "0x9",
973
833
"Unit": "UPI"
974
834
},
975
835
{
976
836
"BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
837
+
"Counter": "0,1,2,3",
977
838
"EventCode": "0x05",
978
839
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
840
+
"Experimental": "1",
979
841
"PerPkg": "1",
980
842
"UMask": "0x109",
981
843
"Unit": "UPI"
982
844
},
983
845
{
984
846
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
847
+
"Counter": "0,1,2,3",
985
848
"EventCode": "0x05",
986
849
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
987
850
"PerPkg": "1",
···
1009
834
},
1010
835
{
1011
836
"BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
837
+
"Counter": "0,1,2,3",
1012
838
"EventCode": "0x05",
1013
839
"EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
840
+
"Experimental": "1",
1014
841
"PerPkg": "1",
1015
842
"UMask": "0x10d",
1016
843
"Unit": "UPI"
1017
844
},
1018
845
{
1019
846
"BriefDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
847
+
"Counter": "0,1,2,3",
1020
848
"EventCode": "0x03",
1021
849
"EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
1022
850
"PerPkg": "1",
···
1028
850
},
1029
851
{
1030
852
"BriefDescription": "Null FLITs received from any slot",
853
+
"Counter": "0,1,2,3",
1031
854
"EventCode": "0x03",
1032
855
"EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
856
+
"Experimental": "1",
1033
857
"PerPkg": "1",
1034
858
"PublicDescription": "Valid Flits Received : Null FLITs received from any slot",
1035
859
"UMask": "0x27",
···
1039
859
},
1040
860
{
1041
861
"BriefDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
862
+
"Counter": "0,1,2,3",
1042
863
"EventCode": "0x03",
1043
864
"EventName": "UNC_UPI_RxL_FLITS.DATA",
865
+
"Experimental": "1",
1044
866
"PerPkg": "1",
1045
867
"UMask": "0x8",
1046
868
"Unit": "UPI"
1047
869
},
1048
870
{
1049
871
"BriefDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).",
872
+
"Counter": "0,1,2,3",
1050
873
"EventCode": "0x03",
1051
874
"EventName": "UNC_UPI_RxL_FLITS.IDLE",
875
+
"Experimental": "1",
1052
876
"PerPkg": "1",
1053
877
"UMask": "0x47",
1054
878
"Unit": "UPI"
1055
879
},
1056
880
{
1057
881
"BriefDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
882
+
"Counter": "0,1,2,3",
1058
883
"EventCode": "0x03",
1059
884
"EventName": "UNC_UPI_RxL_FLITS.LLCRD",
885
+
"Experimental": "1",
1060
886
"PerPkg": "1",
1061
887
"UMask": "0x10",
1062
888
"Unit": "UPI"
1063
889
},
1064
890
{
1065
891
"BriefDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
892
+
"Counter": "0,1,2,3",
1066
893
"EventCode": "0x03",
1067
894
"EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
895
+
"Experimental": "1",
1068
896
"PerPkg": "1",
1069
897
"UMask": "0x40",
1070
898
"Unit": "UPI"
1071
899
},
1072
900
{
1073
901
"BriefDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
902
+
"Counter": "0,1,2,3",
1074
903
"EventCode": "0x03",
1075
904
"EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
1076
905
"PerPkg": "1",
···
1088
899
},
1089
900
{
1090
901
"BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
902
+
"Counter": "0,1,2,3",
1091
903
"EventCode": "0x03",
1092
904
"EventName": "UNC_UPI_RxL_FLITS.NULL",
905
+
"Experimental": "1",
1093
906
"PerPkg": "1",
1094
907
"UMask": "0x20",
1095
908
"Unit": "UPI"
1096
909
},
1097
910
{
1098
911
"BriefDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
912
+
"Counter": "0,1,2,3",
1099
913
"EventCode": "0x03",
1100
914
"EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
915
+
"Experimental": "1",
1101
916
"PerPkg": "1",
1102
917
"UMask": "0x80",
1103
918
"Unit": "UPI"
1104
919
},
1105
920
{
1106
921
"BriefDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
922
+
"Counter": "0,1,2,3",
1107
923
"EventCode": "0x03",
1108
924
"EventName": "UNC_UPI_RxL_FLITS.SLOT0",
925
+
"Experimental": "1",
1109
926
"PerPkg": "1",
1110
927
"UMask": "0x1",
1111
928
"Unit": "UPI"
1112
929
},
1113
930
{
1114
931
"BriefDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
932
+
"Counter": "0,1,2,3",
1115
933
"EventCode": "0x03",
1116
934
"EventName": "UNC_UPI_RxL_FLITS.SLOT1",
935
+
"Experimental": "1",
1117
936
"PerPkg": "1",
1118
937
"UMask": "0x2",
1119
938
"Unit": "UPI"
1120
939
},
1121
940
{
1122
941
"BriefDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
942
+
"Counter": "0,1,2,3",
1123
943
"EventCode": "0x03",
1124
944
"EventName": "UNC_UPI_RxL_FLITS.SLOT2",
945
+
"Experimental": "1",
1125
946
"PerPkg": "1",
1126
947
"UMask": "0x4",
1127
948
"Unit": "UPI"
1128
949
},
1129
950
{
1130
951
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
952
+
"Counter": "0,1,2,3",
1131
953
"EventCode": "0x30",
1132
954
"EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
955
+
"Experimental": "1",
1133
956
"PerPkg": "1",
1134
957
"UMask": "0x1",
1135
958
"Unit": "UPI"
1136
959
},
1137
960
{
1138
961
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
962
+
"Counter": "0,1,2,3",
1139
963
"EventCode": "0x30",
1140
964
"EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
965
+
"Experimental": "1",
1141
966
"PerPkg": "1",
1142
967
"UMask": "0x2",
1143
968
"Unit": "UPI"
1144
969
},
1145
970
{
1146
971
"BriefDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
972
+
"Counter": "0,1,2,3",
1147
973
"EventCode": "0x30",
1148
974
"EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
975
+
"Experimental": "1",
1149
976
"PerPkg": "1",
1150
977
"UMask": "0x4",
1151
978
"Unit": "UPI"
1152
979
},
1153
980
{
1154
981
"BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
982
+
"Counter": "0,1,2,3",
1155
983
"EventCode": "0x32",
1156
984
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
985
+
"Experimental": "1",
1157
986
"PerPkg": "1",
1158
987
"UMask": "0x1",
1159
988
"Unit": "UPI"
1160
989
},
1161
990
{
1162
991
"BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
992
+
"Counter": "0,1,2,3",
1163
993
"EventCode": "0x32",
1164
994
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
995
+
"Experimental": "1",
1165
996
"PerPkg": "1",
1166
997
"UMask": "0x2",
1167
998
"Unit": "UPI"
1168
999
},
1169
1000
{
1170
1001
"BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
1002
+
"Counter": "0,1,2,3",
1171
1003
"EventCode": "0x32",
1172
1004
"EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
1005
+
"Experimental": "1",
1173
1006
"PerPkg": "1",
1174
1007
"UMask": "0x4",
1175
1008
"Unit": "UPI"
1176
1009
},
1177
1010
{
1178
1011
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
1012
+
"Counter": "0,1,2,3",
1179
1013
"EventCode": "0x04",
1180
1014
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
1015
+
"Experimental": "1",
1181
1016
"PerPkg": "1",
1182
1017
"UMask": "0xe",
1183
1018
"Unit": "UPI"
1184
1019
},
1185
1020
{
1186
1021
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
1022
+
"Counter": "0,1,2,3",
1187
1023
"EventCode": "0x04",
1188
1024
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
1025
+
"Experimental": "1",
1189
1026
"PerPkg": "1",
1190
1027
"UMask": "0x10e",
1191
1028
"Unit": "UPI"
1192
1029
},
1193
1030
{
1194
1031
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
1032
+
"Counter": "0,1,2,3",
1195
1033
"EventCode": "0x04",
1196
1034
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
1035
+
"Experimental": "1",
1197
1036
"PerPkg": "1",
1198
1037
"UMask": "0xf",
1199
1038
"Unit": "UPI"
1200
1039
},
1201
1040
{
1202
1041
"BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
1042
+
"Counter": "0,1,2,3",
1203
1043
"EventCode": "0x04",
1204
1044
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
1045
+
"Experimental": "1",
1205
1046
"PerPkg": "1",
1206
1047
"UMask": "0x10f",
1207
1048
"Unit": "UPI"
1208
1049
},
1209
1050
{
1210
1051
"BriefDescription": "Matches on Transmit path of a UPI Port : Request",
1052
+
"Counter": "0,1,2,3",
1211
1053
"EventCode": "0x04",
1212
1054
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
1055
+
"Experimental": "1",
1213
1056
"PerPkg": "1",
1214
1057
"UMask": "0x8",
1215
1058
"Unit": "UPI"
1216
1059
},
1217
1060
{
1218
1061
"BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
1062
+
"Counter": "0,1,2,3",
1219
1063
"EventCode": "0x04",
1220
1064
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
1065
+
"Experimental": "1",
1221
1066
"PerPkg": "1",
1222
1067
"UMask": "0x108",
1223
1068
"Unit": "UPI"
1224
1069
},
1225
1070
{
1226
1071
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
1072
+
"Counter": "0,1,2,3",
1227
1073
"EventCode": "0x04",
1228
1074
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
1075
+
"Experimental": "1",
1229
1076
"PerPkg": "1",
1230
1077
"UMask": "0x1aa",
1231
1078
"Unit": "UPI"
1232
1079
},
1233
1080
{
1234
1081
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
1082
+
"Counter": "0,1,2,3",
1235
1083
"EventCode": "0x04",
1236
1084
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
1085
+
"Experimental": "1",
1237
1086
"PerPkg": "1",
1238
1087
"UMask": "0x12a",
1239
1088
"Unit": "UPI"
1240
1089
},
1241
1090
{
1242
1091
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
1092
+
"Counter": "0,1,2,3",
1243
1093
"EventCode": "0x04",
1244
1094
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
1095
+
"Experimental": "1",
1245
1096
"PerPkg": "1",
1246
1097
"UMask": "0xc",
1247
1098
"Unit": "UPI"
1248
1099
},
1249
1100
{
1250
1101
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
1102
+
"Counter": "0,1,2,3",
1251
1103
"EventCode": "0x04",
1252
1104
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
1105
+
"Experimental": "1",
1253
1106
"PerPkg": "1",
1254
1107
"UMask": "0x10c",
1255
1108
"Unit": "UPI"
1256
1109
},
1257
1110
{
1258
1111
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
1112
+
"Counter": "0,1,2,3",
1259
1113
"EventCode": "0x04",
1260
1114
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
1115
+
"Experimental": "1",
1261
1116
"PerPkg": "1",
1262
1117
"UMask": "0xa",
1263
1118
"Unit": "UPI"
1264
1119
},
1265
1120
{
1266
1121
"BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
1122
+
"Counter": "0,1,2,3",
1267
1123
"EventCode": "0x04",
1268
1124
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
1125
+
"Experimental": "1",
1269
1126
"PerPkg": "1",
1270
1127
"UMask": "0x10a",
1271
1128
"Unit": "UPI"
1272
1129
},
1273
1130
{
1274
1131
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
1132
+
"Counter": "0,1,2,3",
1275
1133
"EventCode": "0x04",
1276
1134
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
1135
+
"Experimental": "1",
1277
1136
"PerPkg": "1",
1278
1137
"UMask": "0x9",
1279
1138
"Unit": "UPI"
1280
1139
},
1281
1140
{
1282
1141
"BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
1142
+
"Counter": "0,1,2,3",
1283
1143
"EventCode": "0x04",
1284
1144
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
1145
+
"Experimental": "1",
1285
1146
"PerPkg": "1",
1286
1147
"UMask": "0x109",
1287
1148
"Unit": "UPI"
1288
1149
},
1289
1150
{
1290
1151
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
1152
+
"Counter": "0,1,2,3",
1291
1153
"EventCode": "0x04",
1292
1154
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
1155
+
"Experimental": "1",
1293
1156
"PerPkg": "1",
1294
1157
"UMask": "0xd",
1295
1158
"Unit": "UPI"
1296
1159
},
1297
1160
{
1298
1161
"BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
1162
+
"Counter": "0,1,2,3",
1299
1163
"EventCode": "0x04",
1300
1164
"EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
1165
+
"Experimental": "1",
1301
1166
"PerPkg": "1",
1302
1167
"UMask": "0x10d",
1303
1168
"Unit": "UPI"
1304
1169
},
1305
1170
{
1306
1171
"BriefDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.",
1172
+
"Counter": "0,1,2,3",
1307
1173
"EventCode": "0x02",
1308
1174
"EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
1309
1175
"PerPkg": "1",
···
1367
1123
},
1368
1124
{
1369
1125
"BriefDescription": "All Null Flits",
1126
+
"Counter": "0,1,2,3",
1370
1127
"EventCode": "0x02",
1371
1128
"EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
1372
1129
"PerPkg": "1",
···
1377
1132
},
1378
1133
{
1379
1134
"BriefDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
1135
+
"Counter": "0,1,2,3",
1380
1136
"EventCode": "0x02",
1381
1137
"EventName": "UNC_UPI_TxL_FLITS.DATA",
1138
+
"Experimental": "1",
1382
1139
"PerPkg": "1",
1383
1140
"UMask": "0x8",
1384
1141
"Unit": "UPI"
1385
1142
},
1386
1143
{
1387
1144
"BriefDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
1145
+
"Counter": "0,1,2,3",
1388
1146
"EventCode": "0x02",
1389
1147
"EventName": "UNC_UPI_TxL_FLITS.IDLE",
1390
1148
"PerPkg": "1",
···
1396
1148
},
1397
1149
{
1398
1150
"BriefDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
1151
+
"Counter": "0,1,2,3",
1399
1152
"EventCode": "0x02",
1400
1153
"EventName": "UNC_UPI_TxL_FLITS.LLCRD",
1154
+
"Experimental": "1",
1401
1155
"PerPkg": "1",
1402
1156
"UMask": "0x10",
1403
1157
"Unit": "UPI"
1404
1158
},
1405
1159
{
1406
1160
"BriefDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
1161
+
"Counter": "0,1,2,3",
1407
1162
"EventCode": "0x02",
1408
1163
"EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
1164
+
"Experimental": "1",
1409
1165
"PerPkg": "1",
1410
1166
"UMask": "0x40",
1411
1167
"Unit": "UPI"
1412
1168
},
1413
1169
{
1414
1170
"BriefDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
1171
+
"Counter": "0,1,2,3",
1415
1172
"EventCode": "0x02",
1416
1173
"EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
1417
1174
"PerPkg": "1",
···
1426
1173
},
1427
1174
{
1428
1175
"BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
1176
+
"Counter": "0,1,2,3",
1429
1177
"EventCode": "0x02",
1430
1178
"EventName": "UNC_UPI_TxL_FLITS.NULL",
1179
+
"Experimental": "1",
1431
1180
"PerPkg": "1",
1432
1181
"UMask": "0x20",
1433
1182
"Unit": "UPI"
1434
1183
},
1435
1184
{
1436
1185
"BriefDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
1186
+
"Counter": "0,1,2,3",
1437
1187
"EventCode": "0x02",
1438
1188
"EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
1189
+
"Experimental": "1",
1439
1190
"PerPkg": "1",
1440
1191
"UMask": "0x80",
1441
1192
"Unit": "UPI"
1442
1193
},
1443
1194
{
1444
1195
"BriefDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
1196
+
"Counter": "0,1,2,3",
1445
1197
"EventCode": "0x02",
1446
1198
"EventName": "UNC_UPI_TxL_FLITS.SLOT0",
1199
+
"Experimental": "1",
1447
1200
"PerPkg": "1",
1448
1201
"UMask": "0x1",
1449
1202
"Unit": "UPI"
1450
1203
},
1451
1204
{
1452
1205
"BriefDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
1206
+
"Counter": "0,1,2,3",
1453
1207
"EventCode": "0x02",
1454
1208
"EventName": "UNC_UPI_TxL_FLITS.SLOT1",
1209
+
"Experimental": "1",
1455
1210
"PerPkg": "1",
1456
1211
"UMask": "0x2",
1457
1212
"Unit": "UPI"
1458
1213
},
1459
1214
{
1460
1215
"BriefDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
1216
+
"Counter": "0,1,2,3",
1461
1217
"EventCode": "0x02",
1462
1218
"EventName": "UNC_UPI_TxL_FLITS.SLOT2",
1219
+
"Experimental": "1",
1463
1220
"PerPkg": "1",
1464
1221
"UMask": "0x4",
1465
1222
"Unit": "UPI"
1466
1223
},
1467
1224
{
1468
1225
"BriefDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
1226
+
"Counter": "0,1,2,3",
1469
1227
"EventCode": "0x40",
1470
1228
"EventName": "UNC_UPI_TxL_INSERTS",
1229
+
"Experimental": "1",
1471
1230
"PerPkg": "1",
1472
1231
"Unit": "UPI"
1473
1232
},
1474
1233
{
1475
1234
"BriefDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
1235
+
"Counter": "0,1,2,3",
1476
1236
"EventCode": "0x42",
1477
1237
"EventName": "UNC_UPI_TxL_OCCUPANCY",
1238
+
"Experimental": "1",
1478
1239
"PerPkg": "1",
1479
1240
"Unit": "UPI"
1480
1241
}
+267
tools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json
+267
tools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "IIO Clockticks",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x01",
5
6
"EventName": "UNC_IIO_CLOCKTICKS",
6
7
"PerPkg": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0xC2",
14
14
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
15
+
"Experimental": "1",
15
16
"FCMask": "0x07",
16
17
"PerPkg": "1",
17
18
"PortMask": "0x0FF",
···
22
19
},
23
20
{
24
21
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
22
+
"Counter": "0,1,2,3",
25
23
"EventCode": "0xC2",
26
24
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
25
+
"Experimental": "1",
27
26
"FCMask": "0x07",
28
27
"PerPkg": "1",
29
28
"PortMask": "0x001",
···
34
29
},
35
30
{
36
31
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
32
+
"Counter": "0,1,2,3",
37
33
"EventCode": "0xC2",
38
34
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
35
+
"Experimental": "1",
39
36
"FCMask": "0x07",
40
37
"PerPkg": "1",
41
38
"PortMask": "0x002",
···
46
39
},
47
40
{
48
41
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
42
+
"Counter": "0,1,2,3",
49
43
"EventCode": "0xC2",
50
44
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
45
+
"Experimental": "1",
51
46
"FCMask": "0x07",
52
47
"PerPkg": "1",
53
48
"PortMask": "0x004",
···
58
49
},
59
50
{
60
51
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
52
+
"Counter": "0,1,2,3",
61
53
"EventCode": "0xC2",
62
54
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
55
+
"Experimental": "1",
63
56
"FCMask": "0x07",
64
57
"PerPkg": "1",
65
58
"PortMask": "0x008",
···
70
59
},
71
60
{
72
61
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
62
+
"Counter": "0,1,2,3",
73
63
"EventCode": "0xC2",
74
64
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
65
+
"Experimental": "1",
75
66
"FCMask": "0x07",
76
67
"PerPkg": "1",
77
68
"PortMask": "0x010",
···
82
69
},
83
70
{
84
71
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
72
+
"Counter": "0,1,2,3",
85
73
"EventCode": "0xC2",
86
74
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
75
+
"Experimental": "1",
87
76
"FCMask": "0x07",
88
77
"PerPkg": "1",
89
78
"PortMask": "0x020",
···
94
79
},
95
80
{
96
81
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
82
+
"Counter": "0,1,2,3",
97
83
"EventCode": "0xC2",
98
84
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
85
+
"Experimental": "1",
99
86
"FCMask": "0x07",
100
87
"PerPkg": "1",
101
88
"PortMask": "0x040",
···
106
89
},
107
90
{
108
91
"BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
92
+
"Counter": "0,1,2,3",
109
93
"EventCode": "0xC2",
110
94
"EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
95
+
"Experimental": "1",
111
96
"FCMask": "0x07",
112
97
"PerPkg": "1",
113
98
"PortMask": "0x080",
···
118
99
},
119
100
{
120
101
"BriefDescription": "Count of allocations in the completion buffer",
102
+
"Counter": "2,3",
121
103
"EventCode": "0xD5",
122
104
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
105
+
"Experimental": "1",
123
106
"FCMask": "0x07",
124
107
"PerPkg": "1",
125
108
"PortMask": "0x0FF",
···
130
109
},
131
110
{
132
111
"BriefDescription": "Count of allocations in the completion buffer",
112
+
"Counter": "2,3",
133
113
"EventCode": "0xD5",
134
114
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
115
+
"Experimental": "1",
135
116
"FCMask": "0x07",
136
117
"PerPkg": "1",
137
118
"PortMask": "0x001",
···
142
119
},
143
120
{
144
121
"BriefDescription": "Count of allocations in the completion buffer",
122
+
"Counter": "2,3",
145
123
"EventCode": "0xD5",
146
124
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
125
+
"Experimental": "1",
147
126
"FCMask": "0x07",
148
127
"PerPkg": "1",
149
128
"PortMask": "0x002",
···
154
129
},
155
130
{
156
131
"BriefDescription": "Count of allocations in the completion buffer",
132
+
"Counter": "2,3",
157
133
"EventCode": "0xD5",
158
134
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
135
+
"Experimental": "1",
159
136
"FCMask": "0x07",
160
137
"PerPkg": "1",
161
138
"PortMask": "0x004",
···
166
139
},
167
140
{
168
141
"BriefDescription": "Count of allocations in the completion buffer",
142
+
"Counter": "2,3",
169
143
"EventCode": "0xD5",
170
144
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
145
+
"Experimental": "1",
171
146
"FCMask": "0x07",
172
147
"PerPkg": "1",
173
148
"PortMask": "0x008",
···
178
149
},
179
150
{
180
151
"BriefDescription": "Count of allocations in the completion buffer",
152
+
"Counter": "2,3",
181
153
"EventCode": "0xD5",
182
154
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
155
+
"Experimental": "1",
183
156
"FCMask": "0x07",
184
157
"PerPkg": "1",
185
158
"PortMask": "0x010",
···
190
159
},
191
160
{
192
161
"BriefDescription": "Count of allocations in the completion buffer",
162
+
"Counter": "2,3",
193
163
"EventCode": "0xD5",
194
164
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
165
+
"Experimental": "1",
195
166
"FCMask": "0x07",
196
167
"PerPkg": "1",
197
168
"PortMask": "0x020",
···
202
169
},
203
170
{
204
171
"BriefDescription": "Count of allocations in the completion buffer",
172
+
"Counter": "2,3",
205
173
"EventCode": "0xD5",
206
174
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
175
+
"Experimental": "1",
207
176
"FCMask": "0x07",
208
177
"PerPkg": "1",
209
178
"PortMask": "0x040",
···
214
179
},
215
180
{
216
181
"BriefDescription": "Count of allocations in the completion buffer",
182
+
"Counter": "2,3",
217
183
"EventCode": "0xD5",
218
184
"EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
185
+
"Experimental": "1",
219
186
"FCMask": "0x07",
220
187
"PerPkg": "1",
221
188
"PortMask": "0x080",
···
226
189
},
227
190
{
228
191
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
192
+
"Counter": "2,3",
229
193
"EventCode": "0xC0",
230
194
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS",
195
+
"Experimental": "1",
231
196
"FCMask": "0x07",
232
197
"PerPkg": "1",
233
198
"PortMask": "0x0FF",
···
238
199
},
239
200
{
240
201
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
202
+
"Counter": "2,3",
241
203
"EventCode": "0xC0",
242
204
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
205
+
"Experimental": "1",
243
206
"FCMask": "0x07",
244
207
"PerPkg": "1",
245
208
"PortMask": "0x001",
···
250
209
},
251
210
{
252
211
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
212
+
"Counter": "2,3",
253
213
"EventCode": "0xC0",
254
214
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
215
+
"Experimental": "1",
255
216
"FCMask": "0x07",
256
217
"PerPkg": "1",
257
218
"PortMask": "0x002",
···
262
219
},
263
220
{
264
221
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
222
+
"Counter": "2,3",
265
223
"EventCode": "0xC0",
266
224
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
225
+
"Experimental": "1",
267
226
"FCMask": "0x07",
268
227
"PerPkg": "1",
269
228
"PortMask": "0x004",
···
274
229
},
275
230
{
276
231
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
232
+
"Counter": "2,3",
277
233
"EventCode": "0xC0",
278
234
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
235
+
"Experimental": "1",
279
236
"FCMask": "0x07",
280
237
"PerPkg": "1",
281
238
"PortMask": "0x008",
···
286
239
},
287
240
{
288
241
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
242
+
"Counter": "2,3",
289
243
"EventCode": "0xC0",
290
244
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
245
+
"Experimental": "1",
291
246
"FCMask": "0x07",
292
247
"PerPkg": "1",
293
248
"PortMask": "0x010",
···
298
249
},
299
250
{
300
251
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
252
+
"Counter": "2,3",
301
253
"EventCode": "0xC0",
302
254
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
255
+
"Experimental": "1",
303
256
"FCMask": "0x07",
304
257
"PerPkg": "1",
305
258
"PortMask": "0x020",
···
310
259
},
311
260
{
312
261
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
262
+
"Counter": "2,3",
313
263
"EventCode": "0xC0",
314
264
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
265
+
"Experimental": "1",
315
266
"FCMask": "0x07",
316
267
"PerPkg": "1",
317
268
"PortMask": "0x040",
···
322
269
},
323
270
{
324
271
"BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
272
+
"Counter": "2,3",
325
273
"EventCode": "0xC0",
326
274
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
275
+
"Experimental": "1",
327
276
"FCMask": "0x07",
328
277
"PerPkg": "1",
329
278
"PortMask": "0x080",
···
334
279
},
335
280
{
336
281
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
282
+
"Counter": "2,3",
337
283
"EventCode": "0xC0",
338
284
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",
285
+
"Experimental": "1",
339
286
"FCMask": "0x07",
340
287
"PerPkg": "1",
341
288
"PortMask": "0x0FF",
···
346
289
},
347
290
{
348
291
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
292
+
"Counter": "2,3",
349
293
"EventCode": "0xC0",
350
294
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
351
295
"FCMask": "0x07",
···
357
299
},
358
300
{
359
301
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
302
+
"Counter": "2,3",
360
303
"EventCode": "0xC0",
361
304
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
362
305
"FCMask": "0x07",
···
368
309
},
369
310
{
370
311
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
312
+
"Counter": "2,3",
371
313
"EventCode": "0xC0",
372
314
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
373
315
"FCMask": "0x07",
···
379
319
},
380
320
{
381
321
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
322
+
"Counter": "2,3",
382
323
"EventCode": "0xC0",
383
324
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
384
325
"FCMask": "0x07",
···
390
329
},
391
330
{
392
331
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
332
+
"Counter": "2,3",
393
333
"EventCode": "0xC0",
394
334
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
395
335
"FCMask": "0x07",
···
401
339
},
402
340
{
403
341
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
342
+
"Counter": "2,3",
404
343
"EventCode": "0xC0",
405
344
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
406
345
"FCMask": "0x07",
···
412
349
},
413
350
{
414
351
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
352
+
"Counter": "2,3",
415
353
"EventCode": "0xC0",
416
354
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
417
355
"FCMask": "0x07",
···
423
359
},
424
360
{
425
361
"BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
362
+
"Counter": "2,3",
426
363
"EventCode": "0xC0",
427
364
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
428
365
"FCMask": "0x07",
···
434
369
},
435
370
{
436
371
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
372
+
"Counter": "2,3",
437
373
"EventCode": "0xC0",
438
374
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS",
439
375
"FCMask": "0x07",
···
445
379
},
446
380
{
447
381
"BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
382
+
"Counter": "2,3",
448
383
"EventCode": "0xC0",
449
384
"EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS",
450
385
"FCMask": "0x07",
···
456
389
},
457
390
{
458
391
"BriefDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.",
392
+
"Counter": "0,1",
459
393
"EventCode": "0x83",
460
394
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS",
461
395
"FCMask": "0x07",
···
467
399
},
468
400
{
469
401
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
402
+
"Counter": "0,1",
470
403
"EventCode": "0x83",
471
404
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
472
405
"FCMask": "0x07",
···
478
409
},
479
410
{
480
411
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
412
+
"Counter": "0,1",
481
413
"EventCode": "0x83",
482
414
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
483
415
"FCMask": "0x07",
···
489
419
},
490
420
{
491
421
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
422
+
"Counter": "0,1",
492
423
"EventCode": "0x83",
493
424
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
494
425
"FCMask": "0x07",
···
500
429
},
501
430
{
502
431
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
432
+
"Counter": "0,1",
503
433
"EventCode": "0x83",
504
434
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
505
435
"FCMask": "0x07",
···
511
439
},
512
440
{
513
441
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
442
+
"Counter": "0,1",
514
443
"EventCode": "0x83",
515
444
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
516
445
"FCMask": "0x07",
···
522
449
},
523
450
{
524
451
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
452
+
"Counter": "0,1",
525
453
"EventCode": "0x83",
526
454
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
527
455
"FCMask": "0x07",
···
533
459
},
534
460
{
535
461
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
462
+
"Counter": "0,1",
536
463
"EventCode": "0x83",
537
464
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
538
465
"FCMask": "0x07",
···
544
469
},
545
470
{
546
471
"BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
472
+
"Counter": "0,1",
547
473
"EventCode": "0x83",
548
474
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
549
475
"FCMask": "0x07",
···
555
479
},
556
480
{
557
481
"BriefDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.",
482
+
"Counter": "0,1",
558
483
"EventCode": "0x83",
559
484
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS",
560
485
"FCMask": "0x07",
···
566
489
},
567
490
{
568
491
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
492
+
"Counter": "0,1",
569
493
"EventCode": "0x83",
570
494
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
571
495
"FCMask": "0x07",
···
577
499
},
578
500
{
579
501
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
502
+
"Counter": "0,1",
580
503
"EventCode": "0x83",
581
504
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
582
505
"FCMask": "0x07",
···
588
509
},
589
510
{
590
511
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
512
+
"Counter": "0,1",
591
513
"EventCode": "0x83",
592
514
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
593
515
"FCMask": "0x07",
···
599
519
},
600
520
{
601
521
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
522
+
"Counter": "0,1",
602
523
"EventCode": "0x83",
603
524
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
604
525
"FCMask": "0x07",
···
610
529
},
611
530
{
612
531
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
532
+
"Counter": "0,1",
613
533
"EventCode": "0x83",
614
534
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
615
535
"FCMask": "0x07",
···
621
539
},
622
540
{
623
541
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
542
+
"Counter": "0,1",
624
543
"EventCode": "0x83",
625
544
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
626
545
"FCMask": "0x07",
···
632
549
},
633
550
{
634
551
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
552
+
"Counter": "0,1",
635
553
"EventCode": "0x83",
636
554
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
637
555
"FCMask": "0x07",
···
643
559
},
644
560
{
645
561
"BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
562
+
"Counter": "0,1",
646
563
"EventCode": "0x83",
647
564
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
648
565
"FCMask": "0x07",
···
654
569
},
655
570
{
656
571
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
572
+
"Counter": "0,1",
657
573
"EventCode": "0x83",
658
574
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
575
+
"Experimental": "1",
659
576
"FCMask": "0x07",
660
577
"PerPkg": "1",
661
578
"PortMask": "0x001",
···
666
579
},
667
580
{
668
581
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
582
+
"Counter": "0,1",
669
583
"EventCode": "0x83",
670
584
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
585
+
"Experimental": "1",
671
586
"FCMask": "0x07",
672
587
"PerPkg": "1",
673
588
"PortMask": "0x002",
···
678
589
},
679
590
{
680
591
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
592
+
"Counter": "0,1",
681
593
"EventCode": "0x83",
682
594
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
595
+
"Experimental": "1",
683
596
"FCMask": "0x07",
684
597
"PerPkg": "1",
685
598
"PortMask": "0x004",
···
690
599
},
691
600
{
692
601
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
602
+
"Counter": "0,1",
693
603
"EventCode": "0x83",
694
604
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
605
+
"Experimental": "1",
695
606
"FCMask": "0x07",
696
607
"PerPkg": "1",
697
608
"PortMask": "0x008",
···
702
609
},
703
610
{
704
611
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
612
+
"Counter": "0,1",
705
613
"EventCode": "0x83",
706
614
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
615
+
"Experimental": "1",
707
616
"FCMask": "0x07",
708
617
"PerPkg": "1",
709
618
"PortMask": "0x010",
···
714
619
},
715
620
{
716
621
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
622
+
"Counter": "0,1",
717
623
"EventCode": "0x83",
718
624
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
625
+
"Experimental": "1",
719
626
"FCMask": "0x07",
720
627
"PerPkg": "1",
721
628
"PortMask": "0x020",
···
726
629
},
727
630
{
728
631
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
632
+
"Counter": "0,1",
729
633
"EventCode": "0x83",
730
634
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
635
+
"Experimental": "1",
731
636
"FCMask": "0x07",
732
637
"PerPkg": "1",
733
638
"PortMask": "0x040",
···
738
639
},
739
640
{
740
641
"BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
642
+
"Counter": "0,1",
741
643
"EventCode": "0x83",
742
644
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
645
+
"Experimental": "1",
743
646
"FCMask": "0x07",
744
647
"PerPkg": "1",
745
648
"PortMask": "0x080",
···
750
649
},
751
650
{
752
651
"BriefDescription": "Counts once for every 4 bytes written from this card to a peer device's IO space.",
652
+
"Counter": "0,1",
753
653
"EventCode": "0x83",
754
654
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.ALL_PARTS",
655
+
"Experimental": "1",
755
656
"FCMask": "0x07",
756
657
"PerPkg": "1",
757
658
"PortMask": "0x0FF",
···
762
659
},
763
660
{
764
661
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
662
+
"Counter": "0,1",
765
663
"EventCode": "0x83",
766
664
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
665
+
"Experimental": "1",
767
666
"FCMask": "0x07",
768
667
"PerPkg": "1",
769
668
"PortMask": "0x001",
···
774
669
},
775
670
{
776
671
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
672
+
"Counter": "0,1",
777
673
"EventCode": "0x83",
778
674
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
675
+
"Experimental": "1",
779
676
"FCMask": "0x07",
780
677
"PerPkg": "1",
781
678
"PortMask": "0x002",
···
786
679
},
787
680
{
788
681
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
682
+
"Counter": "0,1",
789
683
"EventCode": "0x83",
790
684
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
685
+
"Experimental": "1",
791
686
"FCMask": "0x07",
792
687
"PerPkg": "1",
793
688
"PortMask": "0x004",
···
798
689
},
799
690
{
800
691
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
692
+
"Counter": "0,1",
801
693
"EventCode": "0x83",
802
694
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
695
+
"Experimental": "1",
803
696
"FCMask": "0x07",
804
697
"PerPkg": "1",
805
698
"PortMask": "0x008",
···
810
699
},
811
700
{
812
701
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
702
+
"Counter": "0,1",
813
703
"EventCode": "0x83",
814
704
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
705
+
"Experimental": "1",
815
706
"FCMask": "0x07",
816
707
"PerPkg": "1",
817
708
"PortMask": "0x010",
···
822
709
},
823
710
{
824
711
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
712
+
"Counter": "0,1",
825
713
"EventCode": "0x83",
826
714
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
715
+
"Experimental": "1",
827
716
"FCMask": "0x07",
828
717
"PerPkg": "1",
829
718
"PortMask": "0x020",
···
834
719
},
835
720
{
836
721
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
722
+
"Counter": "0,1",
837
723
"EventCode": "0x83",
838
724
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
725
+
"Experimental": "1",
839
726
"FCMask": "0x07",
840
727
"PerPkg": "1",
841
728
"PortMask": "0x040",
···
846
729
},
847
730
{
848
731
"BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
732
+
"Counter": "0,1",
849
733
"EventCode": "0x83",
850
734
"EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
735
+
"Experimental": "1",
851
736
"FCMask": "0x07",
852
737
"PerPkg": "1",
853
738
"PortMask": "0x080",
···
858
739
},
859
740
{
860
741
"BriefDescription": "IOTLB Hits to a 1G Page",
742
+
"Counter": "0,1,2,3",
861
743
"EventCode": "0x40",
862
744
"EventName": "UNC_IIO_IOMMU0.1G_HITS",
745
+
"Experimental": "1",
863
746
"PerPkg": "1",
864
747
"PortMask": "0x000",
865
748
"UMask": "0x10",
···
869
748
},
870
749
{
871
750
"BriefDescription": "IOTLB Hits to a 2M Page",
751
+
"Counter": "0,1,2,3",
872
752
"EventCode": "0x40",
873
753
"EventName": "UNC_IIO_IOMMU0.2M_HITS",
754
+
"Experimental": "1",
874
755
"PerPkg": "1",
875
756
"PortMask": "0x000",
876
757
"UMask": "0x8",
···
880
757
},
881
758
{
882
759
"BriefDescription": "IOTLB Hits to a 4K Page",
760
+
"Counter": "0,1,2,3",
883
761
"EventCode": "0x40",
884
762
"EventName": "UNC_IIO_IOMMU0.4K_HITS",
763
+
"Experimental": "1",
885
764
"PerPkg": "1",
886
765
"PortMask": "0x000",
887
766
"UMask": "0x4",
···
891
766
},
892
767
{
893
768
"BriefDescription": "IOTLB lookups all",
769
+
"Counter": "0,1,2,3",
894
770
"EventCode": "0x40",
895
771
"EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
772
+
"Experimental": "1",
896
773
"PerPkg": "1",
897
774
"PortMask": "0x000",
898
775
"UMask": "0x2",
···
902
775
},
903
776
{
904
777
"BriefDescription": "Context cache hits",
778
+
"Counter": "0,1,2,3",
905
779
"EventCode": "0x40",
906
780
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
781
+
"Experimental": "1",
907
782
"PerPkg": "1",
908
783
"PortMask": "0x000",
909
784
"UMask": "0x80",
···
913
784
},
914
785
{
915
786
"BriefDescription": "Context cache lookups",
787
+
"Counter": "0,1,2,3",
916
788
"EventCode": "0x40",
917
789
"EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
790
+
"Experimental": "1",
918
791
"PerPkg": "1",
919
792
"PortMask": "0x000",
920
793
"UMask": "0x40",
···
924
793
},
925
794
{
926
795
"BriefDescription": "IOTLB lookups first",
796
+
"Counter": "0,1,2,3",
927
797
"EventCode": "0x40",
928
798
"EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
799
+
"Experimental": "1",
929
800
"PerPkg": "1",
930
801
"PortMask": "0x000",
931
802
"UMask": "0x1",
···
935
802
},
936
803
{
937
804
"BriefDescription": "IOTLB Fills (same as IOTLB miss)",
805
+
"Counter": "0,1,2,3",
938
806
"EventCode": "0x40",
939
807
"EventName": "UNC_IIO_IOMMU0.MISSES",
808
+
"Experimental": "1",
940
809
"PerPkg": "1",
941
810
"PortMask": "0x000",
942
811
"UMask": "0x20",
···
946
811
},
947
812
{
948
813
"BriefDescription": "IOMMU memory access (both low and high priority)",
814
+
"Counter": "0,1,2,3",
949
815
"EventCode": "0x41",
950
816
"EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
817
+
"Experimental": "1",
951
818
"PerPkg": "1",
952
819
"PortMask": "0x000",
953
820
"UMask": "0xc0",
···
957
820
},
958
821
{
959
822
"BriefDescription": "IOMMU high priority memory access",
823
+
"Counter": "0,1,2,3",
960
824
"EventCode": "0x41",
961
825
"EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_HIGH",
826
+
"Experimental": "1",
962
827
"PerPkg": "1",
963
828
"PortMask": "0x000",
964
829
"UMask": "0x80",
···
968
829
},
969
830
{
970
831
"BriefDescription": "IOMMU low priority memory access",
832
+
"Counter": "0,1,2,3",
971
833
"EventCode": "0x41",
972
834
"EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_LOW",
835
+
"Experimental": "1",
973
836
"PerPkg": "1",
974
837
"PortMask": "0x000",
975
838
"UMask": "0x40",
···
979
838
},
980
839
{
981
840
"BriefDescription": "Second Level Page Walk Cache Hit to a 1G page",
841
+
"Counter": "0,1,2,3",
982
842
"EventCode": "0x41",
983
843
"EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS",
844
+
"Experimental": "1",
984
845
"PerPkg": "1",
985
846
"PortMask": "0x000",
986
847
"UMask": "0x4",
···
990
847
},
991
848
{
992
849
"BriefDescription": "Second Level Page Walk Cache Hit to a 256T page",
850
+
"Counter": "0,1,2,3",
993
851
"EventCode": "0x41",
994
852
"EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS",
853
+
"Experimental": "1",
995
854
"PerPkg": "1",
996
855
"PortMask": "0x000",
997
856
"UMask": "0x10",
···
1001
856
},
1002
857
{
1003
858
"BriefDescription": "Second Level Page Walk Cache Hit to a 2M page",
859
+
"Counter": "0,1,2,3",
1004
860
"EventCode": "0x41",
1005
861
"EventName": "UNC_IIO_IOMMU1.SLPWC_2M_HITS",
862
+
"Experimental": "1",
1006
863
"PerPkg": "1",
1007
864
"PortMask": "0x000",
1008
865
"UMask": "0x2",
···
1012
865
},
1013
866
{
1014
867
"BriefDescription": "Second Level Page Walk Cache Hit to a 512G page",
868
+
"Counter": "0,1,2,3",
1015
869
"EventCode": "0x41",
1016
870
"EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS",
871
+
"Experimental": "1",
1017
872
"PerPkg": "1",
1018
873
"PortMask": "0x000",
1019
874
"UMask": "0x8",
···
1023
874
},
1024
875
{
1025
876
"BriefDescription": "Second Level Page Walk Cache fill",
877
+
"Counter": "0,1,2,3",
1026
878
"EventCode": "0x41",
1027
879
"EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_FILLS",
880
+
"Experimental": "1",
1028
881
"PerPkg": "1",
1029
882
"PortMask": "0x000",
1030
883
"UMask": "0x20",
···
1034
883
},
1035
884
{
1036
885
"BriefDescription": "Second Level Page Walk Cache lookup",
886
+
"Counter": "0,1,2,3",
1037
887
"EventCode": "0x41",
1038
888
"EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_LOOKUPS",
889
+
"Experimental": "1",
1039
890
"PerPkg": "1",
1040
891
"PortMask": "0x000",
1041
892
"UMask": "0x1",
···
1045
892
},
1046
893
{
1047
894
"BriefDescription": "Cycles PWT full",
895
+
"Counter": "0,1,2,3",
1048
896
"EventCode": "0x43",
1049
897
"EventName": "UNC_IIO_IOMMU3.CYC_PWT_FULL",
898
+
"Experimental": "1",
1050
899
"PerPkg": "1",
1051
900
"PortMask": "0x000",
1052
901
"UMask": "0x2",
···
1056
901
},
1057
902
{
1058
903
"BriefDescription": "Interrupt Entry cache hit",
904
+
"Counter": "0,1,2,3",
1059
905
"EventCode": "0x43",
1060
906
"EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
907
+
"Experimental": "1",
1061
908
"PerPkg": "1",
1062
909
"PortMask": "0x000",
1063
910
"UMask": "0x80",
···
1067
910
},
1068
911
{
1069
912
"BriefDescription": "Interrupt Entry cache lookup",
913
+
"Counter": "0,1,2,3",
1070
914
"EventCode": "0x43",
1071
915
"EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
916
+
"Experimental": "1",
1072
917
"PerPkg": "1",
1073
918
"PortMask": "0x000",
1074
919
"UMask": "0x40",
···
1078
919
},
1079
920
{
1080
921
"BriefDescription": "Context Cache invalidation events",
922
+
"Counter": "0,1,2,3",
1081
923
"EventCode": "0x43",
1082
924
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_CTXT_CACHE",
925
+
"Experimental": "1",
1083
926
"PerPkg": "1",
1084
927
"PortMask": "0x000",
1085
928
"UMask": "0x8",
···
1089
928
},
1090
929
{
1091
930
"BriefDescription": "Interrupt Entry Cache invalidation events",
931
+
"Counter": "0,1,2,3",
1092
932
"EventCode": "0x43",
1093
933
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_INT_CACHE",
934
+
"Experimental": "1",
1094
935
"PerPkg": "1",
1095
936
"PortMask": "0x000",
1096
937
"UMask": "0x20",
···
1100
937
},
1101
938
{
1102
939
"BriefDescription": "IOTLB invalidation events",
940
+
"Counter": "0,1,2,3",
1103
941
"EventCode": "0x43",
1104
942
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_IOTLB",
943
+
"Experimental": "1",
1105
944
"PerPkg": "1",
1106
945
"PortMask": "0x000",
1107
946
"UMask": "0x4",
···
1111
946
},
1112
947
{
1113
948
"BriefDescription": "PASID Cache invalidation events",
949
+
"Counter": "0,1,2,3",
1114
950
"EventCode": "0x43",
1115
951
"EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PASID_CACHE",
952
+
"Experimental": "1",
1116
953
"PerPkg": "1",
1117
954
"PortMask": "0x000",
1118
955
"UMask": "0x10",
···
1122
955
},
1123
956
{
1124
957
"BriefDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing",
958
+
"Counter": "2,3",
1125
959
"EventCode": "0xc5",
1126
960
"EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
961
+
"Experimental": "1",
1127
962
"FCMask": "0x07",
1128
963
"PerPkg": "1",
1129
964
"PortMask": "0x0FF",
···
1134
965
},
1135
966
{
1136
967
"BriefDescription": "Passing data to be written",
968
+
"Counter": "0,1,2,3",
1137
969
"EventCode": "0x88",
1138
970
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
971
+
"Experimental": "1",
1139
972
"FCMask": "0x07",
1140
973
"PerPkg": "1",
1141
974
"PortMask": "0x0FF",
···
1146
975
},
1147
976
{
1148
977
"BriefDescription": "Issuing final read or write of line",
978
+
"Counter": "0,1,2,3",
1149
979
"EventCode": "0x88",
1150
980
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
981
+
"Experimental": "1",
1151
982
"FCMask": "0x07",
1152
983
"PerPkg": "1",
1153
984
"PortMask": "0x0FF",
···
1158
985
},
1159
986
{
1160
987
"BriefDescription": "Processing response from IOMMU",
988
+
"Counter": "0,1,2,3",
1161
989
"EventCode": "0x88",
1162
990
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
991
+
"Experimental": "1",
1163
992
"FCMask": "0x07",
1164
993
"PerPkg": "1",
1165
994
"PortMask": "0x0FF",
···
1170
995
},
1171
996
{
1172
997
"BriefDescription": "Issuing to IOMMU",
998
+
"Counter": "0,1,2,3",
1173
999
"EventCode": "0x88",
1174
1000
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
1001
+
"Experimental": "1",
1175
1002
"FCMask": "0x07",
1176
1003
"PerPkg": "1",
1177
1004
"PortMask": "0x0FF",
···
1182
1005
},
1183
1006
{
1184
1007
"BriefDescription": "Request Ownership",
1008
+
"Counter": "0,1,2,3",
1185
1009
"EventCode": "0x88",
1186
1010
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
1011
+
"Experimental": "1",
1187
1012
"FCMask": "0x07",
1188
1013
"PerPkg": "1",
1189
1014
"PortMask": "0x0FF",
···
1194
1015
},
1195
1016
{
1196
1017
"BriefDescription": "Writing line",
1018
+
"Counter": "0,1,2,3",
1197
1019
"EventCode": "0x88",
1198
1020
"EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
1021
+
"Experimental": "1",
1199
1022
"FCMask": "0x07",
1200
1023
"PerPkg": "1",
1201
1024
"PortMask": "0x0FF",
···
1206
1025
},
1207
1026
{
1208
1027
"BriefDescription": "-",
1028
+
"Counter": "0,1,2,3",
1209
1029
"EventCode": "0x8e",
1210
1030
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
1031
+
"Experimental": "1",
1211
1032
"FCMask": "0x07",
1212
1033
"PerPkg": "1",
1213
1034
"PortMask": "0x0FF",
···
1218
1035
},
1219
1036
{
1220
1037
"BriefDescription": "-",
1038
+
"Counter": "0,1,2,3",
1221
1039
"EventCode": "0x8e",
1222
1040
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
1041
+
"Experimental": "1",
1223
1042
"FCMask": "0x07",
1224
1043
"PerPkg": "1",
1225
1044
"PortMask": "0x0FF",
···
1230
1045
},
1231
1046
{
1232
1047
"BriefDescription": "-",
1048
+
"Counter": "0,1,2,3",
1233
1049
"EventCode": "0x8e",
1234
1050
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
1051
+
"Experimental": "1",
1235
1052
"FCMask": "0x07",
1236
1053
"PerPkg": "1",
1237
1054
"PortMask": "0x0FF",
···
1242
1055
},
1243
1056
{
1244
1057
"BriefDescription": "-",
1058
+
"Counter": "0,1,2,3",
1245
1059
"EventCode": "0x8e",
1246
1060
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
1061
+
"Experimental": "1",
1247
1062
"FCMask": "0x07",
1248
1063
"PerPkg": "1",
1249
1064
"PortMask": "0x0FF",
···
1254
1065
},
1255
1066
{
1256
1067
"BriefDescription": "-",
1068
+
"Counter": "0,1,2,3",
1257
1069
"EventCode": "0x8e",
1258
1070
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
1071
+
"Experimental": "1",
1259
1072
"FCMask": "0x07",
1260
1073
"PerPkg": "1",
1261
1074
"PortMask": "0x0FF",
···
1266
1075
},
1267
1076
{
1268
1077
"BriefDescription": "-",
1078
+
"Counter": "0,1,2,3",
1269
1079
"EventCode": "0x8e",
1270
1080
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
1081
+
"Experimental": "1",
1271
1082
"FCMask": "0x07",
1272
1083
"PerPkg": "1",
1273
1084
"PortMask": "0x0FF",
···
1278
1085
},
1279
1086
{
1280
1087
"BriefDescription": "-",
1088
+
"Counter": "0,1,2,3",
1281
1089
"EventCode": "0x8e",
1282
1090
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
1091
+
"Experimental": "1",
1283
1092
"FCMask": "0x07",
1284
1093
"PerPkg": "1",
1285
1094
"PortMask": "0x0FF",
···
1290
1095
},
1291
1096
{
1292
1097
"BriefDescription": "-",
1098
+
"Counter": "0,1,2,3",
1293
1099
"EventCode": "0x8e",
1294
1100
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
1101
+
"Experimental": "1",
1295
1102
"FCMask": "0x07",
1296
1103
"PerPkg": "1",
1297
1104
"PortMask": "0x0FF",
···
1302
1105
},
1303
1106
{
1304
1107
"BriefDescription": "All 9 bits of Page Walk Tracker Occupancy",
1108
+
"Counter": "0,1,2,3",
1305
1109
"EventCode": "0x42",
1306
1110
"EventName": "UNC_IIO_PWT_OCCUPANCY",
1111
+
"Experimental": "1",
1307
1112
"PerPkg": "1",
1308
1113
"PortMask": "0x000",
1309
1114
"Unit": "IIO"
1310
1115
},
1311
1116
{
1312
1117
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1118
+
"Counter": "2,3",
1313
1119
"EventCode": "0xC1",
1314
1120
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS",
1315
1121
"FCMask": "0x07",
···
1323
1123
},
1324
1124
{
1325
1125
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1126
+
"Counter": "2,3",
1326
1127
"EventCode": "0xC1",
1327
1128
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
1328
1129
"FCMask": "0x07",
···
1334
1133
},
1335
1134
{
1336
1135
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1136
+
"Counter": "2,3",
1337
1137
"EventCode": "0xC1",
1338
1138
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
1339
1139
"FCMask": "0x07",
···
1345
1143
},
1346
1144
{
1347
1145
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1146
+
"Counter": "2,3",
1348
1147
"EventCode": "0xC1",
1349
1148
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
1350
1149
"FCMask": "0x07",
···
1356
1153
},
1357
1154
{
1358
1155
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1156
+
"Counter": "2,3",
1359
1157
"EventCode": "0xC1",
1360
1158
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
1361
1159
"FCMask": "0x07",
···
1367
1163
},
1368
1164
{
1369
1165
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1166
+
"Counter": "2,3",
1370
1167
"EventCode": "0xC1",
1371
1168
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
1372
1169
"FCMask": "0x07",
···
1378
1173
},
1379
1174
{
1380
1175
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1176
+
"Counter": "2,3",
1381
1177
"EventCode": "0xC1",
1382
1178
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
1383
1179
"FCMask": "0x07",
···
1389
1183
},
1390
1184
{
1391
1185
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1186
+
"Counter": "2,3",
1392
1187
"EventCode": "0xC1",
1393
1188
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
1394
1189
"FCMask": "0x07",
···
1400
1193
},
1401
1194
{
1402
1195
"BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
1196
+
"Counter": "2,3",
1403
1197
"EventCode": "0xC1",
1404
1198
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
1405
1199
"FCMask": "0x07",
···
1411
1203
},
1412
1204
{
1413
1205
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1206
+
"Counter": "2,3",
1414
1207
"EventCode": "0xC1",
1415
1208
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",
1416
1209
"FCMask": "0x07",
···
1422
1213
},
1423
1214
{
1424
1215
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1216
+
"Counter": "2,3",
1425
1217
"EventCode": "0xC1",
1426
1218
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
1427
1219
"FCMask": "0x07",
···
1433
1223
},
1434
1224
{
1435
1225
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1226
+
"Counter": "2,3",
1436
1227
"EventCode": "0xC1",
1437
1228
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
1438
1229
"FCMask": "0x07",
···
1444
1233
},
1445
1234
{
1446
1235
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1236
+
"Counter": "2,3",
1447
1237
"EventCode": "0xC1",
1448
1238
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
1449
1239
"FCMask": "0x07",
···
1455
1243
},
1456
1244
{
1457
1245
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1246
+
"Counter": "2,3",
1458
1247
"EventCode": "0xC1",
1459
1248
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
1460
1249
"FCMask": "0x07",
···
1466
1253
},
1467
1254
{
1468
1255
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1256
+
"Counter": "2,3",
1469
1257
"EventCode": "0xC1",
1470
1258
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
1471
1259
"FCMask": "0x07",
···
1477
1263
},
1478
1264
{
1479
1265
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1266
+
"Counter": "2,3",
1480
1267
"EventCode": "0xC1",
1481
1268
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
1482
1269
"FCMask": "0x07",
···
1488
1273
},
1489
1274
{
1490
1275
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1276
+
"Counter": "2,3",
1491
1277
"EventCode": "0xC1",
1492
1278
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
1493
1279
"FCMask": "0x07",
···
1499
1283
},
1500
1284
{
1501
1285
"BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
1286
+
"Counter": "2,3",
1502
1287
"EventCode": "0xC1",
1503
1288
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
1504
1289
"FCMask": "0x07",
···
1510
1293
},
1511
1294
{
1512
1295
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
1296
+
"Counter": "2,3",
1513
1297
"EventCode": "0xC1",
1514
1298
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS",
1515
1299
"FCMask": "0x07",
···
1521
1303
},
1522
1304
{
1523
1305
"BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
1306
+
"Counter": "2,3",
1524
1307
"EventCode": "0xC1",
1525
1308
"EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS",
1526
1309
"FCMask": "0x07",
···
1532
1313
},
1533
1314
{
1534
1315
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1316
+
"Counter": "0,1",
1535
1317
"EventCode": "0x84",
1536
1318
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
1537
1319
"FCMask": "0x07",
···
1543
1323
},
1544
1324
{
1545
1325
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1326
+
"Counter": "0,1",
1546
1327
"EventCode": "0x84",
1547
1328
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
1548
1329
"FCMask": "0x07",
···
1554
1333
},
1555
1334
{
1556
1335
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1336
+
"Counter": "0,1",
1557
1337
"EventCode": "0x84",
1558
1338
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
1559
1339
"FCMask": "0x07",
···
1565
1343
},
1566
1344
{
1567
1345
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1346
+
"Counter": "0,1",
1568
1347
"EventCode": "0x84",
1569
1348
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
1570
1349
"FCMask": "0x07",
···
1576
1353
},
1577
1354
{
1578
1355
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1356
+
"Counter": "0,1",
1579
1357
"EventCode": "0x84",
1580
1358
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
1581
1359
"FCMask": "0x07",
···
1587
1363
},
1588
1364
{
1589
1365
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1366
+
"Counter": "0,1",
1590
1367
"EventCode": "0x84",
1591
1368
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
1592
1369
"FCMask": "0x07",
···
1598
1373
},
1599
1374
{
1600
1375
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1376
+
"Counter": "0,1",
1601
1377
"EventCode": "0x84",
1602
1378
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
1603
1379
"FCMask": "0x07",
···
1609
1383
},
1610
1384
{
1611
1385
"BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
1386
+
"Counter": "0,1",
1612
1387
"EventCode": "0x84",
1613
1388
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
1614
1389
"FCMask": "0x07",
···
1620
1393
},
1621
1394
{
1622
1395
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1396
+
"Counter": "0,1",
1623
1397
"EventCode": "0x84",
1624
1398
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
1625
1399
"FCMask": "0x07",
···
1631
1403
},
1632
1404
{
1633
1405
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1406
+
"Counter": "0,1",
1634
1407
"EventCode": "0x84",
1635
1408
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
1636
1409
"FCMask": "0x07",
···
1642
1413
},
1643
1414
{
1644
1415
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1416
+
"Counter": "0,1",
1645
1417
"EventCode": "0x84",
1646
1418
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
1647
1419
"FCMask": "0x07",
···
1653
1423
},
1654
1424
{
1655
1425
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1426
+
"Counter": "0,1",
1656
1427
"EventCode": "0x84",
1657
1428
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
1658
1429
"FCMask": "0x07",
···
1664
1433
},
1665
1434
{
1666
1435
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1436
+
"Counter": "0,1",
1667
1437
"EventCode": "0x84",
1668
1438
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
1669
1439
"FCMask": "0x07",
···
1675
1443
},
1676
1444
{
1677
1445
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1446
+
"Counter": "0,1",
1678
1447
"EventCode": "0x84",
1679
1448
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
1680
1449
"FCMask": "0x07",
···
1686
1453
},
1687
1454
{
1688
1455
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1456
+
"Counter": "0,1",
1689
1457
"EventCode": "0x84",
1690
1458
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
1691
1459
"FCMask": "0x07",
···
1697
1463
},
1698
1464
{
1699
1465
"BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
1466
+
"Counter": "0,1",
1700
1467
"EventCode": "0x84",
1701
1468
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
1702
1469
"FCMask": "0x07",
···
1708
1473
},
1709
1474
{
1710
1475
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1476
+
"Counter": "0,1",
1711
1477
"EventCode": "0x84",
1712
1478
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
1479
+
"Experimental": "1",
1713
1480
"FCMask": "0x07",
1714
1481
"PerPkg": "1",
1715
1482
"PortMask": "0x001",
···
1720
1483
},
1721
1484
{
1722
1485
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1486
+
"Counter": "0,1",
1723
1487
"EventCode": "0x84",
1724
1488
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
1489
+
"Experimental": "1",
1725
1490
"FCMask": "0x07",
1726
1491
"PerPkg": "1",
1727
1492
"PortMask": "0x002",
···
1732
1493
},
1733
1494
{
1734
1495
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1496
+
"Counter": "0,1",
1735
1497
"EventCode": "0x84",
1736
1498
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
1499
+
"Experimental": "1",
1737
1500
"FCMask": "0x07",
1738
1501
"PerPkg": "1",
1739
1502
"PortMask": "0x004",
···
1744
1503
},
1745
1504
{
1746
1505
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1506
+
"Counter": "0,1",
1747
1507
"EventCode": "0x84",
1748
1508
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
1509
+
"Experimental": "1",
1749
1510
"FCMask": "0x07",
1750
1511
"PerPkg": "1",
1751
1512
"PortMask": "0x008",
···
1756
1513
},
1757
1514
{
1758
1515
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1516
+
"Counter": "0,1",
1759
1517
"EventCode": "0x84",
1760
1518
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
1519
+
"Experimental": "1",
1761
1520
"FCMask": "0x07",
1762
1521
"PerPkg": "1",
1763
1522
"PortMask": "0x010",
···
1768
1523
},
1769
1524
{
1770
1525
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1526
+
"Counter": "0,1",
1771
1527
"EventCode": "0x84",
1772
1528
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
1529
+
"Experimental": "1",
1773
1530
"FCMask": "0x07",
1774
1531
"PerPkg": "1",
1775
1532
"PortMask": "0x020",
···
1780
1533
},
1781
1534
{
1782
1535
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1536
+
"Counter": "0,1",
1783
1537
"EventCode": "0x84",
1784
1538
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
1539
+
"Experimental": "1",
1785
1540
"FCMask": "0x07",
1786
1541
"PerPkg": "1",
1787
1542
"PortMask": "0x040",
···
1792
1543
},
1793
1544
{
1794
1545
"BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
1546
+
"Counter": "0,1",
1795
1547
"EventCode": "0x84",
1796
1548
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
1549
+
"Experimental": "1",
1797
1550
"FCMask": "0x07",
1798
1551
"PerPkg": "1",
1799
1552
"PortMask": "0x080",
···
1804
1553
},
1805
1554
{
1806
1555
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1556
+
"Counter": "0,1",
1807
1557
"EventCode": "0x84",
1808
1558
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
1559
+
"Experimental": "1",
1809
1560
"FCMask": "0x07",
1810
1561
"PerPkg": "1",
1811
1562
"PortMask": "0x001",
···
1816
1563
},
1817
1564
{
1818
1565
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1566
+
"Counter": "0,1",
1819
1567
"EventCode": "0x84",
1820
1568
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
1569
+
"Experimental": "1",
1821
1570
"FCMask": "0x07",
1822
1571
"PerPkg": "1",
1823
1572
"PortMask": "0x002",
···
1828
1573
},
1829
1574
{
1830
1575
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1576
+
"Counter": "0,1",
1831
1577
"EventCode": "0x84",
1832
1578
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
1579
+
"Experimental": "1",
1833
1580
"FCMask": "0x07",
1834
1581
"PerPkg": "1",
1835
1582
"PortMask": "0x004",
···
1840
1583
},
1841
1584
{
1842
1585
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1586
+
"Counter": "0,1",
1843
1587
"EventCode": "0x84",
1844
1588
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
1589
+
"Experimental": "1",
1845
1590
"FCMask": "0x07",
1846
1591
"PerPkg": "1",
1847
1592
"PortMask": "0x008",
···
1852
1593
},
1853
1594
{
1854
1595
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1596
+
"Counter": "0,1",
1855
1597
"EventCode": "0x84",
1856
1598
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
1599
+
"Experimental": "1",
1857
1600
"FCMask": "0x07",
1858
1601
"PerPkg": "1",
1859
1602
"PortMask": "0x010",
···
1864
1603
},
1865
1604
{
1866
1605
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1606
+
"Counter": "0,1",
1867
1607
"EventCode": "0x84",
1868
1608
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
1609
+
"Experimental": "1",
1869
1610
"FCMask": "0x07",
1870
1611
"PerPkg": "1",
1871
1612
"PortMask": "0x020",
···
1876
1613
},
1877
1614
{
1878
1615
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1616
+
"Counter": "0,1",
1879
1617
"EventCode": "0x84",
1880
1618
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
1619
+
"Experimental": "1",
1881
1620
"FCMask": "0x07",
1882
1621
"PerPkg": "1",
1883
1622
"PortMask": "0x040",
···
1888
1623
},
1889
1624
{
1890
1625
"BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
1626
+
"Counter": "0,1",
1891
1627
"EventCode": "0x84",
1892
1628
"EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
1629
+
"Experimental": "1",
1893
1630
"FCMask": "0x07",
1894
1631
"PerPkg": "1",
1895
1632
"PortMask": "0x080",
+66
tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json
+66
tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
4
+
"Counter": "0,1,2,3",
4
5
"EventCode": "0x02",
5
6
"EventName": "UNC_M_ACT_COUNT.ALL",
6
7
"PerPkg": "1",
···
10
9
},
11
10
{
12
11
"BriefDescription": "DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
12
+
"Counter": "0,1,2,3",
13
13
"EventCode": "0x02",
14
14
"EventName": "UNC_M_ACT_COUNT.RD",
15
+
"Experimental": "1",
15
16
"PerPkg": "1",
16
17
"UMask": "0xf1",
17
18
"Unit": "IMC"
18
19
},
19
20
{
20
21
"BriefDescription": "DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
22
+
"Counter": "0,1,2,3",
21
23
"EventCode": "0x02",
22
24
"EventName": "UNC_M_ACT_COUNT.UFILL",
25
+
"Experimental": "1",
23
26
"PerPkg": "1",
24
27
"UMask": "0xf4",
25
28
"Unit": "IMC"
26
29
},
27
30
{
28
31
"BriefDescription": "DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
32
+
"Counter": "0,1,2,3",
29
33
"EventCode": "0x02",
30
34
"EventName": "UNC_M_ACT_COUNT.WR",
35
+
"Experimental": "1",
31
36
"PerPkg": "1",
32
37
"UMask": "0xf2",
33
38
"Unit": "IMC"
34
39
},
35
40
{
36
41
"BriefDescription": "CAS count for SubChannel 0, all CAS operations",
42
+
"Counter": "0,1,2,3",
37
43
"EventCode": "0x05",
38
44
"EventName": "UNC_M_CAS_COUNT_SCH0.ALL",
39
45
"PerPkg": "1",
···
49
41
},
50
42
{
51
43
"BriefDescription": "CAS count for SubChannel 0, all reads",
44
+
"Counter": "0,1,2,3",
52
45
"EventCode": "0x05",
53
46
"EventName": "UNC_M_CAS_COUNT_SCH0.RD",
54
47
"PerPkg": "1",
···
58
49
},
59
50
{
60
51
"BriefDescription": "CAS count for SubChannel 0 regular reads",
52
+
"Counter": "0,1,2,3",
61
53
"EventCode": "0x05",
62
54
"EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG",
63
55
"PerPkg": "1",
···
67
57
},
68
58
{
69
59
"BriefDescription": "CAS count for SubChannel 0 underfill reads",
60
+
"Counter": "0,1,2,3",
70
61
"EventCode": "0x05",
71
62
"EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL",
72
63
"PerPkg": "1",
···
76
65
},
77
66
{
78
67
"BriefDescription": "CAS count for SubChannel 0, all writes",
68
+
"Counter": "0,1,2,3",
79
69
"EventCode": "0x05",
80
70
"EventName": "UNC_M_CAS_COUNT_SCH0.WR",
81
71
"PerPkg": "1",
···
85
73
},
86
74
{
87
75
"BriefDescription": "CAS count for SubChannel 0 regular writes",
76
+
"Counter": "0,1,2,3",
88
77
"EventCode": "0x05",
89
78
"EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE",
79
+
"Experimental": "1",
90
80
"PerPkg": "1",
91
81
"UMask": "0xd0",
92
82
"Unit": "IMC"
93
83
},
94
84
{
95
85
"BriefDescription": "CAS count for SubChannel 0 auto-precharge writes",
86
+
"Counter": "0,1,2,3",
96
87
"EventCode": "0x05",
97
88
"EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE",
89
+
"Experimental": "1",
98
90
"PerPkg": "1",
99
91
"UMask": "0xe0",
100
92
"Unit": "IMC"
101
93
},
102
94
{
103
95
"BriefDescription": "CAS count for SubChannel 1, all CAS operations",
96
+
"Counter": "0,1,2,3",
104
97
"EventCode": "0x06",
105
98
"EventName": "UNC_M_CAS_COUNT_SCH1.ALL",
106
99
"PerPkg": "1",
···
114
97
},
115
98
{
116
99
"BriefDescription": "CAS count for SubChannel 1, all reads",
100
+
"Counter": "0,1,2,3",
117
101
"EventCode": "0x06",
118
102
"EventName": "UNC_M_CAS_COUNT_SCH1.RD",
119
103
"PerPkg": "1",
···
123
105
},
124
106
{
125
107
"BriefDescription": "CAS count for SubChannel 1 regular reads",
108
+
"Counter": "0,1,2,3",
126
109
"EventCode": "0x06",
127
110
"EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG",
128
111
"PerPkg": "1",
···
132
113
},
133
114
{
134
115
"BriefDescription": "CAS count for SubChannel 1 underfill reads",
116
+
"Counter": "0,1,2,3",
135
117
"EventCode": "0x06",
136
118
"EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL",
137
119
"PerPkg": "1",
···
141
121
},
142
122
{
143
123
"BriefDescription": "CAS count for SubChannel 1, all writes",
124
+
"Counter": "0,1,2,3",
144
125
"EventCode": "0x06",
145
126
"EventName": "UNC_M_CAS_COUNT_SCH1.WR",
146
127
"PerPkg": "1",
···
150
129
},
151
130
{
152
131
"BriefDescription": "CAS count for SubChannel 1 regular writes",
132
+
"Counter": "0,1,2,3",
153
133
"EventCode": "0x06",
154
134
"EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE",
135
+
"Experimental": "1",
155
136
"PerPkg": "1",
156
137
"UMask": "0xd0",
157
138
"Unit": "IMC"
158
139
},
159
140
{
160
141
"BriefDescription": "CAS count for SubChannel 1 auto-precharge writes",
142
+
"Counter": "0,1,2,3",
161
143
"EventCode": "0x06",
162
144
"EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE",
145
+
"Experimental": "1",
163
146
"PerPkg": "1",
164
147
"UMask": "0xe0",
165
148
"Unit": "IMC"
166
149
},
167
150
{
168
151
"BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled",
152
+
"Counter": "0,1,2,3",
169
153
"EventCode": "0x01",
170
154
"EventName": "UNC_M_CLOCKTICKS",
171
155
"PerPkg": "1",
···
180
154
},
181
155
{
182
156
"BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
157
+
"Counter": "0,1,2,3",
183
158
"EventCode": "0x01",
184
159
"EventName": "UNC_M_HCLOCKTICKS",
160
+
"Experimental": "1",
185
161
"PerPkg": "1",
186
162
"PublicDescription": "DRAM Clockticks",
187
163
"Unit": "IMC"
188
164
},
189
165
{
190
166
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
167
+
"Counter": "0,1,2,3",
191
168
"EventCode": "0x03",
192
169
"EventName": "UNC_M_PRE_COUNT.ALL",
193
170
"PerPkg": "1",
···
199
170
},
200
171
{
201
172
"BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
173
+
"Counter": "0,1,2,3",
202
174
"EventCode": "0x03",
203
175
"EventName": "UNC_M_PRE_COUNT.PGT",
204
176
"PerPkg": "1",
···
208
178
},
209
179
{
210
180
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
181
+
"Counter": "0,1,2,3",
211
182
"EventCode": "0x03",
212
183
"EventName": "UNC_M_PRE_COUNT.RD",
184
+
"Experimental": "1",
213
185
"PerPkg": "1",
214
186
"UMask": "0xf1",
215
187
"Unit": "IMC"
216
188
},
217
189
{
218
190
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
191
+
"Counter": "0,1,2,3",
219
192
"EventCode": "0x03",
220
193
"EventName": "UNC_M_PRE_COUNT.UFILL",
194
+
"Experimental": "1",
221
195
"PerPkg": "1",
222
196
"UMask": "0xf4",
223
197
"Unit": "IMC"
224
198
},
225
199
{
226
200
"BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
201
+
"Counter": "0,1,2,3",
227
202
"EventCode": "0x03",
228
203
"EventName": "UNC_M_PRE_COUNT.WR",
204
+
"Experimental": "1",
229
205
"PerPkg": "1",
230
206
"UMask": "0xf2",
231
207
"Unit": "IMC"
232
208
},
233
209
{
234
210
"BriefDescription": "Read buffer inserts on subchannel 0",
211
+
"Counter": "0,1,2,3",
235
212
"EventCode": "0x17",
236
213
"EventName": "UNC_M_RDB_INSERTS.SCH0",
214
+
"Experimental": "1",
237
215
"PerPkg": "1",
238
216
"UMask": "0x40",
239
217
"Unit": "IMC"
240
218
},
241
219
{
242
220
"BriefDescription": "Read buffer inserts on subchannel 1",
221
+
"Counter": "0,1,2,3",
243
222
"EventCode": "0x17",
244
223
"EventName": "UNC_M_RDB_INSERTS.SCH1",
224
+
"Experimental": "1",
245
225
"PerPkg": "1",
246
226
"UMask": "0x80",
247
227
"Unit": "IMC"
248
228
},
249
229
{
250
230
"BriefDescription": "Read buffer occupancy on subchannel 0",
231
+
"Counter": "0,1,2,3",
251
232
"EventCode": "0x1a",
252
233
"EventName": "UNC_M_RDB_OCCUPANCY_SCH0",
253
234
"PerPkg": "1",
···
266
225
},
267
226
{
268
227
"BriefDescription": "Read buffer occupancy on subchannel 1",
228
+
"Counter": "0,1,2,3",
269
229
"EventCode": "0x1b",
270
230
"EventName": "UNC_M_RDB_OCCUPANCY_SCH1",
271
231
"PerPkg": "1",
···
274
232
},
275
233
{
276
234
"BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
235
+
"Counter": "0,1,2,3",
277
236
"EventCode": "0x10",
278
237
"EventName": "UNC_M_RPQ_INSERTS.PCH0",
238
+
"Experimental": "1",
279
239
"PerPkg": "1",
280
240
"UMask": "0x50",
281
241
"Unit": "IMC"
282
242
},
283
243
{
284
244
"BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
245
+
"Counter": "0,1,2,3",
285
246
"EventCode": "0x10",
286
247
"EventName": "UNC_M_RPQ_INSERTS.PCH1",
248
+
"Experimental": "1",
287
249
"PerPkg": "1",
288
250
"UMask": "0xa0",
289
251
"Unit": "IMC"
290
252
},
291
253
{
292
254
"BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0",
255
+
"Counter": "0,1,2,3",
293
256
"EventCode": "0x10",
294
257
"EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0",
295
258
"PerPkg": "1",
···
303
256
},
304
257
{
305
258
"BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1",
259
+
"Counter": "0,1,2,3",
306
260
"EventCode": "0x10",
307
261
"EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1",
308
262
"PerPkg": "1",
···
312
264
},
313
265
{
314
266
"BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0",
267
+
"Counter": "0,1,2,3",
315
268
"EventCode": "0x10",
316
269
"EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0",
317
270
"PerPkg": "1",
···
321
272
},
322
273
{
323
274
"BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1",
275
+
"Counter": "0,1,2,3",
324
276
"EventCode": "0x10",
325
277
"EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1",
326
278
"PerPkg": "1",
···
330
280
},
331
281
{
332
282
"BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0",
283
+
"Counter": "0,1,2,3",
333
284
"EventCode": "0x80",
334
285
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0",
335
286
"PerPkg": "1",
···
338
287
},
339
288
{
340
289
"BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1",
290
+
"Counter": "0,1,2,3",
341
291
"EventCode": "0x81",
342
292
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1",
343
293
"PerPkg": "1",
···
346
294
},
347
295
{
348
296
"BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0",
297
+
"Counter": "0,1,2,3",
349
298
"EventCode": "0x82",
350
299
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0",
351
300
"PerPkg": "1",
···
354
301
},
355
302
{
356
303
"BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1",
304
+
"Counter": "0,1,2,3",
357
305
"EventCode": "0x83",
358
306
"EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1",
359
307
"PerPkg": "1",
···
362
308
},
363
309
{
364
310
"BriefDescription": "Write Pending Queue Allocations",
311
+
"Counter": "0,1,2,3",
365
312
"EventCode": "0x22",
366
313
"EventName": "UNC_M_WPQ_INSERTS.PCH0",
314
+
"Experimental": "1",
367
315
"PerPkg": "1",
368
316
"UMask": "0x50",
369
317
"Unit": "IMC"
370
318
},
371
319
{
372
320
"BriefDescription": "Write Pending Queue Allocations",
321
+
"Counter": "0,1,2,3",
373
322
"EventCode": "0x22",
374
323
"EventName": "UNC_M_WPQ_INSERTS.PCH1",
324
+
"Experimental": "1",
375
325
"PerPkg": "1",
376
326
"UMask": "0xa0",
377
327
"Unit": "IMC"
378
328
},
379
329
{
380
330
"BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0",
331
+
"Counter": "0,1,2,3",
381
332
"EventCode": "0x22",
382
333
"EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0",
383
334
"PerPkg": "1",
···
391
332
},
392
333
{
393
334
"BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1",
335
+
"Counter": "0,1,2,3",
394
336
"EventCode": "0x22",
395
337
"EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1",
396
338
"PerPkg": "1",
···
400
340
},
401
341
{
402
342
"BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0",
343
+
"Counter": "0,1,2,3",
403
344
"EventCode": "0x22",
404
345
"EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0",
405
346
"PerPkg": "1",
···
409
348
},
410
349
{
411
350
"BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1",
351
+
"Counter": "0,1,2,3",
412
352
"EventCode": "0x22",
413
353
"EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1",
414
354
"PerPkg": "1",
···
418
356
},
419
357
{
420
358
"BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0",
359
+
"Counter": "0,1,2,3",
421
360
"EventCode": "0x84",
422
361
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0",
423
362
"PerPkg": "1",
···
426
363
},
427
364
{
428
365
"BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1",
366
+
"Counter": "0,1,2,3",
429
367
"EventCode": "0x85",
430
368
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1",
431
369
"PerPkg": "1",
···
434
370
},
435
371
{
436
372
"BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0",
373
+
"Counter": "0,1,2,3",
437
374
"EventCode": "0x86",
438
375
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0",
439
376
"PerPkg": "1",
···
442
377
},
443
378
{
444
379
"BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1",
380
+
"Counter": "0,1,2,3",
445
381
"EventCode": "0x87",
446
382
"EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1",
447
383
"PerPkg": "1",
+1
tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json
+1
tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json
+17
tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
+17
tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json
···
1
1
[
2
2
{
3
3
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
4
+
"Counter": "0,1,2,3,4,5,6,7",
4
5
"EventCode": "0x08",
5
6
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
6
7
"SampleAfterValue": "200003",
···
9
8
},
10
9
{
11
10
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
11
+
"Counter": "0,1,2,3,4,5,6,7",
12
12
"EventCode": "0x08",
13
13
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
14
14
"SampleAfterValue": "200003",
···
17
15
},
18
16
{
19
17
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
18
+
"Counter": "0,1,2,3,4,5,6,7",
20
19
"EventCode": "0x08",
21
20
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
22
21
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
···
26
23
},
27
24
{
28
25
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
26
+
"Counter": "0,1,2,3,4,5,6,7",
29
27
"EventCode": "0x08",
30
28
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
31
29
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
···
35
31
},
36
32
{
37
33
"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.",
34
+
"Counter": "0,1,2,3,4,5,6,7",
38
35
"EventCode": "0x08",
39
36
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
40
37
"PublicDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
···
44
39
},
45
40
{
46
41
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.",
42
+
"Counter": "0,1,2,3,4,5,6,7",
47
43
"EventCode": "0x49",
48
44
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
49
45
"SampleAfterValue": "2000003",
···
52
46
},
53
47
{
54
48
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
49
+
"Counter": "0,1,2,3,4,5,6,7",
55
50
"EventCode": "0x49",
56
51
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
57
52
"SampleAfterValue": "2000003",
···
60
53
},
61
54
{
62
55
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
56
+
"Counter": "0,1,2,3,4,5,6,7",
63
57
"EventCode": "0x49",
64
58
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
65
59
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
···
69
61
},
70
62
{
71
63
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
64
+
"Counter": "0,1,2,3,4,5,6,7",
72
65
"EventCode": "0x49",
73
66
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
74
67
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
···
78
69
},
79
70
{
80
71
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
72
+
"Counter": "0,1,2,3,4,5,6,7",
81
73
"EventCode": "0x49",
82
74
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
83
75
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
···
87
77
},
88
78
{
89
79
"BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
80
+
"Counter": "0,1,2,3,4,5,6,7",
90
81
"EventCode": "0x85",
91
82
"EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
92
83
"SampleAfterValue": "1000003",
···
95
84
},
96
85
{
97
86
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
87
+
"Counter": "0,1,2,3,4,5,6,7",
98
88
"EventCode": "0x85",
99
89
"EventName": "ITLB_MISSES.STLB_HIT",
100
90
"SampleAfterValue": "2000003",
···
103
91
},
104
92
{
105
93
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
94
+
"Counter": "0,1,2,3,4,5,6,7",
106
95
"EventCode": "0x85",
107
96
"EventName": "ITLB_MISSES.WALK_COMPLETED",
108
97
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
···
112
99
},
113
100
{
114
101
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
102
+
"Counter": "0,1,2,3,4,5,6,7",
115
103
"EventCode": "0x85",
116
104
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
117
105
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
···
121
107
},
122
108
{
123
109
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
110
+
"Counter": "0,1,2,3,4,5,6,7",
124
111
"EventCode": "0x85",
125
112
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
126
113
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
···
130
115
},
131
116
{
132
117
"BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.",
118
+
"Counter": "0,1,2,3,4,5,6,7",
133
119
"EventCode": "0x85",
134
120
"EventName": "ITLB_MISSES.WALK_PENDING",
135
121
"PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.",
···
139
123
},
140
124
{
141
125
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
126
+
"Counter": "0,1,2,3,4,5,6,7",
142
127
"EventCode": "0x05",
143
128
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
144
129
"SampleAfterValue": "1000003",