Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-11-09' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly fixes, usual leaders in amdgpu and xe, then a panel quirk, and
some fixes to imagination and panthor drivers. Seems around the usual
level for this time and don't know of any big problems.
amdgpu:
- Brightness fix
- DC vbios parsing fix
- ACPI fix
- SMU 14.x fix
- Power workload profile fix
- GC partitioning fix
- Debugfs fixes
imagination:
- Track PVR context per file
- Break ref-counting cycle
panel-orientation-quirks:
- Fix matching Lenovo Yoga Tab 3 X90F
panthor:
- Lock VM array
- Be strict about I/O mapping flags
xe:
- Fix ccs_mode setting for Xe2 and later
- Synchronize ccs_mode setting with client creation
- Apply scheduling WA for LNL in additional places as needed
- Fix leak and lock handling in error paths of xe_exec ioctl
- Fix GGTT allocation leak leading to eventual crash in SR-IOV
- Move run_ticks update out of job handling to avoid synchronization
with reader"
* tag 'drm-fixes-2024-11-09' of https://gitlab.freedesktop.org/drm/kernel: (23 commits)
drm/panthor: Be stricter about IO mapping flags
drm/panthor: Lock XArray when getting entries for the VM
drm: panel-orientation-quirks: Make Lenovo Yoga Tab 3 X90F DMI match less strict
drm/xe: Stop accumulating LRC timestamp on job_free
drm/xe/pf: Fix potential GGTT allocation leak
drm/xe: Drop VM dma-resv lock on xe_sync_in_fence_get failure in exec IOCTL
drm/xe: Fix possible exec queue leak in exec IOCTL
drm/amdgpu: add missing size check in amdgpu_debugfs_gprwave_read()
drm/amdgpu: Adjust debugfs eviction and IB access permissions
drm/amdgpu: Adjust debugfs register access permissions
drm/amdgpu: Fix DPX valid mode check on GC 9.4.3
drm/amd/pm: correct the workload setting
drm/amd/pm: always pick the pptable from IFWI
drm/amdgpu: prevent NULL pointer dereference if ATIF is not supported
drm/amd/display: parse umc_info or vram_info based on ASIC
drm/amd/display: Fix brightness level not retained over reboot
drm/xe/guc/tlb: Flush g2h worker in case of tlb timeout
drm/xe/ufence: Flush xe ordered_wq in case of ufence timeout
drm/xe: Move LNL scheduling WA to xe_device.h
drm/xe: Use the filelist from drm for ccs_mode change
...
+257
-155
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
···
172
172
&buffer);
173
173
obj = (union acpi_object *)buffer.pointer;
174
174
175
-
/* Fail if calling the method fails and ATIF is supported */
176
-
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
175
+
/* Fail if calling the method fails */
176
+
if (ACPI_FAILURE(status)) {
177
177
DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n",
178
178
acpi_format_exception(status));
179
179
kfree(obj);
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
···
402
402
int r;
403
403
uint32_t *data, x;
404
404
405
-
if (size & 0x3 || *pos & 0x3)
405
+
if (size > 4096 || size & 0x3 || *pos & 0x3)
406
406
return -EINVAL;
407
407
408
408
r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
···
1648
1648
1649
1649
for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1650
1650
ent = debugfs_create_file(debugfs_regs_names[i],
1651
-
S_IFREG | 0444, root,
1651
+
S_IFREG | 0400, root,
1652
1652
adev, debugfs_regs[i]);
1653
1653
if (!i && !IS_ERR_OR_NULL(ent))
1654
1654
i_size_write(ent->d_inode, adev->rmmio_size);
···
2100
2100
amdgpu_securedisplay_debugfs_init(adev);
2101
2101
amdgpu_fw_attestation_debugfs_init(adev);
2102
2102
2103
-
debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
2103
+
debugfs_create_file("amdgpu_evict_vram", 0400, root, adev,
2104
2104
&amdgpu_evict_vram_fops);
2105
-
debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
2105
+
debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev,
2106
2106
&amdgpu_evict_gtt_fops);
2107
-
debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
2107
+
debugfs_create_file("amdgpu_test_ib", 0400, root, adev,
2108
2108
&amdgpu_debugfs_test_ib_fops);
2109
2109
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
2110
2110
&amdgpu_debugfs_vm_info_fops);
+1
-1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
+1
-1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
···
482
482
case AMDGPU_SPX_PARTITION_MODE:
483
483
return adev->gmc.num_mem_partitions == 1 && num_xcc > 0;
484
484
case AMDGPU_DPX_PARTITION_MODE:
485
-
return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0;
485
+
return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0;
486
486
case AMDGPU_TPX_PARTITION_MODE:
487
487
return (adev->gmc.num_mem_partitions == 1 ||
488
488
adev->gmc.num_mem_partitions == 3) &&
+15
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+15
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
9429
9429
bool mode_set_reset_required = false;
9430
9430
u32 i;
9431
9431
struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count};
9432
+
bool set_backlight_level = false;
9432
9433
9433
9434
/* Disable writeback */
9434
9435
for_each_old_connector_in_state(state, connector, old_con_state, i) {
···
9549
9548
acrtc->hw_mode = new_crtc_state->mode;
9550
9549
crtc->hwmode = new_crtc_state->mode;
9551
9550
mode_set_reset_required = true;
9551
+
set_backlight_level = true;
9552
9552
} else if (modereset_required(new_crtc_state)) {
9553
9553
drm_dbg_atomic(dev,
9554
9554
"Atomic commit: RESET. crtc id %d:[%p]\n",
···
9599
9597
dm_new_crtc_state->stream, acrtc);
9600
9598
else
9601
9599
acrtc->otg_inst = status->primary_otg_inst;
9600
+
}
9601
+
}
9602
+
9603
+
/* During boot up and resume the DC layer will reset the panel brightness
9604
+
* to fix a flicker issue.
9605
+
* It will cause the dm->actual_brightness is not the current panel brightness
9606
+
* level. (the dm->brightness is the correct panel level)
9607
+
* So we set the backlight level with dm->brightness value after set mode
9608
+
*/
9609
+
if (set_backlight_level) {
9610
+
for (i = 0; i < dm->num_of_edps; i++) {
9611
+
if (dm->backlight_dev[i])
9612
+
amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9602
9613
}
9603
9614
}
9604
9615
}
+3
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+3
-1
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
···
3127
3127
struct atom_data_revision revision;
3128
3128
3129
3129
// vram info moved to umc_info for DCN4x
3130
-
if (info && DATA_TABLES(umc_info)) {
3130
+
if (dcb->ctx->dce_version >= DCN_VERSION_4_01 &&
3131
+
dcb->ctx->dce_version < DCN_VERSION_MAX &&
3132
+
info && DATA_TABLES(umc_info)) {
3131
3133
header = GET_IMAGE(struct atom_common_table_header,
3132
3134
DATA_TABLES(umc_info));
3133
3135
+35
-14
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+35
-14
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
1259
1259
smu->watermarks_bitmap = 0;
1260
1260
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1261
1261
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1262
+
smu->user_dpm_profile.user_workload_mask = 0;
1262
1263
1263
1264
atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1264
1265
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1265
1266
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
1266
1267
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
1267
1268
1268
-
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1269
-
smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1270
-
smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1271
-
smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1272
-
smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1273
-
smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1274
-
smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1269
+
smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1270
+
smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1271
+
smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1272
+
smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1273
+
smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4;
1274
+
smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1275
+
smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1275
1276
1276
1277
if (smu->is_apu ||
1277
-
!smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D))
1278
-
smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1279
-
else
1280
-
smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1278
+
!smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) {
1279
+
smu->driver_workload_mask =
1280
+
1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1281
+
} else {
1282
+
smu->driver_workload_mask =
1283
+
1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1284
+
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1285
+
}
1281
1286
1287
+
smu->workload_mask = smu->driver_workload_mask |
1288
+
smu->user_dpm_profile.user_workload_mask;
1282
1289
smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1283
1290
smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1284
1291
smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
···
2355
2348
return -EINVAL;
2356
2349
2357
2350
if (!en) {
2358
-
smu->workload_mask &= ~(1 << smu->workload_prority[type]);
2351
+
smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]);
2359
2352
index = fls(smu->workload_mask);
2360
2353
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2361
2354
workload[0] = smu->workload_setting[index];
2362
2355
} else {
2363
-
smu->workload_mask |= (1 << smu->workload_prority[type]);
2356
+
smu->driver_workload_mask |= (1 << smu->workload_priority[type]);
2364
2357
index = fls(smu->workload_mask);
2365
2358
index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2366
2359
workload[0] = smu->workload_setting[index];
2367
2360
}
2361
+
2362
+
smu->workload_mask = smu->driver_workload_mask |
2363
+
smu->user_dpm_profile.user_workload_mask;
2368
2364
2369
2365
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2370
2366
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
···
3059
3049
uint32_t param_size)
3060
3050
{
3061
3051
struct smu_context *smu = handle;
3052
+
int ret;
3062
3053
3063
3054
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
3064
3055
!smu->ppt_funcs->set_power_profile_mode)
3065
3056
return -EOPNOTSUPP;
3066
3057
3067
-
return smu_bump_power_profile_mode(smu, param, param_size);
3058
+
if (smu->user_dpm_profile.user_workload_mask &
3059
+
(1 << smu->workload_priority[param[param_size]]))
3060
+
return 0;
3061
+
3062
+
smu->user_dpm_profile.user_workload_mask =
3063
+
(1 << smu->workload_priority[param[param_size]]);
3064
+
smu->workload_mask = smu->user_dpm_profile.user_workload_mask |
3065
+
smu->driver_workload_mask;
3066
+
ret = smu_bump_power_profile_mode(smu, param, param_size);
3067
+
3068
+
return ret;
3068
3069
}
3069
3070
3070
3071
static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
+3
-1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+3
-1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
···
240
240
/* user clock state information */
241
241
uint32_t clk_mask[SMU_CLK_COUNT];
242
242
uint32_t clk_dependency;
243
+
uint32_t user_workload_mask;
243
244
};
244
245
245
246
#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
···
558
557
bool disable_uclk_switch;
559
558
560
559
uint32_t workload_mask;
561
-
uint32_t workload_prority[WORKLOAD_POLICY_MAX];
560
+
uint32_t driver_workload_mask;
561
+
uint32_t workload_priority[WORKLOAD_POLICY_MAX];
562
562
uint32_t workload_setting[WORKLOAD_POLICY_MAX];
563
563
uint32_t power_profile_mode;
564
564
uint32_t default_power_profile_mode;
+2
-3
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+2
-3
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
···
1455
1455
return -EINVAL;
1456
1456
}
1457
1457
1458
-
1459
1458
if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1460
1459
(smu->smc_fw_version >= 0x360d00)) {
1461
1460
if (size != 10)
···
1522
1523
1523
1524
ret = smu_cmn_send_smc_msg_with_param(smu,
1524
1525
SMU_MSG_SetWorkloadMask,
1525
-
1 << workload_type,
1526
+
smu->workload_mask,
1526
1527
NULL);
1527
1528
if (ret) {
1528
1529
dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1529
1530
return ret;
1530
1531
}
1531
1532
1532
-
smu->power_profile_mode = profile_mode;
1533
+
smu_cmn_assign_power_profile(smu);
1533
1534
1534
1535
return 0;
1535
1536
}
+4
-1
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+4
-1
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
···
1786
1786
smu->power_profile_mode);
1787
1787
if (workload_type < 0)
1788
1788
return -EINVAL;
1789
+
1789
1790
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1790
-
1 << workload_type, NULL);
1791
+
smu->workload_mask, NULL);
1791
1792
if (ret)
1792
1793
dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);
1794
+
else
1795
+
smu_cmn_assign_power_profile(smu);
1793
1796
1794
1797
return ret;
1795
1798
}
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
···
1079
1079
}
1080
1080
1081
1081
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1082
-
1 << workload_type,
1082
+
smu->workload_mask,
1083
1083
NULL);
1084
1084
if (ret) {
1085
1085
dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
···
1087
1087
return ret;
1088
1088
}
1089
1089
1090
-
smu->power_profile_mode = profile_mode;
1090
+
smu_cmn_assign_power_profile(smu);
1091
1091
1092
1092
return 0;
1093
1093
}
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
···
890
890
}
891
891
892
892
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
893
-
1 << workload_type,
893
+
smu->workload_mask,
894
894
NULL);
895
895
if (ret) {
896
896
dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
897
897
return ret;
898
898
}
899
899
900
-
smu->power_profile_mode = profile_mode;
900
+
smu_cmn_assign_power_profile(smu);
901
901
902
902
return 0;
903
903
}
+15
-5
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+15
-5
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
···
2485
2485
DpmActivityMonitorCoeffInt_t *activity_monitor =
2486
2486
&(activity_monitor_external.DpmActivityMonitorCoeffInt);
2487
2487
int workload_type, ret = 0;
2488
-
u32 workload_mask, selected_workload_mask;
2488
+
u32 workload_mask;
2489
2489
2490
2490
smu->power_profile_mode = input[size];
2491
2491
···
2552
2552
if (workload_type < 0)
2553
2553
return -EINVAL;
2554
2554
2555
-
selected_workload_mask = workload_mask = 1 << workload_type;
2555
+
workload_mask = 1 << workload_type;
2556
2556
2557
2557
/* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2558
2558
if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
···
2567
2567
workload_mask |= 1 << workload_type;
2568
2568
}
2569
2569
2570
+
smu->workload_mask |= workload_mask;
2570
2571
ret = smu_cmn_send_smc_msg_with_param(smu,
2571
2572
SMU_MSG_SetWorkloadMask,
2572
-
workload_mask,
2573
+
smu->workload_mask,
2573
2574
NULL);
2574
-
if (!ret)
2575
-
smu->workload_mask = selected_workload_mask;
2575
+
if (!ret) {
2576
+
smu_cmn_assign_power_profile(smu);
2577
+
if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) {
2578
+
workload_type = smu_cmn_to_asic_specific_index(smu,
2579
+
CMN2ASIC_MAPPING_WORKLOAD,
2580
+
PP_SMC_POWER_PROFILE_FULLSCREEN3D);
2581
+
smu->power_profile_mode = smu->workload_mask & (1 << workload_type)
2582
+
? PP_SMC_POWER_PROFILE_FULLSCREEN3D
2583
+
: PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
2584
+
}
2585
+
}
2576
2586
2577
2587
return ret;
2578
2588
}
+3
-2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+3
-2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
···
2499
2499
smu->power_profile_mode);
2500
2500
if (workload_type < 0)
2501
2501
return -EINVAL;
2502
+
2502
2503
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2503
-
1 << workload_type, NULL);
2504
+
smu->workload_mask, NULL);
2504
2505
2505
2506
if (ret)
2506
2507
dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);
2507
2508
else
2508
-
smu->workload_mask = (1 << workload_type);
2509
+
smu_cmn_assign_power_profile(smu);
2509
2510
2510
2511
return ret;
2511
2512
}
+5
-69
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+5
-69
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
···
367
367
return 0;
368
368
}
369
369
370
-
#ifndef atom_smc_dpm_info_table_14_0_0
371
-
struct atom_smc_dpm_info_table_14_0_0 {
372
-
struct atom_common_table_header table_header;
373
-
BoardTable_t BoardTable;
374
-
};
375
-
#endif
376
-
377
-
static int smu_v14_0_2_append_powerplay_table(struct smu_context *smu)
378
-
{
379
-
struct smu_table_context *table_context = &smu->smu_table;
380
-
PPTable_t *smc_pptable = table_context->driver_pptable;
381
-
struct atom_smc_dpm_info_table_14_0_0 *smc_dpm_table;
382
-
BoardTable_t *BoardTable = &smc_pptable->BoardTable;
383
-
int index, ret;
384
-
385
-
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
386
-
smc_dpm_info);
387
-
388
-
ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
389
-
(uint8_t **)&smc_dpm_table);
390
-
if (ret)
391
-
return ret;
392
-
393
-
memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
394
-
395
-
return 0;
396
-
}
397
-
398
-
#if 0
399
-
static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
400
-
void **table,
401
-
uint32_t *size)
402
-
{
403
-
struct smu_table_context *smu_table = &smu->smu_table;
404
-
void *combo_pptable = smu_table->combo_pptable;
405
-
int ret = 0;
406
-
407
-
ret = smu_cmn_get_combo_pptable(smu);
408
-
if (ret)
409
-
return ret;
410
-
411
-
*table = combo_pptable;
412
-
*size = sizeof(struct smu_14_0_powerplay_table);
413
-
414
-
return 0;
415
-
}
416
-
#endif
417
-
418
370
static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
419
371
void **table,
420
372
uint32_t *size)
···
388
436
static int smu_v14_0_2_setup_pptable(struct smu_context *smu)
389
437
{
390
438
struct smu_table_context *smu_table = &smu->smu_table;
391
-
struct amdgpu_device *adev = smu->adev;
392
439
int ret = 0;
393
440
394
441
if (amdgpu_sriov_vf(smu->adev))
395
442
return 0;
396
443
397
-
if (!adev->scpm_enabled)
398
-
ret = smu_v14_0_setup_pptable(smu);
399
-
else
400
-
ret = smu_v14_0_2_get_pptable_from_pmfw(smu,
444
+
ret = smu_v14_0_2_get_pptable_from_pmfw(smu,
401
445
&smu_table->power_play_table,
402
446
&smu_table->power_play_table_size);
403
447
if (ret)
···
402
454
ret = smu_v14_0_2_store_powerplay_table(smu);
403
455
if (ret)
404
456
return ret;
405
-
406
-
/*
407
-
* With SCPM enabled, the operation below will be handled
408
-
* by PSP. Driver involvment is unnecessary and useless.
409
-
*/
410
-
if (!adev->scpm_enabled) {
411
-
ret = smu_v14_0_2_append_powerplay_table(smu);
412
-
if (ret)
413
-
return ret;
414
-
}
415
457
416
458
ret = smu_v14_0_2_check_powerplay_table(smu);
417
459
if (ret)
···
1807
1869
if (workload_type < 0)
1808
1870
return -EINVAL;
1809
1871
1810
-
ret = smu_cmn_send_smc_msg_with_param(smu,
1811
-
SMU_MSG_SetWorkloadMask,
1812
-
1 << workload_type,
1813
-
NULL);
1872
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1873
+
smu->workload_mask, NULL);
1874
+
1814
1875
if (!ret)
1815
-
smu->workload_mask = 1 << workload_type;
1876
+
smu_cmn_assign_power_profile(smu);
1816
1877
1817
1878
return ret;
1818
1879
}
···
2736
2799
.check_fw_status = smu_v14_0_check_fw_status,
2737
2800
.setup_pptable = smu_v14_0_2_setup_pptable,
2738
2801
.check_fw_version = smu_v14_0_check_fw_version,
2739
-
.write_pptable = smu_cmn_write_pptable,
2740
2802
.set_driver_table_location = smu_v14_0_set_driver_table_location,
2741
2803
.system_features_control = smu_v14_0_system_features_control,
2742
2804
.set_allowed_mask = smu_v14_0_set_allowed_mask,
+8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
···
1138
1138
return ret;
1139
1139
}
1140
1140
1141
+
void smu_cmn_assign_power_profile(struct smu_context *smu)
1142
+
{
1143
+
uint32_t index;
1144
+
index = fls(smu->workload_mask);
1145
+
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1146
+
smu->power_profile_mode = smu->workload_setting[index];
1147
+
}
1148
+
1141
1149
bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
1142
1150
{
1143
1151
struct pci_dev *p = NULL;
+2
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+2
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
···
130
130
int smu_cmn_set_mp1_state(struct smu_context *smu,
131
131
enum pp_mp1_state mp1_state);
132
132
133
+
void smu_cmn_assign_power_profile(struct smu_context *smu);
134
+
133
135
/*
134
136
* Helper function to make sysfs_emit_at() happy. Align buf to
135
137
* the current page boundary and record the offset.
-1
drivers/gpu/drm/drm_panel_orientation_quirks.c
-1
drivers/gpu/drm/drm_panel_orientation_quirks.c
···
403
403
}, { /* Lenovo Yoga Tab 3 X90F */
404
404
.matches = {
405
405
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
406
-
DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
407
406
DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
408
407
},
409
408
.driver_data = (void *)&lcd1600x2560_rightside_up,
+33
drivers/gpu/drm/imagination/pvr_context.c
+33
drivers/gpu/drm/imagination/pvr_context.c
···
17
17
18
18
#include <drm/drm_auth.h>
19
19
#include <drm/drm_managed.h>
20
+
21
+
#include <linux/bug.h>
20
22
#include <linux/errno.h>
21
23
#include <linux/kernel.h>
24
+
#include <linux/list.h>
22
25
#include <linux/sched.h>
23
26
#include <linux/slab.h>
27
+
#include <linux/spinlock.h>
24
28
#include <linux/string.h>
25
29
#include <linux/types.h>
26
30
#include <linux/xarray.h>
···
358
354
return err;
359
355
}
360
356
357
+
spin_lock(&pvr_dev->ctx_list_lock);
358
+
list_add_tail(&ctx->file_link, &pvr_file->contexts);
359
+
spin_unlock(&pvr_dev->ctx_list_lock);
360
+
361
361
return 0;
362
362
363
363
err_destroy_fw_obj:
···
387
379
struct pvr_context *ctx =
388
380
container_of(ref_count, struct pvr_context, ref_count);
389
381
struct pvr_device *pvr_dev = ctx->pvr_dev;
382
+
383
+
WARN_ON(in_interrupt());
384
+
spin_lock(&pvr_dev->ctx_list_lock);
385
+
list_del(&ctx->file_link);
386
+
spin_unlock(&pvr_dev->ctx_list_lock);
390
387
391
388
xa_erase(&pvr_dev->ctx_ids, ctx->ctx_id);
392
389
pvr_context_destroy_queues(ctx);
···
450
437
*/
451
438
void pvr_destroy_contexts_for_file(struct pvr_file *pvr_file)
452
439
{
440
+
struct pvr_device *pvr_dev = pvr_file->pvr_dev;
453
441
struct pvr_context *ctx;
454
442
unsigned long handle;
455
443
456
444
xa_for_each(&pvr_file->ctx_handles, handle, ctx)
457
445
pvr_context_destroy(pvr_file, handle);
446
+
447
+
spin_lock(&pvr_dev->ctx_list_lock);
448
+
ctx = list_first_entry(&pvr_file->contexts, struct pvr_context, file_link);
449
+
450
+
while (!list_entry_is_head(ctx, &pvr_file->contexts, file_link)) {
451
+
list_del_init(&ctx->file_link);
452
+
453
+
if (pvr_context_get_if_referenced(ctx)) {
454
+
spin_unlock(&pvr_dev->ctx_list_lock);
455
+
456
+
pvr_vm_unmap_all(ctx->vm_ctx);
457
+
458
+
pvr_context_put(ctx);
459
+
spin_lock(&pvr_dev->ctx_list_lock);
460
+
}
461
+
ctx = list_first_entry(&pvr_file->contexts, struct pvr_context, file_link);
462
+
}
463
+
spin_unlock(&pvr_dev->ctx_list_lock);
458
464
}
459
465
460
466
/**
···
483
451
void pvr_context_device_init(struct pvr_device *pvr_dev)
484
452
{
485
453
xa_init_flags(&pvr_dev->ctx_ids, XA_FLAGS_ALLOC1);
454
+
spin_lock_init(&pvr_dev->ctx_list_lock);
486
455
}
487
456
488
457
/**
+21
drivers/gpu/drm/imagination/pvr_context.h
+21
drivers/gpu/drm/imagination/pvr_context.h
···
85
85
/** @compute: Transfer queue. */
86
86
struct pvr_queue *transfer;
87
87
} queues;
88
+
89
+
/** @file_link: pvr_file PVR context list link. */
90
+
struct list_head file_link;
88
91
};
89
92
90
93
static __always_inline struct pvr_queue *
···
124
121
kref_get(&ctx->ref_count);
125
122
126
123
return ctx;
124
+
}
125
+
126
+
/**
127
+
* pvr_context_get_if_referenced() - Take an additional reference on a still
128
+
* referenced context.
129
+
* @ctx: Context pointer.
130
+
*
131
+
* Call pvr_context_put() to release.
132
+
*
133
+
* Returns:
134
+
* * True on success, or
135
+
* * false if no context pointer passed, or the context wasn't still
136
+
* * referenced.
137
+
*/
138
+
static __always_inline bool
139
+
pvr_context_get_if_referenced(struct pvr_context *ctx)
140
+
{
141
+
return ctx != NULL && kref_get_unless_zero(&ctx->ref_count) != 0;
127
142
}
128
143
129
144
/**
+10
drivers/gpu/drm/imagination/pvr_device.h
+10
drivers/gpu/drm/imagination/pvr_device.h
···
23
23
#include <linux/kernel.h>
24
24
#include <linux/math.h>
25
25
#include <linux/mutex.h>
26
+
#include <linux/spinlock_types.h>
26
27
#include <linux/timer.h>
27
28
#include <linux/types.h>
28
29
#include <linux/wait.h>
···
294
293
295
294
/** @sched_wq: Workqueue for schedulers. */
296
295
struct workqueue_struct *sched_wq;
296
+
297
+
/**
298
+
* @ctx_list_lock: Lock to be held when accessing the context list in
299
+
* struct pvr_file.
300
+
*/
301
+
spinlock_t ctx_list_lock;
297
302
};
298
303
299
304
/**
···
351
344
* This array is used to allocate handles returned to userspace.
352
345
*/
353
346
struct xarray vm_ctx_handles;
347
+
348
+
/** @contexts: PVR context list. */
349
+
struct list_head contexts;
354
350
};
355
351
356
352
/**
+3
drivers/gpu/drm/imagination/pvr_drv.c
+3
drivers/gpu/drm/imagination/pvr_drv.c
···
28
28
#include <linux/export.h>
29
29
#include <linux/fs.h>
30
30
#include <linux/kernel.h>
31
+
#include <linux/list.h>
31
32
#include <linux/mod_devicetable.h>
32
33
#include <linux/module.h>
33
34
#include <linux/moduleparam.h>
···
1326
1325
* private data for convenient access.
1327
1326
*/
1328
1327
pvr_file->pvr_dev = pvr_dev;
1328
+
1329
+
INIT_LIST_HEAD(&pvr_file->contexts);
1329
1330
1330
1331
xa_init_flags(&pvr_file->ctx_handles, XA_FLAGS_ALLOC1);
1331
1332
xa_init_flags(&pvr_file->free_list_handles, XA_FLAGS_ALLOC1);
+18
-4
drivers/gpu/drm/imagination/pvr_vm.c
+18
-4
drivers/gpu/drm/imagination/pvr_vm.c
···
14
14
#include <drm/drm_gem.h>
15
15
#include <drm/drm_gpuvm.h>
16
16
17
+
#include <linux/bug.h>
17
18
#include <linux/container_of.h>
18
19
#include <linux/err.h>
19
20
#include <linux/errno.h>
···
598
597
}
599
598
600
599
/**
601
-
* pvr_vm_context_release() - Teardown a VM context.
602
-
* @ref_count: Pointer to reference counter of the VM context.
600
+
* pvr_vm_unmap_all() - Unmap all mappings associated with a VM context.
601
+
* @vm_ctx: Target VM context.
603
602
*
604
603
* This function ensures that no mappings are left dangling by unmapping them
605
604
* all in order of ascending device-virtual address.
605
+
*/
606
+
void
607
+
pvr_vm_unmap_all(struct pvr_vm_context *vm_ctx)
608
+
{
609
+
WARN_ON(pvr_vm_unmap(vm_ctx, vm_ctx->gpuvm_mgr.mm_start,
610
+
vm_ctx->gpuvm_mgr.mm_range));
611
+
}
612
+
613
+
/**
614
+
* pvr_vm_context_release() - Teardown a VM context.
615
+
* @ref_count: Pointer to reference counter of the VM context.
616
+
*
617
+
* This function also ensures that no mappings are left dangling by calling
618
+
* pvr_vm_unmap_all.
606
619
*/
607
620
static void
608
621
pvr_vm_context_release(struct kref *ref_count)
···
627
612
if (vm_ctx->fw_mem_ctx_obj)
628
613
pvr_fw_object_destroy(vm_ctx->fw_mem_ctx_obj);
629
614
630
-
WARN_ON(pvr_vm_unmap(vm_ctx, vm_ctx->gpuvm_mgr.mm_start,
631
-
vm_ctx->gpuvm_mgr.mm_range));
615
+
pvr_vm_unmap_all(vm_ctx);
632
616
633
617
pvr_mmu_context_destroy(vm_ctx->mmu_ctx);
634
618
drm_gem_private_object_fini(&vm_ctx->dummy_gem);
+1
drivers/gpu/drm/imagination/pvr_vm.h
+1
drivers/gpu/drm/imagination/pvr_vm.h
···
39
39
struct pvr_gem_object *pvr_obj, u64 pvr_obj_offset,
40
40
u64 device_addr, u64 size);
41
41
int pvr_vm_unmap(struct pvr_vm_context *vm_ctx, u64 device_addr, u64 size);
42
+
void pvr_vm_unmap_all(struct pvr_vm_context *vm_ctx);
42
43
43
44
dma_addr_t pvr_vm_get_page_table_root_addr(struct pvr_vm_context *vm_ctx);
44
45
struct dma_resv *pvr_vm_get_dma_resv(struct pvr_vm_context *vm_ctx);
+4
drivers/gpu/drm/panthor/panthor_device.c
+4
drivers/gpu/drm/panthor/panthor_device.c
···
390
390
{
391
391
u64 offset = (u64)vma->vm_pgoff << PAGE_SHIFT;
392
392
393
+
if ((vma->vm_flags & VM_SHARED) == 0)
394
+
return -EINVAL;
395
+
393
396
switch (offset) {
394
397
case DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET:
395
398
if (vma->vm_end - vma->vm_start != PAGE_SIZE ||
396
399
(vma->vm_flags & (VM_WRITE | VM_EXEC)))
397
400
return -EINVAL;
401
+
vm_flags_clear(vma, VM_MAYWRITE);
398
402
399
403
break;
400
404
+2
drivers/gpu/drm/panthor/panthor_mmu.c
+2
drivers/gpu/drm/panthor/panthor_mmu.c
+1
-1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
+1
-1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
···
517
517
* [4-6] RSVD
518
518
* [7] Disabled
519
519
*/
520
-
#define CCS_MODE XE_REG(0x14804)
520
+
#define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED)
521
521
#define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */
522
522
#define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */
523
523
#define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1)
-10
drivers/gpu/drm/xe/xe_device.c
-10
drivers/gpu/drm/xe/xe_device.c
···
87
87
mutex_init(&xef->exec_queue.lock);
88
88
xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1);
89
89
90
-
spin_lock(&xe->clients.lock);
91
-
xe->clients.count++;
92
-
spin_unlock(&xe->clients.lock);
93
-
94
90
file->driver_priv = xef;
95
91
kref_init(&xef->refcount);
96
92
···
103
107
static void xe_file_destroy(struct kref *ref)
104
108
{
105
109
struct xe_file *xef = container_of(ref, struct xe_file, refcount);
106
-
struct xe_device *xe = xef->xe;
107
110
108
111
xa_destroy(&xef->exec_queue.xa);
109
112
mutex_destroy(&xef->exec_queue.lock);
110
113
xa_destroy(&xef->vm.xa);
111
114
mutex_destroy(&xef->vm.lock);
112
-
113
-
spin_lock(&xe->clients.lock);
114
-
xe->clients.count--;
115
-
spin_unlock(&xe->clients.lock);
116
115
117
116
xe_drm_client_put(xef->client);
118
117
kfree(xef->process_name);
···
324
333
xe->info.force_execlist = xe_modparam.force_execlist;
325
334
326
335
spin_lock_init(&xe->irq.lock);
327
-
spin_lock_init(&xe->clients.lock);
328
336
329
337
init_waitqueue_head(&xe->ufence_wq);
330
338
+14
drivers/gpu/drm/xe/xe_device.h
+14
drivers/gpu/drm/xe/xe_device.h
···
178
178
struct xe_file *xe_file_get(struct xe_file *xef);
179
179
void xe_file_put(struct xe_file *xef);
180
180
181
+
/*
182
+
* Occasionally it is seen that the G2H worker starts running after a delay of more than
183
+
* a second even after being queued and activated by the Linux workqueue subsystem. This
184
+
* leads to G2H timeout error. The root cause of issue lies with scheduling latency of
185
+
* Lunarlake Hybrid CPU. Issue disappears if we disable Lunarlake atom cores from BIOS
186
+
* and this is beyond xe kmd.
187
+
*
188
+
* TODO: Drop this change once workqueue scheduling delay issue is fixed on LNL Hybrid CPU.
189
+
*/
190
+
#define LNL_FLUSH_WORKQUEUE(wq__) \
191
+
flush_workqueue(wq__)
192
+
#define LNL_FLUSH_WORK(wrk__) \
193
+
flush_work(wrk__)
194
+
181
195
#endif
-9
drivers/gpu/drm/xe/xe_device_types.h
-9
drivers/gpu/drm/xe/xe_device_types.h
···
353
353
struct workqueue_struct *wq;
354
354
} sriov;
355
355
356
-
/** @clients: drm clients info */
357
-
struct {
358
-
/** @clients.lock: Protects drm clients info */
359
-
spinlock_t lock;
360
-
361
-
/** @clients.count: number of drm clients */
362
-
u64 count;
363
-
} clients;
364
-
365
356
/** @usm: unified memory state */
366
357
struct {
367
358
/** @usm.asid: convert a ASID to VM */
+9
-4
drivers/gpu/drm/xe/xe_exec.c
+9
-4
drivers/gpu/drm/xe/xe_exec.c
···
132
132
if (XE_IOCTL_DBG(xe, !q))
133
133
return -ENOENT;
134
134
135
-
if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM))
136
-
return -EINVAL;
135
+
if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) {
136
+
err = -EINVAL;
137
+
goto err_exec_queue;
138
+
}
137
139
138
140
if (XE_IOCTL_DBG(xe, args->num_batch_buffer &&
139
-
q->width != args->num_batch_buffer))
140
-
return -EINVAL;
141
+
q->width != args->num_batch_buffer)) {
142
+
err = -EINVAL;
143
+
goto err_exec_queue;
144
+
}
141
145
142
146
if (XE_IOCTL_DBG(xe, q->ops->reset_status(q))) {
143
147
err = -ECANCELED;
···
224
220
fence = xe_sync_in_fence_get(syncs, num_syncs, q, vm);
225
221
if (IS_ERR(fence)) {
226
222
err = PTR_ERR(fence);
223
+
xe_vm_unlock(vm);
227
224
goto err_unlock_list;
228
225
}
229
226
for (i = 0; i < num_syncs; i++)
+6
drivers/gpu/drm/xe/xe_exec_queue.c
+6
drivers/gpu/drm/xe/xe_exec_queue.c
···
260
260
{
261
261
int i;
262
262
263
+
/*
264
+
* Before releasing our ref to lrc and xef, accumulate our run ticks
265
+
*/
266
+
xe_exec_queue_update_run_ticks(q);
267
+
263
268
for (i = 0; i < q->width; ++i)
264
269
xe_lrc_put(q->lrc[i]);
270
+
265
271
__xe_exec_queue_free(q);
266
272
}
267
273
+11
-4
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+11
-4
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
···
68
68
}
69
69
}
70
70
71
+
/*
72
+
* Mask bits need to be set for the register. Though only Xe2+
73
+
* platforms require setting of mask bits, it won't harm for older
74
+
* platforms as these bits are unused there.
75
+
*/
76
+
mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
71
77
xe_mmio_write32(gt, CCS_MODE, mode);
72
78
73
79
xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
···
139
133
}
140
134
141
135
/* CCS mode can only be updated when there are no drm clients */
142
-
spin_lock(&xe->clients.lock);
143
-
if (xe->clients.count) {
144
-
spin_unlock(&xe->clients.lock);
136
+
mutex_lock(&xe->drm.filelist_mutex);
137
+
if (!list_empty(&xe->drm.filelist)) {
138
+
mutex_unlock(&xe->drm.filelist_mutex);
139
+
xe_gt_dbg(gt, "Rejecting compute mode change as there are active drm clients\n");
145
140
return -EBUSY;
146
141
}
147
142
···
153
146
xe_gt_reset_async(gt);
154
147
}
155
148
156
-
spin_unlock(&xe->clients.lock);
149
+
mutex_unlock(&xe->drm.filelist_mutex);
157
150
158
151
return count;
159
152
}
+3
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
+3
-1
drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
···
387
387
* the xe_ggtt_clear() called by below xe_ggtt_remove_node().
388
388
*/
389
389
xe_ggtt_node_remove(node, false);
390
+
} else {
391
+
xe_ggtt_node_fini(node);
390
392
}
391
393
}
392
394
···
444
442
config->ggtt_region = node;
445
443
return 0;
446
444
err:
447
-
xe_ggtt_node_fini(node);
445
+
pf_release_ggtt(tile, node);
448
446
return err;
449
447
}
450
448
+2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+2
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
···
72
72
struct xe_device *xe = gt_to_xe(gt);
73
73
struct xe_gt_tlb_invalidation_fence *fence, *next;
74
74
75
+
LNL_FLUSH_WORK(>->uc.guc.ct.g2h_worker);
76
+
75
77
spin_lock_irq(>->tlb_invalidation.pending_lock);
76
78
list_for_each_entry_safe(fence, next,
77
79
>->tlb_invalidation.pending_fences, link) {
+1
-10
drivers/gpu/drm/xe/xe_guc_ct.c
+1
-10
drivers/gpu/drm/xe/xe_guc_ct.c
···
897
897
898
898
ret = wait_event_timeout(ct->g2h_fence_wq, g2h_fence.done, HZ);
899
899
900
-
/*
901
-
* Occasionally it is seen that the G2H worker starts running after a delay of more than
902
-
* a second even after being queued and activated by the Linux workqueue subsystem. This
903
-
* leads to G2H timeout error. The root cause of issue lies with scheduling latency of
904
-
* Lunarlake Hybrid CPU. Issue dissappears if we disable Lunarlake atom cores from BIOS
905
-
* and this is beyond xe kmd.
906
-
*
907
-
* TODO: Drop this change once workqueue scheduling delay issue is fixed on LNL Hybrid CPU.
908
-
*/
909
900
if (!ret) {
910
-
flush_work(&ct->g2h_worker);
901
+
LNL_FLUSH_WORK(&ct->g2h_worker);
911
902
if (g2h_fence.done) {
912
903
xe_gt_warn(gt, "G2H fence %u, action %04x, done\n",
913
904
g2h_fence.seqno, action[0]);
-2
drivers/gpu/drm/xe/xe_guc_submit.c
-2
drivers/gpu/drm/xe/xe_guc_submit.c
+7
drivers/gpu/drm/xe/xe_wait_user_fence.c
+7
drivers/gpu/drm/xe/xe_wait_user_fence.c
···
155
155
}
156
156
157
157
if (!timeout) {
158
+
LNL_FLUSH_WORKQUEUE(xe->ordered_wq);
159
+
err = do_compare(addr, args->value, args->mask,
160
+
args->op);
161
+
if (err <= 0) {
162
+
drm_dbg(&xe->drm, "LNL_FLUSH_WORKQUEUE resolved ufence timeout\n");
163
+
break;
164
+
}
158
165
err = -ETIME;
159
166
break;
160
167
}